./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 18:32:50,151 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 18:32:50,153 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 18:32:50,188 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 18:32:50,188 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 18:32:50,189 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 18:32:50,191 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 18:32:50,198 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 18:32:50,203 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 18:32:50,209 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 18:32:50,210 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 18:32:50,212 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 18:32:50,212 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 18:32:50,215 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 18:32:50,218 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 18:32:50,219 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 18:32:50,219 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 18:32:50,220 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 18:32:50,222 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 18:32:50,223 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 18:32:50,224 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 18:32:50,228 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 18:32:50,232 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 18:32:50,233 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 18:32:50,245 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 18:32:50,246 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 18:32:50,246 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 18:32:50,247 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 18:32:50,248 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 18:32:50,249 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 18:32:50,249 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 18:32:50,250 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 18:32:50,252 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 18:32:50,253 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 18:32:50,254 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 18:32:50,254 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 18:32:50,254 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 18:32:50,255 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 18:32:50,255 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 18:32:50,256 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 18:32:50,256 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 18:32:50,257 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-18 18:32:50,298 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 18:32:50,298 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 18:32:50,299 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 18:32:50,299 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 18:32:50,300 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 18:32:50,300 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 18:32:50,301 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 18:32:50,301 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 18:32:50,301 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 18:32:50,301 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 18:32:50,302 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 18:32:50,302 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 18:32:50,302 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 18:32:50,303 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 18:32:50,303 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 18:32:50,303 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 18:32:50,303 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 18:32:50,303 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 18:32:50,304 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 18:32:50,304 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 18:32:50,304 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 18:32:50,304 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 18:32:50,304 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 18:32:50,306 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 18:32:50,306 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 18:32:50,306 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 18:32:50,306 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 18:32:50,307 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 18:32:50,308 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 18:32:50,308 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2022-11-18 18:32:50,587 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 18:32:50,618 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 18:32:50,621 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 18:32:50,622 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 18:32:50,623 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 18:32:50,624 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-18 18:32:50,692 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/data/3953aef29/42672a7cabf141ee9181735b12cf7b11/FLAGbf96d3d95 [2022-11-18 18:32:51,292 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 18:32:51,293 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-18 18:32:51,301 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/data/3953aef29/42672a7cabf141ee9181735b12cf7b11/FLAGbf96d3d95 [2022-11-18 18:32:51,595 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/data/3953aef29/42672a7cabf141ee9181735b12cf7b11 [2022-11-18 18:32:51,597 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 18:32:51,599 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 18:32:51,600 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 18:32:51,601 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 18:32:51,604 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 18:32:51,605 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:32:51" (1/1) ... [2022-11-18 18:32:51,606 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6000df3e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:51, skipping insertion in model container [2022-11-18 18:32:51,606 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:32:51" (1/1) ... [2022-11-18 18:32:51,613 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 18:32:51,639 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 18:32:52,013 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:32:52,024 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 18:32:52,080 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:32:52,118 INFO L208 MainTranslator]: Completed translation [2022-11-18 18:32:52,119 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52 WrapperNode [2022-11-18 18:32:52,120 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 18:32:52,121 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 18:32:52,121 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 18:32:52,121 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 18:32:52,129 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,146 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,164 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-18 18:32:52,165 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 18:32:52,165 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 18:32:52,166 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 18:32:52,166 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 18:32:52,172 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,173 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,174 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,179 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,182 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,183 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,184 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,186 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 18:32:52,187 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 18:32:52,187 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 18:32:52,187 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 18:32:52,188 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (1/1) ... [2022-11-18 18:32:52,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:52,205 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:52,218 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:52,225 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 18:32:52,263 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 18:32:52,263 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 18:32:52,263 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 18:32:52,263 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 18:32:52,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 18:32:52,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 18:32:52,341 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 18:32:52,343 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 18:32:52,540 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 18:32:52,553 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 18:32:52,554 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 18:32:52,556 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:32:52 BoogieIcfgContainer [2022-11-18 18:32:52,557 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 18:32:52,558 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 18:32:52,558 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 18:32:52,563 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 18:32:52,564 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:52,564 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 06:32:51" (1/3) ... [2022-11-18 18:32:52,565 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a9c99ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:32:52, skipping insertion in model container [2022-11-18 18:32:52,566 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:52,566 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:52" (2/3) ... [2022-11-18 18:32:52,566 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a9c99ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:32:52, skipping insertion in model container [2022-11-18 18:32:52,567 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:52,567 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:32:52" (3/3) ... [2022-11-18 18:32:52,568 INFO L332 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2022-11-18 18:32:52,668 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 18:32:52,669 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 18:32:52,669 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 18:32:52,669 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 18:32:52,669 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 18:32:52,669 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 18:32:52,669 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 18:32:52,670 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 18:32:52,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:52,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:32:52,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:52,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:52,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 18:32:52,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:52,718 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 18:32:52,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:52,720 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:32:52,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:52,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:52,720 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 18:32:52,720 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:52,729 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-18 18:32:52,729 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-18 18:32:52,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:52,735 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-18 18:32:52,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:52,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388881678] [2022-11-18 18:32:52,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:52,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:52,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:52,893 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:52,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:52,942 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:52,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:52,945 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-18 18:32:52,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:52,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655452111] [2022-11-18 18:32:52,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:52,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:52,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:52,981 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:52,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:52,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:53,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:53,011 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-18 18:32:53,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:53,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575900653] [2022-11-18 18:32:53,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:53,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:53,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:53,068 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:53,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:53,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:53,458 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 18:32:53,459 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 18:32:53,459 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 18:32:53,459 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 18:32:53,459 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 18:32:53,459 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:53,460 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 18:32:53,460 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 18:32:53,460 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2022-11-18 18:32:53,460 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 18:32:53,460 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 18:32:53,478 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,488 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,492 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,496 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,499 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,501 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,632 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,635 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,638 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,640 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,643 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,646 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:53,950 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 18:32:53,954 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 18:32:53,956 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:53,956 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:53,964 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:53,967 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 18:32:53,968 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:53,982 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:53,982 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:53,982 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:53,983 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:53,983 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:53,984 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:53,985 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:54,001 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,010 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,010 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,012 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,043 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,044 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 18:32:54,057 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,058 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,058 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,058 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,062 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:54,062 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:54,074 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,077 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,081 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,093 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 18:32:54,094 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,105 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,105 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:54,105 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,106 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,106 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,107 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:54,107 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:54,124 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,134 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,134 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,135 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,136 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,145 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,157 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,158 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:54,158 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,158 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,158 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,159 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:54,159 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:54,158 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 18:32:54,168 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,180 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,184 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,189 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 18:32:54,201 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,201 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:54,201 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,201 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,201 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,202 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:54,202 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:54,203 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,208 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,210 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,213 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 18:32:54,213 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,223 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,223 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:54,224 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,224 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,224 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,225 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:54,225 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:54,229 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,232 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,232 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,232 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,233 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,235 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 18:32:54,236 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,246 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,247 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,247 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,247 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,251 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:54,252 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:54,263 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,268 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2022-11-18 18:32:54,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,269 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,270 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,273 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 18:32:54,273 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,283 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,283 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,283 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,283 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,286 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:54,286 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:54,298 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:54,307 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2022-11-18 18:32:54,307 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,307 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,309 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,320 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-18 18:32:54,321 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:54,336 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:54,336 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:54,336 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:54,336 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:54,355 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:54,356 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:54,374 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 18:32:54,420 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-18 18:32:54,420 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-18 18:32:54,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:54,422 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:54,425 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:54,444 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 18:32:54,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-18 18:32:54,463 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 18:32:54,464 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 18:32:54,464 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2022-11-18 18:32:54,471 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:54,482 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-18 18:32:54,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:54,529 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 18:32:54,530 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:54,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:54,553 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:32:54,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:54,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:54,621 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 18:32:54,622 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:54,665 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-18 18:32:54,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 18:32:54,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:54,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-18 18:32:54,678 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-18 18:32:54,679 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:54,679 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-18 18:32:54,679 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:54,679 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-18 18:32:54,679 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:54,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-18 18:32:54,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:54,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-18 18:32:54,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-18 18:32:54,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 18:32:54,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-18 18:32:54,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:54,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:32:54,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-18 18:32:54,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-18 18:32:54,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:54,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-18 18:32:54,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:32:54,714 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:32:54,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 18:32:54,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-18 18:32:54,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:54,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:54,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:54,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:54,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:54,716 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-18 18:32:54,716 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 118#L378-2 [2022-11-18 18:32:54,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,717 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-18 18:32:54,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:54,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354680153] [2022-11-18 18:32:54,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:54,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:54,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:54,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:54,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:54,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354680153] [2022-11-18 18:32:54,800 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354680153] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:32:54,801 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:32:54,801 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 18:32:54,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616553343] [2022-11-18 18:32:54,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:32:54,803 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:54,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,804 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-18 18:32:54,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:54,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459304803] [2022-11-18 18:32:54,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:54,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:54,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,810 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:54,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,815 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:54,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:54,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:32:54,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:32:54,870 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:54,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:54,897 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-18 18:32:54,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-18 18:32:54,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:54,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-18 18:32:54,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-18 18:32:54,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 18:32:54,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-18 18:32:54,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:54,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-18 18:32:54,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-18 18:32:54,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-18 18:32:54,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:54,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-18 18:32:54,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 18:32:54,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 18:32:54,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 18:32:54,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 18:32:54,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-18 18:32:54,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:54,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:54,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:54,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:54,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:54,904 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-18 18:32:54,905 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 151#L378-2 [2022-11-18 18:32:54,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-18 18:32:54,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:54,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140891311] [2022-11-18 18:32:54,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:54,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:54,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,934 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:54,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:54,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,959 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-18 18:32:54,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:54,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498170969] [2022-11-18 18:32:54,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:54,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:54,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,964 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:54,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:54,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:54,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:54,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-18 18:32:54,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:54,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20486040] [2022-11-18 18:32:54,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:54,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:55,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:55,088 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:55,445 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:55,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:55,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20486040] [2022-11-18 18:32:55,446 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20486040] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:55,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [570572865] [2022-11-18 18:32:55,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:55,447 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:55,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:55,459 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:55,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-18 18:32:55,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:55,519 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 18:32:55,521 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:55,567 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-18 18:32:55,633 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:32:55,648 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:55,648 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:55,741 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:32:55,750 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-18 18:32:55,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:55,771 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [570572865] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:55,772 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:55,772 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-18 18:32:55,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025376524] [2022-11-18 18:32:55,777 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:55,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:55,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-18 18:32:55,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2022-11-18 18:32:55,834 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:55,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:55,991 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2022-11-18 18:32:55,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2022-11-18 18:32:55,997 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:55,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2022-11-18 18:32:55,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-18 18:32:55,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-18 18:32:55,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2022-11-18 18:32:56,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:56,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2022-11-18 18:32:56,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2022-11-18 18:32:56,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2022-11-18 18:32:56,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:56,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2022-11-18 18:32:56,008 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-18 18:32:56,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:32:56,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-18 18:32:56,010 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 18:32:56,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2022-11-18 18:32:56,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:56,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:56,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:56,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:56,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:56,015 INFO L748 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 277#L367 assume !(main_~length~0#1 < 1); 271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 278#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 279#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 280#L370-4 main_~j~0#1 := 0; 284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 275#L378-2 [2022-11-18 18:32:56,016 INFO L750 eck$LassoCheckResult]: Loop: 275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 282#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 275#L378-2 [2022-11-18 18:32:56,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-18 18:32:56,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497358814] [2022-11-18 18:32:56,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,046 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:56,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:56,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,076 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-18 18:32:56,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365840927] [2022-11-18 18:32:56,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,080 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:56,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:56,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,084 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2022-11-18 18:32:56,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959182069] [2022-11-18 18:32:56,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:56,214 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:56,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:56,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959182069] [2022-11-18 18:32:56,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959182069] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:56,215 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [126489133] [2022-11-18 18:32:56,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:56,215 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:56,217 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:56,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-18 18:32:56,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:56,281 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 18:32:56,282 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:56,343 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:56,343 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:56,400 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:56,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [126489133] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:56,401 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:56,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-18 18:32:56,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024702239] [2022-11-18 18:32:56,401 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:56,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:56,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-18 18:32:56,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-18 18:32:56,453 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:56,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:56,577 INFO L93 Difference]: Finished difference Result 43 states and 57 transitions. [2022-11-18 18:32:56,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2022-11-18 18:32:56,581 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:56,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 39 states and 51 transitions. [2022-11-18 18:32:56,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 18:32:56,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 18:32:56,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-18 18:32:56,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:56,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-18 18:32:56,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-18 18:32:56,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-18 18:32:56,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:56,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2022-11-18 18:32:56,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-18 18:32:56,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:32:56,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-18 18:32:56,595 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 18:32:56,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2022-11-18 18:32:56,595 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:56,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:56,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:56,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:56,597 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:56,597 INFO L748 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 444#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 445#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 461#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 457#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 458#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 440#L370-4 main_~j~0#1 := 0; 441#L378-2 [2022-11-18 18:32:56,597 INFO L750 eck$LassoCheckResult]: Loop: 441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 451#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 441#L378-2 [2022-11-18 18:32:56,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-18 18:32:56,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301182050] [2022-11-18 18:32:56,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:56,666 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:56,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:56,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301182050] [2022-11-18 18:32:56,667 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301182050] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:56,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [647216720] [2022-11-18 18:32:56,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,667 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:56,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:56,671 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:56,691 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-18 18:32:56,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:56,729 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:32:56,730 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:56,766 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:56,767 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 18:32:56,767 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [647216720] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:32:56,767 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-18 18:32:56,767 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-18 18:32:56,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121471018] [2022-11-18 18:32:56,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:32:56,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:56,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,768 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-18 18:32:56,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067021085] [2022-11-18 18:32:56,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,772 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:56,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,775 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:56,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:56,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:32:56,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:32:56,825 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:56,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:56,850 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2022-11-18 18:32:56,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2022-11-18 18:32:56,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:56,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2022-11-18 18:32:56,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 18:32:56,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-18 18:32:56,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2022-11-18 18:32:56,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:56,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:32:56,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2022-11-18 18:32:56,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-18 18:32:56,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:56,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-11-18 18:32:56,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:32:56,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:32:56,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:32:56,855 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 18:32:56,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2022-11-18 18:32:56,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:56,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:56,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:56,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:56,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:56,856 INFO L748 eck$LassoCheckResult]: Stem: 542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 551#L367 assume !(main_~length~0#1 < 1); 544#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 545#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 552#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 553#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 558#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 557#L370-4 main_~j~0#1 := 0; 550#L378-2 [2022-11-18 18:32:56,857 INFO L750 eck$LassoCheckResult]: Loop: 550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 556#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 550#L378-2 [2022-11-18 18:32:56,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2022-11-18 18:32:56,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110448033] [2022-11-18 18:32:56,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,879 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:56,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:56,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,898 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-18 18:32:56,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445505859] [2022-11-18 18:32:56,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,904 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:56,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:56,908 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:56,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:56,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2022-11-18 18:32:56,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:56,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142514853] [2022-11-18 18:32:56,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:56,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:56,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:57,307 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:57,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:57,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142514853] [2022-11-18 18:32:57,311 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142514853] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:57,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1762672146] [2022-11-18 18:32:57,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:57,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:57,314 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:57,320 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:57,322 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-18 18:32:57,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:57,381 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-18 18:32:57,385 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:57,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:32:57,477 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:32:57,479 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:32:57,506 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:32:57,506 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:32:57,546 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:32:57,556 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:57,556 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:57,724 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2022-11-18 18:32:57,729 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 62 [2022-11-18 18:32:57,772 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:57,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1762672146] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:57,773 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:57,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 18:32:57,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645216342] [2022-11-18 18:32:57,773 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:57,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:57,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 18:32:57,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-18 18:32:57,825 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:57,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:57,955 INFO L93 Difference]: Finished difference Result 39 states and 51 transitions. [2022-11-18 18:32:57,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 51 transitions. [2022-11-18 18:32:57,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:57,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 51 transitions. [2022-11-18 18:32:57,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:32:57,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:32:57,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-18 18:32:57,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:57,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-18 18:32:57,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-18 18:32:57,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-11-18 18:32:57,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.3703703703703705) internal successors, (37), 26 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:57,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-11-18 18:32:57,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-18 18:32:57,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:32:57,961 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-18 18:32:57,961 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 18:32:57,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 37 transitions. [2022-11-18 18:32:57,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:57,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:57,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:57,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:57,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:57,963 INFO L748 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 723#L367 assume !(main_~length~0#1 < 1); 716#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 717#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 724#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 726#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 739#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 721#L370-4 main_~j~0#1 := 0; 722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 720#L378-2 [2022-11-18 18:32:57,963 INFO L750 eck$LassoCheckResult]: Loop: 720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 733#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 720#L378-2 [2022-11-18 18:32:57,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:57,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-18 18:32:57,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:57,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488240870] [2022-11-18 18:32:57,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:57,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:57,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:57,975 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:57,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:57,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:57,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:57,985 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-18 18:32:57,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:57,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124073595] [2022-11-18 18:32:57,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:57,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:57,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:57,988 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:57,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:57,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:57,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:57,991 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2022-11-18 18:32:57,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:57,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830420848] [2022-11-18 18:32:57,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:57,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:58,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:58,168 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:58,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:58,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830420848] [2022-11-18 18:32:58,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830420848] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:58,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [763849462] [2022-11-18 18:32:58,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:58,169 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:58,169 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:58,172 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:58,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-18 18:32:58,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:58,242 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-18 18:32:58,243 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:58,266 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:32:58,395 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-18 18:32:58,396 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-18 18:32:58,410 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:58,410 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:58,490 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:32:58,494 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2022-11-18 18:32:58,517 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:58,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [763849462] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:58,518 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:58,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2022-11-18 18:32:58,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797736575] [2022-11-18 18:32:58,518 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:58,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:58,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-18 18:32:58,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2022-11-18 18:32:58,572 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. cyclomatic complexity: 13 Second operand has 16 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:58,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:58,697 INFO L93 Difference]: Finished difference Result 36 states and 48 transitions. [2022-11-18 18:32:58,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 48 transitions. [2022-11-18 18:32:58,698 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:58,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 48 transitions. [2022-11-18 18:32:58,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 18:32:58,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 18:32:58,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 48 transitions. [2022-11-18 18:32:58,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:58,699 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36 states and 48 transitions. [2022-11-18 18:32:58,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 48 transitions. [2022-11-18 18:32:58,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 32. [2022-11-18 18:32:58,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:58,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2022-11-18 18:32:58,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-18 18:32:58,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 18:32:58,703 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-18 18:32:58,703 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 18:32:58,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2022-11-18 18:32:58,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:58,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:58,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:58,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:58,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:58,704 INFO L748 eck$LassoCheckResult]: Stem: 898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 906#L367 assume !(main_~length~0#1 < 1); 900#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 901#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 915#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 916#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 905#L370-4 main_~j~0#1 := 0; 904#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 910#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 919#L378-2 [2022-11-18 18:32:58,704 INFO L750 eck$LassoCheckResult]: Loop: 919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 918#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 919#L378-2 [2022-11-18 18:32:58,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:58,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2022-11-18 18:32:58,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:58,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056741095] [2022-11-18 18:32:58,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:58,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:58,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:58,721 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:58,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:58,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:58,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:58,740 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-18 18:32:58,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:58,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229068823] [2022-11-18 18:32:58,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:58,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:58,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:58,744 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:58,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:58,746 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:58,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:58,746 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2022-11-18 18:32:58,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:58,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564755806] [2022-11-18 18:32:58,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:58,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:58,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:58,987 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:58,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:58,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564755806] [2022-11-18 18:32:58,987 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564755806] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:58,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1305177607] [2022-11-18 18:32:58,988 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:32:58,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:58,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:58,992 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:59,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-18 18:32:59,064 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:32:59,064 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:32:59,065 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:32:59,066 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:59,132 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:32:59,235 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:32:59,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:59,237 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:59,308 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:32:59,310 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:32:59,328 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:59,328 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1305177607] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:59,328 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:59,329 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 18:32:59,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961860823] [2022-11-18 18:32:59,329 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:59,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:59,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 18:32:59,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2022-11-18 18:32:59,378 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 14 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:59,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:59,598 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2022-11-18 18:32:59,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 62 transitions. [2022-11-18 18:32:59,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:32:59,600 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 62 transitions. [2022-11-18 18:32:59,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-18 18:32:59,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-18 18:32:59,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 62 transitions. [2022-11-18 18:32:59,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:59,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 62 transitions. [2022-11-18 18:32:59,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 62 transitions. [2022-11-18 18:32:59,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 38. [2022-11-18 18:32:59,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.368421052631579) internal successors, (52), 37 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:59,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 52 transitions. [2022-11-18 18:32:59,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-18 18:32:59,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:32:59,607 INFO L428 stractBuchiCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-18 18:32:59,608 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-18 18:32:59,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 52 transitions. [2022-11-18 18:32:59,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:32:59,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:59,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:59,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:32:59,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:59,611 INFO L748 eck$LassoCheckResult]: Stem: 1105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1113#L367 assume !(main_~length~0#1 < 1); 1107#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1108#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1114#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1116#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1133#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1134#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1130#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1127#L370-4 main_~j~0#1 := 0; 1125#L378-2 [2022-11-18 18:32:59,611 INFO L750 eck$LassoCheckResult]: Loop: 1125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1126#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1125#L378-2 [2022-11-18 18:32:59,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:59,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1518446116, now seen corresponding path program 2 times [2022-11-18 18:32:59,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:59,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325298364] [2022-11-18 18:32:59,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:59,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:59,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:59,622 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:59,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:59,630 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:59,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:59,631 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-18 18:32:59,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:59,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94603141] [2022-11-18 18:32:59,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:59,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:59,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:59,634 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:59,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:59,637 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:59,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:59,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164511, now seen corresponding path program 2 times [2022-11-18 18:32:59,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:59,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855980025] [2022-11-18 18:32:59,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:59,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:59,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:00,162 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:00,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:00,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855980025] [2022-11-18 18:33:00,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855980025] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:00,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1751710180] [2022-11-18 18:33:00,163 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:33:00,163 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:00,164 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:00,167 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:00,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-18 18:33:00,240 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:33:00,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:00,241 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:33:00,245 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:00,287 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:00,382 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:00,383 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:00,398 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:00,399 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:00,433 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:00,434 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:00,448 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:00,449 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:00,507 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:33:00,509 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:33:00,509 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 10 [2022-11-18 18:33:00,522 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:00,522 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:01,076 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 25 [2022-11-18 18:33:01,085 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 74 [2022-11-18 18:33:01,148 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:33:01,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1751710180] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:01,148 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:01,149 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2022-11-18 18:33:01,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230061643] [2022-11-18 18:33:01,151 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:01,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:01,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-18 18:33:01,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=558, Unknown=0, NotChecked=0, Total=702 [2022-11-18 18:33:01,198 INFO L87 Difference]: Start difference. First operand 38 states and 52 transitions. cyclomatic complexity: 18 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:01,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:01,374 INFO L93 Difference]: Finished difference Result 43 states and 56 transitions. [2022-11-18 18:33:01,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 56 transitions. [2022-11-18 18:33:01,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:01,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 56 transitions. [2022-11-18 18:33:01,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:33:01,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:33:01,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 56 transitions. [2022-11-18 18:33:01,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:01,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 56 transitions. [2022-11-18 18:33:01,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 56 transitions. [2022-11-18 18:33:01,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 24. [2022-11-18 18:33:01,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:01,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2022-11-18 18:33:01,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-18 18:33:01,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:33:01,381 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-18 18:33:01,381 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-18 18:33:01,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2022-11-18 18:33:01,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:01,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:01,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:01,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:01,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:01,382 INFO L748 eck$LassoCheckResult]: Stem: 1329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1335#L367 assume !(main_~length~0#1 < 1); 1327#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1328#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1336#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1338#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1341#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1342#L370-4 main_~j~0#1 := 0; 1347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1334#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1340#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1345#L378-2 [2022-11-18 18:33:01,382 INFO L750 eck$LassoCheckResult]: Loop: 1345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1344#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1345#L378-2 [2022-11-18 18:33:01,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,383 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2022-11-18 18:33:01,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049491605] [2022-11-18 18:33:01,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,395 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:01,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,403 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:01,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,403 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-18 18:33:01,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066844611] [2022-11-18 18:33:01,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,406 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:01,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:01,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,409 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2022-11-18 18:33:01,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973120833] [2022-11-18 18:33:01,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:01,517 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:01,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:01,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973120833] [2022-11-18 18:33:01,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973120833] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:01,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1948590756] [2022-11-18 18:33:01,518 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:33:01,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:01,518 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:01,523 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:01,525 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-18 18:33:01,607 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-18 18:33:01,608 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:01,609 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 18:33:01,614 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:01,684 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:01,684 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:01,737 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:01,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1948590756] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:01,737 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:01,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-18 18:33:01,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473354812] [2022-11-18 18:33:01,738 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:01,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:01,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 18:33:01,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-18 18:33:01,784 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:01,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:01,910 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2022-11-18 18:33:01,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2022-11-18 18:33:01,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:01,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2022-11-18 18:33:01,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-18 18:33:01,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-18 18:33:01,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-18 18:33:01,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:01,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-18 18:33:01,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-18 18:33:01,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-11-18 18:33:01,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:01,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2022-11-18 18:33:01,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-18 18:33:01,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 18:33:01,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-18 18:33:01,915 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-18 18:33:01,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2022-11-18 18:33:01,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:01,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:01,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:01,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:01,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:01,917 INFO L748 eck$LassoCheckResult]: Stem: 1521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1530#L367 assume !(main_~length~0#1 < 1); 1523#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1524#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1531#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1534#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1533#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1541#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1540#L370-4 main_~j~0#1 := 0; 1529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1539#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1538#L378-2 [2022-11-18 18:33:01,917 INFO L750 eck$LassoCheckResult]: Loop: 1538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1537#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1538#L378-2 [2022-11-18 18:33:01,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 2 times [2022-11-18 18:33:01,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377895714] [2022-11-18 18:33:01,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:01,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,937 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:01,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,938 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-18 18:33:01,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59145152] [2022-11-18 18:33:01,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,941 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:01,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:01,944 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:01,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:01,944 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 2 times [2022-11-18 18:33:01,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:01,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071778405] [2022-11-18 18:33:01,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:01,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:01,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:02,191 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:02,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:02,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071778405] [2022-11-18 18:33:02,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071778405] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:02,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2124144603] [2022-11-18 18:33:02,192 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:33:02,192 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:02,192 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:02,196 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:02,229 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-18 18:33:02,283 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:33:02,283 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:02,284 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:33:02,286 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:02,349 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:02,436 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:02,438 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:02,452 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:02,452 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:02,572 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:02,574 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:02,574 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:02,725 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:02,728 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:02,749 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:02,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2124144603] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:02,750 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:02,750 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-18 18:33:02,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391254546] [2022-11-18 18:33:02,750 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:02,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:02,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 18:33:02,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-18 18:33:02,801 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:03,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:03,032 INFO L93 Difference]: Finished difference Result 30 states and 37 transitions. [2022-11-18 18:33:03,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2022-11-18 18:33:03,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:03,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 37 transitions. [2022-11-18 18:33:03,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:33:03,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:33:03,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2022-11-18 18:33:03,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:03,034 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 37 transitions. [2022-11-18 18:33:03,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2022-11-18 18:33:03,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 22. [2022-11-18 18:33:03,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:03,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2022-11-18 18:33:03,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-18 18:33:03,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 18:33:03,037 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-18 18:33:03,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-18 18:33:03,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2022-11-18 18:33:03,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:03,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:03,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:03,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:03,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:03,038 INFO L748 eck$LassoCheckResult]: Stem: 1727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1736#L367 assume !(main_~length~0#1 < 1); 1729#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1730#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1737#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1744#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1745#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1739#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1742#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1732#L370-4 main_~j~0#1 := 0; 1733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1734#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1741#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1748#L378-2 [2022-11-18 18:33:03,039 INFO L750 eck$LassoCheckResult]: Loop: 1748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1747#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1748#L378-2 [2022-11-18 18:33:03,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 4 times [2022-11-18 18:33:03,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212996886] [2022-11-18 18:33:03,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:03,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:03,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,064 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-18 18:33:03,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554803476] [2022-11-18 18:33:03,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,067 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:03,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:03,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,070 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2022-11-18 18:33:03,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870287047] [2022-11-18 18:33:03,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:03,320 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:03,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:03,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870287047] [2022-11-18 18:33:03,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870287047] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:03,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2084263890] [2022-11-18 18:33:03,320 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:33:03,320 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:03,320 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:03,323 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:03,327 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-18 18:33:03,394 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:33:03,394 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:03,395 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:33:03,397 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:03,424 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:03,596 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:33:03,598 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:03,599 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:03,681 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:33:03,684 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:33:03,710 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:03,710 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2084263890] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:03,711 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:03,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-18 18:33:03,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717658746] [2022-11-18 18:33:03,711 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:03,758 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:03,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 18:33:03,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-18 18:33:03,759 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:03,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:03,915 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2022-11-18 18:33:03,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 42 transitions. [2022-11-18 18:33:03,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:03,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 42 transitions. [2022-11-18 18:33:03,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:33:03,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:33:03,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2022-11-18 18:33:03,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:03,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 42 transitions. [2022-11-18 18:33:03,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2022-11-18 18:33:03,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 28. [2022-11-18 18:33:03,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:03,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2022-11-18 18:33:03,920 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-18 18:33:03,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:33:03,925 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-18 18:33:03,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-18 18:33:03,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2022-11-18 18:33:03,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:03,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:03,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:03,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:03,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:03,929 INFO L748 eck$LassoCheckResult]: Stem: 1933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1941#L367 assume !(main_~length~0#1 < 1); 1935#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1936#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1952#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1944#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1949#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1950#L370-4 main_~j~0#1 := 0; 1958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1938#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1939#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1945#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1956#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1955#L378-2 [2022-11-18 18:33:03,929 INFO L750 eck$LassoCheckResult]: Loop: 1955#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1954#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1955#L378-2 [2022-11-18 18:33:03,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,930 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 5 times [2022-11-18 18:33:03,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789904761] [2022-11-18 18:33:03,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,944 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:03,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:03,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,956 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-18 18:33:03,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724505380] [2022-11-18 18:33:03,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,962 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:03,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:03,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:03,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:03,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2022-11-18 18:33:03,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:03,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056503609] [2022-11-18 18:33:03,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:03,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:03,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:04,137 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:04,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:04,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056503609] [2022-11-18 18:33:04,137 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056503609] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:04,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [401169681] [2022-11-18 18:33:04,138 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:33:04,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:04,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:04,144 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:04,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-18 18:33:04,230 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-18 18:33:04,230 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:04,231 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 18:33:04,232 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:04,336 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:04,337 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:04,423 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:04,423 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [401169681] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:04,423 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:04,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-18 18:33:04,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039812161] [2022-11-18 18:33:04,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:04,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:04,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 18:33:04,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-18 18:33:04,484 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 9 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:04,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:04,632 INFO L93 Difference]: Finished difference Result 35 states and 42 transitions. [2022-11-18 18:33:04,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 42 transitions. [2022-11-18 18:33:04,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:04,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 27 states and 34 transitions. [2022-11-18 18:33:04,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:04,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:04,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2022-11-18 18:33:04,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:04,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 34 transitions. [2022-11-18 18:33:04,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2022-11-18 18:33:04,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2022-11-18 18:33:04,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.24) internal successors, (31), 24 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:04,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 31 transitions. [2022-11-18 18:33:04,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-18 18:33:04,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 18:33:04,638 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-18 18:33:04,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-18 18:33:04,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 31 transitions. [2022-11-18 18:33:04,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:04,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:04,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:04,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:04,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:04,639 INFO L748 eck$LassoCheckResult]: Stem: 2166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2175#L367 assume !(main_~length~0#1 < 1); 2168#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2169#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2176#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2178#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2187#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2183#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2182#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2171#L370-4 main_~j~0#1 := 0; 2172#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2173#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2180#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2190#L378-2 [2022-11-18 18:33:04,639 INFO L750 eck$LassoCheckResult]: Loop: 2190#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2189#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2190#L378-2 [2022-11-18 18:33:04,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:04,640 INFO L85 PathProgramCache]: Analyzing trace with hash 666851296, now seen corresponding path program 6 times [2022-11-18 18:33:04,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:04,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855404790] [2022-11-18 18:33:04,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:04,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:04,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:04,670 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:04,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:04,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:04,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:04,686 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-18 18:33:04,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:04,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006200512] [2022-11-18 18:33:04,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:04,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:04,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:04,690 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:04,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:04,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:04,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:04,694 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 6 times [2022-11-18 18:33:04,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:04,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872506410] [2022-11-18 18:33:04,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:04,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:04,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:05,077 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:05,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:05,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872506410] [2022-11-18 18:33:05,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872506410] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:05,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1184244169] [2022-11-18 18:33:05,078 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:33:05,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:05,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:05,084 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:05,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-18 18:33:05,174 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-18 18:33:05,174 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:05,175 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-18 18:33:05,177 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:05,276 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:05,375 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:05,376 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:05,522 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:05,525 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:05,525 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:05,680 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:05,687 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:05,728 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:05,728 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1184244169] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:05,729 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:05,729 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2022-11-18 18:33:05,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230294075] [2022-11-18 18:33:05,729 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:05,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:05,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-18 18:33:05,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2022-11-18 18:33:05,778 INFO L87 Difference]: Start difference. First operand 25 states and 31 transitions. cyclomatic complexity: 8 Second operand has 27 states, 26 states have (on average 2.0) internal successors, (52), 27 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:06,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:06,115 INFO L93 Difference]: Finished difference Result 27 states and 33 transitions. [2022-11-18 18:33:06,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 33 transitions. [2022-11-18 18:33:06,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:06,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 33 transitions. [2022-11-18 18:33:06,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-18 18:33:06,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-18 18:33:06,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 33 transitions. [2022-11-18 18:33:06,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:06,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:33:06,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 33 transitions. [2022-11-18 18:33:06,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-11-18 18:33:06,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:06,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2022-11-18 18:33:06,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:33:06,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:33:06,136 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:33:06,137 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-18 18:33:06,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2022-11-18 18:33:06,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:06,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:06,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:06,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:06,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:06,143 INFO L748 eck$LassoCheckResult]: Stem: 2406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2413#L367 assume !(main_~length~0#1 < 1); 2404#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2405#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2414#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2415#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2416#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2425#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2421#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2422#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2420#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2409#L370-4 main_~j~0#1 := 0; 2410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2411#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2418#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2429#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2428#L378-2 [2022-11-18 18:33:06,144 INFO L750 eck$LassoCheckResult]: Loop: 2428#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2427#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2428#L378-2 [2022-11-18 18:33:06,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:06,144 INFO L85 PathProgramCache]: Analyzing trace with hash 893969701, now seen corresponding path program 7 times [2022-11-18 18:33:06,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:06,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995717299] [2022-11-18 18:33:06,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:06,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:06,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:06,158 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:06,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:06,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:06,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:06,173 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-18 18:33:06,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:06,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405497189] [2022-11-18 18:33:06,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:06,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:06,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:06,180 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:06,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:06,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:06,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:06,183 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 7 times [2022-11-18 18:33:06,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:06,184 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693050456] [2022-11-18 18:33:06,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:06,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:06,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:06,462 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:06,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:06,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693050456] [2022-11-18 18:33:06,463 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693050456] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:06,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1677446771] [2022-11-18 18:33:06,463 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:33:06,463 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:06,463 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:06,468 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:06,475 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-18 18:33:06,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:06,554 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 18:33:06,556 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:06,590 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:06,748 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:33:06,751 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:06,751 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:06,862 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:33:06,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:33:06,905 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:06,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1677446771] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:06,906 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:06,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 19 [2022-11-18 18:33:06,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352014858] [2022-11-18 18:33:06,906 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:06,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:06,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 18:33:06,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2022-11-18 18:33:06,955 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 8 Second operand has 20 states, 19 states have (on average 2.1578947368421053) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:07,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:07,203 INFO L93 Difference]: Finished difference Result 43 states and 53 transitions. [2022-11-18 18:33:07,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 53 transitions. [2022-11-18 18:33:07,204 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:07,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 53 transitions. [2022-11-18 18:33:07,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2022-11-18 18:33:07,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2022-11-18 18:33:07,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 53 transitions. [2022-11-18 18:33:07,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:07,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 53 transitions. [2022-11-18 18:33:07,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 53 transitions. [2022-11-18 18:33:07,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 34. [2022-11-18 18:33:07,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:07,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-18 18:33:07,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 18:33:07,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 18:33:07,208 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 18:33:07,208 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-18 18:33:07,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-18 18:33:07,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:07,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:07,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:07,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:07,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:07,210 INFO L748 eck$LassoCheckResult]: Stem: 2657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2665#L367 assume !(main_~length~0#1 < 1); 2659#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2660#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2666#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2668#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2676#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2672#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2673#L370-4 main_~j~0#1 := 0; 2687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2685#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2684#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2683#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2682#L378-2 [2022-11-18 18:33:07,210 INFO L750 eck$LassoCheckResult]: Loop: 2682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2681#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2682#L378-2 [2022-11-18 18:33:07,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:07,210 INFO L85 PathProgramCache]: Analyzing trace with hash 111424810, now seen corresponding path program 8 times [2022-11-18 18:33:07,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:07,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977095764] [2022-11-18 18:33:07,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:07,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:07,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:07,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:07,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:07,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:07,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:07,237 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-18 18:33:07,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:07,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124102896] [2022-11-18 18:33:07,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:07,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:07,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:07,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:07,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:07,243 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:07,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:07,244 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 8 times [2022-11-18 18:33:07,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:07,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652809084] [2022-11-18 18:33:07,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:07,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:07,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:07,448 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:07,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:07,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652809084] [2022-11-18 18:33:07,448 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652809084] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:07,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [105630885] [2022-11-18 18:33:07,449 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:33:07,449 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:07,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:07,456 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:07,467 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-18 18:33:07,550 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:33:07,550 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:07,551 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 18:33:07,552 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:07,705 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:07,705 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:07,815 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:07,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [105630885] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:07,815 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:07,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-18 18:33:07,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693563907] [2022-11-18 18:33:07,815 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:07,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:07,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 18:33:07,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-18 18:33:07,863 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 12 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:08,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:08,030 INFO L93 Difference]: Finished difference Result 49 states and 59 transitions. [2022-11-18 18:33:08,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 59 transitions. [2022-11-18 18:33:08,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:08,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 39 states and 49 transitions. [2022-11-18 18:33:08,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:33:08,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:33:08,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2022-11-18 18:33:08,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:08,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-18 18:33:08,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2022-11-18 18:33:08,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 36. [2022-11-18 18:33:08,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.25) internal successors, (45), 35 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:08,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 45 transitions. [2022-11-18 18:33:08,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-18 18:33:08,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:33:08,038 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-18 18:33:08,038 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-18 18:33:08,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 45 transitions. [2022-11-18 18:33:08,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:08,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:08,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:08,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:08,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:08,040 INFO L748 eck$LassoCheckResult]: Stem: 2945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2953#L367 assume !(main_~length~0#1 < 1); 2947#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2948#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2954#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2970#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2956#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2969#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2966#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2963#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2964#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2960#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2952#L370-4 main_~j~0#1 := 0; 2951#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2958#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2975#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2973#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2972#L378-2 [2022-11-18 18:33:08,040 INFO L750 eck$LassoCheckResult]: Loop: 2972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2971#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2972#L378-2 [2022-11-18 18:33:08,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:08,041 INFO L85 PathProgramCache]: Analyzing trace with hash -188031059, now seen corresponding path program 3 times [2022-11-18 18:33:08,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:08,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394317143] [2022-11-18 18:33:08,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:08,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:08,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:08,067 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:08,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:08,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:08,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:08,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-18 18:33:08,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:08,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647902090] [2022-11-18 18:33:08,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:08,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:08,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:08,090 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:08,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:08,092 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:08,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:08,093 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 3 times [2022-11-18 18:33:08,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:08,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294074434] [2022-11-18 18:33:08,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:08,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:08,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:08,522 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:08,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:08,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294074434] [2022-11-18 18:33:08,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294074434] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:08,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2095471729] [2022-11-18 18:33:08,523 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:33:08,523 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:08,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:08,528 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:08,533 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-18 18:33:08,658 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 18:33:08,658 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:08,660 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:33:08,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:08,746 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:08,864 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:33:08,864 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-18 18:33:08,949 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:33:08,950 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-18 18:33:09,609 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 18:33:09,609 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-18 18:33:09,630 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:09,630 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:10,407 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:33:10,411 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:33:10,488 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 39 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:33:10,488 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2095471729] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:10,488 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:10,488 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 14] total 37 [2022-11-18 18:33:10,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909705733] [2022-11-18 18:33:10,489 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:10,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:10,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:33:10,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1216, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:33:10,547 INFO L87 Difference]: Start difference. First operand 36 states and 45 transitions. cyclomatic complexity: 12 Second operand has 38 states, 37 states have (on average 1.864864864864865) internal successors, (69), 38 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:12,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:12,106 INFO L93 Difference]: Finished difference Result 73 states and 87 transitions. [2022-11-18 18:33:12,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 87 transitions. [2022-11-18 18:33:12,107 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 18:33:12,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 87 transitions. [2022-11-18 18:33:12,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-18 18:33:12,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-18 18:33:12,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 87 transitions. [2022-11-18 18:33:12,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:12,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 87 transitions. [2022-11-18 18:33:12,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 87 transitions. [2022-11-18 18:33:12,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 43. [2022-11-18 18:33:12,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:12,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-18 18:33:12,117 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:33:12,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-18 18:33:12,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:33:12,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-18 18:33:12,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-18 18:33:12,119 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:12,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:12,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:12,120 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:12,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:12,121 INFO L748 eck$LassoCheckResult]: Stem: 3321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3327#L367 assume !(main_~length~0#1 < 1); 3319#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3320#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3337#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3343#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3330#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3331#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3335#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3324#L370-4 main_~j~0#1 := 0; 3325#L378-2 [2022-11-18 18:33:12,121 INFO L750 eck$LassoCheckResult]: Loop: 3325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3326#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3325#L378-2 [2022-11-18 18:33:12,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:12,121 INFO L85 PathProgramCache]: Analyzing trace with hash 438748702, now seen corresponding path program 3 times [2022-11-18 18:33:12,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:12,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2984164] [2022-11-18 18:33:12,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:12,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:12,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,152 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:12,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,165 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:12,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:12,166 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-18 18:33:12,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:12,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149400356] [2022-11-18 18:33:12,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:12,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:12,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:12,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:12,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:12,172 INFO L85 PathProgramCache]: Analyzing trace with hash 730708963, now seen corresponding path program 4 times [2022-11-18 18:33:12,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:12,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989674271] [2022-11-18 18:33:12,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:12,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:12,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,185 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:12,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:12,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:13,999 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 18:33:13,999 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 18:33:13,999 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 18:33:13,999 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 18:33:13,999 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 18:33:13,999 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:13,999 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 18:33:13,999 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 18:33:13,999 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration18_Lasso [2022-11-18 18:33:14,000 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 18:33:14,000 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 18:33:14,002 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,011 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,014 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,017 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,019 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,023 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,373 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,375 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,377 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,378 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,380 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,382 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:33:14,712 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 18:33:14,712 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 18:33:14,712 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,713 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,719 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,729 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:14,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-18 18:33:14,742 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:14,742 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:14,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:14,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:14,744 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:14,744 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:14,757 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:14,767 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:14,768 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,768 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,769 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,787 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:14,800 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:14,800 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:33:14,800 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:14,800 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:14,800 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:14,801 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:33:14,801 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:33:14,803 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-18 18:33:14,824 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:14,828 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:14,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,829 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,830 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,843 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-18 18:33:14,844 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:14,857 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:14,858 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:14,858 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:14,858 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:14,860 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:14,860 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:14,870 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:14,883 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:14,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,883 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,884 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,894 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:14,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-18 18:33:14,907 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:14,907 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:33:14,907 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:14,907 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:14,907 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:14,908 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:33:14,908 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:33:14,924 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:14,933 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:14,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,935 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,938 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:14,950 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:14,951 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:33:14,951 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:14,951 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:14,951 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:14,952 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:33:14,952 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:33:14,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-18 18:33:14,972 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:14,981 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:14,982 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:14,982 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:14,983 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:14,988 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,000 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,003 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,003 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,004 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-18 18:33:15,032 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,041 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,041 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,042 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,043 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,046 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,059 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,059 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,059 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,059 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,068 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,068 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-18 18:33:15,079 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,083 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,084 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,088 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,093 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-11-18 18:33:15,100 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,100 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,101 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,101 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,104 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,104 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,128 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,138 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,139 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,144 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,156 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,157 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,157 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,157 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,159 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,159 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,160 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-11-18 18:33:15,176 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,185 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,187 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,191 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-11-18 18:33:15,203 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,204 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,204 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,204 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,206 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,206 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,224 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,234 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,236 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,240 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,252 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,252 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,252 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,252 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,255 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,256 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-11-18 18:33:15,266 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:33:15,270 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,272 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,275 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:33:15,288 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:33:15,288 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:33:15,288 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:33:15,288 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:33:15,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-11-18 18:33:15,295 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:33:15,295 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:33:15,320 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 18:33:15,387 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-11-18 18:33:15,387 INFO L444 ModelExtractionUtils]: 8 out of 25 variables were initially zero. Simplification set additionally 13 variables to zero. [2022-11-18 18:33:15,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:33:15,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:15,408 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:33:15,415 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 18:33:15,427 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2022-11-18 18:33:15,443 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 18:33:15,444 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 18:33:15,444 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2, ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1) = 1*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 - 1*ULTIMATE.start_main_~arr~0#1.offset - 2*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2022-11-18 18:33:15,447 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2022-11-18 18:33:15,475 INFO L156 tatePredicateManager]: 7 out of 8 supporting invariants were superfluous and have been removed [2022-11-18 18:33:15,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:15,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:15,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:33:15,536 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:15,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:15,619 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 18:33:15,619 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:15,653 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2022-11-18 18:33:15,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:15,677 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-18 18:33:15,678 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:15,723 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 53 states and 68 transitions. Complement of second has 6 states. [2022-11-18 18:33:15,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-18 18:33:15,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:15,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2022-11-18 18:33:15,726 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 2 letters. [2022-11-18 18:33:15,726 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:33:15,726 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 24 letters. Loop has 2 letters. [2022-11-18 18:33:15,726 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:33:15,727 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 4 letters. [2022-11-18 18:33:15,727 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:33:15,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 68 transitions. [2022-11-18 18:33:15,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:15,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 44 states and 56 transitions. [2022-11-18 18:33:15,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 18:33:15,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:15,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2022-11-18 18:33:15,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:15,729 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 56 transitions. [2022-11-18 18:33:15,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2022-11-18 18:33:15,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2022-11-18 18:33:15,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:15,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-18 18:33:15,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:33:15,731 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:33:15,731 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-18 18:33:15,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-18 18:33:15,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:15,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:15,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:15,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:15,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:15,733 INFO L748 eck$LassoCheckResult]: Stem: 3546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3557#L367 assume !(main_~length~0#1 < 1); 3548#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3549#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3558#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3559#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3560#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3586#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3583#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3579#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3574#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3573#L370-4 main_~j~0#1 := 0; 3572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3553#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3562#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3569#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3568#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3551#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-18 18:33:15,734 INFO L750 eck$LassoCheckResult]: Loop: 3552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3565#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-18 18:33:15,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:15,734 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 9 times [2022-11-18 18:33:15,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:15,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856625462] [2022-11-18 18:33:15,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:15,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:15,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:16,081 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:16,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:16,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856625462] [2022-11-18 18:33:16,081 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856625462] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:16,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [639735512] [2022-11-18 18:33:16,081 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:33:16,082 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:16,082 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:16,084 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:16,104 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-18 18:33:16,206 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 18:33:16,206 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:16,208 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-18 18:33:16,209 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:16,315 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:16,798 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:33:16,798 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:33:16,802 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:16,803 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:17,911 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:33:17,915 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:33:18,020 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:18,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [639735512] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:18,020 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:18,021 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2022-11-18 18:33:18,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725526728] [2022-11-18 18:33:18,021 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:18,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:18,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:18,021 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-18 18:33:18,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:18,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113455506] [2022-11-18 18:33:18,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:18,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:18,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:18,025 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:18,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:18,027 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:18,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:18,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-18 18:33:18,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=1287, Unknown=1, NotChecked=0, Total=1482 [2022-11-18 18:33:18,079 INFO L87 Difference]: Start difference. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 39 states, 38 states have (on average 1.9210526315789473) internal successors, (73), 39 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:18,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:18,947 INFO L93 Difference]: Finished difference Result 60 states and 74 transitions. [2022-11-18 18:33:18,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 74 transitions. [2022-11-18 18:33:18,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:18,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 47 states and 59 transitions. [2022-11-18 18:33:18,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:18,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:18,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-18 18:33:18,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:18,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:33:18,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-18 18:33:18,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-11-18 18:33:18,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.2666666666666666) internal successors, (57), 44 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:18,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 57 transitions. [2022-11-18 18:33:18,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-18 18:33:18,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-18 18:33:18,961 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-18 18:33:18,961 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-18 18:33:18,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 57 transitions. [2022-11-18 18:33:18,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:18,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:18,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:18,962 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:18,962 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:18,963 INFO L748 eck$LassoCheckResult]: Stem: 3925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3936#L367 assume !(main_~length~0#1 < 1); 3927#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3928#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3929#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3969#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3939#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3967#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3965#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3964#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3963#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3961#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3942#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3958#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3952#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3934#L370-4 main_~j~0#1 := 0; 3935#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3932#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3933#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3948#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3946#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3930#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-18 18:33:18,963 INFO L750 eck$LassoCheckResult]: Loop: 3931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3944#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-18 18:33:18,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:18,963 INFO L85 PathProgramCache]: Analyzing trace with hash 1236423398, now seen corresponding path program 4 times [2022-11-18 18:33:18,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:18,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315246019] [2022-11-18 18:33:18,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:18,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:18,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:19,589 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:19,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:19,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315246019] [2022-11-18 18:33:19,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315246019] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:19,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [914098411] [2022-11-18 18:33:19,590 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:33:19,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:19,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:19,592 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:19,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-18 18:33:19,697 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:33:19,697 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:19,699 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-18 18:33:19,701 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:19,734 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:19,810 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:33:19,810 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:19,828 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:33:19,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:19,872 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:33:19,872 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:19,976 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:33:19,979 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:19,979 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:20,204 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:20,207 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:20,252 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:33:20,252 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [914098411] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:20,252 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:20,252 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-18 18:33:20,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443298064] [2022-11-18 18:33:20,253 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:20,253 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:20,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:20,254 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-18 18:33:20,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:20,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478184269] [2022-11-18 18:33:20,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:20,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:20,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:20,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:20,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:20,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:20,309 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:20,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-18 18:33:20,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=478, Unknown=0, NotChecked=0, Total=552 [2022-11-18 18:33:20,310 INFO L87 Difference]: Start difference. First operand 45 states and 57 transitions. cyclomatic complexity: 17 Second operand has 24 states, 23 states have (on average 2.217391304347826) internal successors, (51), 24 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:20,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:20,688 INFO L93 Difference]: Finished difference Result 54 states and 66 transitions. [2022-11-18 18:33:20,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 66 transitions. [2022-11-18 18:33:20,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:20,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 65 transitions. [2022-11-18 18:33:20,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:20,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:20,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 65 transitions. [2022-11-18 18:33:20,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:20,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 65 transitions. [2022-11-18 18:33:20,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 65 transitions. [2022-11-18 18:33:20,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 40. [2022-11-18 18:33:20,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.25) internal successors, (50), 39 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:20,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2022-11-18 18:33:20,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-18 18:33:20,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 18:33:20,694 INFO L428 stractBuchiCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-18 18:33:20,695 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-18 18:33:20,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 50 transitions. [2022-11-18 18:33:20,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:20,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:20,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:20,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:20,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:20,696 INFO L748 eck$LassoCheckResult]: Stem: 4253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4264#L367 assume !(main_~length~0#1 < 1); 4255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4270#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4291#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4289#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4288#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4285#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4283#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4282#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4279#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4275#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4262#L370-4 main_~j~0#1 := 0; 4263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4268#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4260#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4258#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-18 18:33:20,696 INFO L750 eck$LassoCheckResult]: Loop: 4259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4274#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-18 18:33:20,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:20,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1503052245, now seen corresponding path program 5 times [2022-11-18 18:33:20,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:20,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303474230] [2022-11-18 18:33:20,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:20,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:20,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:21,155 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:21,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:21,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303474230] [2022-11-18 18:33:21,156 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303474230] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:21,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [311724018] [2022-11-18 18:33:21,156 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:33:21,156 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:21,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:21,160 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:21,180 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-18 18:33:21,290 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-18 18:33:21,290 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:21,291 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-18 18:33:21,293 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:21,467 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:21,541 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:21,542 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:21,861 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:33:21,864 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:33:21,864 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:33:21,890 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:21,890 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:22,435 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 26 [2022-11-18 18:33:22,439 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 86 [2022-11-18 18:33:22,522 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:22,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [311724018] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:22,523 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:22,523 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 16] total 40 [2022-11-18 18:33:22,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36220613] [2022-11-18 18:33:22,523 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:22,524 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:22,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:22,524 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-18 18:33:22,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:22,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808748593] [2022-11-18 18:33:22,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:22,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:22,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:22,528 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:22,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:22,530 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:22,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:22,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:33:22,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=1492, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:33:22,581 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. cyclomatic complexity: 14 Second operand has 41 states, 40 states have (on average 2.075) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:23,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:23,529 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2022-11-18 18:33:23,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 77 transitions. [2022-11-18 18:33:23,530 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:23,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 76 transitions. [2022-11-18 18:33:23,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 18:33:23,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 18:33:23,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 76 transitions. [2022-11-18 18:33:23,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:23,531 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 76 transitions. [2022-11-18 18:33:23,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 76 transitions. [2022-11-18 18:33:23,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 47. [2022-11-18 18:33:23,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2553191489361701) internal successors, (59), 46 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:23,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 59 transitions. [2022-11-18 18:33:23,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:33:23,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:33:23,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:33:23,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-18 18:33:23,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 59 transitions. [2022-11-18 18:33:23,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:23,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:23,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:23,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:23,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:23,541 INFO L748 eck$LassoCheckResult]: Stem: 4622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4633#L367 assume !(main_~length~0#1 < 1); 4624#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4625#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4640#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4636#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4656#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4650#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4648#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4667#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4666#L370-4 main_~j~0#1 := 0; 4637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4629#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4659#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4627#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-18 18:33:23,541 INFO L750 eck$LassoCheckResult]: Loop: 4628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4660#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-18 18:33:23,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:23,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 10 times [2022-11-18 18:33:23,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:23,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156805472] [2022-11-18 18:33:23,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:23,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:23,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:23,968 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:23,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:23,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156805472] [2022-11-18 18:33:23,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156805472] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:23,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [635656921] [2022-11-18 18:33:23,969 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:33:23,969 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:23,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:23,976 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:23,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-18 18:33:24,074 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:33:24,074 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:24,076 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 18:33:24,077 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:24,126 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:24,219 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:33:24,219 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:33:24,379 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:33:24,382 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:24,382 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:24,555 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:24,558 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:24,642 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:24,643 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [635656921] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:24,643 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:24,643 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-11-18 18:33:24,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297605252] [2022-11-18 18:33:24,643 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:24,644 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:24,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:24,644 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-18 18:33:24,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:24,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120351837] [2022-11-18 18:33:24,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:24,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:24,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:24,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:24,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:24,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:24,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:24,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-18 18:33:24,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2022-11-18 18:33:24,702 INFO L87 Difference]: Start difference. First operand 47 states and 59 transitions. cyclomatic complexity: 17 Second operand has 26 states, 25 states have (on average 2.12) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:25,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:25,059 INFO L93 Difference]: Finished difference Result 84 states and 102 transitions. [2022-11-18 18:33:25,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 102 transitions. [2022-11-18 18:33:25,060 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:25,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 101 transitions. [2022-11-18 18:33:25,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-18 18:33:25,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-18 18:33:25,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 101 transitions. [2022-11-18 18:33:25,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:25,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 101 transitions. [2022-11-18 18:33:25,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 101 transitions. [2022-11-18 18:33:25,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 50. [2022-11-18 18:33:25,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.28) internal successors, (64), 49 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:25,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 64 transitions. [2022-11-18 18:33:25,063 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-18 18:33:25,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:33:25,069 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-18 18:33:25,069 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-18 18:33:25,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 64 transitions. [2022-11-18 18:33:25,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:25,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:25,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:25,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:25,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:25,071 INFO L748 eck$LassoCheckResult]: Stem: 4988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4999#L367 assume !(main_~length~0#1 < 1); 4990#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4991#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5000#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5035#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5032#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5029#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5002#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5004#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4993#L370-4 main_~j~0#1 := 0; 4994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4997#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4998#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5006#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5016#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5015#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5014#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5013#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5012#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5010#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4995#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-18 18:33:25,071 INFO L750 eck$LassoCheckResult]: Loop: 4996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5011#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-18 18:33:25,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:25,071 INFO L85 PathProgramCache]: Analyzing trace with hash -1324192720, now seen corresponding path program 6 times [2022-11-18 18:33:25,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:25,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494804427] [2022-11-18 18:33:25,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:25,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:25,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:25,484 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:25,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:25,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494804427] [2022-11-18 18:33:25,485 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494804427] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:25,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1062212844] [2022-11-18 18:33:25,485 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:33:25,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:25,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:25,489 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:25,505 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-18 18:33:25,672 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-18 18:33:25,672 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:25,674 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-18 18:33:25,675 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:25,814 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:26,375 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:33:26,376 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:33:26,382 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:26,382 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:27,106 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:33:27,110 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:33:27,250 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:27,250 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1062212844] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:27,250 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:27,250 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2022-11-18 18:33:27,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852128506] [2022-11-18 18:33:27,250 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:27,251 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:27,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:27,251 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-18 18:33:27,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:27,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347783114] [2022-11-18 18:33:27,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:27,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:27,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:27,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:27,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:27,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:27,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:27,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-18 18:33:27,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=1654, Unknown=0, NotChecked=0, Total=1892 [2022-11-18 18:33:27,305 INFO L87 Difference]: Start difference. First operand 50 states and 64 transitions. cyclomatic complexity: 19 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:28,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:28,376 INFO L93 Difference]: Finished difference Result 72 states and 89 transitions. [2022-11-18 18:33:28,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 89 transitions. [2022-11-18 18:33:28,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:28,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 57 states and 71 transitions. [2022-11-18 18:33:28,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:28,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:28,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 71 transitions. [2022-11-18 18:33:28,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:28,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 71 transitions. [2022-11-18 18:33:28,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 71 transitions. [2022-11-18 18:33:28,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 55. [2022-11-18 18:33:28,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.2545454545454546) internal successors, (69), 54 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:28,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 69 transitions. [2022-11-18 18:33:28,380 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 69 transitions. [2022-11-18 18:33:28,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-11-18 18:33:28,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 69 transitions. [2022-11-18 18:33:28,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-18 18:33:28,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 69 transitions. [2022-11-18 18:33:28,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:28,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:28,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:28,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:28,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:28,388 INFO L748 eck$LassoCheckResult]: Stem: 5426#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5437#L367 assume !(main_~length~0#1 < 1); 5428#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5429#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5430#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5438#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5480#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5440#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5477#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5476#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5475#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5474#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5471#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5469#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5465#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5463#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5462#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5461#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5456#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5431#L370-4 main_~j~0#1 := 0; 5432#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5435#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5436#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5454#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5452#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5450#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5433#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5434#L378-2 [2022-11-18 18:33:28,388 INFO L750 eck$LassoCheckResult]: Loop: 5434#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5448#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5434#L378-2 [2022-11-18 18:33:28,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:28,389 INFO L85 PathProgramCache]: Analyzing trace with hash -1722738829, now seen corresponding path program 11 times [2022-11-18 18:33:28,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:28,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942237153] [2022-11-18 18:33:28,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:28,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:28,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:28,969 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:28,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:28,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942237153] [2022-11-18 18:33:28,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942237153] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:28,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1858403488] [2022-11-18 18:33:28,970 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:33:28,970 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:28,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:28,976 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:28,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-18 18:33:29,115 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-18 18:33:29,116 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:29,118 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-18 18:33:29,119 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:29,297 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:29,417 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:29,417 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:29,466 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:29,467 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:29,799 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:33:29,801 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:33:29,802 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:33:29,805 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 1 proven. 89 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:29,805 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:30,129 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:30,131 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:30,183 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 1 proven. 88 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:33:30,184 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1858403488] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:30,184 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:30,184 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 18] total 38 [2022-11-18 18:33:30,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366664412] [2022-11-18 18:33:30,185 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:30,185 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:30,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:30,185 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-18 18:33:30,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:30,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107973876] [2022-11-18 18:33:30,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:30,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:30,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:30,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:30,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:30,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:30,241 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:30,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-18 18:33:30,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=1324, Unknown=0, NotChecked=0, Total=1482 [2022-11-18 18:33:30,243 INFO L87 Difference]: Start difference. First operand 55 states and 69 transitions. cyclomatic complexity: 19 Second operand has 39 states, 38 states have (on average 2.1315789473684212) internal successors, (81), 39 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:30,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:30,806 INFO L93 Difference]: Finished difference Result 66 states and 80 transitions. [2022-11-18 18:33:30,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 80 transitions. [2022-11-18 18:33:30,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:30,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 65 states and 79 transitions. [2022-11-18 18:33:30,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:30,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:30,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 79 transitions. [2022-11-18 18:33:30,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:30,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65 states and 79 transitions. [2022-11-18 18:33:30,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 79 transitions. [2022-11-18 18:33:30,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 48. [2022-11-18 18:33:30,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.25) internal successors, (60), 47 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:30,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 60 transitions. [2022-11-18 18:33:30,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48 states and 60 transitions. [2022-11-18 18:33:30,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-18 18:33:30,816 INFO L428 stractBuchiCegarLoop]: Abstraction has 48 states and 60 transitions. [2022-11-18 18:33:30,816 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-18 18:33:30,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 60 transitions. [2022-11-18 18:33:30,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:30,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:30,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:30,820 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:30,820 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:30,820 INFO L748 eck$LassoCheckResult]: Stem: 5825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5836#L367 assume !(main_~length~0#1 < 1); 5827#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5828#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5837#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5872#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5869#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5866#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5865#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5864#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5863#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5860#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5859#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5857#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5852#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5851#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5843#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5830#L370-4 main_~j~0#1 := 0; 5831#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5834#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5835#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5841#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5871#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5856#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5853#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5850#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5848#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5846#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5832#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5833#L378-2 [2022-11-18 18:33:30,820 INFO L750 eck$LassoCheckResult]: Loop: 5833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5847#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5833#L378-2 [2022-11-18 18:33:30,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:30,821 INFO L85 PathProgramCache]: Analyzing trace with hash -519513416, now seen corresponding path program 7 times [2022-11-18 18:33:30,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:30,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584373688] [2022-11-18 18:33:30,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:30,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:30,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:31,327 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:31,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:31,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584373688] [2022-11-18 18:33:31,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584373688] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:31,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [98116154] [2022-11-18 18:33:31,328 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:33:31,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:31,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:31,336 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:31,360 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-18 18:33:31,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:31,455 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 18:33:31,457 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:31,672 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:31,748 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:32,081 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:32,108 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:32,108 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:32,516 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-18 18:33:32,519 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 62 [2022-11-18 18:33:32,597 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:32,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [98116154] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:32,598 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:32,598 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 17] total 43 [2022-11-18 18:33:32,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620051952] [2022-11-18 18:33:32,598 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:32,599 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:32,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:32,599 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-18 18:33:32,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:32,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671866825] [2022-11-18 18:33:32,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:32,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:32,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:32,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:32,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:32,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:32,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:32,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-18 18:33:32,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1739, Unknown=0, NotChecked=0, Total=1892 [2022-11-18 18:33:32,656 INFO L87 Difference]: Start difference. First operand 48 states and 60 transitions. cyclomatic complexity: 16 Second operand has 44 states, 43 states have (on average 2.2093023255813953) internal successors, (95), 44 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:33,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:33,690 INFO L93 Difference]: Finished difference Result 77 states and 94 transitions. [2022-11-18 18:33:33,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 94 transitions. [2022-11-18 18:33:33,692 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:33:33,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 76 states and 93 transitions. [2022-11-18 18:33:33,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 18:33:33,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 18:33:33,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 93 transitions. [2022-11-18 18:33:33,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:33,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76 states and 93 transitions. [2022-11-18 18:33:33,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 93 transitions. [2022-11-18 18:33:33,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 60. [2022-11-18 18:33:33,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.25) internal successors, (75), 59 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:33,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2022-11-18 18:33:33,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2022-11-18 18:33:33,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-18 18:33:33,701 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 75 transitions. [2022-11-18 18:33:33,701 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-18 18:33:33,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 75 transitions. [2022-11-18 18:33:33,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:33,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:33,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:33,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:33,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:33,703 INFO L748 eck$LassoCheckResult]: Stem: 6253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6264#L367 assume !(main_~length~0#1 < 1); 6255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6267#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6272#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6296#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6294#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6293#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6292#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6291#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6290#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6287#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6284#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6279#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6274#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6310#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6309#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6308#L370-4 main_~j~0#1 := 0; 6269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6262#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6306#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6305#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6304#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6302#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6301#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6299#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6260#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6261#L378-2 [2022-11-18 18:33:33,703 INFO L750 eck$LassoCheckResult]: Loop: 6261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6300#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6261#L378-2 [2022-11-18 18:33:33,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:33,703 INFO L85 PathProgramCache]: Analyzing trace with hash 2086510138, now seen corresponding path program 8 times [2022-11-18 18:33:33,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:33,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924223992] [2022-11-18 18:33:33,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:33,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:33,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:34,220 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:34,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:34,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924223992] [2022-11-18 18:33:34,221 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924223992] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:34,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1047147352] [2022-11-18 18:33:34,221 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:33:34,221 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:34,221 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:34,225 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:34,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-18 18:33:34,340 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:33:34,340 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:34,342 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 18:33:34,344 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:34,557 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:34,682 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:34,683 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:35,044 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:35,047 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:35,047 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:35,244 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:35,247 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:35,301 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:35,301 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1047147352] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:35,301 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:35,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 18] total 38 [2022-11-18 18:33:35,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692842711] [2022-11-18 18:33:35,302 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:35,302 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:35,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:35,303 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-18 18:33:35,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:35,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726635349] [2022-11-18 18:33:35,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:35,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:35,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:35,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:35,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:35,308 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:35,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:35,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-18 18:33:35,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=1339, Unknown=0, NotChecked=0, Total=1482 [2022-11-18 18:33:35,351 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. cyclomatic complexity: 19 Second operand has 39 states, 38 states have (on average 2.1578947368421053) internal successors, (82), 39 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:36,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:36,038 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2022-11-18 18:33:36,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 87 transitions. [2022-11-18 18:33:36,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:36,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 71 states and 86 transitions. [2022-11-18 18:33:36,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:36,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:36,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 86 transitions. [2022-11-18 18:33:36,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:36,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71 states and 86 transitions. [2022-11-18 18:33:36,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 86 transitions. [2022-11-18 18:33:36,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2022-11-18 18:33:36,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.24) internal successors, (62), 49 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:36,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 62 transitions. [2022-11-18 18:33:36,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-18 18:33:36,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-18 18:33:36,047 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-18 18:33:36,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-18 18:33:36,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 62 transitions. [2022-11-18 18:33:36,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:36,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:36,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:36,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:36,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:36,048 INFO L748 eck$LassoCheckResult]: Stem: 6677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6688#L367 assume !(main_~length~0#1 < 1); 6679#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6680#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6681#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6689#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6723#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6722#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6720#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6719#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6718#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6717#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6716#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6714#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6712#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6711#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6709#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6704#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6703#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6701#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6698#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6686#L370-4 main_~j~0#1 := 0; 6687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6684#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6692#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6726#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6725#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6702#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6696#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6695#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6682#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6683#L378-2 [2022-11-18 18:33:36,048 INFO L750 eck$LassoCheckResult]: Loop: 6683#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6697#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6683#L378-2 [2022-11-18 18:33:36,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:36,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1036183171, now seen corresponding path program 9 times [2022-11-18 18:33:36,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:36,049 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322370426] [2022-11-18 18:33:36,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:36,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:36,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:36,528 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:36,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:36,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322370426] [2022-11-18 18:33:36,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322370426] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:36,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [96070334] [2022-11-18 18:33:36,528 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:33:36,528 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:36,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:36,536 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:36,552 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-18 18:33:36,744 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-18 18:33:36,744 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:36,746 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:33:36,748 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:36,922 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:37,630 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:33:37,630 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:33:37,634 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:37,634 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:38,598 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:33:38,611 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:33:38,787 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:38,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [96070334] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:38,787 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:38,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 20] total 48 [2022-11-18 18:33:38,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541457019] [2022-11-18 18:33:38,788 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:38,788 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:38,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:38,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-18 18:33:38,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:38,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076359137] [2022-11-18 18:33:38,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:38,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:38,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:38,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:38,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:38,803 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:38,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:38,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 18:33:38,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=287, Invalid=2065, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 18:33:38,851 INFO L87 Difference]: Start difference. First operand 50 states and 62 transitions. cyclomatic complexity: 16 Second operand has 49 states, 48 states have (on average 2.0208333333333335) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:40,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:40,108 INFO L93 Difference]: Finished difference Result 75 states and 91 transitions. [2022-11-18 18:33:40,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 91 transitions. [2022-11-18 18:33:40,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:40,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 58 states and 72 transitions. [2022-11-18 18:33:40,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 18:33:40,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 18:33:40,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 72 transitions. [2022-11-18 18:33:40,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:40,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-18 18:33:40,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 72 transitions. [2022-11-18 18:33:40,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2022-11-18 18:33:40,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.25) internal successors, (70), 55 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:40,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 70 transitions. [2022-11-18 18:33:40,114 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56 states and 70 transitions. [2022-11-18 18:33:40,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-18 18:33:40,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 56 states and 70 transitions. [2022-11-18 18:33:40,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-18 18:33:40,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 70 transitions. [2022-11-18 18:33:40,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:40,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:40,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:40,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:40,118 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:40,118 INFO L748 eck$LassoCheckResult]: Stem: 7168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7179#L367 assume !(main_~length~0#1 < 1); 7170#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7171#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7172#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7180#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7183#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7182#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7213#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7212#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7206#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7203#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7201#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7197#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7195#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7186#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7173#L370-4 main_~j~0#1 := 0; 7174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7184#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7177#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7223#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7222#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7221#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7219#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7217#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7216#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7175#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7176#L378-2 [2022-11-18 18:33:40,118 INFO L750 eck$LassoCheckResult]: Loop: 7176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7215#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7176#L378-2 [2022-11-18 18:33:40,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:40,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1188134923, now seen corresponding path program 10 times [2022-11-18 18:33:40,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:40,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431561336] [2022-11-18 18:33:40,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:40,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:40,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:40,646 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:40,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:40,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431561336] [2022-11-18 18:33:40,646 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431561336] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:40,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1561596895] [2022-11-18 18:33:40,646 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:33:40,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:40,647 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:40,650 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:40,672 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-18 18:33:40,780 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:33:40,780 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:40,782 INFO L263 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-18 18:33:40,783 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:40,851 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:40,952 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:33:40,952 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:33:41,460 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-18 18:33:41,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-18 18:33:41,490 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:41,491 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:44,098 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-18 18:33:44,115 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 138 [2022-11-18 18:33:44,202 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:44,202 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1561596895] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:44,202 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:44,202 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 40 [2022-11-18 18:33:44,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255513897] [2022-11-18 18:33:44,203 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:44,204 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:44,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:44,205 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-18 18:33:44,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:44,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494887674] [2022-11-18 18:33:44,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:44,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:44,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:44,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:44,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:44,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:44,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:44,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:33:44,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=1502, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:33:44,259 INFO L87 Difference]: Start difference. First operand 56 states and 70 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.15) internal successors, (86), 41 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:45,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:45,116 INFO L93 Difference]: Finished difference Result 81 states and 99 transitions. [2022-11-18 18:33:45,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 99 transitions. [2022-11-18 18:33:45,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:45,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 98 transitions. [2022-11-18 18:33:45,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:45,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:45,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 98 transitions. [2022-11-18 18:33:45,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:45,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-18 18:33:45,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 98 transitions. [2022-11-18 18:33:45,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2022-11-18 18:33:45,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.25) internal successors, (85), 67 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:45,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 85 transitions. [2022-11-18 18:33:45,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-18 18:33:45,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-18 18:33:45,128 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-18 18:33:45,128 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-18 18:33:45,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 85 transitions. [2022-11-18 18:33:45,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:45,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:45,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:45,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:45,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:45,130 INFO L748 eck$LassoCheckResult]: Stem: 7632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7643#L367 assume !(main_~length~0#1 < 1); 7634#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7635#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7636#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7644#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7647#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7645#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7690#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7688#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7687#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7686#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7685#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7684#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7682#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7681#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7676#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7670#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7665#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7662#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7651#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7658#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7696#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7695#L370-4 main_~j~0#1 := 0; 7648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7641#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7642#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7693#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7692#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7691#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7667#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7661#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7653#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7652#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7639#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7640#L378-2 [2022-11-18 18:33:45,130 INFO L750 eck$LassoCheckResult]: Loop: 7640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7654#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7640#L378-2 [2022-11-18 18:33:45,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:45,130 INFO L85 PathProgramCache]: Analyzing trace with hash -765433097, now seen corresponding path program 11 times [2022-11-18 18:33:45,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:45,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697959584] [2022-11-18 18:33:45,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:45,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:45,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:45,713 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:45,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:45,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697959584] [2022-11-18 18:33:45,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697959584] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:45,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [326909641] [2022-11-18 18:33:45,714 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:33:45,714 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:45,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:45,720 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:45,724 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-18 18:33:45,918 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2022-11-18 18:33:45,919 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:45,921 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 41 conjunts are in the unsatisfiable core [2022-11-18 18:33:45,922 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:46,185 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:46,317 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:46,318 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:46,805 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:33:46,807 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:33:46,808 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:33:46,811 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:46,811 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:47,093 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:47,096 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:47,160 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:47,161 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [326909641] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:47,161 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:47,161 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 44 [2022-11-18 18:33:47,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794008730] [2022-11-18 18:33:47,161 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:47,161 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:47,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:47,162 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-18 18:33:47,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:47,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555096219] [2022-11-18 18:33:47,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:47,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:47,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:47,165 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:47,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:47,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:47,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:47,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-11-18 18:33:47,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=1811, Unknown=0, NotChecked=0, Total=1980 [2022-11-18 18:33:47,212 INFO L87 Difference]: Start difference. First operand 68 states and 85 transitions. cyclomatic complexity: 21 Second operand has 45 states, 44 states have (on average 2.090909090909091) internal successors, (92), 45 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:48,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:48,027 INFO L93 Difference]: Finished difference Result 82 states and 99 transitions. [2022-11-18 18:33:48,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 99 transitions. [2022-11-18 18:33:48,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:48,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 81 states and 98 transitions. [2022-11-18 18:33:48,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:33:48,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:33:48,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 98 transitions. [2022-11-18 18:33:48,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:48,029 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81 states and 98 transitions. [2022-11-18 18:33:48,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 98 transitions. [2022-11-18 18:33:48,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 58. [2022-11-18 18:33:48,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2413793103448276) internal successors, (72), 57 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:48,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 72 transitions. [2022-11-18 18:33:48,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-18 18:33:48,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 18:33:48,037 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-18 18:33:48,037 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-18 18:33:48,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 72 transitions. [2022-11-18 18:33:48,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:48,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:48,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:48,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:48,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:48,038 INFO L748 eck$LassoCheckResult]: Stem: 8112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8123#L367 assume !(main_~length~0#1 < 1); 8114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8116#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8124#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8164#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8163#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8162#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8161#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8160#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8159#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8156#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8155#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8152#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8149#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8145#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8140#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8139#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8137#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8134#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8121#L370-4 main_~j~0#1 := 0; 8122#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8127#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8128#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8119#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8168#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8167#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8165#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8144#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8143#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8136#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8117#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8118#L378-2 [2022-11-18 18:33:48,038 INFO L750 eck$LassoCheckResult]: Loop: 8118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8133#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8118#L378-2 [2022-11-18 18:33:48,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:48,039 INFO L85 PathProgramCache]: Analyzing trace with hash 663643002, now seen corresponding path program 12 times [2022-11-18 18:33:48,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:48,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856286972] [2022-11-18 18:33:48,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:48,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:48,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:48,657 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:48,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:48,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856286972] [2022-11-18 18:33:48,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856286972] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:48,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1059702684] [2022-11-18 18:33:48,658 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:33:48,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:48,658 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:48,664 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:48,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-18 18:33:49,020 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-18 18:33:49,020 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:49,022 INFO L263 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-18 18:33:49,024 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:49,235 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:50,046 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:33:50,047 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:33:50,051 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:50,051 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:51,048 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:33:51,053 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:33:51,254 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:51,255 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1059702684] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:51,255 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:51,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 53 [2022-11-18 18:33:51,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30494026] [2022-11-18 18:33:51,255 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:51,255 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:51,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:51,256 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-18 18:33:51,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:51,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953610583] [2022-11-18 18:33:51,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:51,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:51,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:51,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:51,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:51,261 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:51,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:51,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-18 18:33:51,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2521, Unknown=0, NotChecked=0, Total=2862 [2022-11-18 18:33:51,304 INFO L87 Difference]: Start difference. First operand 58 states and 72 transitions. cyclomatic complexity: 18 Second operand has 54 states, 53 states have (on average 2.056603773584906) internal successors, (109), 54 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:52,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:52,763 INFO L93 Difference]: Finished difference Result 85 states and 103 transitions. [2022-11-18 18:33:52,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 103 transitions. [2022-11-18 18:33:52,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:52,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 66 states and 82 transitions. [2022-11-18 18:33:52,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 18:33:52,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 18:33:52,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 82 transitions. [2022-11-18 18:33:52,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:52,765 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-18 18:33:52,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 82 transitions. [2022-11-18 18:33:52,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 64. [2022-11-18 18:33:52,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.25) internal successors, (80), 63 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:52,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 80 transitions. [2022-11-18 18:33:52,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 80 transitions. [2022-11-18 18:33:52,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-18 18:33:52,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 80 transitions. [2022-11-18 18:33:52,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-18 18:33:52,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 80 transitions. [2022-11-18 18:33:52,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:52,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:52,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:52,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:52,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:52,769 INFO L748 eck$LassoCheckResult]: Stem: 8666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8667#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8677#L367 assume !(main_~length~0#1 < 1); 8668#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8669#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8670#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8678#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8679#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8680#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8715#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8714#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8713#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8712#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8711#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8709#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8708#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8704#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8702#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8698#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8696#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8692#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8688#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8685#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8671#L370-4 main_~j~0#1 := 0; 8672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8675#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8682#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8728#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8726#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8724#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8723#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8722#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8721#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8673#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8674#L378-2 [2022-11-18 18:33:52,769 INFO L750 eck$LassoCheckResult]: Loop: 8674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8720#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8674#L378-2 [2022-11-18 18:33:52,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:52,770 INFO L85 PathProgramCache]: Analyzing trace with hash -1169012734, now seen corresponding path program 13 times [2022-11-18 18:33:52,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:52,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781138718] [2022-11-18 18:33:52,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:52,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:52,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:53,399 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:53,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:53,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781138718] [2022-11-18 18:33:53,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781138718] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:53,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [340904939] [2022-11-18 18:33:53,400 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:33:53,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:53,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:53,407 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:53,409 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-18 18:33:53,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:53,571 INFO L263 TraceCheckSpWp]: Trace formula consists of 279 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-18 18:33:53,573 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:53,894 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:53,986 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:33:54,458 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:54,493 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:54,493 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:55,018 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-18 18:33:55,021 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 62 [2022-11-18 18:33:55,123 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:55,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [340904939] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:55,124 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:55,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 21] total 53 [2022-11-18 18:33:55,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386648767] [2022-11-18 18:33:55,124 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:55,126 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:55,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:55,126 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-18 18:33:55,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:55,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665234932] [2022-11-18 18:33:55,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:55,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:55,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:55,129 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:55,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:55,132 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:55,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:55,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-18 18:33:55,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=2675, Unknown=0, NotChecked=0, Total=2862 [2022-11-18 18:33:55,189 INFO L87 Difference]: Start difference. First operand 64 states and 80 transitions. cyclomatic complexity: 20 Second operand has 54 states, 53 states have (on average 2.2452830188679247) internal successors, (119), 54 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:57,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:57,076 INFO L93 Difference]: Finished difference Result 126 states and 152 transitions. [2022-11-18 18:33:57,076 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 152 transitions. [2022-11-18 18:33:57,077 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 18:33:57,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 124 states and 150 transitions. [2022-11-18 18:33:57,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-18 18:33:57,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-18 18:33:57,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124 states and 150 transitions. [2022-11-18 18:33:57,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:33:57,077 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124 states and 150 transitions. [2022-11-18 18:33:57,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states and 150 transitions. [2022-11-18 18:33:57,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 82. [2022-11-18 18:33:57,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2682926829268293) internal successors, (104), 81 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:57,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 104 transitions. [2022-11-18 18:33:57,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-18 18:33:57,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-18 18:33:57,082 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-18 18:33:57,082 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-18 18:33:57,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 104 transitions. [2022-11-18 18:33:57,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:33:57,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:57,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:57,083 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:33:57,083 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:33:57,084 INFO L748 eck$LassoCheckResult]: Stem: 9252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9263#L367 assume !(main_~length~0#1 < 1); 9254#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9255#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9256#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9264#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9269#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9310#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9309#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9308#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9307#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9304#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9303#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9301#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9298#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9296#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9294#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9290#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9283#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9280#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9329#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9327#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9326#L370-4 main_~j~0#1 := 0; 9267#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9324#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9323#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9322#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9321#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9320#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9319#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9318#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9316#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9315#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9314#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9313#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9257#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9258#L378-2 [2022-11-18 18:33:57,084 INFO L750 eck$LassoCheckResult]: Loop: 9258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9312#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9258#L378-2 [2022-11-18 18:33:57,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:57,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1320516228, now seen corresponding path program 14 times [2022-11-18 18:33:57,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:57,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649119342] [2022-11-18 18:33:57,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:57,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:57,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:57,705 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:57,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:57,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649119342] [2022-11-18 18:33:57,706 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649119342] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:57,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1131890423] [2022-11-18 18:33:57,706 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:33:57,706 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:57,706 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:57,708 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:57,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-18 18:33:57,840 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:33:57,840 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:57,842 INFO L263 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-18 18:33:57,844 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:58,137 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:33:58,266 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:33:58,266 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:33:58,715 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:33:58,718 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:58,718 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:58,959 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:33:58,962 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:33:59,045 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:59,045 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1131890423] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:59,045 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:59,045 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 46 [2022-11-18 18:33:59,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323952752] [2022-11-18 18:33:59,045 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:59,045 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:59,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:59,046 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-18 18:33:59,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:59,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287241194] [2022-11-18 18:33:59,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:59,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:59,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:59,049 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:59,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:59,052 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:59,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:59,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-18 18:33:59,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1991, Unknown=0, NotChecked=0, Total=2162 [2022-11-18 18:33:59,101 INFO L87 Difference]: Start difference. First operand 82 states and 104 transitions. cyclomatic complexity: 26 Second operand has 47 states, 46 states have (on average 2.217391304347826) internal successors, (102), 47 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:59,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:59,999 INFO L93 Difference]: Finished difference Result 98 states and 120 transitions. [2022-11-18 18:33:59,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 120 transitions. [2022-11-18 18:33:59,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:00,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 97 states and 119 transitions. [2022-11-18 18:34:00,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:34:00,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:34:00,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 119 transitions. [2022-11-18 18:34:00,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:00,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 119 transitions. [2022-11-18 18:34:00,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 119 transitions. [2022-11-18 18:34:00,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 66. [2022-11-18 18:34:00,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.2424242424242424) internal successors, (82), 65 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:00,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 82 transitions. [2022-11-18 18:34:00,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-18 18:34:00,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:34:00,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-18 18:34:00,009 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-18 18:34:00,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 82 transitions. [2022-11-18 18:34:00,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:00,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:00,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:00,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:00,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:00,010 INFO L748 eck$LassoCheckResult]: Stem: 9796#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9807#L367 assume !(main_~length~0#1 < 1); 9798#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9799#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9800#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9808#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9811#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9860#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9859#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9854#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9853#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9852#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9851#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9845#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9843#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9840#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9836#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9834#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9809#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9810#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9814#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9801#L370-4 main_~j~0#1 := 0; 9802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9805#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9806#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9812#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9829#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9828#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9827#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9826#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9820#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9819#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9817#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9803#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9804#L378-2 [2022-11-18 18:34:00,011 INFO L750 eck$LassoCheckResult]: Loop: 9804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9816#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9804#L378-2 [2022-11-18 18:34:00,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:00,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1860197447, now seen corresponding path program 15 times [2022-11-18 18:34:00,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:00,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508597365] [2022-11-18 18:34:00,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:00,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:00,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:00,617 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:00,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:00,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508597365] [2022-11-18 18:34:00,618 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508597365] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:00,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [900828000] [2022-11-18 18:34:00,618 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:34:00,618 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:00,619 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:00,624 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:00,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-18 18:34:00,915 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-18 18:34:00,915 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:00,918 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 18:34:00,920 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:01,171 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:02,053 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:34:02,054 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:34:02,057 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:02,058 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:03,154 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:34:03,157 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:34:03,403 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:03,404 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [900828000] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:03,404 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:03,404 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2022-11-18 18:34:03,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345406513] [2022-11-18 18:34:03,404 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:03,405 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:03,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:03,405 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-18 18:34:03,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:03,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556063520] [2022-11-18 18:34:03,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:03,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:03,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:03,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:03,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:03,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:03,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:03,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 18:34:03,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3022, Unknown=0, NotChecked=0, Total=3422 [2022-11-18 18:34:03,463 INFO L87 Difference]: Start difference. First operand 66 states and 82 transitions. cyclomatic complexity: 20 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:05,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:05,972 INFO L93 Difference]: Finished difference Result 184 states and 219 transitions. [2022-11-18 18:34:05,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 219 transitions. [2022-11-18 18:34:05,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:05,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 160 states and 194 transitions. [2022-11-18 18:34:05,974 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:34:05,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:34:05,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 160 states and 194 transitions. [2022-11-18 18:34:05,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:05,975 INFO L218 hiAutomatonCegarLoop]: Abstraction has 160 states and 194 transitions. [2022-11-18 18:34:05,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states and 194 transitions. [2022-11-18 18:34:05,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 105. [2022-11-18 18:34:05,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.2666666666666666) internal successors, (133), 104 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:05,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 133 transitions. [2022-11-18 18:34:05,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 105 states and 133 transitions. [2022-11-18 18:34:05,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2022-11-18 18:34:05,978 INFO L428 stractBuchiCegarLoop]: Abstraction has 105 states and 133 transitions. [2022-11-18 18:34:05,979 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-18 18:34:05,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 133 transitions. [2022-11-18 18:34:05,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:05,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:05,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:05,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:05,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:05,981 INFO L748 eck$LassoCheckResult]: Stem: 10516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10527#L367 assume !(main_~length~0#1 < 1); 10518#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10519#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10520#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10528#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10529#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10530#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10616#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10600#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10568#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10564#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10563#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10562#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10559#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10560#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10555#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10548#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10547#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10538#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10539#L370-4 main_~j~0#1 := 0; 10531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10523#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10524#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10607#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10605#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10597#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10536#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10521#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10522#L378-2 [2022-11-18 18:34:05,981 INFO L750 eck$LassoCheckResult]: Loop: 10522#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10537#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10522#L378-2 [2022-11-18 18:34:05,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:05,981 INFO L85 PathProgramCache]: Analyzing trace with hash -68075255, now seen corresponding path program 16 times [2022-11-18 18:34:05,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:05,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945143272] [2022-11-18 18:34:05,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:05,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:06,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:06,629 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:06,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:06,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945143272] [2022-11-18 18:34:06,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945143272] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:06,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [557751058] [2022-11-18 18:34:06,630 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:34:06,630 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:06,630 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:06,636 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:06,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-18 18:34:06,777 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:34:06,777 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:06,779 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-18 18:34:06,781 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:06,863 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:07,261 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:34:07,263 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:07,264 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:07,423 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:34:07,433 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:34:07,516 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:07,517 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [557751058] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:07,517 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:07,517 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22] total 34 [2022-11-18 18:34:07,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765852492] [2022-11-18 18:34:07,517 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:07,517 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:07,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:07,518 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-18 18:34:07,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:07,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803229571] [2022-11-18 18:34:07,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:07,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:07,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:07,520 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:07,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:07,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:07,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:07,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 18:34:07,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=1088, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 18:34:07,570 INFO L87 Difference]: Start difference. First operand 105 states and 133 transitions. cyclomatic complexity: 32 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:08,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:08,317 INFO L93 Difference]: Finished difference Result 160 states and 196 transitions. [2022-11-18 18:34:08,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 160 states and 196 transitions. [2022-11-18 18:34:08,318 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:34:08,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 160 states to 159 states and 195 transitions. [2022-11-18 18:34:08,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:34:08,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:34:08,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 159 states and 195 transitions. [2022-11-18 18:34:08,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:08,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 159 states and 195 transitions. [2022-11-18 18:34:08,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states and 195 transitions. [2022-11-18 18:34:08,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 118. [2022-11-18 18:34:08,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.2796610169491525) internal successors, (151), 117 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:08,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 151 transitions. [2022-11-18 18:34:08,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-18 18:34:08,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:34:08,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-18 18:34:08,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-18 18:34:08,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 151 transitions. [2022-11-18 18:34:08,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:08,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:08,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:08,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:08,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:08,326 INFO L748 eck$LassoCheckResult]: Stem: 11127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11138#L367 assume !(main_~length~0#1 < 1); 11129#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11130#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11131#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11139#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11236#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11142#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11143#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11141#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11243#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11242#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11241#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11238#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11229#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11223#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11220#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11214#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11211#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11205#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11166#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11146#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11132#L370-4 main_~j~0#1 := 0; 11133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11169#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11163#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11161#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11160#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11159#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11157#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11156#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11155#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11154#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11153#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11134#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11135#L378-2 [2022-11-18 18:34:08,326 INFO L750 eck$LassoCheckResult]: Loop: 11135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11151#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11135#L378-2 [2022-11-18 18:34:08,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:08,327 INFO L85 PathProgramCache]: Analyzing trace with hash -995807346, now seen corresponding path program 17 times [2022-11-18 18:34:08,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:08,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084338218] [2022-11-18 18:34:08,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:08,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:08,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:08,731 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:08,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:08,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084338218] [2022-11-18 18:34:08,731 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084338218] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:08,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1917747707] [2022-11-18 18:34:08,731 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:34:08,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:08,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:08,735 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:08,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-18 18:34:09,147 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-18 18:34:09,147 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:09,150 INFO L263 TraceCheckSpWp]: Trace formula consists of 309 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 18:34:09,152 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:09,499 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:09,499 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:09,738 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 81 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:09,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1917747707] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:09,738 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:09,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-18 18:34:09,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289507090] [2022-11-18 18:34:09,738 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:09,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:09,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:09,739 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-18 18:34:09,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:09,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963714334] [2022-11-18 18:34:09,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:09,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:09,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:09,742 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:09,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:09,745 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:09,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:09,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 18:34:09,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 18:34:09,788 INFO L87 Difference]: Start difference. First operand 118 states and 151 transitions. cyclomatic complexity: 38 Second operand has 35 states, 35 states have (on average 2.2857142857142856) internal successors, (80), 35 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:10,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:10,061 INFO L93 Difference]: Finished difference Result 144 states and 178 transitions. [2022-11-18 18:34:10,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144 states and 178 transitions. [2022-11-18 18:34:10,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:10,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144 states to 124 states and 158 transitions. [2022-11-18 18:34:10,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:34:10,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:34:10,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124 states and 158 transitions. [2022-11-18 18:34:10,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:10,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124 states and 158 transitions. [2022-11-18 18:34:10,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states and 158 transitions. [2022-11-18 18:34:10,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 82. [2022-11-18 18:34:10,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:10,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-18 18:34:10,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:34:10,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:34:10,073 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:34:10,073 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-18 18:34:10,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-18 18:34:10,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:10,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:10,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:10,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:10,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:10,075 INFO L748 eck$LassoCheckResult]: Stem: 11767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11778#L367 assume !(main_~length~0#1 < 1); 11769#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11770#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11779#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11780#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11781#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11848#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11838#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11832#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11826#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11820#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11815#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11816#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11811#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11806#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11802#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11784#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11772#L370-4 main_~j~0#1 := 0; 11773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11783#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11800#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11798#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11797#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11796#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11795#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11794#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11792#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11790#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11787#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11774#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11775#L378-2 [2022-11-18 18:34:10,075 INFO L750 eck$LassoCheckResult]: Loop: 11775#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11788#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11775#L378-2 [2022-11-18 18:34:10,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:10,076 INFO L85 PathProgramCache]: Analyzing trace with hash 307442051, now seen corresponding path program 18 times [2022-11-18 18:34:10,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:10,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139297821] [2022-11-18 18:34:10,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:10,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:10,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:10,878 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:10,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:10,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139297821] [2022-11-18 18:34:10,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139297821] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:10,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2008143926] [2022-11-18 18:34:10,879 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:34:10,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:10,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:10,883 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:10,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-18 18:34:11,823 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-18 18:34:11,823 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:11,826 INFO L263 TraceCheckSpWp]: Trace formula consists of 312 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-18 18:34:11,828 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:12,104 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:12,265 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:34:12,265 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-18 18:34:12,363 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:34:12,363 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-18 18:34:13,603 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 18:34:13,604 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-18 18:34:13,632 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 64 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:13,633 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:15,098 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:34:15,102 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:34:15,374 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 56 proven. 159 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:34:15,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2008143926] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:15,375 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:15,375 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 24] total 62 [2022-11-18 18:34:15,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983773201] [2022-11-18 18:34:15,375 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:15,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:15,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:15,376 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-18 18:34:15,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:15,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003936579] [2022-11-18 18:34:15,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:15,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:15,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:15,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:15,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:15,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:15,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:15,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2022-11-18 18:34:15,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=440, Invalid=3466, Unknown=0, NotChecked=0, Total=3906 [2022-11-18 18:34:15,431 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 63 states, 62 states have (on average 2.0806451612903225) internal successors, (129), 63 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:19,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:19,673 INFO L93 Difference]: Finished difference Result 176 states and 204 transitions. [2022-11-18 18:34:19,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 204 transitions. [2022-11-18 18:34:19,675 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:34:19,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 133 states and 159 transitions. [2022-11-18 18:34:19,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:34:19,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:34:19,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133 states and 159 transitions. [2022-11-18 18:34:19,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:19,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133 states and 159 transitions. [2022-11-18 18:34:19,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states and 159 transitions. [2022-11-18 18:34:19,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 68. [2022-11-18 18:34:19,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.25) internal successors, (85), 67 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:19,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 85 transitions. [2022-11-18 18:34:19,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-18 18:34:19,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2022-11-18 18:34:19,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-18 18:34:19,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-18 18:34:19,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 85 transitions. [2022-11-18 18:34:19,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:19,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:19,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:19,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:19,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:19,680 INFO L748 eck$LassoCheckResult]: Stem: 12563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12574#L367 assume !(main_~length~0#1 < 1); 12565#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12566#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12575#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12580#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12576#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12577#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12628#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12627#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12625#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12622#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12619#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12614#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12613#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12612#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12611#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12610#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12609#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12583#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12572#L370-4 main_~j~0#1 := 0; 12573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12570#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12600#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12598#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12594#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12592#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12590#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12568#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12569#L378-2 [2022-11-18 18:34:19,680 INFO L750 eck$LassoCheckResult]: Loop: 12569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12586#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12569#L378-2 [2022-11-18 18:34:19,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:19,680 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 12 times [2022-11-18 18:34:19,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:19,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239504621] [2022-11-18 18:34:19,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:19,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:19,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:20,426 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:20,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:20,426 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239504621] [2022-11-18 18:34:20,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239504621] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:20,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [347976773] [2022-11-18 18:34:20,427 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:34:20,427 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:20,427 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:20,431 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:20,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-18 18:34:21,094 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-18 18:34:21,095 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:21,097 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 18:34:21,098 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:21,386 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:22,383 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:34:22,383 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:34:22,386 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:22,386 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:23,642 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:34:23,645 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:34:23,933 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:23,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [347976773] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:23,933 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:23,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-18 18:34:23,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029406379] [2022-11-18 18:34:23,934 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:23,934 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:23,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:23,934 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-18 18:34:23,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:23,934 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402836927] [2022-11-18 18:34:23,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:23,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:23,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:23,937 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:23,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:23,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:23,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:23,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-18 18:34:23,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=3568, Unknown=0, NotChecked=0, Total=4032 [2022-11-18 18:34:23,992 INFO L87 Difference]: Start difference. First operand 68 states and 85 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:26,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:26,027 INFO L93 Difference]: Finished difference Result 105 states and 128 transitions. [2022-11-18 18:34:26,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 128 transitions. [2022-11-18 18:34:26,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:26,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 82 states and 103 transitions. [2022-11-18 18:34:26,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:34:26,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:34:26,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 103 transitions. [2022-11-18 18:34:26,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:26,030 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:34:26,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 103 transitions. [2022-11-18 18:34:26,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2022-11-18 18:34:26,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:26,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-18 18:34:26,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:34:26,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-18 18:34:26,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:34:26,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-18 18:34:26,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-18 18:34:26,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:26,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:26,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:26,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:26,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:26,035 INFO L748 eck$LassoCheckResult]: Stem: 13233#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13244#L367 assume !(main_~length~0#1 < 1); 13235#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13236#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13237#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13245#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13250#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13247#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13314#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13313#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13312#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13309#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13307#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13305#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13300#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13290#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13285#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13282#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13274#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13272#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13266#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13242#L370-4 main_~j~0#1 := 0; 13243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13268#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13240#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13265#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13263#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13262#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13261#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13257#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13255#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13252#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13238#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13239#L378-2 [2022-11-18 18:34:26,035 INFO L750 eck$LassoCheckResult]: Loop: 13239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13253#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13239#L378-2 [2022-11-18 18:34:26,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:26,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1364903176, now seen corresponding path program 19 times [2022-11-18 18:34:26,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:26,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140575124] [2022-11-18 18:34:26,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:26,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:26,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:26,714 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:26,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:26,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140575124] [2022-11-18 18:34:26,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140575124] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:26,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1963691725] [2022-11-18 18:34:26,715 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:34:26,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:26,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:26,716 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:26,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-18 18:34:26,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:26,870 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-18 18:34:26,872 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:26,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:27,431 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:34:27,437 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:27,437 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:27,595 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:34:27,597 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:34:27,683 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:27,684 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1963691725] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:27,684 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:27,684 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24] total 37 [2022-11-18 18:34:27,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442593726] [2022-11-18 18:34:27,684 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:27,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:27,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:27,685 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-18 18:34:27,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:27,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5797700] [2022-11-18 18:34:27,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:27,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:27,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:27,688 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:27,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:27,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:27,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:27,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:34:27,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1295, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:34:27,733 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:28,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:28,605 INFO L93 Difference]: Finished difference Result 151 states and 187 transitions. [2022-11-18 18:34:28,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 187 transitions. [2022-11-18 18:34:28,606 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 22 [2022-11-18 18:34:28,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 150 states and 186 transitions. [2022-11-18 18:34:28,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-18 18:34:28,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-18 18:34:28,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150 states and 186 transitions. [2022-11-18 18:34:28,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:28,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150 states and 186 transitions. [2022-11-18 18:34:28,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states and 186 transitions. [2022-11-18 18:34:28,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 129. [2022-11-18 18:34:28,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.2635658914728682) internal successors, (163), 128 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:28,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 163 transitions. [2022-11-18 18:34:28,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 163 transitions. [2022-11-18 18:34:28,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 18:34:28,611 INFO L428 stractBuchiCegarLoop]: Abstraction has 129 states and 163 transitions. [2022-11-18 18:34:28,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-18 18:34:28,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 163 transitions. [2022-11-18 18:34:28,612 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 20 [2022-11-18 18:34:28,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:28,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:28,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:28,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:34:28,613 INFO L748 eck$LassoCheckResult]: Stem: 13845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13856#L367 assume !(main_~length~0#1 < 1); 13847#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13848#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13849#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13902#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13900#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13899#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13896#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13895#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13893#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13889#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13890#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13862#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13863#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13905#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13938#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13875#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13936#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13933#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13932#L370-4 main_~j~0#1 := 0; 13931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13930#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13929#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13928#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13926#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13925#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13924#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13922#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13920#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13918#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13917#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13916#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13911#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13957#L378-2 [2022-11-18 18:34:28,613 INFO L750 eck$LassoCheckResult]: Loop: 13957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13959#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13956#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13957#L378-2 [2022-11-18 18:34:28,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:28,614 INFO L85 PathProgramCache]: Analyzing trace with hash 568849027, now seen corresponding path program 20 times [2022-11-18 18:34:28,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:28,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498183402] [2022-11-18 18:34:28,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:28,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:28,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 0 proven. 248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:29,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:29,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498183402] [2022-11-18 18:34:29,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498183402] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:29,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [177229215] [2022-11-18 18:34:29,498 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:34:29,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:29,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:29,502 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:29,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-18 18:34:29,682 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:34:29,682 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:29,685 INFO L263 TraceCheckSpWp]: Trace formula consists of 302 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-18 18:34:29,687 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:30,082 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:30,226 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:34:30,227 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:34:30,234 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:34:30,234 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:34:30,289 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:34:30,289 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:34:30,833 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:34:30,836 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:30,836 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:31,180 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:34:31,182 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:34:31,262 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 246 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:34:31,262 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [177229215] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:31,262 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:31,262 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 25] total 52 [2022-11-18 18:34:31,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605843919] [2022-11-18 18:34:31,262 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:31,263 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:31,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:31,263 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 1 times [2022-11-18 18:34:31,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:31,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374653005] [2022-11-18 18:34:31,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:31,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:31,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:31,267 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:31,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:31,270 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:31,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:31,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-18 18:34:31,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=2554, Unknown=0, NotChecked=0, Total=2756 [2022-11-18 18:34:31,356 INFO L87 Difference]: Start difference. First operand 129 states and 163 transitions. cyclomatic complexity: 41 Second operand has 53 states, 52 states have (on average 2.3076923076923075) internal successors, (120), 53 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:32,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:32,589 INFO L93 Difference]: Finished difference Result 128 states and 152 transitions. [2022-11-18 18:34:32,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 152 transitions. [2022-11-18 18:34:32,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:32,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 126 states and 150 transitions. [2022-11-18 18:34:32,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-18 18:34:32,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-18 18:34:32,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 150 transitions. [2022-11-18 18:34:32,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:32,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126 states and 150 transitions. [2022-11-18 18:34:32,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 150 transitions. [2022-11-18 18:34:32,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 87. [2022-11-18 18:34:32,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.2528735632183907) internal successors, (109), 86 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:32,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 109 transitions. [2022-11-18 18:34:32,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 109 transitions. [2022-11-18 18:34:32,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-18 18:34:32,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 87 states and 109 transitions. [2022-11-18 18:34:32,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-18 18:34:32,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 109 transitions. [2022-11-18 18:34:32,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:32,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:32,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:32,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:32,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:32,606 INFO L748 eck$LassoCheckResult]: Stem: 14522#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14533#L367 assume !(main_~length~0#1 < 1); 14524#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14525#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14526#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14534#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14600#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14597#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14594#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14592#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14591#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14587#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14537#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14606#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14605#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14604#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14550#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14548#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14527#L370-4 main_~j~0#1 := 0; 14528#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14540#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14531#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14560#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14559#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14558#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14557#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14556#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14555#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14554#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14553#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14552#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14551#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14549#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14547#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14546#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14543#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14529#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14530#L378-2 [2022-11-18 18:34:32,607 INFO L750 eck$LassoCheckResult]: Loop: 14530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14544#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14530#L378-2 [2022-11-18 18:34:32,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:32,607 INFO L85 PathProgramCache]: Analyzing trace with hash 1706930125, now seen corresponding path program 21 times [2022-11-18 18:34:32,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:32,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490813101] [2022-11-18 18:34:32,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:32,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:32,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:33,073 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:33,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:33,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490813101] [2022-11-18 18:34:33,074 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490813101] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:33,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1260239644] [2022-11-18 18:34:33,074 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:34:33,074 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:33,074 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:33,079 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:33,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-18 18:34:33,916 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 18:34:33,916 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:33,919 INFO L263 TraceCheckSpWp]: Trace formula consists of 302 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 18:34:33,921 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:34,316 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:34,316 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:34,613 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:34,613 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1260239644] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:34,614 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:34,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-18 18:34:34,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998109537] [2022-11-18 18:34:34,617 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:34,617 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:34,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:34,617 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-18 18:34:34,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:34,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735524646] [2022-11-18 18:34:34,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:34,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:34,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:34,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:34,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:34,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:34,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:34,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:34:34,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:34:34,674 INFO L87 Difference]: Start difference. First operand 87 states and 109 transitions. cyclomatic complexity: 27 Second operand has 38 states, 38 states have (on average 2.3157894736842106) internal successors, (88), 38 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:35,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:35,001 INFO L93 Difference]: Finished difference Result 115 states and 138 transitions. [2022-11-18 18:34:35,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 138 transitions. [2022-11-18 18:34:35,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:35,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 93 states and 116 transitions. [2022-11-18 18:34:35,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:34:35,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:34:35,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 116 transitions. [2022-11-18 18:34:35,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:35,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 116 transitions. [2022-11-18 18:34:35,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 116 transitions. [2022-11-18 18:34:35,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 75. [2022-11-18 18:34:35,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.24) internal successors, (93), 74 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:35,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 93 transitions. [2022-11-18 18:34:35,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 93 transitions. [2022-11-18 18:34:35,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:34:35,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 93 transitions. [2022-11-18 18:34:35,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-18 18:34:35,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 93 transitions. [2022-11-18 18:34:35,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:35,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:35,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:35,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:35,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:35,007 INFO L748 eck$LassoCheckResult]: Stem: 15137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15148#L367 assume !(main_~length~0#1 < 1); 15139#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15140#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15151#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15206#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15204#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15203#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15202#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15200#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15198#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15197#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15194#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15191#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15189#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15186#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15188#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15173#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15176#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15175#L370-4 main_~j~0#1 := 0; 15152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15144#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15171#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15170#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15169#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15168#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15167#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15165#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15164#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15163#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15161#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15160#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15159#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15156#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15155#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15142#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15143#L378-2 [2022-11-18 18:34:35,007 INFO L750 eck$LassoCheckResult]: Loop: 15143#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15157#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15143#L378-2 [2022-11-18 18:34:35,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:35,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1414945998, now seen corresponding path program 22 times [2022-11-18 18:34:35,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:35,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184987203] [2022-11-18 18:34:35,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:35,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:35,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:35,878 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:35,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:35,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184987203] [2022-11-18 18:34:35,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184987203] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:35,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [442068403] [2022-11-18 18:34:35,878 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:34:35,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:35,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:35,882 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:35,884 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-18 18:34:36,070 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:34:36,070 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:36,072 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-18 18:34:36,074 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:36,172 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:36,290 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:34:36,290 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:34:36,312 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:34:36,313 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:34:36,717 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:34:36,719 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:36,719 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:36,981 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:34:36,983 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:34:37,088 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:37,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [442068403] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:37,088 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:37,089 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-11-18 18:34:37,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918895807] [2022-11-18 18:34:37,089 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:37,089 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:37,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:37,089 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-18 18:34:37,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:37,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799266829] [2022-11-18 18:34:37,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:37,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:37,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:37,093 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:37,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:37,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:37,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:37,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:34:37,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=1525, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:34:37,146 INFO L87 Difference]: Start difference. First operand 75 states and 93 transitions. cyclomatic complexity: 23 Second operand has 41 states, 40 states have (on average 2.225) internal successors, (89), 41 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:38,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:38,298 INFO L93 Difference]: Finished difference Result 158 states and 185 transitions. [2022-11-18 18:34:38,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158 states and 185 transitions. [2022-11-18 18:34:38,300 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 18:34:38,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158 states to 157 states and 184 transitions. [2022-11-18 18:34:38,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-18 18:34:38,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-18 18:34:38,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157 states and 184 transitions. [2022-11-18 18:34:38,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:38,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 157 states and 184 transitions. [2022-11-18 18:34:38,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states and 184 transitions. [2022-11-18 18:34:38,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 81. [2022-11-18 18:34:38,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.271604938271605) internal successors, (103), 80 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:38,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 103 transitions. [2022-11-18 18:34:38,304 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81 states and 103 transitions. [2022-11-18 18:34:38,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2022-11-18 18:34:38,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 81 states and 103 transitions. [2022-11-18 18:34:38,309 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-18 18:34:38,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 103 transitions. [2022-11-18 18:34:38,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:34:38,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:38,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:38,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:38,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:34:38,313 INFO L748 eck$LassoCheckResult]: Stem: 15792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15803#L367 assume !(main_~length~0#1 < 1); 15794#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15795#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15804#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15807#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15845#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15842#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15841#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15839#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15837#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15836#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15835#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15834#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15833#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15832#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15830#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15827#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15825#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15824#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15823#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15822#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15820#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15811#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15797#L370-4 main_~j~0#1 := 0; 15798#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15864#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15801#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15863#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15857#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15855#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15853#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15851#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15850#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15848#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15847#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15799#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15800#L378-2 [2022-11-18 18:34:38,313 INFO L750 eck$LassoCheckResult]: Loop: 15800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15849#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15800#L378-2 [2022-11-18 18:34:38,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:38,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1229278031, now seen corresponding path program 23 times [2022-11-18 18:34:38,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:38,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805556217] [2022-11-18 18:34:38,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:38,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:38,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:39,076 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:39,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:39,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805556217] [2022-11-18 18:34:39,077 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805556217] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:39,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1147961789] [2022-11-18 18:34:39,077 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:34:39,077 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:39,077 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:39,082 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:39,102 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-18 18:34:39,411 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-18 18:34:39,411 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:39,414 INFO L263 TraceCheckSpWp]: Trace formula consists of 316 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-18 18:34:39,415 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:39,870 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:34:40,737 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:34:40,739 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:34:40,740 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:34:40,743 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:40,743 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:41,055 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:34:41,057 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:34:41,150 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:41,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1147961789] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:41,150 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:41,150 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 27] total 56 [2022-11-18 18:34:41,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018711908] [2022-11-18 18:34:41,150 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:41,151 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:34:41,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:41,151 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-18 18:34:41,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:41,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908779975] [2022-11-18 18:34:41,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:41,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:41,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:41,154 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:34:41,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:34:41,157 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:34:41,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:41,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2022-11-18 18:34:41,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=2980, Unknown=0, NotChecked=0, Total=3192 [2022-11-18 18:34:41,205 INFO L87 Difference]: Start difference. First operand 81 states and 103 transitions. cyclomatic complexity: 27 Second operand has 57 states, 56 states have (on average 2.25) internal successors, (126), 57 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:42,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:42,802 INFO L93 Difference]: Finished difference Result 162 states and 201 transitions. [2022-11-18 18:34:42,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162 states and 201 transitions. [2022-11-18 18:34:42,803 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 25 [2022-11-18 18:34:42,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162 states to 161 states and 200 transitions. [2022-11-18 18:34:42,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2022-11-18 18:34:42,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2022-11-18 18:34:42,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161 states and 200 transitions. [2022-11-18 18:34:42,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:34:42,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 161 states and 200 transitions. [2022-11-18 18:34:42,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states and 200 transitions. [2022-11-18 18:34:42,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 136. [2022-11-18 18:34:42,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.2720588235294117) internal successors, (173), 135 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:42,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 173 transitions. [2022-11-18 18:34:42,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 173 transitions. [2022-11-18 18:34:42,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-18 18:34:42,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 136 states and 173 transitions. [2022-11-18 18:34:42,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-18 18:34:42,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 173 transitions. [2022-11-18 18:34:42,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:34:42,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:34:42,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:34:42,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:42,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:34:42,812 INFO L748 eck$LassoCheckResult]: Stem: 16469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16480#L367 assume !(main_~length~0#1 < 1); 16471#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16472#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16481#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16485#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16523#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16521#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16520#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16517#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16514#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16511#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16508#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16507#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16505#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16504#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16502#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16497#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16559#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16556#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16554#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16553#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16551#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16550#L370-4 main_~j~0#1 := 0; 16549#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16548#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16547#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16546#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16543#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16542#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16536#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16534#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16532#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16525#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16526#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16586#L378-2 [2022-11-18 18:34:42,813 INFO L750 eck$LassoCheckResult]: Loop: 16586#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16585#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16586#L378-2 [2022-11-18 18:34:42,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:42,813 INFO L85 PathProgramCache]: Analyzing trace with hash -719241402, now seen corresponding path program 24 times [2022-11-18 18:34:42,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:42,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081576020] [2022-11-18 18:34:42,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:42,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:42,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:43,676 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:43,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:43,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081576020] [2022-11-18 18:34:43,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081576020] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:43,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1091277049] [2022-11-18 18:34:43,677 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:34:43,677 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:43,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:43,684 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:43,705 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-18 18:34:44,605 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2022-11-18 18:34:44,606 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:34:44,609 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-18 18:34:44,611 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:45,047 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:34:45,151 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:34:45,162 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:34:45,285 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:34:45,286 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:34:45,289 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:34:45,289 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 18:34:46,018 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:34:46,018 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-18 18:34:46,057 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:34:46,057 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:05,062 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 31 [2022-11-18 18:36:05,076 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 249 treesize of output 241 [2022-11-18 18:36:05,815 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 299 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:05,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1091277049] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:05,816 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:05,816 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 28, 27] total 78 [2022-11-18 18:36:05,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377056477] [2022-11-18 18:36:05,816 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:05,816 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:05,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:05,817 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-18 18:36:05,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:05,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670974155] [2022-11-18 18:36:05,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:05,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:05,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:05,821 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:05,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:05,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:05,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:05,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2022-11-18 18:36:05,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=5780, Unknown=10, NotChecked=0, Total=6162 [2022-11-18 18:36:05,928 INFO L87 Difference]: Start difference. First operand 136 states and 173 transitions. cyclomatic complexity: 44 Second operand has 79 states, 78 states have (on average 2.3205128205128207) internal successors, (181), 79 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:08,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:08,638 INFO L93 Difference]: Finished difference Result 273 states and 324 transitions. [2022-11-18 18:36:08,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 273 states and 324 transitions. [2022-11-18 18:36:08,639 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26 [2022-11-18 18:36:08,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 273 states to 270 states and 321 transitions. [2022-11-18 18:36:08,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2022-11-18 18:36:08,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2022-11-18 18:36:08,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 321 transitions. [2022-11-18 18:36:08,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:08,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 321 transitions. [2022-11-18 18:36:08,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 321 transitions. [2022-11-18 18:36:08,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 142. [2022-11-18 18:36:08,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 142 states have (on average 1.2887323943661972) internal successors, (183), 141 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:08,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 183 transitions. [2022-11-18 18:36:08,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142 states and 183 transitions. [2022-11-18 18:36:08,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-18 18:36:08,649 INFO L428 stractBuchiCegarLoop]: Abstraction has 142 states and 183 transitions. [2022-11-18 18:36:08,649 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-18 18:36:08,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142 states and 183 transitions. [2022-11-18 18:36:08,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:08,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:08,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:08,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:08,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:36:08,651 INFO L748 eck$LassoCheckResult]: Stem: 17369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17380#L367 assume !(main_~length~0#1 < 1); 17371#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17372#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17381#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17384#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17386#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17425#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17422#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17420#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17419#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17416#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17414#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17413#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17412#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17411#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17410#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17409#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17407#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17405#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17404#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17399#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17401#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17382#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17383#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17459#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17457#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17454#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17456#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17477#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17476#L370-4 main_~j~0#1 := 0; 17475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17474#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17473#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17470#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17466#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17464#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17463#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17462#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17461#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17429#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17432#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17430#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17433#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17377#L378-2 [2022-11-18 18:36:08,651 INFO L750 eck$LassoCheckResult]: Loop: 17377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17426#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17377#L378-2 [2022-11-18 18:36:08,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:08,651 INFO L85 PathProgramCache]: Analyzing trace with hash -562595642, now seen corresponding path program 25 times [2022-11-18 18:36:08,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:08,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22089470] [2022-11-18 18:36:08,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:08,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:08,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:09,667 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:09,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:09,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22089470] [2022-11-18 18:36:09,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [22089470] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:09,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1877022273] [2022-11-18 18:36:09,668 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:36:09,668 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:09,668 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:09,671 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:09,672 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-18 18:36:09,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:09,849 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-18 18:36:09,852 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:10,296 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:36:10,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:36:10,470 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:36:10,527 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:36:10,528 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:36:10,539 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:36:11,209 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:36:11,211 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:11,211 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:11,766 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-18 18:36:11,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 61 [2022-11-18 18:36:11,881 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:11,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1877022273] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:11,882 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:11,882 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 28] total 58 [2022-11-18 18:36:11,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038897825] [2022-11-18 18:36:11,882 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:11,883 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:11,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:11,883 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-18 18:36:11,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:11,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530372859] [2022-11-18 18:36:11,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:11,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:11,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:11,886 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:11,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:11,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:11,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:11,940 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 18:36:11,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=3190, Unknown=0, NotChecked=0, Total=3422 [2022-11-18 18:36:11,941 INFO L87 Difference]: Start difference. First operand 142 states and 183 transitions. cyclomatic complexity: 50 Second operand has 59 states, 58 states have (on average 2.2586206896551726) internal successors, (131), 59 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:14,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:14,544 INFO L93 Difference]: Finished difference Result 493 states and 572 transitions. [2022-11-18 18:36:14,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 493 states and 572 transitions. [2022-11-18 18:36:14,546 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 30 [2022-11-18 18:36:14,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 493 states to 487 states and 566 transitions. [2022-11-18 18:36:14,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78 [2022-11-18 18:36:14,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78 [2022-11-18 18:36:14,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 566 transitions. [2022-11-18 18:36:14,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:14,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 566 transitions. [2022-11-18 18:36:14,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 566 transitions. [2022-11-18 18:36:14,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 163. [2022-11-18 18:36:14,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.3374233128834356) internal successors, (218), 162 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:14,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 218 transitions. [2022-11-18 18:36:14,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163 states and 218 transitions. [2022-11-18 18:36:14,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-11-18 18:36:14,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 163 states and 218 transitions. [2022-11-18 18:36:14,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-18 18:36:14,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 218 transitions. [2022-11-18 18:36:14,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:14,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:14,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:14,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:14,563 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:36:14,563 INFO L748 eck$LassoCheckResult]: Stem: 18515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18526#L367 assume !(main_~length~0#1 < 1); 18517#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18518#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18527#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18613#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18602#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18601#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18600#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18595#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18594#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18593#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18592#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18591#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18590#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18589#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18588#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18586#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18587#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18654#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18534#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18568#L370-4 main_~j~0#1 := 0; 18650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18649#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18522#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18523#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18628#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18627#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18626#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18624#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18621#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18617#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18616#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18615#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18539#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18543#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18521#L378-2 [2022-11-18 18:36:14,563 INFO L750 eck$LassoCheckResult]: Loop: 18521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18536#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18521#L378-2 [2022-11-18 18:36:14,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:14,564 INFO L85 PathProgramCache]: Analyzing trace with hash 220184660, now seen corresponding path program 26 times [2022-11-18 18:36:14,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:14,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271218909] [2022-11-18 18:36:14,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:14,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:14,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:15,100 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:15,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:15,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271218909] [2022-11-18 18:36:15,101 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271218909] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:15,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1658642896] [2022-11-18 18:36:15,101 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:36:15,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:15,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:15,110 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:15,111 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-18 18:36:15,299 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:36:15,300 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:36:15,301 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 18:36:15,302 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:15,772 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:15,772 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:16,130 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:16,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1658642896] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:16,130 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:16,130 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 41 [2022-11-18 18:36:16,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007944762] [2022-11-18 18:36:16,130 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:16,131 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:16,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:16,131 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-18 18:36:16,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:16,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87466804] [2022-11-18 18:36:16,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:16,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:16,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:16,134 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:16,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:16,136 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:16,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:16,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:36:16,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=1258, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:36:16,184 INFO L87 Difference]: Start difference. First operand 163 states and 218 transitions. cyclomatic complexity: 64 Second operand has 41 states, 41 states have (on average 2.317073170731707) internal successors, (95), 41 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:16,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:16,578 INFO L93 Difference]: Finished difference Result 193 states and 249 transitions. [2022-11-18 18:36:16,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 249 transitions. [2022-11-18 18:36:16,579 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:16,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 169 states and 223 transitions. [2022-11-18 18:36:16,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-18 18:36:16,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-18 18:36:16,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 169 states and 223 transitions. [2022-11-18 18:36:16,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:16,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 169 states and 223 transitions. [2022-11-18 18:36:16,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states and 223 transitions. [2022-11-18 18:36:16,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 165. [2022-11-18 18:36:16,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 165 states, 165 states have (on average 1.3212121212121213) internal successors, (218), 164 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:16,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 218 transitions. [2022-11-18 18:36:16,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 165 states and 218 transitions. [2022-11-18 18:36:16,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 18:36:16,585 INFO L428 stractBuchiCegarLoop]: Abstraction has 165 states and 218 transitions. [2022-11-18 18:36:16,585 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-18 18:36:16,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 165 states and 218 transitions. [2022-11-18 18:36:16,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:16,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:16,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:16,587 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:16,587 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:36:16,587 INFO L748 eck$LassoCheckResult]: Stem: 19319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19330#L367 assume !(main_~length~0#1 < 1); 19321#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19322#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19331#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19458#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19457#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19455#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19453#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19452#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19451#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19450#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19449#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19447#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19446#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19444#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19443#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19441#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19440#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19437#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19436#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19435#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19434#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19432#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19431#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19338#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19335#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19337#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19333#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19344#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19328#L370-4 main_~j~0#1 := 0; 19329#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19334#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19386#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19384#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19382#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19380#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19378#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19368#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19364#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19349#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19355#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19350#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19351#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19352#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19325#L378-2 [2022-11-18 18:36:16,588 INFO L750 eck$LassoCheckResult]: Loop: 19325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19464#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19325#L378-2 [2022-11-18 18:36:16,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:16,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1622914383, now seen corresponding path program 27 times [2022-11-18 18:36:16,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:16,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671730419] [2022-11-18 18:36:16,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:16,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:16,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:17,603 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:17,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:17,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671730419] [2022-11-18 18:36:17,604 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671730419] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:17,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1065205346] [2022-11-18 18:36:17,604 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:36:17,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:17,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:17,611 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:17,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-18 18:36:18,457 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2022-11-18 18:36:18,457 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:36:18,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 338 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 18:36:18,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:18,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:36:19,031 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:36:19,032 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-18 18:36:19,156 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:36:19,157 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-18 18:36:22,614 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 18:36:22,614 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-18 18:36:22,653 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 100 proven. 220 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:22,653 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:36,627 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:36:36,631 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-18 18:36:37,024 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 90 proven. 228 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:36:37,024 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1065205346] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:37,024 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:37,024 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 31, 28] total 72 [2022-11-18 18:36:37,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031325203] [2022-11-18 18:36:37,025 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:37,025 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:37,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:37,025 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-18 18:36:37,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:37,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444968616] [2022-11-18 18:36:37,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:37,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:37,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:37,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:37,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:37,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:37,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:37,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2022-11-18 18:36:37,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=4673, Unknown=1, NotChecked=0, Total=5256 [2022-11-18 18:36:37,080 INFO L87 Difference]: Start difference. First operand 165 states and 218 transitions. cyclomatic complexity: 62 Second operand has 73 states, 72 states have (on average 2.125) internal successors, (153), 73 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:42,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:42,934 INFO L93 Difference]: Finished difference Result 444 states and 553 transitions. [2022-11-18 18:36:42,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 444 states and 553 transitions. [2022-11-18 18:36:42,937 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:42,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 444 states to 395 states and 496 transitions. [2022-11-18 18:36:42,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2022-11-18 18:36:42,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2022-11-18 18:36:42,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 395 states and 496 transitions. [2022-11-18 18:36:42,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:42,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 395 states and 496 transitions. [2022-11-18 18:36:42,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states and 496 transitions. [2022-11-18 18:36:42,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 241. [2022-11-18 18:36:42,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 241 states, 241 states have (on average 1.2987551867219918) internal successors, (313), 240 states have internal predecessors, (313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:42,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 313 transitions. [2022-11-18 18:36:42,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 241 states and 313 transitions. [2022-11-18 18:36:42,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2022-11-18 18:36:42,947 INFO L428 stractBuchiCegarLoop]: Abstraction has 241 states and 313 transitions. [2022-11-18 18:36:42,947 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-18 18:36:42,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 241 states and 313 transitions. [2022-11-18 18:36:42,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:42,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:42,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:42,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:42,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:36:42,949 INFO L748 eck$LassoCheckResult]: Stem: 20501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20512#L367 assume !(main_~length~0#1 < 1); 20503#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20504#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20505#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20513#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20584#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20615#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20614#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20573#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20610#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20609#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20569#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20607#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20604#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20557#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20601#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20600#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20599#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20597#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20594#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20596#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20514#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20515#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20694#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20689#L370-4 main_~j~0#1 := 0; 20516#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20517#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20675#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20674#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20672#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20668#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20666#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20621#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20625#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20507#L378-2 [2022-11-18 18:36:42,949 INFO L750 eck$LassoCheckResult]: Loop: 20507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20618#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20507#L378-2 [2022-11-18 18:36:42,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:42,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1062214605, now seen corresponding path program 28 times [2022-11-18 18:36:42,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:42,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524902465] [2022-11-18 18:36:42,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:42,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:42,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:43,881 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:43,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:43,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524902465] [2022-11-18 18:36:43,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524902465] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:43,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846597489] [2022-11-18 18:36:43,882 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:36:43,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:43,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:43,884 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:43,886 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-18 18:36:44,073 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:36:44,073 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:36:44,076 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 55 conjunts are in the unsatisfiable core [2022-11-18 18:36:44,078 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:44,181 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:36:44,311 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:36:44,311 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:36:44,334 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:36:44,334 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:36:44,881 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:36:44,883 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:44,883 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:45,196 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:36:45,199 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:36:45,312 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:45,313 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1846597489] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:45,313 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:45,313 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2022-11-18 18:36:45,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023625411] [2022-11-18 18:36:45,313 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:45,313 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:45,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:45,314 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-18 18:36:45,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:45,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982052886] [2022-11-18 18:36:45,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:45,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:45,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:45,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:45,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:45,319 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:45,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:45,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-18 18:36:45,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1769, Unknown=0, NotChecked=0, Total=1892 [2022-11-18 18:36:45,370 INFO L87 Difference]: Start difference. First operand 241 states and 313 transitions. cyclomatic complexity: 82 Second operand has 44 states, 43 states have (on average 2.2325581395348837) internal successors, (96), 44 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:46,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:46,874 INFO L93 Difference]: Finished difference Result 332 states and 414 transitions. [2022-11-18 18:36:46,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 332 states and 414 transitions. [2022-11-18 18:36:46,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26 [2022-11-18 18:36:46,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 332 states to 331 states and 413 transitions. [2022-11-18 18:36:46,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2022-11-18 18:36:46,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2022-11-18 18:36:46,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 331 states and 413 transitions. [2022-11-18 18:36:46,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:46,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 331 states and 413 transitions. [2022-11-18 18:36:46,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states and 413 transitions. [2022-11-18 18:36:46,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 249. [2022-11-18 18:36:46,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 249 states have (on average 1.3092369477911647) internal successors, (326), 248 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:46,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 326 transitions. [2022-11-18 18:36:46,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 249 states and 326 transitions. [2022-11-18 18:36:46,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-18 18:36:46,886 INFO L428 stractBuchiCegarLoop]: Abstraction has 249 states and 326 transitions. [2022-11-18 18:36:46,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-18 18:36:46,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 326 transitions. [2022-11-18 18:36:46,887 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:36:46,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:46,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:46,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:46,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:36:46,890 INFO L748 eck$LassoCheckResult]: Stem: 21531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21542#L367 assume !(main_~length~0#1 < 1); 21533#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21534#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21543#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21623#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21608#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21593#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21581#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21573#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21633#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21568#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21548#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21740#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21550#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21551#L370-4 main_~j~0#1 := 0; 21546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21547#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21705#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21703#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21701#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21699#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21697#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21696#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21695#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21694#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21652#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21654#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21657#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21537#L378-2 [2022-11-18 18:36:46,890 INFO L750 eck$LassoCheckResult]: Loop: 21537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21653#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21537#L378-2 [2022-11-18 18:36:46,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:46,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1669916558, now seen corresponding path program 29 times [2022-11-18 18:36:46,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:46,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805380857] [2022-11-18 18:36:46,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:46,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:46,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:47,819 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:47,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:47,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805380857] [2022-11-18 18:36:47,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805380857] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:47,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [679918321] [2022-11-18 18:36:47,819 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:36:47,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:47,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:47,833 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:47,834 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-18 18:36:48,193 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-11-18 18:36:48,194 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:36:48,197 INFO L263 TraceCheckSpWp]: Trace formula consists of 357 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-18 18:36:48,199 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:48,774 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:36:49,870 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:36:49,872 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:36:49,873 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:36:49,876 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:49,876 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:36:50,189 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:36:50,192 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:36:50,335 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:50,335 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [679918321] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:36:50,335 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:36:50,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29] total 60 [2022-11-18 18:36:50,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719588434] [2022-11-18 18:36:50,335 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:36:50,336 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:36:50,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:50,336 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-18 18:36:50,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:50,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910080513] [2022-11-18 18:36:50,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:50,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:50,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:50,339 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:36:50,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:36:50,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:36:50,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:36:50,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-11-18 18:36:50,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=227, Invalid=3433, Unknown=0, NotChecked=0, Total=3660 [2022-11-18 18:36:50,388 INFO L87 Difference]: Start difference. First operand 249 states and 326 transitions. cyclomatic complexity: 87 Second operand has 61 states, 60 states have (on average 2.2666666666666666) internal successors, (136), 61 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:52,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:36:52,329 INFO L93 Difference]: Finished difference Result 366 states and 467 transitions. [2022-11-18 18:36:52,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 467 transitions. [2022-11-18 18:36:52,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48 [2022-11-18 18:36:52,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 365 states and 466 transitions. [2022-11-18 18:36:52,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2022-11-18 18:36:52,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2022-11-18 18:36:52,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 365 states and 466 transitions. [2022-11-18 18:36:52,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:36:52,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 365 states and 466 transitions. [2022-11-18 18:36:52,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365 states and 466 transitions. [2022-11-18 18:36:52,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365 to 337. [2022-11-18 18:36:52,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 337 states, 337 states have (on average 1.2937685459940653) internal successors, (436), 336 states have internal predecessors, (436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:36:52,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 436 transitions. [2022-11-18 18:36:52,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 337 states and 436 transitions. [2022-11-18 18:36:52,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-18 18:36:52,348 INFO L428 stractBuchiCegarLoop]: Abstraction has 337 states and 436 transitions. [2022-11-18 18:36:52,348 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-18 18:36:52,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states and 436 transitions. [2022-11-18 18:36:52,350 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-18 18:36:52,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:36:52,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:36:52,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 11, 10, 9, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:36:52,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:36:52,352 INFO L748 eck$LassoCheckResult]: Stem: 22614#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22625#L367 assume !(main_~length~0#1 < 1); 22616#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22617#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22626#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22707#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22701#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22696#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22695#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22690#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22689#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22685#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22683#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22679#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22677#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22671#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22666#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22663#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22658#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22719#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22650#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22631#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22836#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22830#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22828#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22824#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22770#L370-4 main_~j~0#1 := 0; 22820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22816#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22814#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22812#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22810#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22808#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22806#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22802#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22798#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22796#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22794#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22786#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22787#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22779#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22740#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22741#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22792#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22909#L378-2 [2022-11-18 18:36:52,352 INFO L750 eck$LassoCheckResult]: Loop: 22909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22917#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22908#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22909#L378-2 [2022-11-18 18:36:52,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:36:52,353 INFO L85 PathProgramCache]: Analyzing trace with hash -2004200815, now seen corresponding path program 30 times [2022-11-18 18:36:52,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:36:52,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978832865] [2022-11-18 18:36:52,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:36:52,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:36:52,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:36:53,371 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 0 proven. 357 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:36:53,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:36:53,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978832865] [2022-11-18 18:36:53,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978832865] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:36:53,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [387605215] [2022-11-18 18:36:53,372 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:36:53,372 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:36:53,372 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:36:53,380 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:36:53,400 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-18 18:36:54,372 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2022-11-18 18:36:54,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:36:54,376 INFO L263 TraceCheckSpWp]: Trace formula consists of 368 conjuncts, 52 conjunts are in the unsatisfiable core [2022-11-18 18:36:54,379 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:36:54,722 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:36:54,820 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:36:54,828 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:36:54,949 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:36:54,950 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 42 [2022-11-18 18:36:54,964 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:36:54,964 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 42 [2022-11-18 18:36:55,114 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 57 [2022-11-18 18:37:05,080 INFO L321 Elim1Store]: treesize reduction 14, result has 74.5 percent of original size [2022-11-18 18:37:05,080 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 59 treesize of output 56 [2022-11-18 18:37:05,164 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 100 proven. 257 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:37:05,164 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:37:07,685 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 18:37:07,689 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 22 [2022-11-18 18:37:08,072 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 90 proven. 254 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-18 18:37:08,072 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [387605215] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:37:08,072 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:37:08,072 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 33, 27] total 76 [2022-11-18 18:37:08,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103816594] [2022-11-18 18:37:08,073 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:37:08,073 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:37:08,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:37:08,073 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2022-11-18 18:37:08,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:37:08,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884255567] [2022-11-18 18:37:08,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:37:08,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:37:08,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:37:08,077 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:37:08,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:37:08,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:37:08,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:37:08,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2022-11-18 18:37:08,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=574, Invalid=5276, Unknown=2, NotChecked=0, Total=5852 [2022-11-18 18:37:08,184 INFO L87 Difference]: Start difference. First operand 337 states and 436 transitions. cyclomatic complexity: 112 Second operand has 77 states, 76 states have (on average 2.1842105263157894) internal successors, (166), 77 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:39:05,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:39:05,872 INFO L93 Difference]: Finished difference Result 711 states and 859 transitions. [2022-11-18 18:39:05,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 711 states and 859 transitions. [2022-11-18 18:39:05,876 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-18 18:39:05,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 711 states to 387 states and 473 transitions. [2022-11-18 18:39:05,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83 [2022-11-18 18:39:05,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2022-11-18 18:39:05,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387 states and 473 transitions. [2022-11-18 18:39:05,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:39:05,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 387 states and 473 transitions. [2022-11-18 18:39:05,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states and 473 transitions. [2022-11-18 18:39:05,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 193. [2022-11-18 18:39:05,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 193 states have (on average 1.2487046632124352) internal successors, (241), 192 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:39:05,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 241 transitions. [2022-11-18 18:39:05,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193 states and 241 transitions. [2022-11-18 18:39:05,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 181 states. [2022-11-18 18:39:05,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 193 states and 241 transitions. [2022-11-18 18:39:05,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-18 18:39:05,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 241 transitions. [2022-11-18 18:39:05,886 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-18 18:39:05,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:39:05,887 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:39:05,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 12, 10, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:39:05,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:39:05,888 INFO L748 eck$LassoCheckResult]: Stem: 24500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24509#L367 assume !(main_~length~0#1 < 1); 24502#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24503#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24510#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24569#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24568#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24513#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24514#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24511#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24512#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24565#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24564#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24563#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24559#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24557#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24554#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24553#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24552#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24551#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24550#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24541#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24536#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24534#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24548#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24546#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24531#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24543#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24527#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24539#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24517#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24518#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24516#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24505#L370-4 main_~j~0#1 := 0; 24506#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24515#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24589#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24588#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24587#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24586#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24585#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24584#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24583#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24581#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24580#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24577#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24574#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24570#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24508#L378-2 [2022-11-18 18:39:05,888 INFO L750 eck$LassoCheckResult]: Loop: 24508#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24571#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24508#L378-2 [2022-11-18 18:39:05,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:39:05,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1909429774, now seen corresponding path program 31 times [2022-11-18 18:39:05,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:39:05,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713185047] [2022-11-18 18:39:05,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:39:05,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:39:05,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:39:07,448 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 18 proven. 402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:39:07,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:39:07,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713185047] [2022-11-18 18:39:07,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713185047] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:39:07,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [115424087] [2022-11-18 18:39:07,450 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:39:07,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:39:07,450 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:39:07,451 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:39:07,456 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1fbbcc84-36f8-46c3-ab99-7a15c1fba2b0/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-11-18 18:39:07,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:39:07,670 INFO L263 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 76 conjunts are in the unsatisfiable core [2022-11-18 18:39:07,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:39:08,198 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:39:08,387 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:39:08,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:39:08,485 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:39:08,495 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:39:08,569 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:39:08,570 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:39:08,583 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:39:08,583 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:39:08,654 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:39:08,655 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:39:08,736 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:39:09,507 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:39:09,509 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:39:09,510 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:39:11,136 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 53 [2022-11-18 18:39:11,155 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 70137 treesize of output 69625