./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array13_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array13_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash bcb4bc0abad87560c498c61782d3ccf631503b41762d0db8553a6c831cbdcaff --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 18:49:44,358 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 18:49:44,364 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 18:49:44,400 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 18:49:44,401 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 18:49:44,405 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 18:49:44,407 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 18:49:44,412 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 18:49:44,414 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 18:49:44,417 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 18:49:44,419 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 18:49:44,423 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 18:49:44,424 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 18:49:44,429 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 18:49:44,432 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 18:49:44,434 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 18:49:44,435 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 18:49:44,438 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 18:49:44,445 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 18:49:44,448 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 18:49:44,453 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 18:49:44,454 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 18:49:44,456 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 18:49:44,459 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 18:49:44,465 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 18:49:44,471 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 18:49:44,472 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 18:49:44,473 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 18:49:44,475 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 18:49:44,476 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 18:49:44,478 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 18:49:44,479 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 18:49:44,480 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 18:49:44,482 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 18:49:44,483 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 18:49:44,484 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 18:49:44,486 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 18:49:44,486 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 18:49:44,486 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 18:49:44,487 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 18:49:44,488 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 18:49:44,489 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-18 18:49:44,535 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 18:49:44,535 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 18:49:44,536 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 18:49:44,536 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 18:49:44,538 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 18:49:44,538 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 18:49:44,539 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 18:49:44,539 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 18:49:44,539 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 18:49:44,540 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 18:49:44,541 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 18:49:44,541 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 18:49:44,541 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 18:49:44,542 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 18:49:44,542 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 18:49:44,542 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 18:49:44,543 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 18:49:44,543 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 18:49:44,543 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 18:49:44,543 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 18:49:44,544 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 18:49:44,544 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 18:49:44,544 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 18:49:44,544 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 18:49:44,545 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 18:49:44,545 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 18:49:44,545 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 18:49:44,546 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 18:49:44,547 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 18:49:44,547 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcb4bc0abad87560c498c61782d3ccf631503b41762d0db8553a6c831cbdcaff [2022-11-18 18:49:44,872 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 18:49:44,912 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 18:49:44,915 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 18:49:44,916 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 18:49:44,919 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 18:49:44,920 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/termination-15/array13_alloca.i [2022-11-18 18:49:45,000 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/data/e0fe07f6c/fabff007817447a589537a8a289572c1/FLAGba025404d [2022-11-18 18:49:45,697 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 18:49:45,698 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/sv-benchmarks/c/termination-15/array13_alloca.i [2022-11-18 18:49:45,720 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/data/e0fe07f6c/fabff007817447a589537a8a289572c1/FLAGba025404d [2022-11-18 18:49:45,953 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/data/e0fe07f6c/fabff007817447a589537a8a289572c1 [2022-11-18 18:49:45,956 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 18:49:45,958 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 18:49:45,960 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 18:49:45,960 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 18:49:45,964 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 18:49:45,965 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:49:45" (1/1) ... [2022-11-18 18:49:45,966 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@79e1e181 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:45, skipping insertion in model container [2022-11-18 18:49:45,966 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:49:45" (1/1) ... [2022-11-18 18:49:45,975 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 18:49:46,028 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 18:49:46,418 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:49:46,432 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 18:49:46,507 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:49:46,535 INFO L208 MainTranslator]: Completed translation [2022-11-18 18:49:46,535 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46 WrapperNode [2022-11-18 18:49:46,536 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 18:49:46,537 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 18:49:46,537 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 18:49:46,537 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 18:49:46,545 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,567 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,587 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-18 18:49:46,587 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 18:49:46,588 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 18:49:46,588 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 18:49:46,589 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 18:49:46,598 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,598 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,600 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,601 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,605 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,609 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,611 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,615 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,617 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 18:49:46,618 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 18:49:46,618 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 18:49:46,618 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 18:49:46,619 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (1/1) ... [2022-11-18 18:49:46,627 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:46,643 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:46,659 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:46,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 18:49:46,717 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 18:49:46,717 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 18:49:46,718 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 18:49:46,719 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 18:49:46,719 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 18:49:46,719 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 18:49:46,845 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 18:49:46,848 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 18:49:47,069 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 18:49:47,076 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 18:49:47,089 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 18:49:47,091 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:49:47 BoogieIcfgContainer [2022-11-18 18:49:47,091 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 18:49:47,093 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 18:49:47,093 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 18:49:47,101 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 18:49:47,102 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:49:47,102 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 06:49:45" (1/3) ... [2022-11-18 18:49:47,103 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@46944af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:49:47, skipping insertion in model container [2022-11-18 18:49:47,116 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:49:47,116 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:49:46" (2/3) ... [2022-11-18 18:49:47,117 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@46944af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:49:47, skipping insertion in model container [2022-11-18 18:49:47,117 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:49:47,117 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:49:47" (3/3) ... [2022-11-18 18:49:47,119 INFO L332 chiAutomizerObserver]: Analyzing ICFG array13_alloca.i [2022-11-18 18:49:47,206 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 18:49:47,207 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 18:49:47,207 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 18:49:47,207 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 18:49:47,207 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 18:49:47,207 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 18:49:47,207 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 18:49:47,208 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 18:49:47,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:47,244 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:49:47,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:47,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:47,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 18:49:47,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:49:47,253 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 18:49:47,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:47,257 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:49:47,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:47,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:47,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 18:49:47,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:49:47,268 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-18 18:49:47,271 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-18 18:49:47,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:47,287 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-18 18:49:47,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:47,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703363826] [2022-11-18 18:49:47,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:47,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:47,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,471 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:47,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,528 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:47,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:47,531 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-18 18:49:47,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:47,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782594879] [2022-11-18 18:49:47,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:47,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:47,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,573 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:47,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,589 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:47,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:47,591 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-18 18:49:47,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:47,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752530929] [2022-11-18 18:49:47,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:47,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:47,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,650 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:47,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:47,705 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:48,092 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 18:49:48,093 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 18:49:48,093 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 18:49:48,093 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 18:49:48,093 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 18:49:48,094 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:48,094 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 18:49:48,094 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 18:49:48,094 INFO L133 ssoRankerPreferences]: Filename of dumped script: array13_alloca.i_Iteration1_Lasso [2022-11-18 18:49:48,095 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 18:49:48,095 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 18:49:48,121 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,133 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,138 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,143 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,150 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,154 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,368 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,371 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,375 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,378 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,381 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,385 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:49:48,775 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 18:49:48,782 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 18:49:48,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:48,784 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:48,791 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:48,803 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:48,817 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 18:49:48,819 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:48,819 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:49:48,820 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:48,820 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:48,820 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:48,823 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:49:48,823 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:49:48,834 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:48,851 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:48,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:48,852 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:48,853 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:48,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 18:49:48,859 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:48,875 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:48,875 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:48,875 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:48,875 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:48,880 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:49:48,880 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:49:48,892 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:48,903 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:48,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:48,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:48,905 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:48,910 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:48,926 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 18:49:48,927 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:48,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:49:48,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:48,928 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:48,928 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:48,930 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:49:48,930 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:49:48,940 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:48,951 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:48,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:48,952 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:48,953 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:48,969 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:48,986 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 18:49:48,987 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:48,987 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:49:48,988 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:48,988 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:48,988 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:48,989 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:49:48,990 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:49:49,007 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:49,014 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:49,015 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,015 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,016 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,024 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:49,039 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 18:49:49,040 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:49,040 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:49:49,040 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:49,040 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:49,040 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:49,041 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:49:49,042 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:49:49,051 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:49,061 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:49,063 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,063 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,065 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 18:49:49,084 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:49,097 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:49,097 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:49:49,097 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:49,097 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:49,098 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:49,099 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:49:49,099 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:49:49,108 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:49,119 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-11-18 18:49:49,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,120 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,126 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,138 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:49,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 18:49:49,154 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:49,154 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:49,154 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:49,154 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:49,158 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:49:49,158 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:49:49,183 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:49,192 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:49,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,195 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,204 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:49,215 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 18:49:49,222 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:49,222 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:49,222 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:49,223 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:49,232 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:49:49,232 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:49:49,249 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:49:49,254 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:49,254 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,256 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-18 18:49:49,263 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:49:49,278 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:49:49,279 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:49:49,279 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:49:49,279 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:49:49,290 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:49:49,290 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:49:49,319 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 18:49:49,385 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-18 18:49:49,385 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-18 18:49:49,387 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:49:49,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:49,389 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:49:49,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-18 18:49:49,408 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 18:49:49,423 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 18:49:49,424 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 18:49:49,424 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~arr~0#1.offset) = -4*ULTIMATE.start_main_~i~0#1 + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2022-11-18 18:49:49,429 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2022-11-18 18:49:49,444 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-18 18:49:49,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:49,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:49,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 18:49:49,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:49,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:49,527 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:49:49,528 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:49,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:49,619 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 18:49:49,621 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:49,706 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-18 18:49:49,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 18:49:49,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:49,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-18 18:49:49,717 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-18 18:49:49,718 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:49:49,718 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-18 18:49:49,719 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:49:49,719 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-18 18:49:49,719 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:49:49,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-18 18:49:49,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:49,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-18 18:49:49,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-18 18:49:49,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 18:49:49,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-18 18:49:49,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:49,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:49:49,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-18 18:49:49,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-18 18:49:49,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:49,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-18 18:49:49,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:49:49,763 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 18:49:49,764 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 18:49:49,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-18 18:49:49,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:49,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:49,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:49,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:49,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:49,766 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-18 18:49:49,766 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 118#L378-2 [2022-11-18 18:49:49,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:49,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-18 18:49:49,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:49,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541535547] [2022-11-18 18:49:49,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:49,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:49,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:49,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:49,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:49,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541535547] [2022-11-18 18:49:49,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541535547] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:49:49,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:49:49,868 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 18:49:49,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231888699] [2022-11-18 18:49:49,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:49:49,871 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:49:49,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:49,871 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-18 18:49:49,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:49,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884654815] [2022-11-18 18:49:49,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:49,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:49,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:49,878 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:49,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:49,884 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:49,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:49,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:49:49,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:49:49,949 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:49,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:49,994 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-18 18:49:49,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-18 18:49:49,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:50,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-18 18:49:50,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-18 18:49:50,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 18:49:50,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-18 18:49:50,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:50,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-18 18:49:50,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-18 18:49:50,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-18 18:49:50,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:50,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-18 18:49:50,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 18:49:50,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 18:49:50,007 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 18:49:50,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 18:49:50,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-18 18:49:50,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:50,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:50,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:50,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:50,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:50,012 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-18 18:49:50,013 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 151#L378-2 [2022-11-18 18:49:50,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:50,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-18 18:49:50,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:50,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658697783] [2022-11-18 18:49:50,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:50,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:50,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:50,051 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:50,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:50,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:50,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:50,087 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-18 18:49:50,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:50,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532691257] [2022-11-18 18:49:50,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:50,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:50,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:50,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:50,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:50,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:50,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:50,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-18 18:49:50,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:50,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282961256] [2022-11-18 18:49:50,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:50,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:50,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:50,399 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-18 18:49:50,608 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:50,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:50,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282961256] [2022-11-18 18:49:50,609 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282961256] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:50,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [199338115] [2022-11-18 18:49:50,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:50,610 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:50,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:50,611 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:50,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-18 18:49:50,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:50,696 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 18:49:50,699 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:50,774 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-18 18:49:50,864 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:49:50,875 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:50,876 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:50,973 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2022-11-18 18:49:50,978 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2022-11-18 18:49:50,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:50,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [199338115] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:50,994 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:50,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-18 18:49:50,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430670002] [2022-11-18 18:49:50,994 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:51,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:51,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-18 18:49:51,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2022-11-18 18:49:51,051 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:51,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:51,216 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2022-11-18 18:49:51,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2022-11-18 18:49:51,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:51,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2022-11-18 18:49:51,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-18 18:49:51,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-18 18:49:51,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2022-11-18 18:49:51,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:51,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2022-11-18 18:49:51,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2022-11-18 18:49:51,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2022-11-18 18:49:51,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:51,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2022-11-18 18:49:51,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-18 18:49:51,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:49:51,223 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-18 18:49:51,223 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 18:49:51,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2022-11-18 18:49:51,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:51,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:51,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:51,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:51,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:51,227 INFO L748 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 277#L367 assume !(main_~length~0#1 < 1); 271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 278#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 279#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 280#L370-4 main_~j~0#1 := 0; 284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 274#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 275#L378-2 [2022-11-18 18:49:51,227 INFO L750 eck$LassoCheckResult]: Loop: 275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 282#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 275#L378-2 [2022-11-18 18:49:51,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:51,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-18 18:49:51,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:51,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174690930] [2022-11-18 18:49:51,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:51,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:51,241 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:51,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:51,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:51,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:51,254 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-18 18:49:51,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:51,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345606618] [2022-11-18 18:49:51,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:51,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:51,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:51,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:51,263 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:51,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:51,264 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2022-11-18 18:49:51,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:51,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050087988] [2022-11-18 18:49:51,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:51,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:51,386 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:51,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:51,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050087988] [2022-11-18 18:49:51,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050087988] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:51,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [37100782] [2022-11-18 18:49:51,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:51,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:51,389 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:51,415 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-18 18:49:51,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:51,464 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 18:49:51,466 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:51,529 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:51,529 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:51,581 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:51,581 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [37100782] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:51,582 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:51,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-18 18:49:51,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28952758] [2022-11-18 18:49:51,582 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:51,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:51,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-18 18:49:51,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-18 18:49:51,650 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:51,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:51,813 INFO L93 Difference]: Finished difference Result 43 states and 57 transitions. [2022-11-18 18:49:51,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2022-11-18 18:49:51,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:51,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 39 states and 51 transitions. [2022-11-18 18:49:51,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 18:49:51,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 18:49:51,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-18 18:49:51,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:51,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-18 18:49:51,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-18 18:49:51,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-18 18:49:51,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:51,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2022-11-18 18:49:51,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-18 18:49:51,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:49:51,822 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-18 18:49:51,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 18:49:51,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2022-11-18 18:49:51,823 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:51,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:51,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:51,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:51,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:51,825 INFO L748 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 444#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 445#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 461#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 457#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 458#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 440#L370-4 main_~j~0#1 := 0; 441#L378-2 [2022-11-18 18:49:51,825 INFO L750 eck$LassoCheckResult]: Loop: 441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 451#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 441#L378-2 [2022-11-18 18:49:51,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:51,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-18 18:49:51,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:51,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467983420] [2022-11-18 18:49:51,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:51,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:51,890 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:51,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:51,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467983420] [2022-11-18 18:49:51,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467983420] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:51,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [491220330] [2022-11-18 18:49:51,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:51,892 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:51,892 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:51,896 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:51,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-18 18:49:51,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:51,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:49:51,974 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:52,029 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:52,029 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 18:49:52,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [491220330] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:49:52,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-18 18:49:52,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-18 18:49:52,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470285834] [2022-11-18 18:49:52,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:49:52,031 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:49:52,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:52,032 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-18 18:49:52,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:52,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692483454] [2022-11-18 18:49:52,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:52,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:52,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,040 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:52,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,046 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:52,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:52,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:49:52,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:49:52,114 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:52,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:52,141 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2022-11-18 18:49:52,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2022-11-18 18:49:52,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:52,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2022-11-18 18:49:52,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 18:49:52,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-18 18:49:52,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2022-11-18 18:49:52,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:52,148 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:49:52,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2022-11-18 18:49:52,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-18 18:49:52,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:52,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-11-18 18:49:52,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:49:52,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:49:52,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-18 18:49:52,159 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 18:49:52,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2022-11-18 18:49:52,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:52,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:52,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:52,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:52,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:52,164 INFO L748 eck$LassoCheckResult]: Stem: 542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 551#L367 assume !(main_~length~0#1 < 1); 544#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 545#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 552#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 553#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 558#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 557#L370-4 main_~j~0#1 := 0; 550#L378-2 [2022-11-18 18:49:52,164 INFO L750 eck$LassoCheckResult]: Loop: 550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 556#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 550#L378-2 [2022-11-18 18:49:52,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:52,165 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2022-11-18 18:49:52,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:52,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597836698] [2022-11-18 18:49:52,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:52,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:52,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:52,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:52,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:52,220 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-18 18:49:52,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:52,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36378464] [2022-11-18 18:49:52,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:52,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:52,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,226 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:52,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:52,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:52,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:52,231 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2022-11-18 18:49:52,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:52,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215527398] [2022-11-18 18:49:52,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:52,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:52,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:52,777 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:52,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:52,778 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215527398] [2022-11-18 18:49:52,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215527398] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:52,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [292300227] [2022-11-18 18:49:52,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:52,782 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:52,783 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:52,790 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:52,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-18 18:49:52,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:52,867 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-18 18:49:52,869 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:52,897 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:49:52,985 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:52,987 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:53,021 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:53,022 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:53,079 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:49:53,090 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:53,090 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:53,311 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:49:53,317 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 54 [2022-11-18 18:49:53,380 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:53,380 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [292300227] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:53,380 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:53,380 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 18:49:53,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294001651] [2022-11-18 18:49:53,381 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:53,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:53,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 18:49:53,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-18 18:49:53,443 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:53,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:53,590 INFO L93 Difference]: Finished difference Result 39 states and 51 transitions. [2022-11-18 18:49:53,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 51 transitions. [2022-11-18 18:49:53,590 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:53,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 51 transitions. [2022-11-18 18:49:53,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:49:53,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:49:53,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-18 18:49:53,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:53,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-18 18:49:53,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-18 18:49:53,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-11-18 18:49:53,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.3703703703703705) internal successors, (37), 26 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:53,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-11-18 18:49:53,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-18 18:49:53,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:49:53,596 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-18 18:49:53,596 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 18:49:53,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 37 transitions. [2022-11-18 18:49:53,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:53,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:53,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:53,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:53,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:53,598 INFO L748 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 723#L367 assume !(main_~length~0#1 < 1); 716#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 717#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 724#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 739#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 721#L370-4 main_~j~0#1 := 0; 722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 719#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 720#L378-2 [2022-11-18 18:49:53,598 INFO L750 eck$LassoCheckResult]: Loop: 720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 733#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 720#L378-2 [2022-11-18 18:49:53,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:53,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-18 18:49:53,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:53,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463498921] [2022-11-18 18:49:53,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:53,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:53,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:53,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:53,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:53,625 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:53,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:53,626 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-18 18:49:53,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:53,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87310971] [2022-11-18 18:49:53,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:53,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:53,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:53,631 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:53,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:53,634 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:53,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:53,635 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2022-11-18 18:49:53,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:53,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937916047] [2022-11-18 18:49:53,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:53,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:53,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:53,837 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:53,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:53,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937916047] [2022-11-18 18:49:53,838 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937916047] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:53,838 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2018657315] [2022-11-18 18:49:53,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:53,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:53,839 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:53,847 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:53,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-18 18:49:53,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:53,930 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-18 18:49:53,932 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:53,959 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:49:54,117 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-18 18:49:54,117 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-18 18:49:54,133 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:54,134 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:54,231 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:49:54,236 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:49:54,264 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:54,264 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2018657315] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:54,264 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:54,265 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2022-11-18 18:49:54,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775981708] [2022-11-18 18:49:54,265 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:54,333 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:54,334 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-18 18:49:54,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2022-11-18 18:49:54,337 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. cyclomatic complexity: 13 Second operand has 16 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:54,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:54,530 INFO L93 Difference]: Finished difference Result 36 states and 48 transitions. [2022-11-18 18:49:54,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 48 transitions. [2022-11-18 18:49:54,531 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:54,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 48 transitions. [2022-11-18 18:49:54,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 18:49:54,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 18:49:54,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 48 transitions. [2022-11-18 18:49:54,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:54,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36 states and 48 transitions. [2022-11-18 18:49:54,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 48 transitions. [2022-11-18 18:49:54,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 32. [2022-11-18 18:49:54,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:54,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2022-11-18 18:49:54,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-18 18:49:54,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 18:49:54,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-18 18:49:54,537 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 18:49:54,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2022-11-18 18:49:54,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:54,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:54,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:54,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:54,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:54,539 INFO L748 eck$LassoCheckResult]: Stem: 898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 906#L367 assume !(main_~length~0#1 < 1); 900#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 901#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 907#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 909#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 915#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 916#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 905#L370-4 main_~j~0#1 := 0; 904#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 910#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 919#L378-2 [2022-11-18 18:49:54,539 INFO L750 eck$LassoCheckResult]: Loop: 919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 918#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 919#L378-2 [2022-11-18 18:49:54,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:54,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2022-11-18 18:49:54,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:54,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260511752] [2022-11-18 18:49:54,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:54,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:54,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:54,553 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:54,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:54,564 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:54,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:54,565 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-18 18:49:54,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:54,565 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575034292] [2022-11-18 18:49:54,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:54,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:54,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:54,569 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:54,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:54,573 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:54,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:54,574 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2022-11-18 18:49:54,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:54,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807330935] [2022-11-18 18:49:54,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:54,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:54,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:54,755 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:54,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:54,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807330935] [2022-11-18 18:49:54,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807330935] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:54,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [957728576] [2022-11-18 18:49:54,756 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:49:54,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:54,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:54,763 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:54,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-18 18:49:54,843 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:49:54,843 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:49:54,845 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:49:54,847 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:54,925 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:49:55,074 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:49:55,077 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:55,078 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:55,173 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:49:55,178 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:49:55,198 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:55,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [957728576] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:55,198 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:55,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 18:49:55,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508738063] [2022-11-18 18:49:55,199 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:55,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:55,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 18:49:55,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2022-11-18 18:49:55,257 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 14 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:55,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:55,508 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2022-11-18 18:49:55,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 62 transitions. [2022-11-18 18:49:55,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:49:55,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 62 transitions. [2022-11-18 18:49:55,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-18 18:49:55,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-18 18:49:55,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 62 transitions. [2022-11-18 18:49:55,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:55,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 62 transitions. [2022-11-18 18:49:55,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 62 transitions. [2022-11-18 18:49:55,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 38. [2022-11-18 18:49:55,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.368421052631579) internal successors, (52), 37 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:55,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 52 transitions. [2022-11-18 18:49:55,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-18 18:49:55,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:49:55,515 INFO L428 stractBuchiCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-18 18:49:55,516 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-18 18:49:55,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 52 transitions. [2022-11-18 18:49:55,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:55,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:55,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:55,517 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:55,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:55,518 INFO L748 eck$LassoCheckResult]: Stem: 1105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1113#L367 assume !(main_~length~0#1 < 1); 1107#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1108#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1114#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1116#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1133#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1134#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1130#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1127#L370-4 main_~j~0#1 := 0; 1125#L378-2 [2022-11-18 18:49:55,518 INFO L750 eck$LassoCheckResult]: Loop: 1125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1126#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1125#L378-2 [2022-11-18 18:49:55,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:55,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1518446116, now seen corresponding path program 2 times [2022-11-18 18:49:55,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:55,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354038960] [2022-11-18 18:49:55,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:55,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:55,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:55,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:55,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:55,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:55,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:55,554 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-18 18:49:55,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:55,554 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577027717] [2022-11-18 18:49:55,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:55,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:55,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:55,570 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:55,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:55,573 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:55,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:55,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164511, now seen corresponding path program 2 times [2022-11-18 18:49:55,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:55,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387721971] [2022-11-18 18:49:55,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:55,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:55,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:56,174 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:56,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:56,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387721971] [2022-11-18 18:49:56,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387721971] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:56,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1607851559] [2022-11-18 18:49:56,175 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:49:56,176 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:56,176 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:56,183 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:56,198 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-18 18:49:56,263 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:49:56,264 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:49:56,265 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:49:56,268 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:56,307 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:49:56,456 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:56,457 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:56,485 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:56,486 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:56,533 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:56,534 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:56,569 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:56,570 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:49:56,641 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:49:56,644 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:49:56,644 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 10 [2022-11-18 18:49:56,658 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:56,658 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:57,361 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-18 18:49:57,396 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 66 [2022-11-18 18:49:57,472 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:49:57,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1607851559] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:57,473 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:57,473 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2022-11-18 18:49:57,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110964343] [2022-11-18 18:49:57,476 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:57,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:57,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-18 18:49:57,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=558, Unknown=0, NotChecked=0, Total=702 [2022-11-18 18:49:57,540 INFO L87 Difference]: Start difference. First operand 38 states and 52 transitions. cyclomatic complexity: 18 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:57,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:57,735 INFO L93 Difference]: Finished difference Result 43 states and 56 transitions. [2022-11-18 18:49:57,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 56 transitions. [2022-11-18 18:49:57,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:57,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 56 transitions. [2022-11-18 18:49:57,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:49:57,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:49:57,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 56 transitions. [2022-11-18 18:49:57,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:57,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 56 transitions. [2022-11-18 18:49:57,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 56 transitions. [2022-11-18 18:49:57,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 24. [2022-11-18 18:49:57,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:57,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2022-11-18 18:49:57,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-18 18:49:57,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 18:49:57,744 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-18 18:49:57,744 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-18 18:49:57,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2022-11-18 18:49:57,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:57,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:57,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:57,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:57,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:57,746 INFO L748 eck$LassoCheckResult]: Stem: 1329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1335#L367 assume !(main_~length~0#1 < 1); 1327#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1328#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1336#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1338#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1341#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1342#L370-4 main_~j~0#1 := 0; 1347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1334#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1340#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1345#L378-2 [2022-11-18 18:49:57,747 INFO L750 eck$LassoCheckResult]: Loop: 1345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1344#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1345#L378-2 [2022-11-18 18:49:57,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:57,747 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2022-11-18 18:49:57,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:57,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735148278] [2022-11-18 18:49:57,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:57,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:57,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:57,765 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:57,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:57,775 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:57,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:57,776 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-18 18:49:57,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:57,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621978792] [2022-11-18 18:49:57,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:57,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:57,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:57,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:57,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:57,784 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:57,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:57,785 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2022-11-18 18:49:57,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:57,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810497069] [2022-11-18 18:49:57,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:57,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:57,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:57,908 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:57,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:57,908 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810497069] [2022-11-18 18:49:57,908 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810497069] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:57,909 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [254573519] [2022-11-18 18:49:57,909 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:49:57,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:57,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:57,914 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:57,943 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-18 18:49:58,000 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-18 18:49:58,000 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:49:58,003 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 18:49:58,004 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:58,094 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:58,095 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:58,162 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:58,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [254573519] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:58,163 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:58,163 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-18 18:49:58,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681323658] [2022-11-18 18:49:58,164 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:58,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:58,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 18:49:58,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-18 18:49:58,215 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:58,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:58,334 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2022-11-18 18:49:58,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2022-11-18 18:49:58,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:58,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2022-11-18 18:49:58,335 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-18 18:49:58,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-18 18:49:58,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-18 18:49:58,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:58,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-18 18:49:58,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-18 18:49:58,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-11-18 18:49:58,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:58,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2022-11-18 18:49:58,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-18 18:49:58,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 18:49:58,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-18 18:49:58,340 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-18 18:49:58,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2022-11-18 18:49:58,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:58,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:58,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:58,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:58,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:58,341 INFO L748 eck$LassoCheckResult]: Stem: 1521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1530#L367 assume !(main_~length~0#1 < 1); 1523#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1524#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1531#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1534#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1533#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1541#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1540#L370-4 main_~j~0#1 := 0; 1529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1539#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1538#L378-2 [2022-11-18 18:49:58,341 INFO L750 eck$LassoCheckResult]: Loop: 1538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1537#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1538#L378-2 [2022-11-18 18:49:58,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:58,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 2 times [2022-11-18 18:49:58,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:58,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026916143] [2022-11-18 18:49:58,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:58,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:58,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:58,364 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:58,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:58,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:58,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:58,382 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-18 18:49:58,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:58,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816115524] [2022-11-18 18:49:58,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:58,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:58,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:58,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:58,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:58,397 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:58,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:58,398 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 2 times [2022-11-18 18:49:58,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:58,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135856187] [2022-11-18 18:49:58,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:58,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:58,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:49:58,761 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:58,761 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:49:58,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135856187] [2022-11-18 18:49:58,762 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135856187] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:49:58,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1099482831] [2022-11-18 18:49:58,762 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:49:58,762 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:49:58,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:49:58,767 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:49:58,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-18 18:49:58,869 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:49:58,869 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:49:58,870 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:49:58,872 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:49:58,945 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:49:59,057 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:59,058 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:49:59,079 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:49:59,080 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:49:59,198 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:49:59,201 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:59,202 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:49:59,366 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:49:59,370 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:49:59,394 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:49:59,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1099482831] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:49:59,395 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:49:59,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-18 18:49:59,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213941936] [2022-11-18 18:49:59,395 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:49:59,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:49:59,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 18:49:59,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-18 18:49:59,453 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:59,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:49:59,730 INFO L93 Difference]: Finished difference Result 30 states and 37 transitions. [2022-11-18 18:49:59,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2022-11-18 18:49:59,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:59,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 37 transitions. [2022-11-18 18:49:59,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:49:59,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:49:59,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2022-11-18 18:49:59,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:49:59,732 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 37 transitions. [2022-11-18 18:49:59,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2022-11-18 18:49:59,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 22. [2022-11-18 18:49:59,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:49:59,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2022-11-18 18:49:59,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-18 18:49:59,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 18:49:59,737 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-18 18:49:59,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-18 18:49:59,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2022-11-18 18:49:59,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:49:59,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:49:59,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:49:59,739 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:49:59,739 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:49:59,739 INFO L748 eck$LassoCheckResult]: Stem: 1727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1736#L367 assume !(main_~length~0#1 < 1); 1729#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1730#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1737#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1744#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1745#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1739#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1742#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1732#L370-4 main_~j~0#1 := 0; 1733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1734#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1741#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1748#L378-2 [2022-11-18 18:49:59,740 INFO L750 eck$LassoCheckResult]: Loop: 1748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1747#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1748#L378-2 [2022-11-18 18:49:59,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:59,740 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 4 times [2022-11-18 18:49:59,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:59,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788560699] [2022-11-18 18:49:59,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:59,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:59,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:59,784 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:59,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:59,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:59,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:59,801 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-18 18:49:59,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:59,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183353880] [2022-11-18 18:49:59,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:59,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:59,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:59,807 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:49:59,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:49:59,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:49:59,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:49:59,811 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2022-11-18 18:49:59,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:49:59,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415874941] [2022-11-18 18:49:59,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:49:59,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:49:59,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:00,062 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:00,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:00,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415874941] [2022-11-18 18:50:00,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415874941] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:00,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1122745902] [2022-11-18 18:50:00,063 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:50:00,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:00,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:00,070 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:00,096 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-18 18:50:00,160 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:50:00,160 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:00,161 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:50:00,164 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:00,208 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:00,351 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:00,354 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:00,354 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:00,444 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:50:00,447 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:50:00,477 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:00,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1122745902] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:00,477 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:00,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-18 18:50:00,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923862618] [2022-11-18 18:50:00,478 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:00,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:00,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 18:50:00,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-18 18:50:00,534 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:00,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:00,693 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2022-11-18 18:50:00,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 42 transitions. [2022-11-18 18:50:00,693 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:50:00,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 42 transitions. [2022-11-18 18:50:00,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 18:50:00,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 18:50:00,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2022-11-18 18:50:00,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:00,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 42 transitions. [2022-11-18 18:50:00,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2022-11-18 18:50:00,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 28. [2022-11-18 18:50:00,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:00,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2022-11-18 18:50:00,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-18 18:50:00,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:50:00,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-18 18:50:00,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-18 18:50:00,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2022-11-18 18:50:00,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:00,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:00,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:00,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:00,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:00,702 INFO L748 eck$LassoCheckResult]: Stem: 1933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1941#L367 assume !(main_~length~0#1 < 1); 1935#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1936#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1942#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1952#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1944#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1949#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1950#L370-4 main_~j~0#1 := 0; 1958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1938#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1939#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1945#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1956#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1955#L378-2 [2022-11-18 18:50:00,702 INFO L750 eck$LassoCheckResult]: Loop: 1955#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1954#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1955#L378-2 [2022-11-18 18:50:00,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:00,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 5 times [2022-11-18 18:50:00,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:00,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741703365] [2022-11-18 18:50:00,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:00,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:00,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:00,717 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:00,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:00,733 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:00,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:00,735 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-18 18:50:00,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:00,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661493209] [2022-11-18 18:50:00,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:00,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:00,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:00,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:00,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:00,745 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:00,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:00,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2022-11-18 18:50:00,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:00,746 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782106169] [2022-11-18 18:50:00,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:00,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:00,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:00,941 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:00,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:00,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782106169] [2022-11-18 18:50:00,942 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782106169] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:00,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1596945043] [2022-11-18 18:50:00,943 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:50:00,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:00,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:00,951 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:00,959 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-18 18:50:01,051 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-18 18:50:01,051 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:01,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 18:50:01,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:01,180 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:01,180 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:01,281 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:01,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1596945043] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:01,281 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:01,281 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-18 18:50:01,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134296836] [2022-11-18 18:50:01,281 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:01,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:01,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 18:50:01,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-18 18:50:01,341 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 9 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:01,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:01,534 INFO L93 Difference]: Finished difference Result 35 states and 42 transitions. [2022-11-18 18:50:01,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 42 transitions. [2022-11-18 18:50:01,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:01,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 27 states and 34 transitions. [2022-11-18 18:50:01,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:50:01,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:50:01,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2022-11-18 18:50:01,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:01,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 34 transitions. [2022-11-18 18:50:01,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2022-11-18 18:50:01,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2022-11-18 18:50:01,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.24) internal successors, (31), 24 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:01,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 31 transitions. [2022-11-18 18:50:01,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-18 18:50:01,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 18:50:01,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-18 18:50:01,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-18 18:50:01,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 31 transitions. [2022-11-18 18:50:01,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:01,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:01,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:01,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:01,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:01,543 INFO L748 eck$LassoCheckResult]: Stem: 2166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2175#L367 assume !(main_~length~0#1 < 1); 2168#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2169#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2176#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2178#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2187#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2183#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2182#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2171#L370-4 main_~j~0#1 := 0; 2172#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2173#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2180#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2190#L378-2 [2022-11-18 18:50:01,543 INFO L750 eck$LassoCheckResult]: Loop: 2190#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2189#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2190#L378-2 [2022-11-18 18:50:01,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:01,543 INFO L85 PathProgramCache]: Analyzing trace with hash 666851296, now seen corresponding path program 6 times [2022-11-18 18:50:01,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:01,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128628862] [2022-11-18 18:50:01,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:01,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:01,561 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:01,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:01,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:01,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:01,584 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-18 18:50:01,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:01,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926390646] [2022-11-18 18:50:01,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:01,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:01,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:01,588 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:01,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:01,590 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:01,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:01,591 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 6 times [2022-11-18 18:50:01,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:01,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840164844] [2022-11-18 18:50:01,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:01,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:01,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:01,933 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:01,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:01,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [840164844] [2022-11-18 18:50:01,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [840164844] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:01,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1508689772] [2022-11-18 18:50:01,934 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:50:01,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:01,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:01,939 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:01,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-18 18:50:02,047 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-18 18:50:02,047 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:02,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-18 18:50:02,051 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:02,192 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:02,307 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:02,308 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:02,478 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:50:02,481 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:02,481 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:02,673 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:50:02,677 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:50:02,718 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:02,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1508689772] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:02,719 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:02,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2022-11-18 18:50:02,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174722941] [2022-11-18 18:50:02,719 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:02,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:02,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-18 18:50:02,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2022-11-18 18:50:02,780 INFO L87 Difference]: Start difference. First operand 25 states and 31 transitions. cyclomatic complexity: 8 Second operand has 27 states, 26 states have (on average 2.0) internal successors, (52), 27 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:03,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:03,137 INFO L93 Difference]: Finished difference Result 27 states and 33 transitions. [2022-11-18 18:50:03,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 33 transitions. [2022-11-18 18:50:03,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:03,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 33 transitions. [2022-11-18 18:50:03,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-18 18:50:03,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-18 18:50:03,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 33 transitions. [2022-11-18 18:50:03,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:03,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:50:03,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 33 transitions. [2022-11-18 18:50:03,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-11-18 18:50:03,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:03,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2022-11-18 18:50:03,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:50:03,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:50:03,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-18 18:50:03,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-18 18:50:03,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2022-11-18 18:50:03,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:03,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:03,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:03,149 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:03,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:03,153 INFO L748 eck$LassoCheckResult]: Stem: 2406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2413#L367 assume !(main_~length~0#1 < 1); 2404#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2405#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2414#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2415#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2416#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2425#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2421#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2422#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2420#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2409#L370-4 main_~j~0#1 := 0; 2410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2411#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2418#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2429#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2428#L378-2 [2022-11-18 18:50:03,153 INFO L750 eck$LassoCheckResult]: Loop: 2428#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2427#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2428#L378-2 [2022-11-18 18:50:03,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:03,156 INFO L85 PathProgramCache]: Analyzing trace with hash 893969701, now seen corresponding path program 7 times [2022-11-18 18:50:03,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:03,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035667008] [2022-11-18 18:50:03,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:03,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:03,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:03,173 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:03,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:03,187 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:03,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:03,188 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-18 18:50:03,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:03,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886019895] [2022-11-18 18:50:03,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:03,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:03,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:03,194 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:03,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:03,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:03,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:03,198 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 7 times [2022-11-18 18:50:03,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:03,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249521391] [2022-11-18 18:50:03,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:03,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:03,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:03,544 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:03,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:03,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249521391] [2022-11-18 18:50:03,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [249521391] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:03,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1401867358] [2022-11-18 18:50:03,545 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:50:03,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:03,546 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:03,549 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:03,586 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-18 18:50:03,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:03,655 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 18:50:03,657 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:03,698 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:03,883 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:03,886 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:03,887 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:04,005 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:50:04,008 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:50:04,047 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:04,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1401867358] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:04,048 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:04,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 19 [2022-11-18 18:50:04,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901737554] [2022-11-18 18:50:04,049 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:04,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:04,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 18:50:04,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2022-11-18 18:50:04,104 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 8 Second operand has 20 states, 19 states have (on average 2.1578947368421053) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:04,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:04,359 INFO L93 Difference]: Finished difference Result 43 states and 53 transitions. [2022-11-18 18:50:04,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 53 transitions. [2022-11-18 18:50:04,360 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:50:04,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 53 transitions. [2022-11-18 18:50:04,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2022-11-18 18:50:04,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2022-11-18 18:50:04,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 53 transitions. [2022-11-18 18:50:04,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:04,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 53 transitions. [2022-11-18 18:50:04,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 53 transitions. [2022-11-18 18:50:04,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 34. [2022-11-18 18:50:04,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:04,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-18 18:50:04,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 18:50:04,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 18:50:04,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 18:50:04,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-18 18:50:04,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-18 18:50:04,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:04,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:04,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:04,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:04,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:04,366 INFO L748 eck$LassoCheckResult]: Stem: 2657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2665#L367 assume !(main_~length~0#1 < 1); 2659#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2660#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2666#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2668#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2679#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2676#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2672#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2673#L370-4 main_~j~0#1 := 0; 2687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2664#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2670#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2685#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2684#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2683#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2682#L378-2 [2022-11-18 18:50:04,366 INFO L750 eck$LassoCheckResult]: Loop: 2682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2681#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2682#L378-2 [2022-11-18 18:50:04,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:04,366 INFO L85 PathProgramCache]: Analyzing trace with hash 111424810, now seen corresponding path program 8 times [2022-11-18 18:50:04,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:04,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849798201] [2022-11-18 18:50:04,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:04,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:04,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:04,383 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:04,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:04,401 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:04,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:04,401 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-18 18:50:04,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:04,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448021949] [2022-11-18 18:50:04,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:04,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:04,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:04,405 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:04,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:04,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:04,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:04,410 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 8 times [2022-11-18 18:50:04,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:04,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661948842] [2022-11-18 18:50:04,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:04,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:04,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:04,625 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:04,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:04,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661948842] [2022-11-18 18:50:04,626 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661948842] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:04,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1620234676] [2022-11-18 18:50:04,626 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:50:04,626 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:04,626 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:04,634 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:04,664 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-18 18:50:04,742 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:50:04,742 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:04,744 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 18:50:04,745 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:04,921 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:04,921 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:05,075 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:05,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1620234676] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:05,075 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:05,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-18 18:50:05,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436459647] [2022-11-18 18:50:05,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:05,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:05,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 18:50:05,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-18 18:50:05,131 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 12 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:05,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:05,329 INFO L93 Difference]: Finished difference Result 49 states and 59 transitions. [2022-11-18 18:50:05,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 59 transitions. [2022-11-18 18:50:05,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:05,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 39 states and 49 transitions. [2022-11-18 18:50:05,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:50:05,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:50:05,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2022-11-18 18:50:05,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:05,331 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-18 18:50:05,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2022-11-18 18:50:05,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 36. [2022-11-18 18:50:05,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.25) internal successors, (45), 35 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:05,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 45 transitions. [2022-11-18 18:50:05,333 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-18 18:50:05,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:50:05,334 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-18 18:50:05,334 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-18 18:50:05,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 45 transitions. [2022-11-18 18:50:05,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:05,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:05,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:05,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:05,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:05,336 INFO L748 eck$LassoCheckResult]: Stem: 2945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2953#L367 assume !(main_~length~0#1 < 1); 2947#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2948#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2954#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2970#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2956#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2969#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2966#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2963#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2964#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2960#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2952#L370-4 main_~j~0#1 := 0; 2951#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2958#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2975#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2973#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2972#L378-2 [2022-11-18 18:50:05,336 INFO L750 eck$LassoCheckResult]: Loop: 2972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2971#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2972#L378-2 [2022-11-18 18:50:05,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:05,337 INFO L85 PathProgramCache]: Analyzing trace with hash -188031059, now seen corresponding path program 3 times [2022-11-18 18:50:05,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:05,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300763387] [2022-11-18 18:50:05,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:05,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:05,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:05,354 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:05,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:05,369 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:05,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:05,370 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-18 18:50:05,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:05,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714459550] [2022-11-18 18:50:05,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:05,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:05,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:05,374 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:05,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:05,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:05,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:05,377 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 3 times [2022-11-18 18:50:05,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:05,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168122755] [2022-11-18 18:50:05,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:05,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:05,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:05,821 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:05,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:05,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168122755] [2022-11-18 18:50:05,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168122755] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:05,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [96605049] [2022-11-18 18:50:05,822 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:50:05,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:05,822 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:05,830 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:05,836 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-18 18:50:05,957 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 18:50:05,957 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:05,959 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 18:50:05,961 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:06,051 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:06,190 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:50:06,191 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-18 18:50:06,306 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:50:06,306 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-18 18:50:06,951 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 18:50:06,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-18 18:50:06,969 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:06,969 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:07,923 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:50:07,929 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:50:08,029 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 39 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:50:08,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [96605049] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:08,030 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:08,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 14] total 37 [2022-11-18 18:50:08,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529912500] [2022-11-18 18:50:08,030 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:08,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:08,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:50:08,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1216, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:50:08,087 INFO L87 Difference]: Start difference. First operand 36 states and 45 transitions. cyclomatic complexity: 12 Second operand has 38 states, 37 states have (on average 1.864864864864865) internal successors, (69), 38 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:09,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:09,099 INFO L93 Difference]: Finished difference Result 73 states and 87 transitions. [2022-11-18 18:50:09,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 87 transitions. [2022-11-18 18:50:09,100 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 18:50:09,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 87 transitions. [2022-11-18 18:50:09,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-18 18:50:09,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-18 18:50:09,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 87 transitions. [2022-11-18 18:50:09,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:50:09,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 87 transitions. [2022-11-18 18:50:09,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 87 transitions. [2022-11-18 18:50:09,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 43. [2022-11-18 18:50:09,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:09,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-18 18:50:09,104 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:50:09,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-18 18:50:09,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:50:09,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-18 18:50:09,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-18 18:50:09,112 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:50:09,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:09,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:09,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:09,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:09,115 INFO L748 eck$LassoCheckResult]: Stem: 3321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3327#L367 assume !(main_~length~0#1 < 1); 3319#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3320#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3328#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3343#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3340#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3330#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3331#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3335#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3324#L370-4 main_~j~0#1 := 0; 3325#L378-2 [2022-11-18 18:50:09,115 INFO L750 eck$LassoCheckResult]: Loop: 3325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3326#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3325#L378-2 [2022-11-18 18:50:09,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:09,116 INFO L85 PathProgramCache]: Analyzing trace with hash 438748702, now seen corresponding path program 3 times [2022-11-18 18:50:09,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:09,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673738703] [2022-11-18 18:50:09,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:09,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:09,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:09,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:09,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:09,148 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-18 18:50:09,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:09,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661877981] [2022-11-18 18:50:09,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:09,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:09,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,151 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:09,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:09,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:09,154 INFO L85 PathProgramCache]: Analyzing trace with hash 730708963, now seen corresponding path program 4 times [2022-11-18 18:50:09,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:09,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452317182] [2022-11-18 18:50:09,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:09,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:09,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:09,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:09,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:11,106 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 18:50:11,106 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 18:50:11,106 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 18:50:11,107 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 18:50:11,107 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 18:50:11,107 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:11,107 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 18:50:11,107 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 18:50:11,107 INFO L133 ssoRankerPreferences]: Filename of dumped script: array13_alloca.i_Iteration18_Lasso [2022-11-18 18:50:11,108 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 18:50:11,108 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 18:50:11,111 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,116 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,119 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,124 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,127 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,130 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,571 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,573 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,575 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,577 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,579 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,582 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:50:11,969 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 18:50:11,969 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 18:50:11,969 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:11,969 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:11,998 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,039 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-18 18:50:12,040 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,054 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,054 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,054 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,055 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,058 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,058 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,079 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,087 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,087 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,087 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,089 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,100 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,101 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-18 18:50:12,113 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,113 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:50:12,113 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,114 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,114 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,116 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:50:12,116 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:50:12,128 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,139 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,139 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,141 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-18 18:50:12,148 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,163 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,163 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,163 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,163 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,171 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,171 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,182 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,194 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,196 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,200 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-18 18:50:12,214 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,214 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:50:12,215 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,215 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,215 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,215 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:50:12,215 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:50:12,230 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,235 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,236 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,241 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-18 18:50:12,255 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,255 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:50:12,255 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,255 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,255 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,257 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:50:12,257 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:50:12,271 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,275 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,275 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,277 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,282 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,295 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-18 18:50:12,296 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,296 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,296 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,297 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,300 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,300 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,319 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,329 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,331 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,335 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-18 18:50:12,349 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,350 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,350 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,350 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,360 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,360 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,379 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,389 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,390 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,391 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,402 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,415 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-11-18 18:50:12,416 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,416 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,416 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,416 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,425 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,425 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,443 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,452 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,453 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,454 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,459 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-11-18 18:50:12,473 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,473 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,473 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,474 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,476 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,476 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,487 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,495 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,497 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,507 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-11-18 18:50:12,521 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,522 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,522 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,522 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,524 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,524 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,539 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,550 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,551 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,553 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,559 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-11-18 18:50:12,574 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,574 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,574 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,574 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,578 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,578 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,591 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:50:12,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2022-11-18 18:50:12,594 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,595 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,596 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-11-18 18:50:12,598 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:50:12,610 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:50:12,610 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:50:12,610 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:50:12,610 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:50:12,618 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:50:12,618 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:50:12,633 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 18:50:12,664 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-11-18 18:50:12,664 INFO L444 ModelExtractionUtils]: 8 out of 25 variables were initially zero. Simplification set additionally 13 variables to zero. [2022-11-18 18:50:12,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:50:12,664 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:12,671 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:50:12,672 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 18:50:12,685 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2022-11-18 18:50:12,699 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 18:50:12,699 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 18:50:12,699 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2, ULTIMATE.start_main_~j~0#1) = -1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 - 2*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2022-11-18 18:50:12,711 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:12,761 INFO L156 tatePredicateManager]: 7 out of 8 supporting invariants were superfluous and have been removed [2022-11-18 18:50:12,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:12,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:12,838 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 18:50:12,839 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:12,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:12,922 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 18:50:12,922 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:12,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:12,948 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-18 18:50:12,949 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:12,989 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 53 states and 68 transitions. Complement of second has 6 states. [2022-11-18 18:50:12,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-18 18:50:12,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:12,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2022-11-18 18:50:12,991 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 2 letters. [2022-11-18 18:50:12,991 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:50:12,991 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 24 letters. Loop has 2 letters. [2022-11-18 18:50:12,991 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:50:12,992 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 4 letters. [2022-11-18 18:50:12,992 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:50:12,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 68 transitions. [2022-11-18 18:50:12,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:12,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 44 states and 56 transitions. [2022-11-18 18:50:12,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 18:50:12,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:50:12,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2022-11-18 18:50:12,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:12,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 56 transitions. [2022-11-18 18:50:12,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2022-11-18 18:50:12,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2022-11-18 18:50:12,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:12,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-18 18:50:12,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:50:12,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-18 18:50:12,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-18 18:50:12,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-18 18:50:12,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:12,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:12,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:12,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:12,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:12,998 INFO L748 eck$LassoCheckResult]: Stem: 3546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3557#L367 assume !(main_~length~0#1 < 1); 3548#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3549#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3558#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3559#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3560#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3586#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3583#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3579#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3574#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3573#L370-4 main_~j~0#1 := 0; 3572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3553#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3562#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3569#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3568#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3564#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3551#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-18 18:50:12,998 INFO L750 eck$LassoCheckResult]: Loop: 3552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3565#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-18 18:50:12,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:12,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 9 times [2022-11-18 18:50:12,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:12,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532915903] [2022-11-18 18:50:12,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:13,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:13,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:13,223 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2022-11-18 18:50:13,402 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:13,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:13,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532915903] [2022-11-18 18:50:13,403 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532915903] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:13,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1455094053] [2022-11-18 18:50:13,404 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:50:13,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:13,404 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:13,407 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:13,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-18 18:50:13,567 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 18:50:13,567 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:13,569 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-18 18:50:13,571 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:13,703 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:14,256 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:50:14,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:50:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:14,262 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:14,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:50:14,955 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:50:15,065 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:15,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1455094053] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:15,065 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:15,065 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2022-11-18 18:50:15,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832694658] [2022-11-18 18:50:15,066 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:15,066 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:15,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:15,066 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-18 18:50:15,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:15,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264959835] [2022-11-18 18:50:15,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:15,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:15,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:15,070 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:15,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:15,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:15,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:15,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-18 18:50:15,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=1288, Unknown=0, NotChecked=0, Total=1482 [2022-11-18 18:50:15,127 INFO L87 Difference]: Start difference. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 39 states, 38 states have (on average 1.9210526315789473) internal successors, (73), 39 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:16,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:16,069 INFO L93 Difference]: Finished difference Result 60 states and 74 transitions. [2022-11-18 18:50:16,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 74 transitions. [2022-11-18 18:50:16,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:16,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 47 states and 59 transitions. [2022-11-18 18:50:16,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:50:16,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:50:16,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-18 18:50:16,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:16,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:50:16,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-18 18:50:16,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-11-18 18:50:16,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.2666666666666666) internal successors, (57), 44 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:16,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 57 transitions. [2022-11-18 18:50:16,073 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-18 18:50:16,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-18 18:50:16,074 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-18 18:50:16,074 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-18 18:50:16,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 57 transitions. [2022-11-18 18:50:16,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:16,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:16,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:16,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:16,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:16,076 INFO L748 eck$LassoCheckResult]: Stem: 3925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3936#L367 assume !(main_~length~0#1 < 1); 3927#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3928#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3929#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3969#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3939#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3967#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3965#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3964#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3963#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3961#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3942#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3958#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3952#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3934#L370-4 main_~j~0#1 := 0; 3935#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3932#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3933#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3948#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3946#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3930#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-18 18:50:16,077 INFO L750 eck$LassoCheckResult]: Loop: 3931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3944#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-18 18:50:16,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:16,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1236423398, now seen corresponding path program 4 times [2022-11-18 18:50:16,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:16,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549602485] [2022-11-18 18:50:16,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:16,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:16,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:16,654 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:16,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:16,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549602485] [2022-11-18 18:50:16,655 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549602485] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:16,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1550651231] [2022-11-18 18:50:16,655 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:50:16,655 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:16,655 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:16,657 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:16,677 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-18 18:50:16,770 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:50:16,771 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:16,773 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-18 18:50:16,775 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:16,823 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:16,912 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:16,912 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:16,933 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:16,934 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:17,008 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:17,008 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:17,137 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:17,141 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:17,141 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:17,390 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:50:17,393 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:50:17,440 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:50:17,440 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1550651231] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:17,440 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:17,441 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-18 18:50:17,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720822912] [2022-11-18 18:50:17,441 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:17,442 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:17,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:17,443 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-18 18:50:17,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:17,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882959685] [2022-11-18 18:50:17,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:17,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:17,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:17,447 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:17,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:17,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:17,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:17,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-18 18:50:17,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=478, Unknown=0, NotChecked=0, Total=552 [2022-11-18 18:50:17,508 INFO L87 Difference]: Start difference. First operand 45 states and 57 transitions. cyclomatic complexity: 17 Second operand has 24 states, 23 states have (on average 2.217391304347826) internal successors, (51), 24 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:17,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:17,952 INFO L93 Difference]: Finished difference Result 54 states and 66 transitions. [2022-11-18 18:50:17,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 66 transitions. [2022-11-18 18:50:17,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:17,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 65 transitions. [2022-11-18 18:50:17,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:50:17,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:50:17,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 65 transitions. [2022-11-18 18:50:17,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:17,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 65 transitions. [2022-11-18 18:50:17,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 65 transitions. [2022-11-18 18:50:17,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 40. [2022-11-18 18:50:17,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.25) internal successors, (50), 39 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:17,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2022-11-18 18:50:17,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-18 18:50:17,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 18:50:17,967 INFO L428 stractBuchiCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-18 18:50:17,967 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-18 18:50:17,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 50 transitions. [2022-11-18 18:50:17,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:17,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:17,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:17,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:17,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:17,969 INFO L748 eck$LassoCheckResult]: Stem: 4253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4264#L367 assume !(main_~length~0#1 < 1); 4255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4265#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4270#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4291#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4289#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4288#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4285#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4283#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4282#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4279#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4275#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4262#L370-4 main_~j~0#1 := 0; 4263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4268#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4260#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4258#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-18 18:50:17,969 INFO L750 eck$LassoCheckResult]: Loop: 4259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4274#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-18 18:50:17,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:17,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1503052245, now seen corresponding path program 5 times [2022-11-18 18:50:17,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:17,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20061826] [2022-11-18 18:50:17,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:17,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:17,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:18,443 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:18,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:18,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20061826] [2022-11-18 18:50:18,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20061826] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:18,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1599428002] [2022-11-18 18:50:18,443 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:50:18,443 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:18,443 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:18,451 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:18,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-18 18:50:18,594 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-18 18:50:18,595 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:18,597 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-18 18:50:18,598 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:18,830 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:18,905 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:18,906 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:19,321 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:50:19,326 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:50:19,326 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:50:19,355 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:19,355 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:20,068 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-18 18:50:20,076 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 78 [2022-11-18 18:50:20,172 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:20,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1599428002] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:20,173 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:20,173 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 16] total 40 [2022-11-18 18:50:20,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375009311] [2022-11-18 18:50:20,173 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:20,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:20,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:20,174 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-18 18:50:20,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:20,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351064617] [2022-11-18 18:50:20,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:20,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:20,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:20,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:20,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:20,182 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:20,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:20,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:50:20,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=1492, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:50:20,232 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. cyclomatic complexity: 14 Second operand has 41 states, 40 states have (on average 2.075) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:21,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:21,184 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2022-11-18 18:50:21,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 77 transitions. [2022-11-18 18:50:21,185 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:50:21,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 76 transitions. [2022-11-18 18:50:21,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 18:50:21,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 18:50:21,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 76 transitions. [2022-11-18 18:50:21,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:21,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 76 transitions. [2022-11-18 18:50:21,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 76 transitions. [2022-11-18 18:50:21,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 47. [2022-11-18 18:50:21,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2553191489361701) internal successors, (59), 46 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:21,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 59 transitions. [2022-11-18 18:50:21,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:50:21,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:50:21,195 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-18 18:50:21,196 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-18 18:50:21,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 59 transitions. [2022-11-18 18:50:21,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:21,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:21,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:21,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:21,197 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:21,198 INFO L748 eck$LassoCheckResult]: Stem: 4622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4633#L367 assume !(main_~length~0#1 < 1); 4624#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4625#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4634#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4640#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4636#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4656#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4650#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4648#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4667#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4666#L370-4 main_~j~0#1 := 0; 4637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4629#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4664#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4662#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4659#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4627#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-18 18:50:21,198 INFO L750 eck$LassoCheckResult]: Loop: 4628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4660#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-18 18:50:21,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:21,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 10 times [2022-11-18 18:50:21,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:21,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327050195] [2022-11-18 18:50:21,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:21,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:21,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:21,722 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:21,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:21,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327050195] [2022-11-18 18:50:21,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327050195] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:21,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1764733304] [2022-11-18 18:50:21,722 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:50:21,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:21,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:21,727 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:21,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-18 18:50:21,837 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:50:21,837 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:21,839 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 18:50:21,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:21,895 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:22,001 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:50:22,001 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:50:22,192 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:22,194 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:22,195 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:22,413 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:50:22,416 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:50:22,497 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:22,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1764733304] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:22,498 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:22,498 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-11-18 18:50:22,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478512948] [2022-11-18 18:50:22,498 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:22,498 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:22,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:22,499 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-18 18:50:22,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:22,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970765611] [2022-11-18 18:50:22,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:22,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:22,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:22,503 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:22,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:22,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:22,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:22,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-18 18:50:22,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2022-11-18 18:50:22,567 INFO L87 Difference]: Start difference. First operand 47 states and 59 transitions. cyclomatic complexity: 17 Second operand has 26 states, 25 states have (on average 2.12) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:22,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:22,960 INFO L93 Difference]: Finished difference Result 84 states and 102 transitions. [2022-11-18 18:50:22,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 102 transitions. [2022-11-18 18:50:22,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:50:22,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 101 transitions. [2022-11-18 18:50:22,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-18 18:50:22,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-18 18:50:22,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 101 transitions. [2022-11-18 18:50:22,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:22,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 101 transitions. [2022-11-18 18:50:22,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 101 transitions. [2022-11-18 18:50:22,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 50. [2022-11-18 18:50:22,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.28) internal successors, (64), 49 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:22,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 64 transitions. [2022-11-18 18:50:22,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-18 18:50:22,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:50:22,965 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-18 18:50:22,965 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-18 18:50:22,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 64 transitions. [2022-11-18 18:50:22,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:22,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:22,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:22,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:22,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:22,967 INFO L748 eck$LassoCheckResult]: Stem: 4988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4999#L367 assume !(main_~length~0#1 < 1); 4990#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4991#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5000#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5035#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5032#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5029#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5002#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5004#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4993#L370-4 main_~j~0#1 := 0; 4994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4997#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4998#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5006#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5016#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5015#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5014#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5013#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5012#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5010#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4995#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-18 18:50:22,967 INFO L750 eck$LassoCheckResult]: Loop: 4996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5011#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-18 18:50:22,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:22,967 INFO L85 PathProgramCache]: Analyzing trace with hash -1324192720, now seen corresponding path program 6 times [2022-11-18 18:50:22,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:22,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108804523] [2022-11-18 18:50:22,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:22,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:22,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:23,435 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:23,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:23,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108804523] [2022-11-18 18:50:23,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108804523] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:23,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [146566087] [2022-11-18 18:50:23,435 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:50:23,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:23,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:23,442 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:23,455 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-18 18:50:23,617 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-18 18:50:23,617 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:23,619 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-18 18:50:23,620 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:23,870 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:50:24,281 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:50:24,285 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:24,286 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:24,437 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:50:24,441 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:50:24,512 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:24,512 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [146566087] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:24,512 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:24,512 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 16] total 34 [2022-11-18 18:50:24,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469530430] [2022-11-18 18:50:24,512 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:24,513 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:24,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:24,513 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-18 18:50:24,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:24,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26509468] [2022-11-18 18:50:24,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:24,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:24,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:24,517 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:24,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:24,520 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:24,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:24,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 18:50:24,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=1066, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 18:50:24,575 INFO L87 Difference]: Start difference. First operand 50 states and 64 transitions. cyclomatic complexity: 19 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:25,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:25,290 INFO L93 Difference]: Finished difference Result 105 states and 133 transitions. [2022-11-18 18:50:25,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 133 transitions. [2022-11-18 18:50:25,291 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14 [2022-11-18 18:50:25,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 132 transitions. [2022-11-18 18:50:25,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2022-11-18 18:50:25,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2022-11-18 18:50:25,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 132 transitions. [2022-11-18 18:50:25,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:25,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104 states and 132 transitions. [2022-11-18 18:50:25,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 132 transitions. [2022-11-18 18:50:25,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 89. [2022-11-18 18:50:25,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.2921348314606742) internal successors, (115), 88 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:25,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 115 transitions. [2022-11-18 18:50:25,305 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89 states and 115 transitions. [2022-11-18 18:50:25,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-18 18:50:25,306 INFO L428 stractBuchiCegarLoop]: Abstraction has 89 states and 115 transitions. [2022-11-18 18:50:25,306 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-18 18:50:25,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 115 transitions. [2022-11-18 18:50:25,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-18 18:50:25,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:25,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:25,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:25,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:25,308 INFO L748 eck$LassoCheckResult]: Stem: 5405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5416#L367 assume !(main_~length~0#1 < 1); 5407#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5408#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5409#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5417#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5445#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5444#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5443#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5442#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5441#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5440#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5438#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5437#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5436#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5434#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5433#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5432#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5468#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5464#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5466#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5476#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5475#L370-4 main_~j~0#1 := 0; 5474#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5472#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5470#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5448#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5450#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5452#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5411#L378-2 [2022-11-18 18:50:25,309 INFO L750 eck$LassoCheckResult]: Loop: 5411#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5446#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5411#L378-2 [2022-11-18 18:50:25,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:25,310 INFO L85 PathProgramCache]: Analyzing trace with hash -711621579, now seen corresponding path program 7 times [2022-11-18 18:50:25,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:25,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637247068] [2022-11-18 18:50:25,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:25,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:25,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:25,979 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:25,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:25,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637247068] [2022-11-18 18:50:25,980 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637247068] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:25,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2087452586] [2022-11-18 18:50:25,980 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:50:25,980 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:25,980 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:25,991 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:25,999 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-18 18:50:26,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:26,119 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-18 18:50:26,122 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:26,331 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:26,459 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:26,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:26,523 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:26,524 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:26,536 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:50:26,828 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:50:26,832 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:26,832 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:27,268 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-18 18:50:27,273 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 61 [2022-11-18 18:50:27,352 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:27,352 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2087452586] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:27,353 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:27,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 38 [2022-11-18 18:50:27,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479251359] [2022-11-18 18:50:27,353 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:27,353 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:27,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:27,354 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-18 18:50:27,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:27,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588767259] [2022-11-18 18:50:27,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:27,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:27,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:27,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:27,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:27,363 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:27,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:27,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-18 18:50:27,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=1320, Unknown=0, NotChecked=0, Total=1482 [2022-11-18 18:50:27,414 INFO L87 Difference]: Start difference. First operand 89 states and 115 transitions. cyclomatic complexity: 34 Second operand has 39 states, 38 states have (on average 2.1315789473684212) internal successors, (81), 39 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:28,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:28,626 INFO L93 Difference]: Finished difference Result 234 states and 286 transitions. [2022-11-18 18:50:28,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234 states and 286 transitions. [2022-11-18 18:50:28,639 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 18 [2022-11-18 18:50:28,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234 states to 231 states and 283 transitions. [2022-11-18 18:50:28,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61 [2022-11-18 18:50:28,646 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61 [2022-11-18 18:50:28,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231 states and 283 transitions. [2022-11-18 18:50:28,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:28,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 231 states and 283 transitions. [2022-11-18 18:50:28,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states and 283 transitions. [2022-11-18 18:50:28,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 103. [2022-11-18 18:50:28,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.3398058252427185) internal successors, (138), 102 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:28,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 138 transitions. [2022-11-18 18:50:28,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 138 transitions. [2022-11-18 18:50:28,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2022-11-18 18:50:28,656 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 138 transitions. [2022-11-18 18:50:28,656 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-18 18:50:28,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 138 transitions. [2022-11-18 18:50:28,657 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-18 18:50:28,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:28,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:28,658 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:28,658 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:28,659 INFO L748 eck$LassoCheckResult]: Stem: 6029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6040#L367 assume !(main_~length~0#1 < 1); 6031#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6032#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6041#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6100#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6099#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6098#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6097#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6096#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6095#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6094#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6093#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6092#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6087#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6104#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6048#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6073#L370-4 main_~j~0#1 := 0; 6118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6117#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6038#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6109#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6108#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6107#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6106#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6052#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6057#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6055#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6058#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6037#L378-2 [2022-11-18 18:50:28,659 INFO L750 eck$LassoCheckResult]: Loop: 6037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6054#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6037#L378-2 [2022-11-18 18:50:28,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:28,659 INFO L85 PathProgramCache]: Analyzing trace with hash -1238881035, now seen corresponding path program 8 times [2022-11-18 18:50:28,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:28,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207211258] [2022-11-18 18:50:28,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:28,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:28,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:28,970 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:28,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:28,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207211258] [2022-11-18 18:50:28,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [207211258] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:28,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937823051] [2022-11-18 18:50:28,970 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:50:28,970 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:28,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:28,979 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:29,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-18 18:50:29,113 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:50:29,113 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:29,115 INFO L263 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-18 18:50:29,116 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:29,368 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:29,368 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:29,547 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:29,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937823051] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:29,548 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:29,548 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 26 [2022-11-18 18:50:29,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572105331] [2022-11-18 18:50:29,549 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:29,549 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:29,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:29,550 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-18 18:50:29,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:29,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993604172] [2022-11-18 18:50:29,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:29,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:29,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:29,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:29,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:29,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:29,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:29,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-18 18:50:29,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=493, Unknown=0, NotChecked=0, Total=650 [2022-11-18 18:50:29,616 INFO L87 Difference]: Start difference. First operand 103 states and 138 transitions. cyclomatic complexity: 43 Second operand has 26 states, 26 states have (on average 2.3076923076923075) internal successors, (60), 26 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:29,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:29,868 INFO L93 Difference]: Finished difference Result 129 states and 167 transitions. [2022-11-18 18:50:29,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 167 transitions. [2022-11-18 18:50:29,869 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-18 18:50:29,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 115 states and 151 transitions. [2022-11-18 18:50:29,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2022-11-18 18:50:29,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-11-18 18:50:29,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 151 transitions. [2022-11-18 18:50:29,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:29,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 151 transitions. [2022-11-18 18:50:29,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 151 transitions. [2022-11-18 18:50:29,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 107. [2022-11-18 18:50:29,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107 states, 107 states have (on average 1.3177570093457944) internal successors, (141), 106 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:29,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 141 transitions. [2022-11-18 18:50:29,876 INFO L240 hiAutomatonCegarLoop]: Abstraction has 107 states and 141 transitions. [2022-11-18 18:50:29,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:50:29,877 INFO L428 stractBuchiCegarLoop]: Abstraction has 107 states and 141 transitions. [2022-11-18 18:50:29,877 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-18 18:50:29,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states and 141 transitions. [2022-11-18 18:50:29,878 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-18 18:50:29,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:29,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:29,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:29,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:29,879 INFO L748 eck$LassoCheckResult]: Stem: 6534#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6545#L367 assume !(main_~length~0#1 < 1); 6536#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6537#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6538#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6546#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6622#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6619#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6616#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6610#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6611#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6630#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6549#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6551#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6547#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6548#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6584#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6582#L370-4 main_~j~0#1 := 0; 6579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6552#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6573#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6569#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6567#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6557#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6564#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6559#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6560#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6563#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6542#L378-2 [2022-11-18 18:50:29,879 INFO L750 eck$LassoCheckResult]: Loop: 6542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6631#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6542#L378-2 [2022-11-18 18:50:29,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:29,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1187388804, now seen corresponding path program 9 times [2022-11-18 18:50:29,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:29,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690052494] [2022-11-18 18:50:29,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:29,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:29,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:30,569 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:30,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:30,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690052494] [2022-11-18 18:50:30,570 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690052494] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:30,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [764892480] [2022-11-18 18:50:30,570 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:50:30,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:30,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:30,574 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:30,595 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-18 18:50:30,878 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-18 18:50:30,878 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:30,880 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-18 18:50:30,883 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:30,938 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:31,051 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:50:31,052 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:50:31,086 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:50:31,086 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:50:31,310 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:31,313 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:31,313 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:31,544 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:50:31,548 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:50:31,623 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:31,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [764892480] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:31,624 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:31,624 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-11-18 18:50:31,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [861519011] [2022-11-18 18:50:31,625 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:31,625 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:31,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:31,626 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-18 18:50:31,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:31,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880067737] [2022-11-18 18:50:31,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:31,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:31,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:31,630 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:31,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:31,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:31,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:31,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-18 18:50:31,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=729, Unknown=0, NotChecked=0, Total=812 [2022-11-18 18:50:31,690 INFO L87 Difference]: Start difference. First operand 107 states and 141 transitions. cyclomatic complexity: 42 Second operand has 29 states, 28 states have (on average 2.1785714285714284) internal successors, (61), 29 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:32,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:32,425 INFO L93 Difference]: Finished difference Result 222 states and 283 transitions. [2022-11-18 18:50:32,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 283 transitions. [2022-11-18 18:50:32,427 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36 [2022-11-18 18:50:32,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 221 states and 282 transitions. [2022-11-18 18:50:32,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2022-11-18 18:50:32,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2022-11-18 18:50:32,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 282 transitions. [2022-11-18 18:50:32,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:32,430 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 282 transitions. [2022-11-18 18:50:32,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 282 transitions. [2022-11-18 18:50:32,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 121. [2022-11-18 18:50:32,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121 states, 121 states have (on average 1.3553719008264462) internal successors, (164), 120 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:32,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 164 transitions. [2022-11-18 18:50:32,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121 states and 164 transitions. [2022-11-18 18:50:32,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 18:50:32,436 INFO L428 stractBuchiCegarLoop]: Abstraction has 121 states and 164 transitions. [2022-11-18 18:50:32,436 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-18 18:50:32,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121 states and 164 transitions. [2022-11-18 18:50:32,437 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-18 18:50:32,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:32,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:32,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:32,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:32,438 INFO L748 eck$LassoCheckResult]: Stem: 7145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7156#L367 assume !(main_~length~0#1 < 1); 7147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7157#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7191#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7189#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7186#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7183#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7182#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7179#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7180#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7170#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7171#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7223#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7224#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7212#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7218#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7243#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7242#L370-4 main_~j~0#1 := 0; 7241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7237#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7196#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7201#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7198#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7200#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7153#L378-2 [2022-11-18 18:50:32,438 INFO L750 eck$LassoCheckResult]: Loop: 7153#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7256#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7153#L378-2 [2022-11-18 18:50:32,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:32,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1946926163, now seen corresponding path program 10 times [2022-11-18 18:50:32,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:32,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76581496] [2022-11-18 18:50:32,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:32,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:32,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:33,182 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 3 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:33,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:33,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76581496] [2022-11-18 18:50:33,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76581496] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:33,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [312543739] [2022-11-18 18:50:33,183 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:50:33,183 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:33,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:33,191 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:33,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-18 18:50:33,341 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:50:33,341 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:33,343 INFO L263 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-18 18:50:33,346 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:33,396 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:33,509 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:33,509 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:33,529 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:33,530 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:33,552 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:33,553 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:33,572 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:33,572 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:33,623 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-18 18:50:33,623 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:33,795 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:50:33,798 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 5 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:33,798 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:34,174 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:50:34,177 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:50:34,235 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 2 proven. 105 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-18 18:50:34,235 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [312543739] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:34,236 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:34,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 17] total 27 [2022-11-18 18:50:34,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205587286] [2022-11-18 18:50:34,237 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:34,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:34,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:34,237 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-18 18:50:34,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:34,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372489198] [2022-11-18 18:50:34,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:34,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:34,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:34,241 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:34,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:34,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:34,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:34,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-18 18:50:34,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=666, Unknown=0, NotChecked=0, Total=756 [2022-11-18 18:50:34,308 INFO L87 Difference]: Start difference. First operand 121 states and 164 transitions. cyclomatic complexity: 51 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:34,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:34,830 INFO L93 Difference]: Finished difference Result 130 states and 167 transitions. [2022-11-18 18:50:34,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 167 transitions. [2022-11-18 18:50:34,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:34,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 128 states and 165 transitions. [2022-11-18 18:50:34,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 18:50:34,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 18:50:34,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 165 transitions. [2022-11-18 18:50:34,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:34,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 165 transitions. [2022-11-18 18:50:34,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 165 transitions. [2022-11-18 18:50:34,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 64. [2022-11-18 18:50:34,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.296875) internal successors, (83), 63 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:34,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 83 transitions. [2022-11-18 18:50:34,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 83 transitions. [2022-11-18 18:50:34,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-18 18:50:34,836 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 83 transitions. [2022-11-18 18:50:34,836 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-18 18:50:34,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 83 transitions. [2022-11-18 18:50:34,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:50:34,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:34,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:34,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:34,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:50:34,838 INFO L748 eck$LassoCheckResult]: Stem: 7679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7690#L367 assume !(main_~length~0#1 < 1); 7681#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7682#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7691#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7735#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7733#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7730#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7728#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7722#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7720#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7719#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7699#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7700#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7684#L370-4 main_~j~0#1 := 0; 7685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7713#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7688#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7712#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7710#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7705#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7702#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7686#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7687#L378-2 [2022-11-18 18:50:34,838 INFO L750 eck$LassoCheckResult]: Loop: 7687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7703#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7687#L378-2 [2022-11-18 18:50:34,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:34,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1036183171, now seen corresponding path program 11 times [2022-11-18 18:50:34,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:34,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334018275] [2022-11-18 18:50:34,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:34,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:34,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:35,393 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:35,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:35,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334018275] [2022-11-18 18:50:35,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334018275] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:35,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [822921486] [2022-11-18 18:50:35,394 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:50:35,394 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:35,394 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:35,398 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:35,418 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-18 18:50:35,553 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-18 18:50:35,553 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:35,555 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-18 18:50:35,557 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:35,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:50:36,354 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:50:36,356 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:50:36,357 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:50:36,360 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:36,361 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:36,588 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:50:36,591 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:50:36,663 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:36,663 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [822921486] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:36,663 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:36,663 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 40 [2022-11-18 18:50:36,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511356575] [2022-11-18 18:50:36,663 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:36,664 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:36,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:36,664 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-18 18:50:36,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:36,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334662355] [2022-11-18 18:50:36,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:36,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:36,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:36,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:36,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:36,671 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:36,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:36,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:50:36,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=1488, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:50:36,723 INFO L87 Difference]: Start difference. First operand 64 states and 83 transitions. cyclomatic complexity: 24 Second operand has 41 states, 40 states have (on average 2.15) internal successors, (86), 41 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:37,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:50:37,554 INFO L93 Difference]: Finished difference Result 121 states and 153 transitions. [2022-11-18 18:50:37,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 153 transitions. [2022-11-18 18:50:37,556 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17 [2022-11-18 18:50:37,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 120 states and 152 transitions. [2022-11-18 18:50:37,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2022-11-18 18:50:37,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36 [2022-11-18 18:50:37,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 152 transitions. [2022-11-18 18:50:37,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:50:37,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 152 transitions. [2022-11-18 18:50:37,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 152 transitions. [2022-11-18 18:50:37,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 103. [2022-11-18 18:50:37,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.2912621359223302) internal successors, (133), 102 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:50:37,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 133 transitions. [2022-11-18 18:50:37,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-18 18:50:37,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:50:37,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-18 18:50:37,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-18 18:50:37,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 133 transitions. [2022-11-18 18:50:37,570 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:50:37,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:50:37,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:50:37,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:50:37,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:50:37,571 INFO L748 eck$LassoCheckResult]: Stem: 8162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8173#L367 assume !(main_~length~0#1 < 1); 8164#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8165#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8166#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8174#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8177#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8207#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8206#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8205#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8204#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8203#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8202#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8201#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8200#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8198#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8193#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8175#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8176#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8234#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8231#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8228#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8227#L370-4 main_~j~0#1 := 0; 8226#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8225#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8224#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8223#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8222#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8221#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8219#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8217#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8211#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8254#L378-2 [2022-11-18 18:50:37,571 INFO L750 eck$LassoCheckResult]: Loop: 8254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8256#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8257#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8258#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8254#L378-2 [2022-11-18 18:50:37,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:37,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1469153072, now seen corresponding path program 12 times [2022-11-18 18:50:37,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:37,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632102828] [2022-11-18 18:50:37,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:37,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:37,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:50:38,280 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:38,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:50:38,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632102828] [2022-11-18 18:50:38,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632102828] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:50:38,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1876866310] [2022-11-18 18:50:38,281 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:50:38,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:50:38,282 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:50:38,287 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:50:38,311 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-18 18:50:38,586 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-18 18:50:38,587 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:50:38,589 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-18 18:50:38,592 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:50:38,847 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:50:38,935 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:38,936 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:38,951 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:38,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:50:39,084 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:39,086 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:39,087 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:39,090 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:50:39,090 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 38 [2022-11-18 18:50:39,740 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:50:39,745 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:50:39,746 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 24 treesize of output 10 [2022-11-18 18:50:39,783 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:50:39,783 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:50:44,314 WARN L837 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_302| Int) (v_ArrVal_917 Int)) (or (< (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_302| 4)) v_ArrVal_917) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 1) (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_302|)))) is different from false [2022-11-18 18:50:44,627 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2022-11-18 18:50:44,633 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 472 treesize of output 456 [2022-11-18 18:50:44,852 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 103 refuted. 3 times theorem prover too weak. 0 trivial. 15 not checked. [2022-11-18 18:50:44,852 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1876866310] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:50:44,853 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:50:44,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 20, 19] total 48 [2022-11-18 18:50:44,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198605602] [2022-11-18 18:50:44,854 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:50:44,855 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:50:44,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:50:44,856 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 1 times [2022-11-18 18:50:44,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:50:44,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39400436] [2022-11-18 18:50:44,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:50:44,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:50:44,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:44,869 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:50:44,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:50:44,874 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:50:44,977 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:50:44,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 18:50:44,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=2044, Unknown=6, NotChecked=92, Total=2352 [2022-11-18 18:50:44,979 INFO L87 Difference]: Start difference. First operand 103 states and 133 transitions. cyclomatic complexity: 37 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:03,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:03,364 INFO L93 Difference]: Finished difference Result 224 states and 274 transitions. [2022-11-18 18:51:03,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224 states and 274 transitions. [2022-11-18 18:51:03,366 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-11-18 18:51:03,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224 states to 222 states and 270 transitions. [2022-11-18 18:51:03,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2022-11-18 18:51:03,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2022-11-18 18:51:03,368 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 270 transitions. [2022-11-18 18:51:03,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:03,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 270 transitions. [2022-11-18 18:51:03,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 270 transitions. [2022-11-18 18:51:03,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 112. [2022-11-18 18:51:03,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 112 states have (on average 1.3125) internal successors, (147), 111 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:03,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 147 transitions. [2022-11-18 18:51:03,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 112 states and 147 transitions. [2022-11-18 18:51:03,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-18 18:51:03,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 112 states and 147 transitions. [2022-11-18 18:51:03,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-18 18:51:03,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112 states and 147 transitions. [2022-11-18 18:51:03,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:51:03,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:03,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:03,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:03,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:03,377 INFO L748 eck$LassoCheckResult]: Stem: 8839#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8850#L367 assume !(main_~length~0#1 < 1); 8841#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8842#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8851#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8905#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8902#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8900#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8899#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8895#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8889#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8888#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8887#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8885#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8882#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8879#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8922#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8921#L370-4 main_~j~0#1 := 0; 8920#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8919#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8918#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8917#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8916#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8915#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8862#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8865#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8863#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8866#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8845#L378-2 [2022-11-18 18:51:03,377 INFO L750 eck$LassoCheckResult]: Loop: 8845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8859#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8845#L378-2 [2022-11-18 18:51:03,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:03,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1585891152, now seen corresponding path program 13 times [2022-11-18 18:51:03,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:03,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146363230] [2022-11-18 18:51:03,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:03,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:03,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:04,140 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:04,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:04,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146363230] [2022-11-18 18:51:04,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146363230] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:04,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1077650098] [2022-11-18 18:51:04,141 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:51:04,141 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:04,141 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:04,146 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:04,163 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-18 18:51:04,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:04,303 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-18 18:51:04,306 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:04,558 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:04,735 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:04,736 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:04,749 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:04,750 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:04,808 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:04,809 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:04,822 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:51:05,197 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:51:05,200 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:05,200 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:05,739 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-18 18:51:05,744 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 129 [2022-11-18 18:51:05,845 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:05,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1077650098] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:05,845 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:05,845 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 20] total 42 [2022-11-18 18:51:05,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698507828] [2022-11-18 18:51:05,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:05,847 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:05,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:05,847 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-18 18:51:05,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:05,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793076414] [2022-11-18 18:51:05,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:05,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:05,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:05,852 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:05,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:05,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:05,909 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:05,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-18 18:51:05,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=1630, Unknown=0, NotChecked=0, Total=1806 [2022-11-18 18:51:05,911 INFO L87 Difference]: Start difference. First operand 112 states and 147 transitions. cyclomatic complexity: 44 Second operand has 43 states, 42 states have (on average 2.1666666666666665) internal successors, (91), 43 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:07,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:07,635 INFO L93 Difference]: Finished difference Result 359 states and 432 transitions. [2022-11-18 18:51:07,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 359 states and 432 transitions. [2022-11-18 18:51:07,638 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22 [2022-11-18 18:51:07,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 359 states to 353 states and 426 transitions. [2022-11-18 18:51:07,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2022-11-18 18:51:07,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2022-11-18 18:51:07,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 426 transitions. [2022-11-18 18:51:07,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:07,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 426 transitions. [2022-11-18 18:51:07,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 426 transitions. [2022-11-18 18:51:07,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 133. [2022-11-18 18:51:07,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 133 states have (on average 1.368421052631579) internal successors, (182), 132 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:07,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 182 transitions. [2022-11-18 18:51:07,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133 states and 182 transitions. [2022-11-18 18:51:07,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-18 18:51:07,647 INFO L428 stractBuchiCegarLoop]: Abstraction has 133 states and 182 transitions. [2022-11-18 18:51:07,647 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-18 18:51:07,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133 states and 182 transitions. [2022-11-18 18:51:07,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:51:07,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:07,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:07,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:07,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:07,650 INFO L748 eck$LassoCheckResult]: Stem: 9663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9674#L367 assume !(main_~length~0#1 < 1); 9665#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9666#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9675#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9744#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9743#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9742#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9741#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9740#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9739#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9735#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9732#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9727#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9792#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9793#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9682#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9708#L370-4 main_~j~0#1 := 0; 9789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9788#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9672#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9767#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9766#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9765#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9764#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9763#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9687#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9688#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9691#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9671#L378-2 [2022-11-18 18:51:07,650 INFO L750 eck$LassoCheckResult]: Loop: 9671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9684#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9671#L378-2 [2022-11-18 18:51:07,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:07,651 INFO L85 PathProgramCache]: Analyzing trace with hash 660388610, now seen corresponding path program 14 times [2022-11-18 18:51:07,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:07,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188118008] [2022-11-18 18:51:07,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:07,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:07,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:08,017 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:08,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:08,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188118008] [2022-11-18 18:51:08,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188118008] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:08,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [577737553] [2022-11-18 18:51:08,018 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:51:08,018 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:08,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:08,022 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:08,043 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-18 18:51:08,184 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:51:08,184 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:08,186 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:51:08,187 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:08,486 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:08,486 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:08,774 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:08,774 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [577737553] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:08,774 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:08,774 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 29 [2022-11-18 18:51:08,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546542917] [2022-11-18 18:51:08,774 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:08,775 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:08,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:08,775 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-18 18:51:08,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:08,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889999256] [2022-11-18 18:51:08,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:08,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:08,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:08,778 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:08,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:08,781 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:08,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:08,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-18 18:51:08,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=618, Unknown=0, NotChecked=0, Total=812 [2022-11-18 18:51:08,831 INFO L87 Difference]: Start difference. First operand 133 states and 182 transitions. cyclomatic complexity: 58 Second operand has 29 states, 29 states have (on average 2.310344827586207) internal successors, (67), 29 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:09,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:09,082 INFO L93 Difference]: Finished difference Result 155 states and 205 transitions. [2022-11-18 18:51:09,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 205 transitions. [2022-11-18 18:51:09,083 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:51:09,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 139 states and 187 transitions. [2022-11-18 18:51:09,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2022-11-18 18:51:09,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2022-11-18 18:51:09,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 187 transitions. [2022-11-18 18:51:09,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:09,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 139 states and 187 transitions. [2022-11-18 18:51:09,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 187 transitions. [2022-11-18 18:51:09,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2022-11-18 18:51:09,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 135 states, 135 states have (on average 1.348148148148148) internal successors, (182), 134 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:09,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 182 transitions. [2022-11-18 18:51:09,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 135 states and 182 transitions. [2022-11-18 18:51:09,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-18 18:51:09,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 135 states and 182 transitions. [2022-11-18 18:51:09,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-18 18:51:09,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135 states and 182 transitions. [2022-11-18 18:51:09,090 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:51:09,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:09,091 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:09,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:09,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:09,092 INFO L748 eck$LassoCheckResult]: Stem: 10259#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10270#L367 assume !(main_~length~0#1 < 1); 10261#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10262#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10263#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10271#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10362#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10361#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10360#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10359#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10358#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10357#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10356#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10355#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10354#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10353#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10352#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10350#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10346#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10342#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10364#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10334#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10315#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10313#L370-4 main_~j~0#1 := 0; 10310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10274#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10307#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10305#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10299#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10297#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10286#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10287#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10291#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10265#L378-2 [2022-11-18 18:51:09,092 INFO L750 eck$LassoCheckResult]: Loop: 10265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10382#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10265#L378-2 [2022-11-18 18:51:09,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:09,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1228711609, now seen corresponding path program 15 times [2022-11-18 18:51:09,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:09,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423735520] [2022-11-18 18:51:09,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:09,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:09,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:09,784 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:09,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:09,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423735520] [2022-11-18 18:51:09,785 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423735520] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:09,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1242762263] [2022-11-18 18:51:09,785 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:51:09,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:09,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:09,791 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:09,809 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-18 18:51:10,094 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2022-11-18 18:51:10,095 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:10,097 INFO L263 TraceCheckSpWp]: Trace formula consists of 246 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-18 18:51:10,099 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:10,168 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:10,301 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:51:10,301 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:51:10,331 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:51:10,331 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:51:10,624 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:51:10,627 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:10,627 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:10,904 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:51:10,908 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:51:10,990 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:10,991 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1242762263] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:10,991 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:10,991 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-11-18 18:51:10,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947175049] [2022-11-18 18:51:10,991 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:10,992 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:10,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:10,992 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-18 18:51:10,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:10,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896931424] [2022-11-18 18:51:10,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:10,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:10,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:10,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:10,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:10,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:11,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:11,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-18 18:51:11,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=901, Unknown=0, NotChecked=0, Total=992 [2022-11-18 18:51:11,049 INFO L87 Difference]: Start difference. First operand 135 states and 182 transitions. cyclomatic complexity: 56 Second operand has 32 states, 31 states have (on average 2.193548387096774) internal successors, (68), 32 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:11,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:11,932 INFO L93 Difference]: Finished difference Result 202 states and 259 transitions. [2022-11-18 18:51:11,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202 states and 259 transitions. [2022-11-18 18:51:11,934 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 18 [2022-11-18 18:51:11,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202 states to 201 states and 258 transitions. [2022-11-18 18:51:11,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2022-11-18 18:51:11,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2022-11-18 18:51:11,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 258 transitions. [2022-11-18 18:51:11,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:11,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 258 transitions. [2022-11-18 18:51:11,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 258 transitions. [2022-11-18 18:51:11,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 143. [2022-11-18 18:51:11,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.3636363636363635) internal successors, (195), 142 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:11,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 195 transitions. [2022-11-18 18:51:11,941 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 195 transitions. [2022-11-18 18:51:11,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-18 18:51:11,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 143 states and 195 transitions. [2022-11-18 18:51:11,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-18 18:51:11,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 195 transitions. [2022-11-18 18:51:11,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-18 18:51:11,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:11,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:11,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:11,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:11,945 INFO L748 eck$LassoCheckResult]: Stem: 10913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10924#L367 assume !(main_~length~0#1 < 1); 10915#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10916#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10925#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10989#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10988#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10986#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10985#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10984#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10983#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10982#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10980#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10978#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10977#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10974#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10975#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11036#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10926#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10927#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10931#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10918#L370-4 main_~j~0#1 := 0; 10919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10922#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10930#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10996#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10994#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10935#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10940#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10937#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10938#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10939#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10921#L378-2 [2022-11-18 18:51:11,945 INFO L750 eck$LassoCheckResult]: Loop: 10921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10936#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10921#L378-2 [2022-11-18 18:51:11,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:11,946 INFO L85 PathProgramCache]: Analyzing trace with hash 663643002, now seen corresponding path program 16 times [2022-11-18 18:51:11,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:11,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956498606] [2022-11-18 18:51:11,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:11,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:11,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:12,564 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:12,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:12,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956498606] [2022-11-18 18:51:12,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956498606] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:12,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937518909] [2022-11-18 18:51:12,564 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:51:12,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:12,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:12,566 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:12,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-18 18:51:12,708 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:51:12,708 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:12,710 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-18 18:51:12,712 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:12,806 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:13,256 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:51:13,259 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:13,259 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:13,444 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:51:13,449 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:51:13,544 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:13,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937518909] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:13,545 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:13,545 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20, 20] total 31 [2022-11-18 18:51:13,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553432166] [2022-11-18 18:51:13,545 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:13,545 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:13,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:13,546 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-18 18:51:13,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:13,546 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126559949] [2022-11-18 18:51:13,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:13,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:13,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:13,549 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:13,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:13,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:13,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:13,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-18 18:51:13,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=899, Unknown=0, NotChecked=0, Total=992 [2022-11-18 18:51:13,616 INFO L87 Difference]: Start difference. First operand 143 states and 195 transitions. cyclomatic complexity: 61 Second operand has 32 states, 31 states have (on average 2.225806451612903) internal successors, (69), 32 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:14,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:14,339 INFO L93 Difference]: Finished difference Result 240 states and 318 transitions. [2022-11-18 18:51:14,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240 states and 318 transitions. [2022-11-18 18:51:14,341 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 42 [2022-11-18 18:51:14,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240 states to 239 states and 317 transitions. [2022-11-18 18:51:14,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2022-11-18 18:51:14,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2022-11-18 18:51:14,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 239 states and 317 transitions. [2022-11-18 18:51:14,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:14,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 239 states and 317 transitions. [2022-11-18 18:51:14,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states and 317 transitions. [2022-11-18 18:51:14,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 219. [2022-11-18 18:51:14,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.3470319634703196) internal successors, (295), 218 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:14,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 295 transitions. [2022-11-18 18:51:14,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219 states and 295 transitions. [2022-11-18 18:51:14,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:51:14,351 INFO L428 stractBuchiCegarLoop]: Abstraction has 219 states and 295 transitions. [2022-11-18 18:51:14,351 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-18 18:51:14,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 295 transitions. [2022-11-18 18:51:14,352 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 40 [2022-11-18 18:51:14,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:14,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:14,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:14,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:51:14,353 INFO L748 eck$LassoCheckResult]: Stem: 11609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11620#L367 assume !(main_~length~0#1 < 1); 11611#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11612#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11621#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11707#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11705#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11704#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11701#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11697#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11693#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11751#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11750#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11746#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11744#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11740#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11721#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11661#L370-4 main_~j~0#1 := 0; 11719#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11716#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11710#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11691#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11692#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11680#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11673#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11639#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11754#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11789#L378-2 [2022-11-18 18:51:14,354 INFO L750 eck$LassoCheckResult]: Loop: 11789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11806#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11788#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11789#L378-2 [2022-11-18 18:51:14,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:14,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1087248771, now seen corresponding path program 17 times [2022-11-18 18:51:14,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:14,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326043045] [2022-11-18 18:51:14,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:14,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:14,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:15,086 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:15,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:15,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326043045] [2022-11-18 18:51:15,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326043045] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:15,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1425811594] [2022-11-18 18:51:15,087 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:51:15,087 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:15,088 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:15,094 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:15,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-18 18:51:15,352 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-18 18:51:15,353 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:15,356 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-18 18:51:15,358 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:15,632 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:15,723 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:15,723 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:15,738 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:15,739 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:15,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:15,791 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:16,325 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:51:16,328 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:51:16,328 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:51:16,368 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 1 proven. 158 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:16,368 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:32,935 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-18 18:51:32,940 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 192 treesize of output 178 [2022-11-18 18:51:33,089 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 156 refuted. 2 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:51:33,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1425811594] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:33,089 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:33,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 53 [2022-11-18 18:51:33,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747063895] [2022-11-18 18:51:33,090 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:33,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:33,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:33,091 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-18 18:51:33,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:33,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922112418] [2022-11-18 18:51:33,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:33,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:33,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:33,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:33,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:33,102 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:33,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:33,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-18 18:51:33,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=205, Invalid=2651, Unknown=6, NotChecked=0, Total=2862 [2022-11-18 18:51:33,212 INFO L87 Difference]: Start difference. First operand 219 states and 295 transitions. cyclomatic complexity: 89 Second operand has 54 states, 53 states have (on average 2.188679245283019) internal successors, (116), 54 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:35,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:35,124 INFO L93 Difference]: Finished difference Result 388 states and 504 transitions. [2022-11-18 18:51:35,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388 states and 504 transitions. [2022-11-18 18:51:35,126 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 68 [2022-11-18 18:51:35,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388 states to 386 states and 502 transitions. [2022-11-18 18:51:35,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119 [2022-11-18 18:51:35,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119 [2022-11-18 18:51:35,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386 states and 502 transitions. [2022-11-18 18:51:35,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:35,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 386 states and 502 transitions. [2022-11-18 18:51:35,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386 states and 502 transitions. [2022-11-18 18:51:35,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386 to 249. [2022-11-18 18:51:35,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 249 states have (on average 1.3493975903614457) internal successors, (336), 248 states have internal predecessors, (336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:35,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 336 transitions. [2022-11-18 18:51:35,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 249 states and 336 transitions. [2022-11-18 18:51:35,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-18 18:51:35,138 INFO L428 stractBuchiCegarLoop]: Abstraction has 249 states and 336 transitions. [2022-11-18 18:51:35,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-18 18:51:35,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 336 transitions. [2022-11-18 18:51:35,140 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 40 [2022-11-18 18:51:35,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:35,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:35,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:35,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:35,141 INFO L748 eck$LassoCheckResult]: Stem: 12591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12602#L367 assume !(main_~length~0#1 < 1); 12593#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12594#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12603#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12637#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12634#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12631#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12627#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12623#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12622#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12621#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12620#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12733#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12728#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12780#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12768#L370-4 main_~j~0#1 := 0; 12779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12778#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12759#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12758#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12757#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12756#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12755#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12648#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12699#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12696#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12659#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12657#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12660#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12599#L378-2 [2022-11-18 18:51:35,142 INFO L750 eck$LassoCheckResult]: Loop: 12599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12646#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12599#L378-2 [2022-11-18 18:51:35,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:35,142 INFO L85 PathProgramCache]: Analyzing trace with hash 772882429, now seen corresponding path program 18 times [2022-11-18 18:51:35,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:35,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086313978] [2022-11-18 18:51:35,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:35,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:35,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:35,919 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:35,919 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:35,919 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086313978] [2022-11-18 18:51:35,919 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086313978] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:35,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [422091692] [2022-11-18 18:51:35,920 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:51:35,920 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:35,920 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:35,921 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:35,924 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-18 18:51:36,327 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2022-11-18 18:51:36,327 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:36,330 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-18 18:51:36,333 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:36,607 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:36,749 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:36,750 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:36,767 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:36,768 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:36,829 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:36,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:36,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:51:37,381 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:51:37,381 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-18 18:51:37,384 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:37,385 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:37,953 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 30 [2022-11-18 18:51:37,959 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 546 treesize of output 530 [2022-11-18 18:51:38,558 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 2 proven. 157 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:38,559 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [422091692] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:38,559 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:38,559 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 54 [2022-11-18 18:51:38,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2098380453] [2022-11-18 18:51:38,559 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:38,560 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:38,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:38,560 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-18 18:51:38,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:38,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663634880] [2022-11-18 18:51:38,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:38,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:38,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:38,563 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:38,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:38,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:38,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:38,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-18 18:51:38,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=2699, Unknown=0, NotChecked=0, Total=2970 [2022-11-18 18:51:38,617 INFO L87 Difference]: Start difference. First operand 249 states and 336 transitions. cyclomatic complexity: 103 Second operand has 55 states, 54 states have (on average 2.259259259259259) internal successors, (122), 55 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:41,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:41,464 INFO L93 Difference]: Finished difference Result 557 states and 711 transitions. [2022-11-18 18:51:41,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 711 transitions. [2022-11-18 18:51:41,468 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 96 [2022-11-18 18:51:41,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 552 states and 706 transitions. [2022-11-18 18:51:41,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 164 [2022-11-18 18:51:41,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 164 [2022-11-18 18:51:41,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 706 transitions. [2022-11-18 18:51:41,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:41,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 706 transitions. [2022-11-18 18:51:41,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 706 transitions. [2022-11-18 18:51:41,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 307. [2022-11-18 18:51:41,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307 states, 307 states have (on average 1.3680781758957654) internal successors, (420), 306 states have internal predecessors, (420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:41,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 420 transitions. [2022-11-18 18:51:41,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307 states and 420 transitions. [2022-11-18 18:51:41,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-18 18:51:41,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 307 states and 420 transitions. [2022-11-18 18:51:41,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-18 18:51:41,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 420 transitions. [2022-11-18 18:51:41,485 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:41,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:41,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:41,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:41,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:41,486 INFO L748 eck$LassoCheckResult]: Stem: 13837#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13848#L367 assume !(main_~length~0#1 < 1); 13839#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13840#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13849#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13886#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13885#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13883#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13882#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13880#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13879#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13878#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13877#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13875#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13874#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13871#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13867#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14038#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14036#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 14034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14035#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13926#L370-4 main_~j~0#1 := 0; 14069#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14068#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13844#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14050#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14041#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14040#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13895#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13944#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13902#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13899#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13900#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13901#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13843#L378-2 [2022-11-18 18:51:41,487 INFO L750 eck$LassoCheckResult]: Loop: 13843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14099#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13843#L378-2 [2022-11-18 18:51:41,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:41,487 INFO L85 PathProgramCache]: Analyzing trace with hash 2105768383, now seen corresponding path program 19 times [2022-11-18 18:51:41,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:41,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897243517] [2022-11-18 18:51:41,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:41,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:41,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:41,895 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:41,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:41,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897243517] [2022-11-18 18:51:41,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897243517] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:41,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [593874202] [2022-11-18 18:51:41,896 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:51:41,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:41,896 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:41,903 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:41,919 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-18 18:51:42,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:42,090 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-18 18:51:42,092 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:42,479 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:42,479 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:42,731 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:42,732 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [593874202] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:42,732 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:42,732 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21] total 32 [2022-11-18 18:51:42,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662177606] [2022-11-18 18:51:42,732 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:42,733 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:42,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:42,733 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-18 18:51:42,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:42,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449674463] [2022-11-18 18:51:42,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:42,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:42,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:42,737 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:42,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:42,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:42,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:42,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-18 18:51:42,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2022-11-18 18:51:42,800 INFO L87 Difference]: Start difference. First operand 307 states and 420 transitions. cyclomatic complexity: 132 Second operand has 32 states, 32 states have (on average 2.3125) internal successors, (74), 32 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:43,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:43,113 INFO L93 Difference]: Finished difference Result 327 states and 439 transitions. [2022-11-18 18:51:43,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 439 transitions. [2022-11-18 18:51:43,115 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:43,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 309 states and 416 transitions. [2022-11-18 18:51:43,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2022-11-18 18:51:43,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2022-11-18 18:51:43,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 416 transitions. [2022-11-18 18:51:43,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:43,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309 states and 416 transitions. [2022-11-18 18:51:43,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 416 transitions. [2022-11-18 18:51:43,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 307. [2022-11-18 18:51:43,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307 states, 307 states have (on average 1.3485342019543973) internal successors, (414), 306 states have internal predecessors, (414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:43,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 414 transitions. [2022-11-18 18:51:43,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307 states and 414 transitions. [2022-11-18 18:51:43,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 18:51:43,126 INFO L428 stractBuchiCegarLoop]: Abstraction has 307 states and 414 transitions. [2022-11-18 18:51:43,127 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-18 18:51:43,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 414 transitions. [2022-11-18 18:51:43,128 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:43,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:43,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:43,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:43,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:51:43,130 INFO L748 eck$LassoCheckResult]: Stem: 14814#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14825#L367 assume !(main_~length~0#1 < 1); 14816#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14817#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14818#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14826#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 14834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14827#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14828#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15026#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15021#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15016#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15035#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15004#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15020#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15017#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15009#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15010#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15006#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14904#L370-4 main_~j~0#1 := 0; 15047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15046#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14823#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14824#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15044#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15116#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15037#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14842#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14857#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15056#L378-2 [2022-11-18 18:51:43,130 INFO L750 eck$LassoCheckResult]: Loop: 15056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15070#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15072#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15055#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15056#L378-2 [2022-11-18 18:51:43,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:43,131 INFO L85 PathProgramCache]: Analyzing trace with hash 2138164678, now seen corresponding path program 20 times [2022-11-18 18:51:43,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:43,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935634513] [2022-11-18 18:51:43,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:43,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:43,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:43,968 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:43,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:43,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935634513] [2022-11-18 18:51:43,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935634513] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:43,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [441227227] [2022-11-18 18:51:43,969 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:51:43,969 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:43,969 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:43,974 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:43,997 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-18 18:51:44,219 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:51:44,219 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:44,221 INFO L263 TraceCheckSpWp]: Trace formula consists of 279 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-18 18:51:44,224 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:44,572 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:44,725 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:44,731 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:44,746 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:44,747 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:45,263 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:51:45,266 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:45,266 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:45,545 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:51:45,548 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:51:45,629 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:45,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [441227227] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:45,630 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:45,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 46 [2022-11-18 18:51:45,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205498494] [2022-11-18 18:51:45,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:45,630 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:45,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:45,631 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2022-11-18 18:51:45,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:45,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688066437] [2022-11-18 18:51:45,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:45,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:45,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:45,635 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:45,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:45,638 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:45,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:45,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-18 18:51:45,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1991, Unknown=0, NotChecked=0, Total=2162 [2022-11-18 18:51:45,752 INFO L87 Difference]: Start difference. First operand 307 states and 414 transitions. cyclomatic complexity: 126 Second operand has 47 states, 46 states have (on average 2.217391304347826) internal successors, (102), 47 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:46,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:46,993 INFO L93 Difference]: Finished difference Result 392 states and 514 transitions. [2022-11-18 18:51:46,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 514 transitions. [2022-11-18 18:51:46,995 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 78 [2022-11-18 18:51:46,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 390 states and 512 transitions. [2022-11-18 18:51:46,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2022-11-18 18:51:46,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2022-11-18 18:51:46,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390 states and 512 transitions. [2022-11-18 18:51:46,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:46,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 390 states and 512 transitions. [2022-11-18 18:51:46,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states and 512 transitions. [2022-11-18 18:51:47,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 260. [2022-11-18 18:51:47,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.3423076923076922) internal successors, (349), 259 states have internal predecessors, (349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:47,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 349 transitions. [2022-11-18 18:51:47,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 349 transitions. [2022-11-18 18:51:47,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:51:47,010 INFO L428 stractBuchiCegarLoop]: Abstraction has 260 states and 349 transitions. [2022-11-18 18:51:47,010 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-18 18:51:47,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 349 transitions. [2022-11-18 18:51:47,012 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:47,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:47,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:47,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:47,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:47,013 INFO L748 eck$LassoCheckResult]: Stem: 15877#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15888#L367 assume !(main_~length~0#1 < 1); 15879#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15880#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15889#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15928#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15927#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15926#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15925#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15924#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15923#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15922#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15921#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15920#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15917#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15915#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15913#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15912#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15910#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15909#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15906#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15905#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15901#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15900#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15882#L370-4 main_~j~0#1 := 0; 15883#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15886#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16040#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16038#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16036#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16034#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16032#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15944#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16000#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15973#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15953#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15954#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15955#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15885#L378-2 [2022-11-18 18:51:47,013 INFO L750 eck$LassoCheckResult]: Loop: 15885#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16073#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15885#L378-2 [2022-11-18 18:51:47,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:47,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1860197447, now seen corresponding path program 21 times [2022-11-18 18:51:47,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:47,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055287089] [2022-11-18 18:51:47,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:47,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:47,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:47,767 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:47,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:47,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055287089] [2022-11-18 18:51:47,768 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055287089] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:47,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [992989114] [2022-11-18 18:51:47,768 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:51:47,768 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:47,768 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:47,775 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:47,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-18 18:51:48,433 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-18 18:51:48,433 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:48,437 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 18:51:48,439 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:48,708 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:49,681 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:51:49,681 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:51:49,686 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:49,686 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:50,973 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:51:50,978 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:51:51,285 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:51,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [992989114] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:51,286 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:51,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2022-11-18 18:51:51,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266121105] [2022-11-18 18:51:51,286 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:51,287 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:51,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:51,287 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-18 18:51:51,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:51,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895816261] [2022-11-18 18:51:51,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:51,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:51,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:51,291 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:51,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:51,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:51,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:51,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 18:51:51,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3022, Unknown=0, NotChecked=0, Total=3422 [2022-11-18 18:51:51,352 INFO L87 Difference]: Start difference. First operand 260 states and 349 transitions. cyclomatic complexity: 104 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:53,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:53,667 INFO L93 Difference]: Finished difference Result 366 states and 472 transitions. [2022-11-18 18:51:53,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 472 transitions. [2022-11-18 18:51:53,670 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:53,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 325 states and 428 transitions. [2022-11-18 18:51:53,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79 [2022-11-18 18:51:53,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79 [2022-11-18 18:51:53,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 325 states and 428 transitions. [2022-11-18 18:51:53,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:53,673 INFO L218 hiAutomatonCegarLoop]: Abstraction has 325 states and 428 transitions. [2022-11-18 18:51:53,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states and 428 transitions. [2022-11-18 18:51:53,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 297. [2022-11-18 18:51:53,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 297 states, 297 states have (on average 1.3367003367003367) internal successors, (397), 296 states have internal predecessors, (397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:53,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 397 transitions. [2022-11-18 18:51:53,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 297 states and 397 transitions. [2022-11-18 18:51:53,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2022-11-18 18:51:53,682 INFO L428 stractBuchiCegarLoop]: Abstraction has 297 states and 397 transitions. [2022-11-18 18:51:53,682 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-18 18:51:53,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 297 states and 397 transitions. [2022-11-18 18:51:53,683 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-18 18:51:53,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:53,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:53,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:53,684 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:51:53,685 INFO L748 eck$LassoCheckResult]: Stem: 16964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16975#L367 assume !(main_~length~0#1 < 1); 16966#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16967#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16976#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17025#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17032#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17031#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17030#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17028#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17027#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17026#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17013#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17010#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17007#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17044#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17000#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16997#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16996#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16995#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16993#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16989#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 16986#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16987#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17128#L370-4 main_~j~0#1 := 0; 17234#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16980#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17232#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17231#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17228#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17226#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17224#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17223#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17221#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17219#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17098#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17080#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17090#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17084#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17083#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17055#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16970#L378-2 [2022-11-18 18:51:53,685 INFO L750 eck$LassoCheckResult]: Loop: 16970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16979#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16970#L378-2 [2022-11-18 18:51:53,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:53,686 INFO L85 PathProgramCache]: Analyzing trace with hash -68075255, now seen corresponding path program 22 times [2022-11-18 18:51:53,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:53,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89957625] [2022-11-18 18:51:53,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:53,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:53,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:54,466 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:54,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:54,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89957625] [2022-11-18 18:51:54,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89957625] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:54,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2072824285] [2022-11-18 18:51:54,467 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:51:54,467 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:54,467 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:54,475 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:54,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-18 18:51:54,682 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:51:54,682 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:54,685 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-18 18:51:54,687 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:54,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:55,314 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:51:55,317 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:55,317 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:55,510 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:51:55,515 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:51:55,623 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:55,623 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2072824285] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:55,623 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:55,623 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22] total 34 [2022-11-18 18:51:55,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951222171] [2022-11-18 18:51:55,623 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:55,624 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:55,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:55,624 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-18 18:51:55,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:55,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100313887] [2022-11-18 18:51:55,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:55,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:55,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:55,627 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:55,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:55,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:55,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:55,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 18:51:55,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=1088, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 18:51:55,689 INFO L87 Difference]: Start difference. First operand 297 states and 397 transitions. cyclomatic complexity: 115 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:56,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:51:56,534 INFO L93 Difference]: Finished difference Result 450 states and 589 transitions. [2022-11-18 18:51:56,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450 states and 589 transitions. [2022-11-18 18:51:56,537 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 92 [2022-11-18 18:51:56,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450 states to 449 states and 588 transitions. [2022-11-18 18:51:56,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139 [2022-11-18 18:51:56,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139 [2022-11-18 18:51:56,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 588 transitions. [2022-11-18 18:51:56,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:51:56,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 588 transitions. [2022-11-18 18:51:56,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 588 transitions. [2022-11-18 18:51:56,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 384. [2022-11-18 18:51:56,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.3307291666666667) internal successors, (511), 383 states have internal predecessors, (511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:51:56,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 511 transitions. [2022-11-18 18:51:56,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 511 transitions. [2022-11-18 18:51:56,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:51:56,551 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 511 transitions. [2022-11-18 18:51:56,552 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-18 18:51:56,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 511 transitions. [2022-11-18 18:51:56,553 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 78 [2022-11-18 18:51:56,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:51:56,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:51:56,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:51:56,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:51:56,555 INFO L748 eck$LassoCheckResult]: Stem: 18057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18068#L367 assume !(main_~length~0#1 < 1); 18059#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18060#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18069#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18124#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18122#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18118#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18116#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18114#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18112#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18108#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18103#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18104#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18099#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18100#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18141#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18295#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18294#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18292#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18282#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18280#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18327#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18326#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18324#L370-4 main_~j~0#1 := 0; 18325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18417#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18416#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18415#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18413#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18411#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18409#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18408#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18406#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18402#L378-2 [2022-11-18 18:51:56,555 INFO L750 eck$LassoCheckResult]: Loop: 18402#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18404#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18407#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18402#L378-2 [2022-11-18 18:51:56,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:56,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1226720964, now seen corresponding path program 23 times [2022-11-18 18:51:56,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:56,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937336034] [2022-11-18 18:51:56,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:56,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:51:57,626 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 18 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:57,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:51:57,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937336034] [2022-11-18 18:51:57,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937336034] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:51:57,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1171810265] [2022-11-18 18:51:57,627 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:51:57,627 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:51:57,627 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:51:57,635 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:51:57,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-18 18:51:57,983 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-18 18:51:57,983 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:51:57,987 INFO L263 TraceCheckSpWp]: Trace formula consists of 285 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-18 18:51:57,991 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:51:58,262 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:51:58,394 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:51:58,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:51:58,456 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:58,457 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:58,522 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:58,523 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:58,593 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:58,596 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:58,607 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:58,608 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:58,667 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:51:58,668 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:51:59,125 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:51:59,127 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:51:59,127 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:51:59,130 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 12 proven. 194 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:51:59,130 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:51:59,805 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:51:59,808 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:51:59,864 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 6 proven. 182 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2022-11-18 18:51:59,864 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1171810265] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:51:59,864 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:51:59,865 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24, 20] total 48 [2022-11-18 18:51:59,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036219741] [2022-11-18 18:51:59,865 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:51:59,865 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:51:59,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:51:59,866 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 4 times [2022-11-18 18:51:59,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:51:59,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026911588] [2022-11-18 18:51:59,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:51:59,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:51:59,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:59,871 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:51:59,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:51:59,875 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:51:59,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:51:59,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 18:51:59,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=2115, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 18:51:59,970 INFO L87 Difference]: Start difference. First operand 384 states and 511 transitions. cyclomatic complexity: 148 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:01,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:01,429 INFO L93 Difference]: Finished difference Result 375 states and 477 transitions. [2022-11-18 18:52:01,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 477 transitions. [2022-11-18 18:52:01,431 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 32 [2022-11-18 18:52:01,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 370 states and 472 transitions. [2022-11-18 18:52:01,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2022-11-18 18:52:01,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2022-11-18 18:52:01,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370 states and 472 transitions. [2022-11-18 18:52:01,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:01,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370 states and 472 transitions. [2022-11-18 18:52:01,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states and 472 transitions. [2022-11-18 18:52:01,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 210. [2022-11-18 18:52:01,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 210 states have (on average 1.319047619047619) internal successors, (277), 209 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:01,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 277 transitions. [2022-11-18 18:52:01,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 210 states and 277 transitions. [2022-11-18 18:52:01,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-18 18:52:01,441 INFO L428 stractBuchiCegarLoop]: Abstraction has 210 states and 277 transitions. [2022-11-18 18:52:01,441 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-18 18:52:01,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 210 states and 277 transitions. [2022-11-18 18:52:01,442 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-18 18:52:01,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:01,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:01,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:01,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:01,444 INFO L748 eck$LassoCheckResult]: Stem: 19204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19215#L367 assume !(main_~length~0#1 < 1); 19206#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19207#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19216#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19319#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19318#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19317#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19316#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19313#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19312#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19309#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19307#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19352#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19351#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19349#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19350#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19345#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19346#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19340#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19223#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19213#L370-4 main_~j~0#1 := 0; 19214#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19211#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19212#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19222#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19327#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19325#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19324#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19323#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19229#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19231#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19232#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19235#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19210#L378-2 [2022-11-18 18:52:01,444 INFO L750 eck$LassoCheckResult]: Loop: 19210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19227#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19210#L378-2 [2022-11-18 18:52:01,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:01,444 INFO L85 PathProgramCache]: Analyzing trace with hash -995807346, now seen corresponding path program 24 times [2022-11-18 18:52:01,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:01,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263676659] [2022-11-18 18:52:01,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:01,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:01,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:01,852 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:01,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:01,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263676659] [2022-11-18 18:52:01,852 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263676659] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:01,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [9555396] [2022-11-18 18:52:01,852 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:52:01,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:01,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:01,854 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:01,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-18 18:52:02,528 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2022-11-18 18:52:02,529 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:02,531 INFO L263 TraceCheckSpWp]: Trace formula consists of 309 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 18:52:02,532 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:02,893 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:02,893 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:03,169 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:03,170 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [9555396] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:03,170 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:03,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-18 18:52:03,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263916290] [2022-11-18 18:52:03,170 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:03,170 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:03,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:03,171 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-18 18:52:03,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:03,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074366283] [2022-11-18 18:52:03,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:03,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:03,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:03,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:03,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:03,178 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:03,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:03,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 18:52:03,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 18:52:03,226 INFO L87 Difference]: Start difference. First operand 210 states and 277 transitions. cyclomatic complexity: 78 Second operand has 35 states, 35 states have (on average 2.3142857142857145) internal successors, (81), 35 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:03,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:03,568 INFO L93 Difference]: Finished difference Result 237 states and 305 transitions. [2022-11-18 18:52:03,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 237 states and 305 transitions. [2022-11-18 18:52:03,570 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-18 18:52:03,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 237 states to 217 states and 283 transitions. [2022-11-18 18:52:03,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2022-11-18 18:52:03,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2022-11-18 18:52:03,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 283 transitions. [2022-11-18 18:52:03,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:03,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 217 states and 283 transitions. [2022-11-18 18:52:03,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 283 transitions. [2022-11-18 18:52:03,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 177. [2022-11-18 18:52:03,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 177 states have (on average 1.305084745762712) internal successors, (231), 176 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:03,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 231 transitions. [2022-11-18 18:52:03,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177 states and 231 transitions. [2022-11-18 18:52:03,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 18:52:03,577 INFO L428 stractBuchiCegarLoop]: Abstraction has 177 states and 231 transitions. [2022-11-18 18:52:03,577 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-18 18:52:03,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 231 transitions. [2022-11-18 18:52:03,578 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-18 18:52:03,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:03,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:03,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 7, 7, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:03,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:52:03,579 INFO L748 eck$LassoCheckResult]: Stem: 20029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20040#L367 assume !(main_~length~0#1 < 1); 20031#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20032#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20041#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20087#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20086#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20085#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20084#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20083#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20082#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20081#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20080#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20079#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20078#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20077#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20075#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20072#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20071#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20070#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20069#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20167#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20164#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20161#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20159#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20151#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20146#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20155#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20145#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20140#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20139#L370-4 main_~j~0#1 := 0; 20044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20036#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20173#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20172#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20171#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20154#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20150#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20098#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20099#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20107#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20181#L378-2 [2022-11-18 18:52:03,579 INFO L750 eck$LassoCheckResult]: Loop: 20181#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20184#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20182#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20180#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20181#L378-2 [2022-11-18 18:52:03,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:03,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1946851207, now seen corresponding path program 25 times [2022-11-18 18:52:03,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:03,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100344336] [2022-11-18 18:52:03,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:03,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:03,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:04,477 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 9 proven. 209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:04,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:04,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100344336] [2022-11-18 18:52:04,478 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100344336] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:04,478 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1417030114] [2022-11-18 18:52:04,478 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:52:04,478 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:04,478 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:04,481 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:04,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-18 18:52:04,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:04,665 INFO L263 TraceCheckSpWp]: Trace formula consists of 296 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-18 18:52:04,669 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:04,973 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:52:05,120 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:52:05,141 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:52:05,210 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:52:05,210 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:52:05,281 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:52:05,281 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:52:05,290 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:52:05,291 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:52:05,355 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:52:05,808 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:52:05,811 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 0 proven. 218 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:05,811 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:06,772 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 45 [2022-11-18 18:52:06,778 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1097 treesize of output 1081 [2022-11-18 18:52:08,126 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 0 proven. 218 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:08,126 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1417030114] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:08,126 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:08,127 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 26] total 54 [2022-11-18 18:52:08,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912208347] [2022-11-18 18:52:08,127 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:08,127 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:08,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:08,127 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 5 times [2022-11-18 18:52:08,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:08,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978224405] [2022-11-18 18:52:08,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:08,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:08,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:08,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:08,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:08,137 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:08,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:08,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-18 18:52:08,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=2675, Unknown=0, NotChecked=0, Total=2970 [2022-11-18 18:52:08,245 INFO L87 Difference]: Start difference. First operand 177 states and 231 transitions. cyclomatic complexity: 65 Second operand has 55 states, 54 states have (on average 2.2037037037037037) internal successors, (119), 55 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:10,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:10,264 INFO L93 Difference]: Finished difference Result 330 states and 397 transitions. [2022-11-18 18:52:10,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 397 transitions. [2022-11-18 18:52:10,265 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8 [2022-11-18 18:52:10,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 326 states and 393 transitions. [2022-11-18 18:52:10,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-18 18:52:10,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-18 18:52:10,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 393 transitions. [2022-11-18 18:52:10,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:10,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 393 transitions. [2022-11-18 18:52:10,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 393 transitions. [2022-11-18 18:52:10,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 82. [2022-11-18 18:52:10,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:10,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-18 18:52:10,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:52:10,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-11-18 18:52:10,272 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 18:52:10,272 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-18 18:52:10,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-18 18:52:10,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:10,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:10,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:10,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:10,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:10,274 INFO L748 eck$LassoCheckResult]: Stem: 20981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20992#L367 assume !(main_~length~0#1 < 1); 20983#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20984#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20985#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20993#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21055#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21054#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21053#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21052#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21051#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21050#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21049#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21048#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21047#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21043#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21042#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21041#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21039#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21036#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21035#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21032#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21029#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20999#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20994#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20995#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21008#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20986#L370-4 main_~j~0#1 := 0; 20987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20990#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21016#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21014#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21012#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21011#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21010#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21006#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21004#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21002#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20988#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20989#L378-2 [2022-11-18 18:52:10,274 INFO L750 eck$LassoCheckResult]: Loop: 20989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21000#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20989#L378-2 [2022-11-18 18:52:10,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:10,274 INFO L85 PathProgramCache]: Analyzing trace with hash 307442051, now seen corresponding path program 26 times [2022-11-18 18:52:10,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:10,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197866084] [2022-11-18 18:52:10,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:10,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:10,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:11,153 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:11,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:11,153 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197866084] [2022-11-18 18:52:11,153 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197866084] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:11,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1483614249] [2022-11-18 18:52:11,154 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:52:11,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:11,154 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:11,158 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:11,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-18 18:52:11,384 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:52:11,384 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:11,387 INFO L263 TraceCheckSpWp]: Trace formula consists of 312 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-18 18:52:11,389 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:11,803 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:52:11,963 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:52:11,963 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:52:11,972 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:52:11,973 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:52:12,581 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:52:12,589 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:12,590 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:12,902 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:52:12,913 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:52:13,019 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:13,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1483614249] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:13,020 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:13,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 50 [2022-11-18 18:52:13,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890951536] [2022-11-18 18:52:13,020 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:13,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:13,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:13,021 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-18 18:52:13,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:13,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465049708] [2022-11-18 18:52:13,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:13,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:13,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:13,025 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:13,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:13,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:13,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:13,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-11-18 18:52:13,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=2365, Unknown=0, NotChecked=0, Total=2550 [2022-11-18 18:52:13,096 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 51 states, 50 states have (on average 2.24) internal successors, (112), 51 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:14,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:14,308 INFO L93 Difference]: Finished difference Result 100 states and 121 transitions. [2022-11-18 18:52:14,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 121 transitions. [2022-11-18 18:52:14,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:14,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 99 states and 120 transitions. [2022-11-18 18:52:14,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:52:14,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:52:14,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 120 transitions. [2022-11-18 18:52:14,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:14,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 120 transitions. [2022-11-18 18:52:14,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 120 transitions. [2022-11-18 18:52:14,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 74. [2022-11-18 18:52:14,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2432432432432432) internal successors, (92), 73 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:14,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 92 transitions. [2022-11-18 18:52:14,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-18 18:52:14,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:52:14,318 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-18 18:52:14,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-18 18:52:14,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 92 transitions. [2022-11-18 18:52:14,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:14,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:14,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:14,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:14,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:14,320 INFO L748 eck$LassoCheckResult]: Stem: 21563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21574#L367 assume !(main_~length~0#1 < 1); 21565#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21566#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21575#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21623#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21621#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21618#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21616#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21615#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21611#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21608#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21604#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21603#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21600#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21596#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21593#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21590#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21585#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21572#L370-4 main_~j~0#1 := 0; 21573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21578#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21570#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21636#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21635#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21634#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21633#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21632#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21631#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21624#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21594#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21589#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21583#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21568#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21569#L378-2 [2022-11-18 18:52:14,321 INFO L750 eck$LassoCheckResult]: Loop: 21569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21584#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21569#L378-2 [2022-11-18 18:52:14,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:14,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1336796612, now seen corresponding path program 27 times [2022-11-18 18:52:14,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:14,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500882453] [2022-11-18 18:52:14,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:14,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:14,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:15,172 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:15,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:15,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500882453] [2022-11-18 18:52:15,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500882453] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:15,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1247362425] [2022-11-18 18:52:15,173 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:52:15,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:15,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:15,174 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:15,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-18 18:52:15,774 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 18:52:15,774 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:15,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 18:52:15,779 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:16,101 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:52:17,429 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:52:17,429 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:52:17,436 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:17,436 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:19,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:52:19,261 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:52:19,582 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:19,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1247362425] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:19,582 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:19,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-18 18:52:19,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972819590] [2022-11-18 18:52:19,583 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:19,584 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:19,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:19,584 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-18 18:52:19,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:19,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523948044] [2022-11-18 18:52:19,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:19,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:19,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:19,588 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:19,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:19,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:19,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:19,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-18 18:52:19,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=3567, Unknown=1, NotChecked=0, Total=4032 [2022-11-18 18:52:19,647 INFO L87 Difference]: Start difference. First operand 74 states and 92 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:21,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:21,951 INFO L93 Difference]: Finished difference Result 121 states and 143 transitions. [2022-11-18 18:52:21,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 143 transitions. [2022-11-18 18:52:21,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:21,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 98 states and 118 transitions. [2022-11-18 18:52:21,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 18:52:21,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 18:52:21,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 118 transitions. [2022-11-18 18:52:21,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:21,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98 states and 118 transitions. [2022-11-18 18:52:21,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 118 transitions. [2022-11-18 18:52:21,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 80. [2022-11-18 18:52:21,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.25) internal successors, (100), 79 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:21,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 100 transitions. [2022-11-18 18:52:21,955 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-18 18:52:21,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-11-18 18:52:21,958 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-18 18:52:21,958 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-18 18:52:21,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 100 transitions. [2022-11-18 18:52:21,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:21,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:21,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:21,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:21,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:21,959 INFO L748 eck$LassoCheckResult]: Stem: 22248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22259#L367 assume !(main_~length~0#1 < 1); 22250#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22251#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22252#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22260#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22263#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22261#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22262#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22325#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22322#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22321#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22320#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22317#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22312#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22308#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22304#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22303#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22299#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22297#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22273#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22271#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22267#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22266#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22253#L370-4 main_~j~0#1 := 0; 22254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22264#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22257#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22295#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22293#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22291#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22289#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22287#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22286#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22285#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22283#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22282#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22255#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22256#L378-2 [2022-11-18 18:52:21,959 INFO L750 eck$LassoCheckResult]: Loop: 22256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22280#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22256#L378-2 [2022-11-18 18:52:21,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:21,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1034942650, now seen corresponding path program 28 times [2022-11-18 18:52:21,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:21,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947918835] [2022-11-18 18:52:21,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:21,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:21,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:22,714 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:22,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:22,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947918835] [2022-11-18 18:52:22,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947918835] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:22,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1208243800] [2022-11-18 18:52:22,715 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:52:22,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:22,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:22,718 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:22,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-18 18:52:22,905 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:52:22,905 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:22,907 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-18 18:52:22,908 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:22,997 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:52:23,505 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-18 18:52:23,508 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:23,508 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:23,680 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:52:23,683 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:52:23,778 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:23,779 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1208243800] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:23,779 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:23,779 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24] total 37 [2022-11-18 18:52:23,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907116268] [2022-11-18 18:52:23,779 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:23,779 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:23,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:23,780 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-18 18:52:23,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:23,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030647] [2022-11-18 18:52:23,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:23,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:23,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:23,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:23,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:23,786 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:23,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:23,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:52:23,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1295, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:52:23,852 INFO L87 Difference]: Start difference. First operand 80 states and 100 transitions. cyclomatic complexity: 24 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:24,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:24,690 INFO L93 Difference]: Finished difference Result 117 states and 143 transitions. [2022-11-18 18:52:24,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 143 transitions. [2022-11-18 18:52:24,691 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:52:24,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 116 states and 142 transitions. [2022-11-18 18:52:24,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 18:52:24,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 18:52:24,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 142 transitions. [2022-11-18 18:52:24,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:24,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 142 transitions. [2022-11-18 18:52:24,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 142 transitions. [2022-11-18 18:52:24,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 93. [2022-11-18 18:52:24,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.2580645161290323) internal successors, (117), 92 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:24,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 117 transitions. [2022-11-18 18:52:24,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 93 states and 117 transitions. [2022-11-18 18:52:24,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 18:52:24,703 INFO L428 stractBuchiCegarLoop]: Abstraction has 93 states and 117 transitions. [2022-11-18 18:52:24,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-18 18:52:24,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 117 transitions. [2022-11-18 18:52:24,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:24,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:24,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:24,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:24,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:24,705 INFO L748 eck$LassoCheckResult]: Stem: 22824#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22835#L367 assume !(main_~length~0#1 < 1); 22826#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22827#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22836#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22882#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22880#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22877#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22874#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22870#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22869#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22868#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22867#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22866#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22865#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22863#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22859#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22855#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22915#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22846#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22843#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22833#L370-4 main_~j~0#1 := 0; 22834#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22909#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22840#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22831#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22832#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22908#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22907#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22906#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22905#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22904#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22903#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22902#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22900#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22899#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22898#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22897#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22896#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22895#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22893#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22892#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22829#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22830#L378-2 [2022-11-18 18:52:24,706 INFO L750 eck$LassoCheckResult]: Loop: 22830#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22894#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22830#L378-2 [2022-11-18 18:52:24,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:24,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1852529291, now seen corresponding path program 29 times [2022-11-18 18:52:24,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:24,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112356822] [2022-11-18 18:52:24,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:24,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:24,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:25,258 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:25,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:25,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112356822] [2022-11-18 18:52:25,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112356822] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:25,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1502784625] [2022-11-18 18:52:25,259 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:52:25,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:25,259 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:25,267 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:25,285 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-18 18:52:25,644 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2022-11-18 18:52:25,644 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:25,648 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 18:52:25,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:26,064 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:26,064 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:26,398 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 100 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:26,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1502784625] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:26,399 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:26,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-18 18:52:26,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818807385] [2022-11-18 18:52:26,399 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:26,400 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:26,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:26,400 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-18 18:52:26,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:26,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183506625] [2022-11-18 18:52:26,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:26,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:26,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:26,404 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:26,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:26,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:26,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:26,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 18:52:26,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:52:26,462 INFO L87 Difference]: Start difference. First operand 93 states and 117 transitions. cyclomatic complexity: 29 Second operand has 38 states, 38 states have (on average 2.289473684210526) internal successors, (87), 38 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:26,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:52:26,831 INFO L93 Difference]: Finished difference Result 121 states and 146 transitions. [2022-11-18 18:52:26,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 146 transitions. [2022-11-18 18:52:26,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:26,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 99 states and 124 transitions. [2022-11-18 18:52:26,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:52:26,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:52:26,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 124 transitions. [2022-11-18 18:52:26,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:52:26,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 124 transitions. [2022-11-18 18:52:26,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 124 transitions. [2022-11-18 18:52:26,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 90. [2022-11-18 18:52:26,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.2555555555555555) internal successors, (113), 89 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:52:26,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 113 transitions. [2022-11-18 18:52:26,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-18 18:52:26,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:52:26,843 INFO L428 stractBuchiCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-18 18:52:26,843 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-18 18:52:26,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 113 transitions. [2022-11-18 18:52:26,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:52:26,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:52:26,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:52:26,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:52:26,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:52:26,844 INFO L748 eck$LassoCheckResult]: Stem: 23451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 23452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 23462#L367 assume !(main_~length~0#1 < 1); 23453#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 23454#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 23455#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23463#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23532#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23530#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23529#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23528#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23527#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23524#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23522#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23521#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23520#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23518#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23517#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23516#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23514#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23510#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23509#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23508#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23506#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23505#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23502#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23503#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23493#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23469#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 23456#L370-4 main_~j~0#1 := 0; 23457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23467#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23488#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23487#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23486#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23485#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23484#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23483#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23482#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23481#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23480#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23479#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23478#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23477#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23476#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23475#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23474#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23472#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23458#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23459#L378-2 [2022-11-18 18:52:26,845 INFO L750 eck$LassoCheckResult]: Loop: 23459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23473#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23459#L378-2 [2022-11-18 18:52:26,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:26,845 INFO L85 PathProgramCache]: Analyzing trace with hash -838679536, now seen corresponding path program 30 times [2022-11-18 18:52:26,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:26,845 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074574912] [2022-11-18 18:52:26,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:26,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:26,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:52:27,764 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:27,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:52:27,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074574912] [2022-11-18 18:52:27,764 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074574912] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:52:27,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [254760049] [2022-11-18 18:52:27,764 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:52:27,764 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:52:27,765 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:52:27,766 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:52:27,768 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-18 18:52:29,071 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-18 18:52:29,071 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:52:29,075 INFO L263 TraceCheckSpWp]: Trace formula consists of 345 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-18 18:52:29,077 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:52:29,444 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:52:30,178 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:52:30,178 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-18 18:52:30,290 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 18:52:30,291 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-18 18:52:34,261 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 18:52:34,261 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-18 18:52:34,296 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 81 proven. 185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:52:34,296 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:52:52,708 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:52:52,712 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:52:53,076 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 72 proven. 192 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:52:53,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [254760049] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:52:53,077 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:52:53,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 29, 26] total 67 [2022-11-18 18:52:53,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072459457] [2022-11-18 18:52:53,077 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:52:53,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:52:53,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:52:53,078 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-18 18:52:53,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:52:53,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277649718] [2022-11-18 18:52:53,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:52:53,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:52:53,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:53,082 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:52:53,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:52:53,085 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:52:53,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:52:53,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2022-11-18 18:52:53,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=511, Invalid=4044, Unknown=1, NotChecked=0, Total=4556 [2022-11-18 18:52:53,144 INFO L87 Difference]: Start difference. First operand 90 states and 113 transitions. cyclomatic complexity: 28 Second operand has 68 states, 67 states have (on average 2.1044776119402986) internal successors, (141), 68 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:11,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:11,355 INFO L93 Difference]: Finished difference Result 174 states and 204 transitions. [2022-11-18 18:53:11,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 204 transitions. [2022-11-18 18:53:11,356 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:53:11,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 127 states and 155 transitions. [2022-11-18 18:53:11,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 18:53:11,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 18:53:11,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 155 transitions. [2022-11-18 18:53:11,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:11,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 155 transitions. [2022-11-18 18:53:11,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 155 transitions. [2022-11-18 18:53:11,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 73. [2022-11-18 18:53:11,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2465753424657535) internal successors, (91), 72 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:11,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 91 transitions. [2022-11-18 18:53:11,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 91 transitions. [2022-11-18 18:53:11,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-11-18 18:53:11,362 INFO L428 stractBuchiCegarLoop]: Abstraction has 73 states and 91 transitions. [2022-11-18 18:53:11,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-18 18:53:11,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 91 transitions. [2022-11-18 18:53:11,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:11,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:11,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:11,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:11,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:11,364 INFO L748 eck$LassoCheckResult]: Stem: 24273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24284#L367 assume !(main_~length~0#1 < 1); 24275#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24276#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24285#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24287#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24343#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24340#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24334#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24331#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24328#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24325#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24322#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24319#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24294#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24292#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24278#L370-4 main_~j~0#1 := 0; 24279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24282#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24289#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24312#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24311#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24309#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24307#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24306#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24305#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24304#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24303#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24302#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24300#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24299#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24296#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24280#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24281#L378-2 [2022-11-18 18:53:11,364 INFO L750 eck$LassoCheckResult]: Loop: 24281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24297#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24281#L378-2 [2022-11-18 18:53:11,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:11,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485871, now seen corresponding path program 11 times [2022-11-18 18:53:11,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:11,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232899370] [2022-11-18 18:53:11,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:11,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:11,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:12,266 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:12,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:12,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232899370] [2022-11-18 18:53:12,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232899370] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:12,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [716183408] [2022-11-18 18:53:12,266 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:53:12,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:12,267 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:12,298 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:12,323 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-18 18:53:12,780 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-18 18:53:12,781 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:12,785 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-18 18:53:12,787 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:13,352 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 18:53:14,369 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:53:14,372 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:53:14,372 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:53:14,376 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:14,376 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:14,700 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-18 18:53:14,703 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 18:53:14,817 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:14,818 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [716183408] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:14,818 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:14,818 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 27] total 56 [2022-11-18 18:53:14,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433875944] [2022-11-18 18:53:14,818 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:14,818 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:14,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:14,819 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-18 18:53:14,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:14,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092663692] [2022-11-18 18:53:14,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:14,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:14,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:14,822 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:14,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:14,824 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:14,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:14,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2022-11-18 18:53:14,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=2980, Unknown=0, NotChecked=0, Total=3192 [2022-11-18 18:53:14,879 INFO L87 Difference]: Start difference. First operand 73 states and 91 transitions. cyclomatic complexity: 23 Second operand has 57 states, 56 states have (on average 2.25) internal successors, (126), 57 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:16,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:16,604 INFO L93 Difference]: Finished difference Result 149 states and 183 transitions. [2022-11-18 18:53:16,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 183 transitions. [2022-11-18 18:53:16,605 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 25 [2022-11-18 18:53:16,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 148 states and 182 transitions. [2022-11-18 18:53:16,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2022-11-18 18:53:16,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2022-11-18 18:53:16,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 182 transitions. [2022-11-18 18:53:16,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:16,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148 states and 182 transitions. [2022-11-18 18:53:16,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 182 transitions. [2022-11-18 18:53:16,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 124. [2022-11-18 18:53:16,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.2580645161290323) internal successors, (156), 123 states have internal predecessors, (156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:16,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 156 transitions. [2022-11-18 18:53:16,610 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 156 transitions. [2022-11-18 18:53:16,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-18 18:53:16,611 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 156 transitions. [2022-11-18 18:53:16,611 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-18 18:53:16,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 156 transitions. [2022-11-18 18:53:16,612 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-18 18:53:16,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:16,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:16,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:16,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 18:53:16,614 INFO L748 eck$LassoCheckResult]: Stem: 24929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24940#L367 assume !(main_~length~0#1 < 1); 24931#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24932#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24941#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24942#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24943#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24979#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24978#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24977#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24975#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24974#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24973#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24972#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24971#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24970#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24969#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24966#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24964#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24963#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24961#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24960#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24959#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24958#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24956#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25014#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25012#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25011#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25010#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25009#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25006#L370-4 main_~j~0#1 := 0; 25005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25004#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25002#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25000#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24999#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24998#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24996#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24994#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24990#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24988#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24982#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25034#L378-2 [2022-11-18 18:53:16,614 INFO L750 eck$LassoCheckResult]: Loop: 25034#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25036#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25035#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25033#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25034#L378-2 [2022-11-18 18:53:16,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:16,614 INFO L85 PathProgramCache]: Analyzing trace with hash -696609148, now seen corresponding path program 31 times [2022-11-18 18:53:16,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:16,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613701956] [2022-11-18 18:53:16,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:16,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:16,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:17,714 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:17,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:17,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1613701956] [2022-11-18 18:53:17,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1613701956] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:17,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1618306687] [2022-11-18 18:53:17,714 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:53:17,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:17,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:17,718 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:17,720 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-18 18:53:17,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:17,945 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-18 18:53:17,948 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:18,600 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:53:18,778 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:53:18,789 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:53:18,858 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 18:53:19,585 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:53:19,588 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:19,588 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:20,198 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-18 18:53:20,203 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 129 [2022-11-18 18:53:20,347 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:20,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1618306687] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:20,348 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:20,348 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 28] total 58 [2022-11-18 18:53:20,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701972993] [2022-11-18 18:53:20,349 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:20,349 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:20,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:20,349 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 6 times [2022-11-18 18:53:20,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:20,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106742208] [2022-11-18 18:53:20,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:20,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:20,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:20,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:20,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:20,364 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:20,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:20,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 18:53:20,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=3190, Unknown=0, NotChecked=0, Total=3422 [2022-11-18 18:53:20,468 INFO L87 Difference]: Start difference. First operand 124 states and 156 transitions. cyclomatic complexity: 39 Second operand has 59 states, 58 states have (on average 2.2586206896551726) internal successors, (131), 59 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:22,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:22,959 INFO L93 Difference]: Finished difference Result 156 states and 181 transitions. [2022-11-18 18:53:22,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156 states and 181 transitions. [2022-11-18 18:53:22,959 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 18:53:22,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156 states to 154 states and 179 transitions. [2022-11-18 18:53:22,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-18 18:53:22,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-18 18:53:22,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154 states and 179 transitions. [2022-11-18 18:53:22,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:22,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154 states and 179 transitions. [2022-11-18 18:53:22,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states and 179 transitions. [2022-11-18 18:53:22,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 78. [2022-11-18 18:53:22,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2435897435897436) internal successors, (97), 77 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:22,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 97 transitions. [2022-11-18 18:53:22,965 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 97 transitions. [2022-11-18 18:53:22,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-11-18 18:53:22,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 97 transitions. [2022-11-18 18:53:22,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-18 18:53:22,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 97 transitions. [2022-11-18 18:53:22,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:22,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:22,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:22,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:22,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:22,969 INFO L748 eck$LassoCheckResult]: Stem: 25695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 25696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 25706#L367 assume !(main_~length~0#1 < 1); 25697#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 25698#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 25699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25707#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25712#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25709#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25770#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25769#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25768#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25767#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25766#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25765#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25764#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25763#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25762#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25761#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25760#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25759#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25758#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25756#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25755#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25754#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25753#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25752#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25751#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25750#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25749#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25748#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25747#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25737#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25722#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25719#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25704#L370-4 main_~j~0#1 := 0; 25705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25702#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25703#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25711#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25734#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25732#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25730#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25728#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25726#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25724#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25723#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25721#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25717#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25714#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25713#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25700#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25701#L378-2 [2022-11-18 18:53:22,970 INFO L750 eck$LassoCheckResult]: Loop: 25701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25715#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25701#L378-2 [2022-11-18 18:53:22,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:22,970 INFO L85 PathProgramCache]: Analyzing trace with hash 921784534, now seen corresponding path program 12 times [2022-11-18 18:53:22,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:22,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727718642] [2022-11-18 18:53:22,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:22,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:22,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:23,449 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:23,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:23,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727718642] [2022-11-18 18:53:23,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727718642] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:23,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1278537967] [2022-11-18 18:53:23,449 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:53:23,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:23,450 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:23,451 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:23,454 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-11-18 18:53:24,626 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-18 18:53:24,627 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:24,629 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 18:53:24,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:25,159 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:25,159 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:25,554 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:25,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1278537967] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:25,555 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:25,555 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 41 [2022-11-18 18:53:25,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691669614] [2022-11-18 18:53:25,555 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:25,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:25,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:25,556 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-18 18:53:25,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:25,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318294340] [2022-11-18 18:53:25,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:25,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:25,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:25,560 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:25,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:25,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:25,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:25,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 18:53:25,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=1258, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:53:25,617 INFO L87 Difference]: Start difference. First operand 78 states and 97 transitions. cyclomatic complexity: 24 Second operand has 41 states, 41 states have (on average 2.317073170731707) internal successors, (95), 41 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:26,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:26,026 INFO L93 Difference]: Finished difference Result 108 states and 128 transitions. [2022-11-18 18:53:26,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 128 transitions. [2022-11-18 18:53:26,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:26,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 84 states and 104 transitions. [2022-11-18 18:53:26,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:53:26,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:53:26,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 104 transitions. [2022-11-18 18:53:26,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:26,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84 states and 104 transitions. [2022-11-18 18:53:26,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 104 transitions. [2022-11-18 18:53:26,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 80. [2022-11-18 18:53:26,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2375) internal successors, (99), 79 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:26,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 99 transitions. [2022-11-18 18:53:26,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 99 transitions. [2022-11-18 18:53:26,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 18:53:26,035 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 99 transitions. [2022-11-18 18:53:26,036 INFO L335 stractBuchiCegarLoop]: ======== Iteration 51 ============ [2022-11-18 18:53:26,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 99 transitions. [2022-11-18 18:53:26,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:26,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:26,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:26,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:26,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:26,037 INFO L748 eck$LassoCheckResult]: Stem: 26329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26340#L367 assume !(main_~length~0#1 < 1); 26331#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26332#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26333#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26341#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26407#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26405#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26404#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26401#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26400#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26399#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26398#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26397#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26396#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26395#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26393#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26392#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26389#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26386#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26383#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26380#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26342#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26343#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26369#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26347#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26334#L370-4 main_~j~0#1 := 0; 26335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26345#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26368#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26367#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26365#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26364#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26363#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26361#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26360#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26359#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26357#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26356#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26355#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26353#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26350#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26336#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26337#L378-2 [2022-11-18 18:53:26,038 INFO L750 eck$LassoCheckResult]: Loop: 26337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26351#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26337#L378-2 [2022-11-18 18:53:26,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:26,038 INFO L85 PathProgramCache]: Analyzing trace with hash 1897673997, now seen corresponding path program 32 times [2022-11-18 18:53:26,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:26,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865834119] [2022-11-18 18:53:26,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:26,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:26,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:27,205 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:27,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:27,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865834119] [2022-11-18 18:53:27,206 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865834119] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:27,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [51873548] [2022-11-18 18:53:27,206 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:53:27,206 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:27,207 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:27,215 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:27,217 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2022-11-18 18:53:27,499 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:53:27,500 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:27,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 59 conjunts are in the unsatisfiable core [2022-11-18 18:53:27,506 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:28,166 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:53:28,362 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:53:28,363 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:53:28,378 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:53:28,379 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:53:29,223 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:53:29,226 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:29,226 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:29,613 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:53:29,617 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:53:29,733 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:29,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [51873548] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:29,734 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:29,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 28] total 58 [2022-11-18 18:53:29,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345004935] [2022-11-18 18:53:29,735 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:29,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:29,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:29,735 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-18 18:53:29,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:29,736 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896239281] [2022-11-18 18:53:29,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:29,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:29,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:29,740 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:29,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:29,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:29,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:29,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 18:53:29,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=3209, Unknown=0, NotChecked=0, Total=3422 [2022-11-18 18:53:29,798 INFO L87 Difference]: Start difference. First operand 80 states and 99 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:31,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:31,763 INFO L93 Difference]: Finished difference Result 102 states and 121 transitions. [2022-11-18 18:53:31,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 121 transitions. [2022-11-18 18:53:31,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:31,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 101 states and 120 transitions. [2022-11-18 18:53:31,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:53:31,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:53:31,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 120 transitions. [2022-11-18 18:53:31,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:31,765 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 120 transitions. [2022-11-18 18:53:31,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 120 transitions. [2022-11-18 18:53:31,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 72. [2022-11-18 18:53:31,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2222222222222223) internal successors, (88), 71 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:31,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 88 transitions. [2022-11-18 18:53:31,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72 states and 88 transitions. [2022-11-18 18:53:31,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2022-11-18 18:53:31,771 INFO L428 stractBuchiCegarLoop]: Abstraction has 72 states and 88 transitions. [2022-11-18 18:53:31,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 52 ============ [2022-11-18 18:53:31,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 88 transitions. [2022-11-18 18:53:31,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:31,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:31,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:31,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:31,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:31,773 INFO L748 eck$LassoCheckResult]: Stem: 26983#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26994#L367 assume !(main_~length~0#1 < 1); 26985#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26986#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26987#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26995#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26998#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27041#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27040#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27039#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27038#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27037#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27036#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27035#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27034#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27033#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27032#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27031#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27030#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27028#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27027#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27026#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27025#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27024#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27023#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27022#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27021#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27020#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27019#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27017#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27016#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27015#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27014#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27001#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26996#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26997#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27008#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27002#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26988#L370-4 main_~j~0#1 := 0; 26989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26999#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27000#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27054#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27053#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27052#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27050#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27048#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27046#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27045#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27044#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27010#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27009#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27005#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26990#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26991#L378-2 [2022-11-18 18:53:31,774 INFO L750 eck$LassoCheckResult]: Loop: 26991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27006#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26991#L378-2 [2022-11-18 18:53:31,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:31,774 INFO L85 PathProgramCache]: Analyzing trace with hash 1387507918, now seen corresponding path program 33 times [2022-11-18 18:53:31,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:31,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51740075] [2022-11-18 18:53:31,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:31,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:31,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:32,842 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:32,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:32,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51740075] [2022-11-18 18:53:32,843 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51740075] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:32,843 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [176658497] [2022-11-18 18:53:32,843 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:53:32,843 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:32,843 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:32,851 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:32,867 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-11-18 18:53:33,749 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2022-11-18 18:53:33,749 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:33,754 INFO L263 TraceCheckSpWp]: Trace formula consists of 341 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-18 18:53:33,757 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:34,247 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:53:36,735 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 18:53:36,736 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 18:53:36,740 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 121 proven. 221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:36,741 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:38,957 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:53:38,961 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-18 18:53:39,444 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 110 proven. 232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:39,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [176658497] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:39,444 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:39,445 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 30] total 73 [2022-11-18 18:53:39,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929133665] [2022-11-18 18:53:39,445 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:39,445 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:39,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:39,446 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-18 18:53:39,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:39,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291354015] [2022-11-18 18:53:39,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:39,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:39,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:39,450 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:39,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:39,452 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:39,515 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:39,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2022-11-18 18:53:39,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=607, Invalid=4795, Unknown=0, NotChecked=0, Total=5402 [2022-11-18 18:53:39,517 INFO L87 Difference]: Start difference. First operand 72 states and 88 transitions. cyclomatic complexity: 20 Second operand has 74 states, 73 states have (on average 2.1506849315068495) internal successors, (157), 74 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:43,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:43,323 INFO L93 Difference]: Finished difference Result 127 states and 147 transitions. [2022-11-18 18:53:43,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127 states and 147 transitions. [2022-11-18 18:53:43,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:43,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127 states to 100 states and 118 transitions. [2022-11-18 18:53:43,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 18:53:43,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 18:53:43,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 118 transitions. [2022-11-18 18:53:43,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:43,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 118 transitions. [2022-11-18 18:53:43,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 118 transitions. [2022-11-18 18:53:43,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 78. [2022-11-18 18:53:43,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 77 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:43,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 96 transitions. [2022-11-18 18:53:43,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 96 transitions. [2022-11-18 18:53:43,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-11-18 18:53:43,330 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 96 transitions. [2022-11-18 18:53:43,330 INFO L335 stractBuchiCegarLoop]: ======== Iteration 53 ============ [2022-11-18 18:53:43,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 96 transitions. [2022-11-18 18:53:43,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:43,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:43,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:43,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 11, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:43,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:43,332 INFO L748 eck$LassoCheckResult]: Stem: 27762#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 27763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 27773#L367 assume !(main_~length~0#1 < 1); 27764#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 27765#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 27766#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27774#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27777#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27775#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27776#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27837#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27834#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27831#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27828#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27827#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27825#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27822#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27819#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27816#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27815#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27795#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27794#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27789#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27784#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27786#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27783#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27780#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 27767#L370-4 main_~j~0#1 := 0; 27768#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27778#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27771#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27772#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27814#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27813#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27812#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27810#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27808#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27807#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27806#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27804#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27803#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27802#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27800#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27798#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27797#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27769#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 27770#L378-2 [2022-11-18 18:53:43,333 INFO L750 eck$LassoCheckResult]: Loop: 27770#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27796#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 27770#L378-2 [2022-11-18 18:53:43,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:43,333 INFO L85 PathProgramCache]: Analyzing trace with hash -1286492714, now seen corresponding path program 34 times [2022-11-18 18:53:43,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:43,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874785538] [2022-11-18 18:53:43,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:43,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:43,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:44,558 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:44,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:44,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874785538] [2022-11-18 18:53:44,559 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874785538] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:44,559 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [397149593] [2022-11-18 18:53:44,559 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:53:44,559 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:44,559 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:44,567 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:44,587 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2022-11-18 18:53:44,855 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:53:44,855 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:44,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 56 conjunts are in the unsatisfiable core [2022-11-18 18:53:44,861 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:45,011 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:53:45,171 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 18:53:45,172 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 18:53:46,364 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-18 18:53:46,365 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-18 18:53:46,407 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:46,407 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:49,596 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2022-11-18 18:53:49,600 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 130 treesize of output 122 [2022-11-18 18:53:49,743 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:49,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [397149593] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:49,744 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:49,744 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 60 [2022-11-18 18:53:49,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782623120] [2022-11-18 18:53:49,744 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:49,745 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:49,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:49,745 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2022-11-18 18:53:49,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:49,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412531042] [2022-11-18 18:53:49,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:49,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:49,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:49,749 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:49,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:49,752 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:49,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:49,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-11-18 18:53:49,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=198, Invalid=3462, Unknown=0, NotChecked=0, Total=3660 [2022-11-18 18:53:49,805 INFO L87 Difference]: Start difference. First operand 78 states and 96 transitions. cyclomatic complexity: 22 Second operand has 61 states, 60 states have (on average 2.183333333333333) internal successors, (131), 61 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:51,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:51,892 INFO L93 Difference]: Finished difference Result 112 states and 133 transitions. [2022-11-18 18:53:51,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 133 transitions. [2022-11-18 18:53:51,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:51,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 111 states and 132 transitions. [2022-11-18 18:53:51,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:53:51,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:53:51,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 132 transitions. [2022-11-18 18:53:51,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:51,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111 states and 132 transitions. [2022-11-18 18:53:51,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 132 transitions. [2022-11-18 18:53:51,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 90. [2022-11-18 18:53:51,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.2333333333333334) internal successors, (111), 89 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:51,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 111 transitions. [2022-11-18 18:53:51,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90 states and 111 transitions. [2022-11-18 18:53:51,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-18 18:53:51,899 INFO L428 stractBuchiCegarLoop]: Abstraction has 90 states and 111 transitions. [2022-11-18 18:53:51,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 54 ============ [2022-11-18 18:53:51,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 111 transitions. [2022-11-18 18:53:51,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:51,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:51,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:51,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:51,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:51,901 INFO L748 eck$LassoCheckResult]: Stem: 28456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 28457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 28467#L367 assume !(main_~length~0#1 < 1); 28458#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 28459#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 28460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28468#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28523#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28521#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28520#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28517#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28514#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28511#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28508#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28507#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28505#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28504#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28502#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28499#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28495#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28494#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28493#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28492#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28469#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28470#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28542#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 28541#L370-4 main_~j~0#1 := 0; 28471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28463#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28464#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28539#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28537#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28536#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28535#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28534#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28533#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28531#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28529#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28528#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28526#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28489#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28482#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28480#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28477#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28476#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28461#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 28462#L378-2 [2022-11-18 18:53:51,902 INFO L750 eck$LassoCheckResult]: Loop: 28462#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28478#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 28462#L378-2 [2022-11-18 18:53:51,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:51,902 INFO L85 PathProgramCache]: Analyzing trace with hash -584892840, now seen corresponding path program 35 times [2022-11-18 18:53:51,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:51,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389915592] [2022-11-18 18:53:51,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:51,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:51,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:53,026 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:53,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:53,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389915592] [2022-11-18 18:53:53,026 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389915592] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:53,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [825359876] [2022-11-18 18:53:53,026 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:53:53,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:53,027 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:53,028 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:53,031 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2022-11-18 18:53:53,509 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2022-11-18 18:53:53,509 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:53:53,513 INFO L263 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-18 18:53:53,516 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:53:54,160 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:53:54,360 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:53:54,360 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 18:53:55,492 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 18:53:55,495 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:53:55,495 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-18 18:53:55,498 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:55,499 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:53:55,995 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-18 18:53:55,998 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-18 18:53:56,132 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:56,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [825359876] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:53:56,132 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:53:56,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 32, 31] total 64 [2022-11-18 18:53:56,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532277416] [2022-11-18 18:53:56,132 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:53:56,133 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:53:56,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:56,133 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2022-11-18 18:53:56,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:56,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214393206] [2022-11-18 18:53:56,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:56,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:56,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:56,137 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:53:56,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:53:56,140 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:53:56,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:53:56,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2022-11-18 18:53:56,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=239, Invalid=3921, Unknown=0, NotChecked=0, Total=4160 [2022-11-18 18:53:56,191 INFO L87 Difference]: Start difference. First operand 90 states and 111 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.21875) internal successors, (142), 65 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:58,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:53:58,548 INFO L93 Difference]: Finished difference Result 114 states and 135 transitions. [2022-11-18 18:53:58,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 135 transitions. [2022-11-18 18:53:58,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:58,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 113 states and 134 transitions. [2022-11-18 18:53:58,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 18:53:58,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 18:53:58,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 134 transitions. [2022-11-18 18:53:58,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 18:53:58,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 113 states and 134 transitions. [2022-11-18 18:53:58,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 134 transitions. [2022-11-18 18:53:58,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 80. [2022-11-18 18:53:58,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.225) internal successors, (98), 79 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:53:58,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 98 transitions. [2022-11-18 18:53:58,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-18 18:53:58,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-18 18:53:58,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-18 18:53:58,563 INFO L335 stractBuchiCegarLoop]: ======== Iteration 55 ============ [2022-11-18 18:53:58,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 98 transitions. [2022-11-18 18:53:58,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 18:53:58,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:53:58,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:53:58,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:53:58,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:53:58,565 INFO L748 eck$LassoCheckResult]: Stem: 29170#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 29171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 29181#L367 assume !(main_~length~0#1 < 1); 29172#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 29173#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 29174#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29182#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29183#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29184#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29234#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29233#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29231#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29230#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29227#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29224#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29221#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29219#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29218#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29216#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29215#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29213#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29212#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29209#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29206#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29204#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29195#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29188#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 29175#L370-4 main_~j~0#1 := 0; 29176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29186#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29187#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29179#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29180#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29249#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29248#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29247#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29245#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29243#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29242#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29241#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29237#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29202#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29200#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29197#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29194#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29192#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29191#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29177#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 29178#L378-2 [2022-11-18 18:53:58,566 INFO L750 eck$LassoCheckResult]: Loop: 29178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29190#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 29178#L378-2 [2022-11-18 18:53:58,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:53:58,570 INFO L85 PathProgramCache]: Analyzing trace with hash 631086363, now seen corresponding path program 36 times [2022-11-18 18:53:58,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:53:58,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453236508] [2022-11-18 18:53:58,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:53:58,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:53:58,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:53:59,818 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:53:59,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:53:59,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453236508] [2022-11-18 18:53:59,819 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453236508] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:53:59,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1179710424] [2022-11-18 18:53:59,819 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:53:59,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:53:59,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:53:59,827 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:53:59,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2022-11-18 18:54:00,840 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2022-11-18 18:54:00,840 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:54:00,846 INFO L263 TraceCheckSpWp]: Trace formula consists of 374 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-18 18:54:00,850 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:54:01,328 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 18:54:01,445 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:54:01,454 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 18:54:01,712 INFO L321 Elim1Store]: treesize reduction 43, result has 49.4 percent of original size [2022-11-18 18:54:01,712 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 39 treesize of output 59 [2022-11-18 18:54:08,483 INFO L321 Elim1Store]: treesize reduction 113, result has 65.7 percent of original size [2022-11-18 18:54:08,484 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 125 treesize of output 273 [2022-11-18 18:54:08,876 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 144 proven. 259 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:54:08,876 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:54:12,232 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 18:54:12,235 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 20 [2022-11-18 18:54:12,860 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 132 proven. 265 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-18 18:54:12,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1179710424] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:54:12,861 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:54:12,861 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 34, 30] total 82 [2022-11-18 18:54:12,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364405686] [2022-11-18 18:54:12,861 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:54:12,862 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:54:12,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:54:12,862 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2022-11-18 18:54:12,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:54:12,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094497707] [2022-11-18 18:54:12,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:54:12,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:54:12,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:54:12,867 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:54:12,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:54:12,871 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:54:12,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:54:12,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2022-11-18 18:54:12,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=737, Invalid=6069, Unknown=0, NotChecked=0, Total=6806 [2022-11-18 18:54:12,925 INFO L87 Difference]: Start difference. First operand 80 states and 98 transitions. cyclomatic complexity: 22 Second operand has 83 states, 82 states have (on average 2.182926829268293) internal successors, (179), 83 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:55:12,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:55:12,145 INFO L93 Difference]: Finished difference Result 233 states and 275 transitions. [2022-11-18 18:55:12,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 275 transitions. [2022-11-18 18:55:12,145 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2022-11-18 18:55:12,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 0 states and 0 transitions. [2022-11-18 18:55:12,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2022-11-18 18:55:12,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2022-11-18 18:55:12,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2022-11-18 18:55:12,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:55:12,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-18 18:55:12,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-18 18:55:12,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2022-11-18 18:55:12,146 INFO L428 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-18 18:55:12,147 INFO L335 stractBuchiCegarLoop]: ======== Iteration 56 ============ [2022-11-18 18:55:12,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2022-11-18 18:55:12,147 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2022-11-18 18:55:12,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2022-11-18 18:55:12,154 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 06:55:12 BoogieIcfgContainer [2022-11-18 18:55:12,155 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-18 18:55:12,155 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-18 18:55:12,156 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-18 18:55:12,156 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-18 18:55:12,157 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:49:47" (3/4) ... [2022-11-18 18:55:12,161 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-18 18:55:12,161 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-18 18:55:12,162 INFO L158 Benchmark]: Toolchain (without parser) took 326203.85ms. Allocated memory was 102.8MB in the beginning and 509.6MB in the end (delta: 406.8MB). Free memory was 69.6MB in the beginning and 268.4MB in the end (delta: -198.8MB). Peak memory consumption was 207.3MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,162 INFO L158 Benchmark]: CDTParser took 0.36ms. Allocated memory is still 102.8MB. Free memory is still 59.3MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 18:55:12,162 INFO L158 Benchmark]: CACSL2BoogieTranslator took 576.35ms. Allocated memory is still 102.8MB. Free memory was 69.6MB in the beginning and 71.7MB in the end (delta: -2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,163 INFO L158 Benchmark]: Boogie Procedure Inliner took 50.84ms. Allocated memory is still 102.8MB. Free memory was 71.7MB in the beginning and 69.8MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,163 INFO L158 Benchmark]: Boogie Preprocessor took 28.75ms. Allocated memory is still 102.8MB. Free memory was 69.8MB in the beginning and 68.8MB in the end (delta: 978.4kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 18:55:12,164 INFO L158 Benchmark]: RCFGBuilder took 474.10ms. Allocated memory is still 102.8MB. Free memory was 68.3MB in the beginning and 58.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,164 INFO L158 Benchmark]: BuchiAutomizer took 325062.33ms. Allocated memory was 102.8MB in the beginning and 509.6MB in the end (delta: 406.8MB). Free memory was 57.9MB in the beginning and 269.4MB in the end (delta: -211.5MB). Peak memory consumption was 197.2MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,165 INFO L158 Benchmark]: Witness Printer took 5.64ms. Allocated memory is still 509.6MB. Free memory was 269.4MB in the beginning and 268.4MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-18 18:55:12,166 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36ms. Allocated memory is still 102.8MB. Free memory is still 59.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 576.35ms. Allocated memory is still 102.8MB. Free memory was 69.6MB in the beginning and 71.7MB in the end (delta: -2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 50.84ms. Allocated memory is still 102.8MB. Free memory was 71.7MB in the beginning and 69.8MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.75ms. Allocated memory is still 102.8MB. Free memory was 69.8MB in the beginning and 68.8MB in the end (delta: 978.4kB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 474.10ms. Allocated memory is still 102.8MB. Free memory was 68.3MB in the beginning and 58.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 325062.33ms. Allocated memory was 102.8MB in the beginning and 509.6MB in the end (delta: 406.8MB). Free memory was 57.9MB in the beginning and 269.4MB in the end (delta: -211.5MB). Peak memory consumption was 197.2MB. Max. memory is 16.1GB. * Witness Printer took 5.64ms. Allocated memory is still 509.6MB. Free memory was 269.4MB in the beginning and 268.4MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 55 terminating modules (53 trivial, 2 deterministic, 0 nondeterministic). One deterministic module has affine ranking function -4 * i + unknown-#length-unknown[arr] + -1 * arr and consists of 5 locations. One deterministic module has affine ranking function -2 * j + unknown-#length-unknown[__builtin_alloca(length*sizeof(int))] + -1 * arr and consists of 4 locations. 53 modules have a trivial ranking function, the largest among these consists of 83 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 324.9s and 56 iterations. TraceHistogramMax:13. Analysis of lassos took 180.5s. Construction of modules took 24.5s. Büchi inclusion checks took 119.5s. Highest rank in rank-based complementation 3. Minimization of det autom 18. Minimization of nondet autom 37. Automata minimization 0.2s AutomataMinimizationTime, 54 MinimizatonAttempts, 2311 StatesRemovedByMinimization, 51 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4110 SdHoareTripleChecker+Valid, 29.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4109 mSDsluCounter, 9974 SdHoareTripleChecker+Invalid, 24.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 4308 IncrementalHoareTripleChecker+Unchecked, 9334 mSDsCounter, 561 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 42509 IncrementalHoareTripleChecker+Invalid, 47378 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 561 mSolverCounterUnsat, 640 mSDtfsCounter, 42509 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc14 concLT0 SILN0 SILU39 SILI0 SILT0 lasso2 LassoPreprocessingBenchmarks: Lassos: inital138 mio100 ax100 hnf100 lsp93 ukn84 mio100 lsp56 div163 bol100 ite100 ukn100 eq150 hnf93 smp72 dnf100 smp100 tf100 neg98 sie103 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 40ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2022-11-18 18:55:12,191 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:12,393 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Ended with exit code 0 [2022-11-18 18:55:12,593 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:12,793 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Ended with exit code 0 [2022-11-18 18:55:12,993 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:13,193 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:13,393 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Ended with exit code 0 [2022-11-18 18:55:13,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Ended with exit code 0 [2022-11-18 18:55:13,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2022-11-18 18:55:13,994 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Ended with exit code 0 [2022-11-18 18:55:14,195 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:14,394 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2022-11-18 18:55:14,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2022-11-18 18:55:14,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Ended with exit code 0 [2022-11-18 18:55:14,995 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Ended with exit code 0 [2022-11-18 18:55:15,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2022-11-18 18:55:15,395 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Ended with exit code 0 [2022-11-18 18:55:15,595 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2022-11-18 18:55:15,795 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2022-11-18 18:55:15,997 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:16,196 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2022-11-18 18:55:16,396 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Ended with exit code 0 [2022-11-18 18:55:16,595 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2022-11-18 18:55:16,796 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Ended with exit code 0 [2022-11-18 18:55:16,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2022-11-18 18:55:17,196 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2022-11-18 18:55:17,397 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Ended with exit code 0 [2022-11-18 18:55:17,597 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2022-11-18 18:55:17,797 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Ended with exit code 0 [2022-11-18 18:55:17,997 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2022-11-18 18:55:18,197 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2022-11-18 18:55:18,397 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2022-11-18 18:55:18,598 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Ended with exit code 0 [2022-11-18 18:55:18,798 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2022-11-18 18:55:18,998 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Ended with exit code 0 [2022-11-18 18:55:19,198 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2022-11-18 18:55:19,398 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2022-11-18 18:55:19,599 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:19,798 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2022-11-18 18:55:20,002 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:20,199 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:20,399 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:20,600 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2022-11-18 18:55:20,800 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:21,000 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2022-11-18 18:55:21,200 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2022-11-18 18:55:21,400 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2022-11-18 18:55:21,600 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2022-11-18 18:55:21,800 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2022-11-18 18:55:22,001 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2022-11-18 18:55:22,201 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-11-18 18:55:22,401 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2022-11-18 18:55:22,687 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4c661570-c99f-4f38-8d0d-9ba5a92350d9/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE