./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 20:10:28,874 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 20:10:28,876 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 20:10:28,898 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 20:10:28,898 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 20:10:28,899 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 20:10:28,901 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 20:10:28,903 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 20:10:28,904 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 20:10:28,905 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 20:10:28,907 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 20:10:28,908 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 20:10:28,908 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 20:10:28,910 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 20:10:28,911 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 20:10:28,917 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 20:10:28,921 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 20:10:28,922 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 20:10:28,924 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 20:10:28,928 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 20:10:28,933 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 20:10:28,935 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 20:10:28,940 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 20:10:28,941 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 20:10:28,945 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 20:10:28,953 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 20:10:28,953 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 20:10:28,954 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 20:10:28,955 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 20:10:28,956 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 20:10:28,956 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 20:10:28,957 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 20:10:28,958 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 20:10:28,958 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 20:10:28,959 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 20:10:28,961 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 20:10:28,963 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 20:10:28,963 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 20:10:28,964 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 20:10:28,965 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 20:10:28,966 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 20:10:28,967 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-18 20:10:29,002 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 20:10:29,006 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 20:10:29,007 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 20:10:29,007 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 20:10:29,008 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 20:10:29,008 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 20:10:29,009 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 20:10:29,009 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 20:10:29,009 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 20:10:29,009 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 20:10:29,010 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 20:10:29,010 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 20:10:29,011 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 20:10:29,011 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 20:10:29,011 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 20:10:29,011 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 20:10:29,012 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 20:10:29,012 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 20:10:29,012 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 20:10:29,012 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 20:10:29,012 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 20:10:29,013 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 20:10:29,013 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 20:10:29,013 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 20:10:29,013 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 20:10:29,013 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 20:10:29,014 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 20:10:29,015 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 20:10:29,016 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 20:10:29,017 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2022-11-18 20:10:29,301 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 20:10:29,323 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 20:10:29,326 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 20:10:29,327 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 20:10:29,334 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 20:10:29,335 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2022-11-18 20:10:29,412 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/data/d53efd93b/5f7f84a2ca72444baf93a551a1a51803/FLAG0fc8754a1 [2022-11-18 20:10:29,896 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 20:10:29,897 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2022-11-18 20:10:29,918 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/data/d53efd93b/5f7f84a2ca72444baf93a551a1a51803/FLAG0fc8754a1 [2022-11-18 20:10:30,229 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/data/d53efd93b/5f7f84a2ca72444baf93a551a1a51803 [2022-11-18 20:10:30,232 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 20:10:30,233 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 20:10:30,238 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 20:10:30,238 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 20:10:30,243 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 20:10:30,244 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,245 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46bb26cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30, skipping insertion in model container [2022-11-18 20:10:30,245 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,252 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 20:10:30,291 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 20:10:30,614 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:10:30,624 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 20:10:30,658 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:10:30,685 INFO L208 MainTranslator]: Completed translation [2022-11-18 20:10:30,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30 WrapperNode [2022-11-18 20:10:30,686 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 20:10:30,687 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 20:10:30,687 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 20:10:30,687 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 20:10:30,694 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,705 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,728 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-18 20:10:30,728 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 20:10:30,730 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 20:10:30,730 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 20:10:30,730 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 20:10:30,738 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,739 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,751 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,751 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,755 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,758 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,759 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,760 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,774 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 20:10:30,774 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 20:10:30,775 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 20:10:30,775 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 20:10:30,777 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (1/1) ... [2022-11-18 20:10:30,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:30,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:30,818 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:30,844 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 20:10:30,862 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 20:10:30,863 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 20:10:30,863 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 20:10:30,864 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 20:10:30,864 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 20:10:30,864 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 20:10:30,968 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 20:10:30,970 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 20:10:31,148 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 20:10:31,154 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 20:10:31,155 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 20:10:31,156 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:10:31 BoogieIcfgContainer [2022-11-18 20:10:31,157 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 20:10:31,158 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 20:10:31,158 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 20:10:31,162 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 20:10:31,163 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:10:31,163 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 08:10:30" (1/3) ... [2022-11-18 20:10:31,164 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71c1ac7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:10:31, skipping insertion in model container [2022-11-18 20:10:31,164 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:10:31,165 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:10:30" (2/3) ... [2022-11-18 20:10:31,165 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71c1ac7c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:10:31, skipping insertion in model container [2022-11-18 20:10:31,165 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:10:31,165 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:10:31" (3/3) ... [2022-11-18 20:10:31,167 INFO L332 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2022-11-18 20:10:31,223 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 20:10:31,224 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 20:10:31,224 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 20:10:31,224 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 20:10:31,224 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 20:10:31,224 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 20:10:31,224 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 20:10:31,225 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 20:10:31,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:31,262 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 20:10:31,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:31,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:31,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 20:10:31,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 20:10:31,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 20:10:31,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:31,270 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 20:10:31,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:31,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:31,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-18 20:10:31,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 20:10:31,279 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-18 20:10:31,279 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-18 20:10:31,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:31,286 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-18 20:10:31,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:31,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648397172] [2022-11-18 20:10:31,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:31,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:31,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:31,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:31,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:31,434 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-18 20:10:31,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:31,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694192034] [2022-11-18 20:10:31,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:31,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:31,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,470 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:31,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:31,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:31,506 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-18 20:10:31,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:31,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486269756] [2022-11-18 20:10:31,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:31,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:31,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,565 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:31,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:31,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:31,971 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 20:10:31,971 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 20:10:31,972 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 20:10:31,972 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 20:10:31,972 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 20:10:31,972 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:31,972 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 20:10:31,972 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 20:10:31,972 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2022-11-18 20:10:31,973 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 20:10:31,973 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 20:10:31,992 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,002 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,006 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,011 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,014 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,016 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,151 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,154 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,156 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,159 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,162 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,165 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:32,706 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 20:10:32,713 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 20:10:32,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:32,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:32,724 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:32,736 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:32,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 20:10:32,757 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:32,758 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:32,759 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:32,759 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:32,759 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:32,762 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:32,762 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:32,773 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:32,784 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2022-11-18 20:10:32,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:32,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:32,787 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:32,802 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:32,812 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 20:10:32,821 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:32,821 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:32,821 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:32,821 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:32,827 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:32,827 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:32,844 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:32,855 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:32,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:32,855 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:32,857 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:32,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 20:10:32,868 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:32,885 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:32,886 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:32,886 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:32,886 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:32,886 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:32,889 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:32,890 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:32,900 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:32,908 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:32,908 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:32,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:32,910 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:32,914 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 20:10:32,916 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:32,935 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:32,935 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:32,935 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:32,935 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:32,935 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:32,936 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:32,937 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:32,946 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:32,962 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:32,962 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:32,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:32,971 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:32,981 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:32,992 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 20:10:32,997 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:32,997 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:32,998 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:32,998 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:32,998 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:33,000 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:33,001 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:33,010 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:33,020 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:33,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:33,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:33,023 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:33,034 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:33,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 20:10:33,052 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:33,052 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:33,053 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:33,053 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:33,053 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:33,054 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:33,054 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:33,076 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:33,084 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:33,085 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:33,085 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:33,086 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:33,096 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:33,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 20:10:33,111 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:33,112 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:33,112 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:33,112 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:33,117 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:33,117 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:33,132 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:33,144 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:33,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:33,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:33,161 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:33,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 20:10:33,177 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:33,188 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:33,189 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:33,189 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:33,189 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:33,192 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:33,193 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:33,200 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:33,208 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:33,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:33,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:33,210 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:33,217 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:33,230 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-18 20:10:33,232 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:33,232 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:33,232 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:33,232 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:33,256 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:33,256 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:33,275 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 20:10:33,324 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-18 20:10:33,324 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-18 20:10:33,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:33,326 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:33,329 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:33,383 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 20:10:33,383 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-18 20:10:33,425 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 20:10:33,425 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 20:10:33,426 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1) = -4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 Supporting invariants [] [2022-11-18 20:10:33,445 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2022-11-18 20:10:33,458 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-18 20:10:33,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:33,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:33,523 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 20:10:33,525 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:33,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:33,557 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 20:10:33,558 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:33,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:33,635 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:33,687 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 20:10:33,689 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:33,762 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-18 20:10:33,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 20:10:33,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:33,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-18 20:10:33,773 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-18 20:10:33,774 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:33,774 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-18 20:10:33,774 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:33,774 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-18 20:10:33,775 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:33,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-18 20:10:33,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:33,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-18 20:10:33,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-18 20:10:33,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 20:10:33,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-18 20:10:33,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:10:33,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 20:10:33,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-18 20:10:33,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-18 20:10:33,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:33,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-18 20:10:33,818 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 20:10:33,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-18 20:10:33,819 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 20:10:33,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-18 20:10:33,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:33,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:33,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:33,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:33,823 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:33,823 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-18 20:10:33,824 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 118#L378-2 [2022-11-18 20:10:33,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:33,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-18 20:10:33,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:33,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911398434] [2022-11-18 20:10:33,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:33,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:33,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:33,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:33,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:33,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911398434] [2022-11-18 20:10:33,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1911398434] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 20:10:33,993 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 20:10:33,993 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 20:10:33,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483399336] [2022-11-18 20:10:33,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 20:10:33,997 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:33,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:33,999 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-18 20:10:33,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:34,000 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418900167] [2022-11-18 20:10:34,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:34,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:34,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,031 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:34,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,039 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:34,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:34,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 20:10:34,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-18 20:10:34,109 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:34,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:34,147 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-18 20:10:34,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-18 20:10:34,150 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:34,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-18 20:10:34,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-18 20:10:34,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-18 20:10:34,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-18 20:10:34,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:10:34,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-18 20:10:34,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-18 20:10:34,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-18 20:10:34,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:34,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-18 20:10:34,158 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 20:10:34,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 20:10:34,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-18 20:10:34,159 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 20:10:34,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-18 20:10:34,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:34,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:34,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:34,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:34,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:34,163 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-18 20:10:34,164 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 151#L378-2 [2022-11-18 20:10:34,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:34,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-18 20:10:34,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:34,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224290160] [2022-11-18 20:10:34,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:34,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:34,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,204 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:34,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:34,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:34,218 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-18 20:10:34,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:34,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606147388] [2022-11-18 20:10:34,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:34,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:34,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,225 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:34,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:34,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:34,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-18 20:10:34,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:34,233 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949749601] [2022-11-18 20:10:34,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:34,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:34,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,253 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:34,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:34,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:34,627 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 20:10:34,627 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 20:10:34,627 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 20:10:34,627 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 20:10:34,627 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 20:10:34,627 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:34,627 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 20:10:34,628 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 20:10:34,628 INFO L133 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2022-11-18 20:10:34,628 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 20:10:34,628 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 20:10:34,631 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,639 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,641 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,646 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,649 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,856 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,859 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,862 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,865 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,868 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:34,878 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:10:35,314 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 20:10:35,315 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 20:10:35,315 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,317 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-18 20:10:35,326 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:35,339 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:35,339 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:35,340 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:35,340 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:35,340 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:35,340 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:35,341 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:35,350 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:35,356 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:35,357 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,357 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,359 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-11-18 20:10:35,370 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:35,382 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:35,382 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:35,382 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:35,382 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:35,382 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:35,386 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:35,386 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:35,395 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:35,404 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:35,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,405 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,406 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,418 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:35,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-11-18 20:10:35,432 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:35,432 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:35,432 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:35,432 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:35,436 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:35,436 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:35,447 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:35,455 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:35,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,457 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2022-11-18 20:10:35,467 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:35,480 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:35,480 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:10:35,480 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:35,480 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:35,480 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:35,481 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:10:35,481 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:10:35,500 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:10:35,503 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:35,504 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,504 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,505 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2022-11-18 20:10:35,512 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:10:35,522 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:10:35,522 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:10:35,523 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:10:35,523 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:10:35,531 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:10:35,531 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:10:35,552 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 20:10:35,591 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-11-18 20:10:35,591 INFO L444 ModelExtractionUtils]: 17 out of 25 variables were initially zero. Simplification set additionally 5 variables to zero. [2022-11-18 20:10:35,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:10:35,592 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:35,593 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:10:35,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2022-11-18 20:10:35,612 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 20:10:35,630 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 20:10:35,631 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 20:10:35,631 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~length~0#1, ULTIMATE.start_main_~j~0#1) = 1*ULTIMATE.start_main_~length~0#1 - 1*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2022-11-18 20:10:35,641 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:35,650 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-18 20:10:35,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:35,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:35,696 INFO L263 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 20:10:35,697 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:35,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:35,732 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 20:10:35,732 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:35,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:35,747 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 20:10:35,747 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:35,768 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 12 states and 16 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 16 states and 22 transitions. Complement of second has 5 states. [2022-11-18 20:10:35,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-18 20:10:35,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:35,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 14 transitions. [2022-11-18 20:10:35,770 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 2 letters. [2022-11-18 20:10:35,771 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:35,771 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 12 letters. Loop has 2 letters. [2022-11-18 20:10:35,771 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:35,771 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 14 transitions. Stem has 10 letters. Loop has 4 letters. [2022-11-18 20:10:35,771 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:10:35,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 22 transitions. [2022-11-18 20:10:35,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:35,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 22 transitions. [2022-11-18 20:10:35,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2022-11-18 20:10:35,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 20:10:35,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 22 transitions. [2022-11-18 20:10:35,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:35,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-18 20:10:35,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 22 transitions. [2022-11-18 20:10:35,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2022-11-18 20:10:35,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.375) internal successors, (22), 15 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:35,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 22 transitions. [2022-11-18 20:10:35,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-18 20:10:35,775 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 22 transitions. [2022-11-18 20:10:35,775 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 20:10:35,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 22 transitions. [2022-11-18 20:10:35,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:35,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:35,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:35,776 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:35,776 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:35,777 INFO L748 eck$LassoCheckResult]: Stem: 241#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 252#L367 assume !(main_~length~0#1 < 1); 243#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 244#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 245#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 253#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 255#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 254#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 246#L370-4 main_~j~0#1 := 0; 247#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 248#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 249#L378-2 [2022-11-18 20:10:35,777 INFO L750 eck$LassoCheckResult]: Loop: 249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 256#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 249#L378-2 [2022-11-18 20:10:35,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:35,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-18 20:10:35,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:35,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950868026] [2022-11-18 20:10:35,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:35,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:35,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:36,290 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:36,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:36,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950868026] [2022-11-18 20:10:36,291 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950868026] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:36,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1797318002] [2022-11-18 20:10:36,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:36,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:36,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:36,293 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:36,324 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-18 20:10:36,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:36,400 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-18 20:10:36,401 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2022-11-18 20:10:36,404 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:36,454 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-18 20:10:36,552 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2022-11-18 20:10:36,565 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:36,565 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:36,688 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2022-11-18 20:10:36,694 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-18 20:10:36,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:36,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1797318002] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:36,716 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:36,716 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-18 20:10:36,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742366422] [2022-11-18 20:10:36,717 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:36,717 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:36,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:36,717 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-18 20:10:36,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:36,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248951420] [2022-11-18 20:10:36,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:36,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:36,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:36,742 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:36,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:36,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:36,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:36,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-18 20:10:36,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2022-11-18 20:10:36,813 INFO L87 Difference]: Start difference. First operand 16 states and 22 transitions. cyclomatic complexity: 9 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:36,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:36,999 INFO L93 Difference]: Finished difference Result 30 states and 41 transitions. [2022-11-18 20:10:36,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 41 transitions. [2022-11-18 20:10:37,000 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:37,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 40 transitions. [2022-11-18 20:10:37,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 20:10:37,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 20:10:37,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 40 transitions. [2022-11-18 20:10:37,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:37,002 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 40 transitions. [2022-11-18 20:10:37,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 40 transitions. [2022-11-18 20:10:37,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2022-11-18 20:10:37,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:37,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2022-11-18 20:10:37,004 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2022-11-18 20:10:37,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 20:10:37,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2022-11-18 20:10:37,009 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 20:10:37,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2022-11-18 20:10:37,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:37,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:37,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:37,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:37,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:37,011 INFO L748 eck$LassoCheckResult]: Stem: 377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 388#L367 assume !(main_~length~0#1 < 1); 379#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 380#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 389#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 397#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 396#L370-4 main_~j~0#1 := 0; 395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 386#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 384#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 385#L378-2 [2022-11-18 20:10:37,011 INFO L750 eck$LassoCheckResult]: Loop: 385#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 393#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 385#L378-2 [2022-11-18 20:10:37,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:37,012 INFO L85 PathProgramCache]: Analyzing trace with hash -645453020, now seen corresponding path program 1 times [2022-11-18 20:10:37,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:37,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824609981] [2022-11-18 20:10:37,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:37,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:37,095 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:37,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:37,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824609981] [2022-11-18 20:10:37,095 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824609981] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:37,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1944218343] [2022-11-18 20:10:37,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,096 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:37,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:37,097 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:37,124 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-18 20:10:37,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:37,169 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 20:10:37,170 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:37,228 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:37,228 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:37,277 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:37,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1944218343] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:37,278 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:37,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-18 20:10:37,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440847738] [2022-11-18 20:10:37,278 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:37,280 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:37,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:37,280 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-18 20:10:37,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:37,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069396739] [2022-11-18 20:10:37,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:37,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:37,287 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:37,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:37,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:37,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:37,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-18 20:10:37,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-18 20:10:37,363 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 13 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:37,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:37,504 INFO L93 Difference]: Finished difference Result 48 states and 64 transitions. [2022-11-18 20:10:37,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 64 transitions. [2022-11-18 20:10:37,506 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:37,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 43 states and 57 transitions. [2022-11-18 20:10:37,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-18 20:10:37,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-18 20:10:37,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 57 transitions. [2022-11-18 20:10:37,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:37,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 57 transitions. [2022-11-18 20:10:37,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 57 transitions. [2022-11-18 20:10:37,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 37. [2022-11-18 20:10:37,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.3513513513513513) internal successors, (50), 36 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:37,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 50 transitions. [2022-11-18 20:10:37,510 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 50 transitions. [2022-11-18 20:10:37,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 20:10:37,512 INFO L428 stractBuchiCegarLoop]: Abstraction has 37 states and 50 transitions. [2022-11-18 20:10:37,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 20:10:37,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 50 transitions. [2022-11-18 20:10:37,513 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:37,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:37,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:37,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:37,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:37,514 INFO L748 eck$LassoCheckResult]: Stem: 549#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 560#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 551#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 552#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 578#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 575#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 572#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 555#L370-4 main_~j~0#1 := 0; 556#L378-2 [2022-11-18 20:10:37,514 INFO L750 eck$LassoCheckResult]: Loop: 556#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 557#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 556#L378-2 [2022-11-18 20:10:37,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:37,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-18 20:10:37,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:37,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193908867] [2022-11-18 20:10:37,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:37,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:37,578 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:37,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:37,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193908867] [2022-11-18 20:10:37,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193908867] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:37,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [366262011] [2022-11-18 20:10:37,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:37,588 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:37,608 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:37,637 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-18 20:10:37,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:37,691 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-18 20:10:37,692 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:37,740 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:37,740 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 20:10:37,741 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [366262011] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 20:10:37,741 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-18 20:10:37,741 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-18 20:10:37,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377085448] [2022-11-18 20:10:37,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 20:10:37,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:37,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:37,748 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-18 20:10:37,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:37,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680824311] [2022-11-18 20:10:37,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:37,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:37,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:37,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:37,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:37,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:37,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 20:10:37,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 20:10:37,856 INFO L87 Difference]: Start difference. First operand 37 states and 50 transitions. cyclomatic complexity: 20 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:37,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:37,883 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2022-11-18 20:10:37,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 39 transitions. [2022-11-18 20:10:37,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:37,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 24 states and 32 transitions. [2022-11-18 20:10:37,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:10:37,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:10:37,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 32 transitions. [2022-11-18 20:10:37,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:37,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-18 20:10:37,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 32 transitions. [2022-11-18 20:10:37,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2022-11-18 20:10:37,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:37,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2022-11-18 20:10:37,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-18 20:10:37,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 20:10:37,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-11-18 20:10:37,890 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 20:10:37,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 32 transitions. [2022-11-18 20:10:37,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:37,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:37,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:37,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:37,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:37,892 INFO L748 eck$LassoCheckResult]: Stem: 662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 673#L367 assume !(main_~length~0#1 < 1); 664#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 665#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 666#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 674#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 675#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 676#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 677#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 684#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 682#L370-4 main_~j~0#1 := 0; 681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 669#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 670#L378-2 [2022-11-18 20:10:37,892 INFO L750 eck$LassoCheckResult]: Loop: 670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 679#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 670#L378-2 [2022-11-18 20:10:37,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:37,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-18 20:10:37,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:37,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873509131] [2022-11-18 20:10:37,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:37,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:37,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:38,470 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:38,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:38,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873509131] [2022-11-18 20:10:38,471 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873509131] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:38,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [153552574] [2022-11-18 20:10:38,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:38,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:38,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:38,475 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:38,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-18 20:10:38,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:38,551 INFO L263 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 20:10:38,554 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:38,580 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:38,684 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:38,685 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2022-11-18 20:10:38,735 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:38,736 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2022-11-18 20:10:38,800 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2022-11-18 20:10:38,816 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:38,816 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:39,159 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 43 [2022-11-18 20:10:39,167 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 138 [2022-11-18 20:10:39,253 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:39,253 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [153552574] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:39,254 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:39,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 20:10:39,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276559483] [2022-11-18 20:10:39,254 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:39,255 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:39,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:39,256 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-18 20:10:39,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:39,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127473723] [2022-11-18 20:10:39,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:39,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:39,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:39,261 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:39,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:39,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:39,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:39,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 20:10:39,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-18 20:10:39,335 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. cyclomatic complexity: 12 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:39,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:39,647 INFO L93 Difference]: Finished difference Result 51 states and 68 transitions. [2022-11-18 20:10:39,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 68 transitions. [2022-11-18 20:10:39,648 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 20:10:39,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 67 transitions. [2022-11-18 20:10:39,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-18 20:10:39,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-18 20:10:39,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 67 transitions. [2022-11-18 20:10:39,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:39,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50 states and 67 transitions. [2022-11-18 20:10:39,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 67 transitions. [2022-11-18 20:10:39,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 30. [2022-11-18 20:10:39,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.4) internal successors, (42), 29 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:39,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 42 transitions. [2022-11-18 20:10:39,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30 states and 42 transitions. [2022-11-18 20:10:39,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 20:10:39,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 30 states and 42 transitions. [2022-11-18 20:10:39,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 20:10:39,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 42 transitions. [2022-11-18 20:10:39,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:39,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:39,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:39,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:39,659 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:39,659 INFO L748 eck$LassoCheckResult]: Stem: 850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 861#L367 assume !(main_~length~0#1 < 1); 852#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 853#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 854#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 862#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 871#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 864#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 866#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 878#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 855#L370-4 main_~j~0#1 := 0; 856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 859#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 857#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 858#L378-2 [2022-11-18 20:10:39,659 INFO L750 eck$LassoCheckResult]: Loop: 858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 868#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 858#L378-2 [2022-11-18 20:10:39,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:39,660 INFO L85 PathProgramCache]: Analyzing trace with hash 123352160, now seen corresponding path program 1 times [2022-11-18 20:10:39,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:39,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051661470] [2022-11-18 20:10:39,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:39,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:39,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:40,005 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:40,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:40,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051661470] [2022-11-18 20:10:40,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051661470] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:40,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [207989470] [2022-11-18 20:10:40,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:40,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:40,006 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:40,012 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:40,035 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-18 20:10:40,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:40,090 INFO L263 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-18 20:10:40,092 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:40,152 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:10:40,237 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 20:10:40,240 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:40,240 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:40,320 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-18 20:10:40,334 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 18 [2022-11-18 20:10:40,357 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:40,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [207989470] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:40,358 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:40,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7] total 18 [2022-11-18 20:10:40,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715926951] [2022-11-18 20:10:40,359 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:40,359 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:40,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:40,359 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-18 20:10:40,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:40,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210397842] [2022-11-18 20:10:40,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:40,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:40,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:40,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:40,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:40,372 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:40,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:40,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 20:10:40,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2022-11-18 20:10:40,432 INFO L87 Difference]: Start difference. First operand 30 states and 42 transitions. cyclomatic complexity: 16 Second operand has 19 states, 18 states have (on average 2.111111111111111) internal successors, (38), 19 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:40,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:40,584 INFO L93 Difference]: Finished difference Result 43 states and 58 transitions. [2022-11-18 20:10:40,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 58 transitions. [2022-11-18 20:10:40,585 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:40,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 57 transitions. [2022-11-18 20:10:40,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:10:40,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:10:40,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 57 transitions. [2022-11-18 20:10:40,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:40,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42 states and 57 transitions. [2022-11-18 20:10:40,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 57 transitions. [2022-11-18 20:10:40,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 36. [2022-11-18 20:10:40,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.3611111111111112) internal successors, (49), 35 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:40,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 49 transitions. [2022-11-18 20:10:40,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 49 transitions. [2022-11-18 20:10:40,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 20:10:40,591 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 49 transitions. [2022-11-18 20:10:40,591 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-18 20:10:40,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 49 transitions. [2022-11-18 20:10:40,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:40,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:40,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:40,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:40,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:40,594 INFO L748 eck$LassoCheckResult]: Stem: 1045#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1056#L367 assume !(main_~length~0#1 < 1); 1047#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1048#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1049#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1057#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1069#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1058#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1059#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1064#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1065#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1054#L370-4 main_~j~0#1 := 0; 1055#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1052#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1053#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1050#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1051#L378-2 [2022-11-18 20:10:40,595 INFO L750 eck$LassoCheckResult]: Loop: 1051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1068#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1051#L378-2 [2022-11-18 20:10:40,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:40,595 INFO L85 PathProgramCache]: Analyzing trace with hash -685994466, now seen corresponding path program 2 times [2022-11-18 20:10:40,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:40,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122877283] [2022-11-18 20:10:40,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:40,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:40,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:40,954 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:40,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:40,955 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122877283] [2022-11-18 20:10:40,955 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122877283] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:40,955 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2069418916] [2022-11-18 20:10:40,955 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:10:40,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:40,956 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:40,964 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:40,976 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-18 20:10:41,042 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:10:41,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:41,046 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-18 20:10:41,053 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:41,116 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:10:41,265 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:10:41,279 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:41,280 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:41,441 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:10:41,445 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:10:41,462 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:41,462 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2069418916] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:41,462 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:41,463 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-18 20:10:41,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679886327] [2022-11-18 20:10:41,463 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:41,463 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:41,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:41,464 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-18 20:10:41,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:41,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079004805] [2022-11-18 20:10:41,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:41,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:41,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:41,471 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:41,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:41,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:41,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:41,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-18 20:10:41,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2022-11-18 20:10:41,549 INFO L87 Difference]: Start difference. First operand 36 states and 49 transitions. cyclomatic complexity: 17 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:41,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:41,828 INFO L93 Difference]: Finished difference Result 53 states and 71 transitions. [2022-11-18 20:10:41,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 71 transitions. [2022-11-18 20:10:41,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:41,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 70 transitions. [2022-11-18 20:10:41,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-11-18 20:10:41,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-11-18 20:10:41,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 70 transitions. [2022-11-18 20:10:41,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:41,830 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 70 transitions. [2022-11-18 20:10:41,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 70 transitions. [2022-11-18 20:10:41,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 41. [2022-11-18 20:10:41,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3902439024390243) internal successors, (57), 40 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:41,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 57 transitions. [2022-11-18 20:10:41,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 57 transitions. [2022-11-18 20:10:41,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 20:10:41,835 INFO L428 stractBuchiCegarLoop]: Abstraction has 41 states and 57 transitions. [2022-11-18 20:10:41,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-18 20:10:41,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 57 transitions. [2022-11-18 20:10:41,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:41,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:41,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:41,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:41,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:41,837 INFO L748 eck$LassoCheckResult]: Stem: 1260#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1271#L367 assume !(main_~length~0#1 < 1); 1262#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1263#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1264#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1272#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1274#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1298#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1288#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1276#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1290#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1289#L370-4 main_~j~0#1 := 0; 1283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1267#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1268#L378-2 [2022-11-18 20:10:41,837 INFO L750 eck$LassoCheckResult]: Loop: 1268#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1278#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1268#L378-2 [2022-11-18 20:10:41,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:41,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164513, now seen corresponding path program 2 times [2022-11-18 20:10:41,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:41,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310562101] [2022-11-18 20:10:41,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:41,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:41,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:42,648 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:42,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:42,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310562101] [2022-11-18 20:10:42,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310562101] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:42,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2055365010] [2022-11-18 20:10:42,649 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:10:42,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:42,650 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:42,656 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:42,659 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-18 20:10:42,731 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:10:42,731 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:42,732 INFO L263 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 20:10:42,741 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:42,777 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:42,863 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:42,864 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:10:42,882 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:42,883 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:10:42,950 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:42,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:10:42,965 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:42,966 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:10:43,033 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:10:43,036 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:43,036 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 12 [2022-11-18 20:10:43,048 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:43,048 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:43,793 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 51 [2022-11-18 20:10:43,806 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 74 [2022-11-18 20:10:43,891 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:10:43,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2055365010] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:43,891 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:43,891 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 25 [2022-11-18 20:10:43,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147516323] [2022-11-18 20:10:43,892 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:43,892 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:43,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:43,892 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-18 20:10:43,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:43,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750159263] [2022-11-18 20:10:43,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:43,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:43,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:43,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:43,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:43,900 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:43,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:43,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-18 20:10:43,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=509, Unknown=0, NotChecked=0, Total=650 [2022-11-18 20:10:43,957 INFO L87 Difference]: Start difference. First operand 41 states and 57 transitions. cyclomatic complexity: 21 Second operand has 26 states, 25 states have (on average 1.84) internal successors, (46), 26 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:44,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:44,178 INFO L93 Difference]: Finished difference Result 43 states and 58 transitions. [2022-11-18 20:10:44,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 58 transitions. [2022-11-18 20:10:44,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:44,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 56 transitions. [2022-11-18 20:10:44,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:10:44,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:10:44,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 56 transitions. [2022-11-18 20:10:44,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:44,180 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42 states and 56 transitions. [2022-11-18 20:10:44,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 56 transitions. [2022-11-18 20:10:44,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 27. [2022-11-18 20:10:44,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2962962962962963) internal successors, (35), 26 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:44,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 35 transitions. [2022-11-18 20:10:44,182 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 35 transitions. [2022-11-18 20:10:44,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 20:10:44,184 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2022-11-18 20:10:44,184 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-18 20:10:44,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 35 transitions. [2022-11-18 20:10:44,184 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:44,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:44,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:44,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:44,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:44,186 INFO L748 eck$LassoCheckResult]: Stem: 1484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1495#L367 assume !(main_~length~0#1 < 1); 1486#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1487#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1488#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1496#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1498#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1499#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1501#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1505#L370-4 main_~j~0#1 := 0; 1504#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1503#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1500#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1493#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1494#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1491#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1492#L378-2 [2022-11-18 20:10:44,186 INFO L750 eck$LassoCheckResult]: Loop: 1492#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1492#L378-2 [2022-11-18 20:10:44,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:44,186 INFO L85 PathProgramCache]: Analyzing trace with hash -2110686111, now seen corresponding path program 3 times [2022-11-18 20:10:44,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:44,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047843289] [2022-11-18 20:10:44,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:44,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:44,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:44,286 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:44,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:44,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047843289] [2022-11-18 20:10:44,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047843289] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:44,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1736351659] [2022-11-18 20:10:44,287 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:10:44,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:44,287 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:44,292 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:44,297 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-18 20:10:44,363 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-18 20:10:44,363 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:44,364 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 20:10:44,365 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:44,436 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:44,436 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:44,492 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:44,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1736351659] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:44,492 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:44,492 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-18 20:10:44,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730399004] [2022-11-18 20:10:44,493 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:44,493 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:44,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:44,493 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-18 20:10:44,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:44,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002617499] [2022-11-18 20:10:44,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:44,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:44,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:44,499 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:44,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:44,510 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:44,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:44,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 20:10:44,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-18 20:10:44,566 INFO L87 Difference]: Start difference. First operand 27 states and 35 transitions. cyclomatic complexity: 12 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:44,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:44,701 INFO L93 Difference]: Finished difference Result 38 states and 47 transitions. [2022-11-18 20:10:44,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 47 transitions. [2022-11-18 20:10:44,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:44,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 32 states and 41 transitions. [2022-11-18 20:10:44,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:10:44,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:10:44,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 41 transitions. [2022-11-18 20:10:44,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:44,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-18 20:10:44,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 41 transitions. [2022-11-18 20:10:44,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2022-11-18 20:10:44,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.2758620689655173) internal successors, (37), 28 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:44,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 37 transitions. [2022-11-18 20:10:44,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-18 20:10:44,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 20:10:44,708 INFO L428 stractBuchiCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-18 20:10:44,708 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-18 20:10:44,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 37 transitions. [2022-11-18 20:10:44,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:44,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:44,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:44,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:44,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:44,709 INFO L748 eck$LassoCheckResult]: Stem: 1682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1693#L367 assume !(main_~length~0#1 < 1); 1684#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1685#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1686#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1694#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1696#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1710#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1702#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1708#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1707#L370-4 main_~j~0#1 := 0; 1706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1699#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1689#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1690#L378-2 [2022-11-18 20:10:44,709 INFO L750 eck$LassoCheckResult]: Loop: 1690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1704#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1690#L378-2 [2022-11-18 20:10:44,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:44,711 INFO L85 PathProgramCache]: Analyzing trace with hash -761055450, now seen corresponding path program 2 times [2022-11-18 20:10:44,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:44,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371189836] [2022-11-18 20:10:44,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:44,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:44,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:45,223 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:45,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:45,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371189836] [2022-11-18 20:10:45,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371189836] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:45,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [515045355] [2022-11-18 20:10:45,223 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:10:45,223 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:45,224 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:45,227 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:45,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-18 20:10:45,299 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:10:45,299 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:45,300 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 20:10:45,302 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:45,363 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:45,462 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:45,462 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:10:45,474 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:45,475 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:10:45,591 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:10:45,605 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:45,605 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:45,804 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:10:45,808 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:10:45,824 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:45,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [515045355] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:45,825 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:45,825 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-18 20:10:45,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457030975] [2022-11-18 20:10:45,826 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:45,826 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:45,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:45,826 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-18 20:10:45,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:45,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517489624] [2022-11-18 20:10:45,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:45,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:45,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:45,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:45,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:45,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:45,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:45,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 20:10:45,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-18 20:10:45,889 INFO L87 Difference]: Start difference. First operand 29 states and 37 transitions. cyclomatic complexity: 12 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:46,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:46,122 INFO L93 Difference]: Finished difference Result 33 states and 41 transitions. [2022-11-18 20:10:46,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 41 transitions. [2022-11-18 20:10:46,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:46,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 32 states and 40 transitions. [2022-11-18 20:10:46,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:10:46,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:10:46,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 40 transitions. [2022-11-18 20:10:46,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:46,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 40 transitions. [2022-11-18 20:10:46,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 40 transitions. [2022-11-18 20:10:46,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 24. [2022-11-18 20:10:46,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.25) internal successors, (30), 23 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:46,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 30 transitions. [2022-11-18 20:10:46,126 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 30 transitions. [2022-11-18 20:10:46,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 20:10:46,127 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 30 transitions. [2022-11-18 20:10:46,127 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-18 20:10:46,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 30 transitions. [2022-11-18 20:10:46,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:46,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:46,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:46,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:46,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:46,129 INFO L748 eck$LassoCheckResult]: Stem: 1890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1901#L367 assume !(main_~length~0#1 < 1); 1892#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1893#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1902#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1905#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1904#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1910#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 1913#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1909#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1895#L370-4 main_~j~0#1 := 0; 1896#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1899#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1900#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1906#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1912#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1897#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 1898#L378-2 [2022-11-18 20:10:46,129 INFO L750 eck$LassoCheckResult]: Loop: 1898#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1911#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 1898#L378-2 [2022-11-18 20:10:46,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:46,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1622874713, now seen corresponding path program 4 times [2022-11-18 20:10:46,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:46,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343844335] [2022-11-18 20:10:46,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:46,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:46,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:46,572 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:46,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:46,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343844335] [2022-11-18 20:10:46,573 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343844335] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:46,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1024583600] [2022-11-18 20:10:46,573 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:10:46,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:46,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:46,580 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:46,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-11-18 20:10:46,649 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:10:46,650 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:46,651 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-18 20:10:46,652 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:46,690 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:46,873 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:10:46,876 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:46,876 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:46,971 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:10:46,975 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:10:47,002 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:47,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1024583600] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:47,003 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:47,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-18 20:10:47,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593240184] [2022-11-18 20:10:47,003 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:47,003 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:47,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:47,004 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-18 20:10:47,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:47,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114975992] [2022-11-18 20:10:47,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:47,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:47,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:47,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:47,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:47,012 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:47,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:47,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 20:10:47,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-18 20:10:47,066 INFO L87 Difference]: Start difference. First operand 24 states and 30 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:47,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:47,267 INFO L93 Difference]: Finished difference Result 42 states and 53 transitions. [2022-11-18 20:10:47,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 53 transitions. [2022-11-18 20:10:47,267 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:10:47,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 41 states and 52 transitions. [2022-11-18 20:10:47,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 20:10:47,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 20:10:47,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 52 transitions. [2022-11-18 20:10:47,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:47,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 52 transitions. [2022-11-18 20:10:47,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 52 transitions. [2022-11-18 20:10:47,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 32. [2022-11-18 20:10:47,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.28125) internal successors, (41), 31 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:47,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 41 transitions. [2022-11-18 20:10:47,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-18 20:10:47,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 20:10:47,277 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 41 transitions. [2022-11-18 20:10:47,277 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-18 20:10:47,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 41 transitions. [2022-11-18 20:10:47,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:47,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:47,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:47,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:47,279 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:47,279 INFO L748 eck$LassoCheckResult]: Stem: 2104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2105#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2115#L367 assume !(main_~length~0#1 < 1); 2106#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2107#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2108#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2116#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2126#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2127#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2128#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2129#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2117#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2118#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2119#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2122#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2109#L370-4 main_~j~0#1 := 0; 2110#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2133#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2132#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2113#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2114#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2121#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2111#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2112#L378-2 [2022-11-18 20:10:47,279 INFO L750 eck$LassoCheckResult]: Loop: 2112#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2130#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2112#L378-2 [2022-11-18 20:10:47,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:47,280 INFO L85 PathProgramCache]: Analyzing trace with hash -509471318, now seen corresponding path program 5 times [2022-11-18 20:10:47,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:47,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186187028] [2022-11-18 20:10:47,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:47,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:47,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:47,420 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:47,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:47,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186187028] [2022-11-18 20:10:47,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186187028] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:47,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [525962960] [2022-11-18 20:10:47,421 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:10:47,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:47,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:47,428 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:47,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-11-18 20:10:47,509 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-18 20:10:47,509 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:47,510 INFO L263 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 20:10:47,511 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:47,614 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:47,614 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:47,704 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:47,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [525962960] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:47,705 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:47,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-18 20:10:47,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896017373] [2022-11-18 20:10:47,705 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:47,706 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:47,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:47,706 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-18 20:10:47,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:47,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081149906] [2022-11-18 20:10:47,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:47,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:47,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:47,710 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:47,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:47,714 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:47,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:47,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 20:10:47,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-18 20:10:47,773 INFO L87 Difference]: Start difference. First operand 32 states and 41 transitions. cyclomatic complexity: 13 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:47,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:47,914 INFO L93 Difference]: Finished difference Result 45 states and 55 transitions. [2022-11-18 20:10:47,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 55 transitions. [2022-11-18 20:10:47,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:47,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 37 states and 47 transitions. [2022-11-18 20:10:47,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:10:47,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:10:47,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 47 transitions. [2022-11-18 20:10:47,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:47,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37 states and 47 transitions. [2022-11-18 20:10:47,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 47 transitions. [2022-11-18 20:10:47,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 34. [2022-11-18 20:10:47,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:47,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-18 20:10:47,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 20:10:47,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 20:10:47,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-18 20:10:47,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-18 20:10:47,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-18 20:10:47,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:47,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:47,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:47,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:47,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:47,924 INFO L748 eck$LassoCheckResult]: Stem: 2349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2360#L367 assume !(main_~length~0#1 < 1); 2351#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2352#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2353#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2361#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2362#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2363#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2366#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2381#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2380#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2379#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2376#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2367#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2368#L370-4 main_~j~0#1 := 0; 2374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2365#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2371#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2356#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2357#L378-2 [2022-11-18 20:10:47,926 INFO L750 eck$LassoCheckResult]: Loop: 2357#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2372#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2357#L378-2 [2022-11-18 20:10:47,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:47,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1285147747, now seen corresponding path program 3 times [2022-11-18 20:10:47,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:47,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627401937] [2022-11-18 20:10:47,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:47,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:47,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:48,578 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:48,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:48,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627401937] [2022-11-18 20:10:48,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627401937] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:48,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2092252522] [2022-11-18 20:10:48,579 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:10:48,579 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:48,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:48,588 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:48,608 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-18 20:10:48,706 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-11-18 20:10:48,706 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:48,707 INFO L263 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-18 20:10:48,711 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:48,775 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:48,891 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 20:10:48,891 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 29 treesize of output 36 [2022-11-18 20:10:48,976 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 20:10:48,976 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 49 [2022-11-18 20:10:49,564 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-18 20:10:49,567 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 36 treesize of output 36 [2022-11-18 20:10:49,626 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 4 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:49,626 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:50,594 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-18 20:10:50,599 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-18 20:10:50,661 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 20:10:50,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2092252522] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:50,661 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:50,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 12] total 32 [2022-11-18 20:10:50,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13422303] [2022-11-18 20:10:50,662 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:50,662 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:50,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:50,663 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-18 20:10:50,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:50,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387850453] [2022-11-18 20:10:50,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:50,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:50,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:50,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:50,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:50,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:50,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:50,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-11-18 20:10:50,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=912, Unknown=0, NotChecked=0, Total=1056 [2022-11-18 20:10:50,732 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 13 Second operand has 33 states, 32 states have (on average 1.78125) internal successors, (57), 33 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:52,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:52,040 INFO L93 Difference]: Finished difference Result 84 states and 103 transitions. [2022-11-18 20:10:52,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 103 transitions. [2022-11-18 20:10:52,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:52,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 67 states and 83 transitions. [2022-11-18 20:10:52,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-18 20:10:52,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-18 20:10:52,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 83 transitions. [2022-11-18 20:10:52,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:52,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 83 transitions. [2022-11-18 20:10:52,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 83 transitions. [2022-11-18 20:10:52,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 49. [2022-11-18 20:10:52,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.2857142857142858) internal successors, (63), 48 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:52,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 63 transitions. [2022-11-18 20:10:52,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 63 transitions. [2022-11-18 20:10:52,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2022-11-18 20:10:52,053 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 63 transitions. [2022-11-18 20:10:52,053 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-18 20:10:52,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 63 transitions. [2022-11-18 20:10:52,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:52,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:52,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:52,054 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:52,054 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:52,055 INFO L748 eck$LassoCheckResult]: Stem: 2691#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2702#L367 assume !(main_~length~0#1 < 1); 2693#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2694#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2703#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2734#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2733#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2731#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2729#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2727#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 2725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2714#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2720#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2718#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2717#L370-4 main_~j~0#1 := 0; 2716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2706#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2712#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2711#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2710#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2696#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 2697#L378-2 [2022-11-18 20:10:52,055 INFO L750 eck$LassoCheckResult]: Loop: 2697#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2709#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 2697#L378-2 [2022-11-18 20:10:52,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:52,056 INFO L85 PathProgramCache]: Analyzing trace with hash -299807453, now seen corresponding path program 4 times [2022-11-18 20:10:52,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:52,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431624501] [2022-11-18 20:10:52,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:52,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:52,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:52,724 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:52,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:52,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431624501] [2022-11-18 20:10:52,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431624501] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:52,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2117336945] [2022-11-18 20:10:52,724 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:10:52,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:52,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:52,732 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:52,756 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-11-18 20:10:52,820 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:10:52,820 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:52,822 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 20:10:52,829 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:52,857 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:52,967 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:10:52,968 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:10:53,001 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:10:53,001 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:10:53,127 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:10:53,130 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:53,131 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:53,379 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:10:53,384 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:10:53,423 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:53,423 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2117336945] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:53,423 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:53,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2022-11-18 20:10:53,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635862244] [2022-11-18 20:10:53,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:53,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:53,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:53,425 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-18 20:10:53,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:53,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040874044] [2022-11-18 20:10:53,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:53,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:53,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:53,429 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:53,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:53,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:53,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:53,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 20:10:53,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=322, Unknown=0, NotChecked=0, Total=380 [2022-11-18 20:10:53,503 INFO L87 Difference]: Start difference. First operand 49 states and 63 transitions. cyclomatic complexity: 19 Second operand has 20 states, 19 states have (on average 2.1052631578947367) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:53,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:53,967 INFO L93 Difference]: Finished difference Result 90 states and 113 transitions. [2022-11-18 20:10:53,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 113 transitions. [2022-11-18 20:10:53,968 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 20:10:53,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 89 states and 112 transitions. [2022-11-18 20:10:53,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-18 20:10:53,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-18 20:10:53,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 112 transitions. [2022-11-18 20:10:53,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:53,970 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89 states and 112 transitions. [2022-11-18 20:10:53,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 112 transitions. [2022-11-18 20:10:53,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 55. [2022-11-18 20:10:53,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.3272727272727274) internal successors, (73), 54 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:53,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 73 transitions. [2022-11-18 20:10:53,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 73 transitions. [2022-11-18 20:10:53,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-18 20:10:53,974 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 73 transitions. [2022-11-18 20:10:53,975 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-18 20:10:53,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 73 transitions. [2022-11-18 20:10:53,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:10:53,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:53,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:53,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:53,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:10:53,976 INFO L748 eck$LassoCheckResult]: Stem: 3007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3018#L367 assume !(main_~length~0#1 < 1); 3009#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3010#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3011#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3019#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3043#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3041#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3036#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3060#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3032#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3029#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3027#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3012#L370-4 main_~j~0#1 := 0; 3013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3016#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3017#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3024#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3052#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3050#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3014#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3015#L378-2 [2022-11-18 20:10:53,976 INFO L750 eck$LassoCheckResult]: Loop: 3015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3051#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3015#L378-2 [2022-11-18 20:10:53,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:53,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1185875042, now seen corresponding path program 5 times [2022-11-18 20:10:53,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:53,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983453588] [2022-11-18 20:10:53,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:53,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:54,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:54,530 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:54,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:54,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983453588] [2022-11-18 20:10:54,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983453588] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:54,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [734832721] [2022-11-18 20:10:54,531 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:10:54,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:54,531 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:54,535 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:54,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-11-18 20:10:54,705 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-11-18 20:10:54,705 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:54,707 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 20:10:54,709 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:54,904 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:10:55,303 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:10:55,306 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:55,307 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-18 20:10:55,331 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:55,331 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:10:55,613 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:10:55,618 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:10:55,675 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:55,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [734832721] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:10:55,675 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:10:55,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 13] total 28 [2022-11-18 20:10:55,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327002516] [2022-11-18 20:10:55,676 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:10:55,678 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:10:55,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:55,679 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-18 20:10:55,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:55,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076019893] [2022-11-18 20:10:55,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:55,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:55,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:55,684 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:10:55,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:10:55,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:10:55,758 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:10:55,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-18 20:10:55,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=706, Unknown=0, NotChecked=0, Total=812 [2022-11-18 20:10:55,760 INFO L87 Difference]: Start difference. First operand 55 states and 73 transitions. cyclomatic complexity: 23 Second operand has 29 states, 28 states have (on average 2.0) internal successors, (56), 29 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:56,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:10:56,431 INFO L93 Difference]: Finished difference Result 94 states and 122 transitions. [2022-11-18 20:10:56,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94 states and 122 transitions. [2022-11-18 20:10:56,433 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11 [2022-11-18 20:10:56,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94 states to 93 states and 121 transitions. [2022-11-18 20:10:56,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2022-11-18 20:10:56,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-11-18 20:10:56,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 121 transitions. [2022-11-18 20:10:56,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:10:56,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 121 transitions. [2022-11-18 20:10:56,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 121 transitions. [2022-11-18 20:10:56,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 82. [2022-11-18 20:10:56,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.3170731707317074) internal successors, (108), 81 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:10:56,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 108 transitions. [2022-11-18 20:10:56,458 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 108 transitions. [2022-11-18 20:10:56,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 20:10:56,459 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 108 transitions. [2022-11-18 20:10:56,460 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-18 20:10:56,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 108 transitions. [2022-11-18 20:10:56,461 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2022-11-18 20:10:56,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:10:56,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:10:56,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:10:56,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 20:10:56,463 INFO L748 eck$LassoCheckResult]: Stem: 3352#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3363#L367 assume !(main_~length~0#1 < 1); 3354#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3355#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3356#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3364#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3388#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3387#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3385#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3383#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3368#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3394#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3395#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3412#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3411#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3410#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3408#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3407#L370-4 main_~j~0#1 := 0; 3406#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3405#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3404#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3403#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3398#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3429#L378-2 [2022-11-18 20:10:56,463 INFO L750 eck$LassoCheckResult]: Loop: 3429#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3431#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3428#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3429#L378-2 [2022-11-18 20:10:56,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:10:56,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1799910937, now seen corresponding path program 6 times [2022-11-18 20:10:56,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:10:56,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881494566] [2022-11-18 20:10:56,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:10:56,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:10:56,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:10:57,143 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:57,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:10:57,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881494566] [2022-11-18 20:10:57,144 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881494566] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:10:57,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [922968641] [2022-11-18 20:10:57,144 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:10:57,145 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:10:57,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:10:57,152 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:10:57,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-18 20:10:57,281 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-11-18 20:10:57,281 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:10:57,284 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-18 20:10:57,287 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:10:57,367 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:10:57,448 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:10:57,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:10:57,559 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,561 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,564 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:57,564 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:10:57,580 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,582 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,589 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:57,590 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:10:57,657 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,659 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:10:57,662 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:57,663 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:10:57,990 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:10:57,990 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-18 20:10:57,994 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:10:57,994 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:15,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 78 [2022-11-18 20:11:15,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 4664 treesize of output 4600 [2022-11-18 20:11:20,253 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:20,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [922968641] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:20,254 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:20,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15, 15] total 39 [2022-11-18 20:11:20,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050620775] [2022-11-18 20:11:20,255 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:20,256 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:20,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:20,257 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 1 times [2022-11-18 20:11:20,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:20,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023510020] [2022-11-18 20:11:20,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:20,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:20,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:20,265 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:20,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:20,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:20,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:20,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-18 20:11:20,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1346, Unknown=1, NotChecked=0, Total=1560 [2022-11-18 20:11:20,464 INFO L87 Difference]: Start difference. First operand 82 states and 108 transitions. cyclomatic complexity: 33 Second operand has 40 states, 39 states have (on average 1.9487179487179487) internal successors, (76), 40 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:21,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:21,966 INFO L93 Difference]: Finished difference Result 196 states and 250 transitions. [2022-11-18 20:11:21,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196 states and 250 transitions. [2022-11-18 20:11:21,968 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 10 [2022-11-18 20:11:21,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196 states to 192 states and 246 transitions. [2022-11-18 20:11:21,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2022-11-18 20:11:21,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2022-11-18 20:11:21,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192 states and 246 transitions. [2022-11-18 20:11:21,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:21,969 INFO L218 hiAutomatonCegarLoop]: Abstraction has 192 states and 246 transitions. [2022-11-18 20:11:21,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states and 246 transitions. [2022-11-18 20:11:21,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 100. [2022-11-18 20:11:21,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.34) internal successors, (134), 99 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:21,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 134 transitions. [2022-11-18 20:11:21,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 134 transitions. [2022-11-18 20:11:21,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 20:11:21,983 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 134 transitions. [2022-11-18 20:11:21,984 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-18 20:11:21,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 134 transitions. [2022-11-18 20:11:21,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2022-11-18 20:11:21,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:21,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:21,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:21,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:21,987 INFO L748 eck$LassoCheckResult]: Stem: 3863#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3874#L367 assume !(main_~length~0#1 < 1); 3865#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3866#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3875#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3912#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3913#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3906#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 3908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3940#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3936#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3898#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3894#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3931#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3929#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3928#L370-4 main_~j~0#1 := 0; 3927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3883#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3885#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3886#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3868#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 3869#L378-2 [2022-11-18 20:11:21,989 INFO L750 eck$LassoCheckResult]: Loop: 3869#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3884#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 3869#L378-2 [2022-11-18 20:11:21,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:21,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1867015015, now seen corresponding path program 7 times [2022-11-18 20:11:21,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:21,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798798404] [2022-11-18 20:11:21,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:21,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:22,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:22,828 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 41 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:22,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:22,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798798404] [2022-11-18 20:11:22,829 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798798404] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:22,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [863435160] [2022-11-18 20:11:22,829 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:11:22,829 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:22,830 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:22,834 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:22,860 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-11-18 20:11:22,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:22,946 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-18 20:11:22,948 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:22,955 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-18 20:11:23,011 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-11-18 20:11:23,101 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:23,249 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:23,250 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:11:23,275 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:23,277 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:11:23,363 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:23,364 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:11:23,377 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:23,378 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:11:23,634 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:11:23,658 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 2 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:23,658 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:24,074 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:11:24,081 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:11:24,169 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 39 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:11:24,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [863435160] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:24,169 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:24,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 14] total 29 [2022-11-18 20:11:24,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233963676] [2022-11-18 20:11:24,170 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:24,170 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:24,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:24,171 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-18 20:11:24,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:24,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798975301] [2022-11-18 20:11:24,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:24,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:24,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:24,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:24,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:24,180 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:24,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:24,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-11-18 20:11:24,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=748, Unknown=0, NotChecked=0, Total=870 [2022-11-18 20:11:24,258 INFO L87 Difference]: Start difference. First operand 100 states and 134 transitions. cyclomatic complexity: 44 Second operand has 30 states, 29 states have (on average 2.1379310344827585) internal successors, (62), 30 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:24,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:24,936 INFO L93 Difference]: Finished difference Result 103 states and 133 transitions. [2022-11-18 20:11:24,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 133 transitions. [2022-11-18 20:11:24,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:24,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 101 states and 131 transitions. [2022-11-18 20:11:24,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:11:24,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:11:24,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 131 transitions. [2022-11-18 20:11:24,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:24,939 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 131 transitions. [2022-11-18 20:11:24,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 131 transitions. [2022-11-18 20:11:24,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 55. [2022-11-18 20:11:24,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.290909090909091) internal successors, (71), 54 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:24,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 71 transitions. [2022-11-18 20:11:24,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-18 20:11:24,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-18 20:11:24,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 71 transitions. [2022-11-18 20:11:24,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-18 20:11:24,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 71 transitions. [2022-11-18 20:11:24,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:24,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:24,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:24,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:24,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:24,958 INFO L748 eck$LassoCheckResult]: Stem: 4269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4280#L367 assume !(main_~length~0#1 < 1); 4271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4281#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4320#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4318#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4315#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4313#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4308#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4305#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4292#L370-4 main_~j~0#1 := 0; 4295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4294#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4285#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4291#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4288#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4287#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4276#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4277#L378-2 [2022-11-18 20:11:24,958 INFO L750 eck$LassoCheckResult]: Loop: 4277#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4289#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4277#L378-2 [2022-11-18 20:11:24,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:24,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1459581349, now seen corresponding path program 8 times [2022-11-18 20:11:24,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:24,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147610967] [2022-11-18 20:11:24,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:24,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:24,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:25,208 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:25,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:25,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147610967] [2022-11-18 20:11:25,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147610967] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:25,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1300278133] [2022-11-18 20:11:25,209 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:11:25,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:25,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:25,215 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:25,232 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-11-18 20:11:25,322 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:11:25,322 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:11:25,323 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 20:11:25,325 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:25,539 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:25,539 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:25,692 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:25,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1300278133] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:25,693 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:25,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-18 20:11:25,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301555235] [2022-11-18 20:11:25,693 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:25,694 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:25,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:25,694 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-18 20:11:25,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:25,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923140548] [2022-11-18 20:11:25,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:25,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:25,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:25,698 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:25,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:25,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:25,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:25,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-18 20:11:25,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-18 20:11:25,797 INFO L87 Difference]: Start difference. First operand 55 states and 71 transitions. cyclomatic complexity: 21 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:26,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:26,040 INFO L93 Difference]: Finished difference Result 71 states and 88 transitions. [2022-11-18 20:11:26,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 88 transitions. [2022-11-18 20:11:26,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:26,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 61 states and 78 transitions. [2022-11-18 20:11:26,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:11:26,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:11:26,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 78 transitions. [2022-11-18 20:11:26,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:26,050 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 78 transitions. [2022-11-18 20:11:26,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 78 transitions. [2022-11-18 20:11:26,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 57. [2022-11-18 20:11:26,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.280701754385965) internal successors, (73), 56 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:26,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 73 transitions. [2022-11-18 20:11:26,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57 states and 73 transitions. [2022-11-18 20:11:26,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 20:11:26,057 INFO L428 stractBuchiCegarLoop]: Abstraction has 57 states and 73 transitions. [2022-11-18 20:11:26,057 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-18 20:11:26,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 73 transitions. [2022-11-18 20:11:26,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:26,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:26,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:26,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:26,063 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:26,063 INFO L748 eck$LassoCheckResult]: Stem: 4598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4609#L367 assume !(main_~length~0#1 < 1); 4600#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4601#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4610#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4647#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4643#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4641#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4635#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 4633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4629#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4625#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4617#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4603#L370-4 main_~j~0#1 := 0; 4604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4615#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4623#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4622#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4620#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4605#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4606#L378-2 [2022-11-18 20:11:26,063 INFO L750 eck$LassoCheckResult]: Loop: 4606#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4621#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4606#L378-2 [2022-11-18 20:11:26,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:26,064 INFO L85 PathProgramCache]: Analyzing trace with hash -380619858, now seen corresponding path program 9 times [2022-11-18 20:11:26,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:26,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544936328] [2022-11-18 20:11:26,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:26,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:26,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:26,927 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:26,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:26,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544936328] [2022-11-18 20:11:26,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544936328] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:26,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [629876403] [2022-11-18 20:11:26,928 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:11:26,928 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:26,928 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:26,929 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:26,932 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-11-18 20:11:27,101 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 20:11:27,102 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:11:27,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-18 20:11:27,105 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:27,162 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:27,342 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:11:27,343 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:11:27,382 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:11:27,382 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:11:28,012 INFO L321 Elim1Store]: treesize reduction 30, result has 9.1 percent of original size [2022-11-18 20:11:28,015 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 17 [2022-11-18 20:11:28,020 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:28,020 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:28,307 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:11:28,317 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:11:28,369 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 1 proven. 45 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:11:28,370 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [629876403] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:28,370 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:28,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 13] total 24 [2022-11-18 20:11:28,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362921422] [2022-11-18 20:11:28,370 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:28,371 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:28,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:28,371 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-18 20:11:28,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:28,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073590418] [2022-11-18 20:11:28,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:28,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:28,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:28,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:28,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:28,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:28,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:28,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-18 20:11:28,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2022-11-18 20:11:28,472 INFO L87 Difference]: Start difference. First operand 57 states and 73 transitions. cyclomatic complexity: 21 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:29,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:29,151 INFO L93 Difference]: Finished difference Result 101 states and 126 transitions. [2022-11-18 20:11:29,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 126 transitions. [2022-11-18 20:11:29,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:11:29,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 100 states and 124 transitions. [2022-11-18 20:11:29,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-18 20:11:29,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-18 20:11:29,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2022-11-18 20:11:29,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:29,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2022-11-18 20:11:29,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2022-11-18 20:11:29,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 64. [2022-11-18 20:11:29,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.328125) internal successors, (85), 63 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:29,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 85 transitions. [2022-11-18 20:11:29,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 85 transitions. [2022-11-18 20:11:29,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 20:11:29,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 85 transitions. [2022-11-18 20:11:29,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-18 20:11:29,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 85 transitions. [2022-11-18 20:11:29,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:29,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:29,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:29,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:29,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:29,167 INFO L748 eck$LassoCheckResult]: Stem: 4966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4977#L367 assume !(main_~length~0#1 < 1); 4968#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4969#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4970#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4978#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4979#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4980#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5023#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5019#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5015#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5013#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5008#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5009#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4990#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4971#L370-4 main_~j~0#1 := 0; 4972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4992#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4984#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4975#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4989#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4988#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4987#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4986#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4973#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 4974#L378-2 [2022-11-18 20:11:29,167 INFO L750 eck$LassoCheckResult]: Loop: 4974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4985#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 4974#L378-2 [2022-11-18 20:11:29,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:29,168 INFO L85 PathProgramCache]: Analyzing trace with hash -126233299, now seen corresponding path program 10 times [2022-11-18 20:11:29,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:29,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580238464] [2022-11-18 20:11:29,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:29,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:29,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:29,933 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:29,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:29,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580238464] [2022-11-18 20:11:29,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580238464] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:29,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [209035561] [2022-11-18 20:11:29,936 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:11:29,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:29,936 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:29,941 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:29,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-11-18 20:11:30,041 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:11:30,041 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:11:30,043 INFO L263 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 20:11:30,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:30,103 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:30,434 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:11:30,438 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:30,438 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:30,619 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:11:30,625 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:11:30,691 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:30,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [209035561] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:30,691 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:30,692 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 22 [2022-11-18 20:11:30,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211609841] [2022-11-18 20:11:30,692 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:30,694 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:30,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:30,695 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-18 20:11:30,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:30,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453180837] [2022-11-18 20:11:30,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:30,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:30,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:30,701 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:30,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:30,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:30,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:30,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 20:11:30,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=442, Unknown=0, NotChecked=0, Total=506 [2022-11-18 20:11:30,785 INFO L87 Difference]: Start difference. First operand 64 states and 85 transitions. cyclomatic complexity: 27 Second operand has 23 states, 22 states have (on average 2.1818181818181817) internal successors, (48), 23 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:31,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:31,394 INFO L93 Difference]: Finished difference Result 81 states and 104 transitions. [2022-11-18 20:11:31,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 104 transitions. [2022-11-18 20:11:31,395 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:11:31,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 103 transitions. [2022-11-18 20:11:31,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:11:31,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:11:31,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 103 transitions. [2022-11-18 20:11:31,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:31,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 103 transitions. [2022-11-18 20:11:31,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 103 transitions. [2022-11-18 20:11:31,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2022-11-18 20:11:31,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.3088235294117647) internal successors, (89), 67 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:31,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 89 transitions. [2022-11-18 20:11:31,399 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 89 transitions. [2022-11-18 20:11:31,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 20:11:31,400 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 89 transitions. [2022-11-18 20:11:31,401 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-18 20:11:31,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 89 transitions. [2022-11-18 20:11:31,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:11:31,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:31,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:31,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:31,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:31,403 INFO L748 eck$LassoCheckResult]: Stem: 5327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5338#L367 assume !(main_~length~0#1 < 1); 5329#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5330#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5339#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5394#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5393#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5388#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5385#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5383#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5377#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5375#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5374#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5371#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5364#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5346#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5347#L370-4 main_~j~0#1 := 0; 5344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5336#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5355#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5353#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5350#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5334#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5335#L378-2 [2022-11-18 20:11:31,403 INFO L750 eck$LassoCheckResult]: Loop: 5335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5351#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5335#L378-2 [2022-11-18 20:11:31,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:31,403 INFO L85 PathProgramCache]: Analyzing trace with hash -703463951, now seen corresponding path program 11 times [2022-11-18 20:11:31,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:31,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666772734] [2022-11-18 20:11:31,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:31,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:31,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:32,063 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:32,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:32,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666772734] [2022-11-18 20:11:32,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666772734] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:32,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1579079538] [2022-11-18 20:11:32,064 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:11:32,065 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:32,065 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:32,069 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:32,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-11-18 20:11:32,199 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-18 20:11:32,199 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:11:32,201 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-18 20:11:32,203 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:32,340 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:32,425 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:32,426 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:11:32,493 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:32,494 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:11:32,502 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 20:11:33,053 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:11:33,055 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:33,058 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:11:33,058 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-18 20:11:33,065 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:33,065 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:34,491 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 72 [2022-11-18 20:11:34,505 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:11:34,505 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 1327 treesize of output 1264 [2022-11-18 20:11:34,883 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:34,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1579079538] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:34,883 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:34,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 17] total 45 [2022-11-18 20:11:34,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293077488] [2022-11-18 20:11:34,884 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:34,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:34,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:34,884 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-18 20:11:34,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:34,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016177494] [2022-11-18 20:11:34,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:34,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:34,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:34,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:34,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:34,893 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:34,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:34,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2022-11-18 20:11:34,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=225, Invalid=1845, Unknown=0, NotChecked=0, Total=2070 [2022-11-18 20:11:34,967 INFO L87 Difference]: Start difference. First operand 68 states and 89 transitions. cyclomatic complexity: 27 Second operand has 46 states, 45 states have (on average 1.9555555555555555) internal successors, (88), 46 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:38,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:38,518 INFO L93 Difference]: Finished difference Result 169 states and 214 transitions. [2022-11-18 20:11:38,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 169 states and 214 transitions. [2022-11-18 20:11:38,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15 [2022-11-18 20:11:38,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 169 states to 166 states and 211 transitions. [2022-11-18 20:11:38,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2022-11-18 20:11:38,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2022-11-18 20:11:38,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166 states and 211 transitions. [2022-11-18 20:11:38,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:38,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 166 states and 211 transitions. [2022-11-18 20:11:38,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states and 211 transitions. [2022-11-18 20:11:38,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 108. [2022-11-18 20:11:38,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.3425925925925926) internal successors, (145), 107 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:38,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 145 transitions. [2022-11-18 20:11:38,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 145 transitions. [2022-11-18 20:11:38,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-11-18 20:11:38,530 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 145 transitions. [2022-11-18 20:11:38,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-18 20:11:38,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 145 transitions. [2022-11-18 20:11:38,531 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-18 20:11:38,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:38,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:38,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:38,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:38,532 INFO L748 eck$LassoCheckResult]: Stem: 5873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5882#L367 assume !(main_~length~0#1 < 1); 5871#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5872#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5883#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5953#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5950#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5947#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5944#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 5943#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5941#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5939#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5937#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5935#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5933#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5930#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5927#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5928#L370-4 main_~j~0#1 := 0; 5889#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5880#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5881#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5962#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5961#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5898#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5902#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5900#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5878#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 5879#L378-2 [2022-11-18 20:11:38,533 INFO L750 eck$LassoCheckResult]: Loop: 5879#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5896#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 5879#L378-2 [2022-11-18 20:11:38,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:38,533 INFO L85 PathProgramCache]: Analyzing trace with hash 67235501, now seen corresponding path program 12 times [2022-11-18 20:11:38,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:38,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312159552] [2022-11-18 20:11:38,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:38,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:38,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:39,088 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:39,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:39,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312159552] [2022-11-18 20:11:39,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312159552] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:39,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2124378529] [2022-11-18 20:11:39,090 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:11:39,090 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:39,090 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:39,095 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:39,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-18 20:11:39,373 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-11-18 20:11:39,374 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:11:39,376 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-18 20:11:39,381 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:39,514 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:39,605 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:11:39,616 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:11:40,503 INFO L321 Elim1Store]: treesize reduction 46, result has 13.2 percent of original size [2022-11-18 20:11:40,503 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 49 treesize of output 21 [2022-11-18 20:11:40,507 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:40,507 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:11:41,711 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 39 [2022-11-18 20:11:41,720 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:11:41,720 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 62 treesize of output 49 [2022-11-18 20:11:41,879 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 6 proven. 47 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 20:11:41,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2124378529] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:11:41,879 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:11:41,880 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 15] total 40 [2022-11-18 20:11:41,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149415723] [2022-11-18 20:11:41,880 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:11:41,880 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:11:41,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:41,881 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-18 20:11:41,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:41,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067447739] [2022-11-18 20:11:41,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:41,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:41,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:41,884 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:11:41,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:11:41,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:11:41,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:11:41,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 20:11:41,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=1437, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 20:11:41,968 INFO L87 Difference]: Start difference. First operand 108 states and 145 transitions. cyclomatic complexity: 44 Second operand has 41 states, 40 states have (on average 2.0) internal successors, (80), 41 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:44,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:11:44,749 INFO L93 Difference]: Finished difference Result 175 states and 217 transitions. [2022-11-18 20:11:44,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 217 transitions. [2022-11-18 20:11:44,750 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-18 20:11:44,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 129 states and 166 transitions. [2022-11-18 20:11:44,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2022-11-18 20:11:44,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2022-11-18 20:11:44,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129 states and 166 transitions. [2022-11-18 20:11:44,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:11:44,753 INFO L218 hiAutomatonCegarLoop]: Abstraction has 129 states and 166 transitions. [2022-11-18 20:11:44,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states and 166 transitions. [2022-11-18 20:11:44,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 88. [2022-11-18 20:11:44,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.3181818181818181) internal successors, (116), 87 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:11:44,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 116 transitions. [2022-11-18 20:11:44,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88 states and 116 transitions. [2022-11-18 20:11:44,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2022-11-18 20:11:44,756 INFO L428 stractBuchiCegarLoop]: Abstraction has 88 states and 116 transitions. [2022-11-18 20:11:44,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-18 20:11:44,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 116 transitions. [2022-11-18 20:11:44,757 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-18 20:11:44,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:11:44,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:11:44,758 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:11:44,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:11:44,759 INFO L748 eck$LassoCheckResult]: Stem: 6466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6477#L367 assume !(main_~length~0#1 < 1); 6468#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6469#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6470#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6478#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6482#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6483#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6480#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6536#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6537#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6533#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6528#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6524#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6505#L370-4 main_~j~0#1 := 0; 6503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6501#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6499#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6490#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6496#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6492#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6493#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6471#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 6472#L378-2 [2022-11-18 20:11:44,759 INFO L750 eck$LassoCheckResult]: Loop: 6472#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6488#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6472#L378-2 [2022-11-18 20:11:44,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:11:44,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1453711780, now seen corresponding path program 13 times [2022-11-18 20:11:44,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:11:44,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472864492] [2022-11-18 20:11:44,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:11:44,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:11:44,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:45,453 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:45,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:11:45,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472864492] [2022-11-18 20:11:45,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472864492] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:11:45,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1520288496] [2022-11-18 20:11:45,454 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:11:45,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:11:45,455 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:11:45,460 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:11:45,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-18 20:11:45,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:11:45,607 INFO L263 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-18 20:11:45,609 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:11:45,783 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:11:45,864 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:45,864 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:11:45,878 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:45,878 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:11:45,932 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:11:45,932 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:11:46,156 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 20:11:46,159 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:11:46,159 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:12,020 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-18 20:12:12,025 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 56 [2022-11-18 20:12:12,105 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 62 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:12:12,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1520288496] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:12,106 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:12,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 36 [2022-11-18 20:12:12,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104000493] [2022-11-18 20:12:12,106 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:12,107 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:12,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:12,107 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-18 20:12:12,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:12,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70056516] [2022-11-18 20:12:12,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:12,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:12,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:12,112 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:12,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:12,115 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:12,185 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:12,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-18 20:12:12,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=1172, Unknown=1, NotChecked=0, Total=1332 [2022-11-18 20:12:12,186 INFO L87 Difference]: Start difference. First operand 88 states and 116 transitions. cyclomatic complexity: 35 Second operand has 37 states, 36 states have (on average 2.2222222222222223) internal successors, (80), 37 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:12,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:12,882 INFO L93 Difference]: Finished difference Result 148 states and 189 transitions. [2022-11-18 20:12:12,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148 states and 189 transitions. [2022-11-18 20:12:12,883 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2022-11-18 20:12:12,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148 states to 146 states and 187 transitions. [2022-11-18 20:12:12,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-18 20:12:12,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-18 20:12:12,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 187 transitions. [2022-11-18 20:12:12,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:12,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 187 transitions. [2022-11-18 20:12:12,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 187 transitions. [2022-11-18 20:12:12,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 100. [2022-11-18 20:12:12,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.35) internal successors, (135), 99 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:12,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 135 transitions. [2022-11-18 20:12:12,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 135 transitions. [2022-11-18 20:12:12,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 20:12:12,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 135 transitions. [2022-11-18 20:12:12,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-18 20:12:12,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 135 transitions. [2022-11-18 20:12:12,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-11-18 20:12:12,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:12,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:12,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:12,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 20:12:12,894 INFO L748 eck$LassoCheckResult]: Stem: 6944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6955#L367 assume !(main_~length~0#1 < 1); 6946#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6947#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6956#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7001#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7000#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6999#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6998#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6997#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6996#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6995#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6994#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6992#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6991#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6990#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6988#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6986#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6984#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 6979#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6980#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6976#L370-4 main_~j~0#1 := 0; 6975#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6974#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6973#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6972#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6971#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6970#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 6964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6966#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7037#L378-2 [2022-11-18 20:12:12,894 INFO L750 eck$LassoCheckResult]: Loop: 7037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7039#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7040#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7041#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7037#L378-2 [2022-11-18 20:12:12,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:12,895 INFO L85 PathProgramCache]: Analyzing trace with hash -540432926, now seen corresponding path program 14 times [2022-11-18 20:12:12,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:12,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713200843] [2022-11-18 20:12:12,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:12,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:12,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:13,668 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:13,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:13,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713200843] [2022-11-18 20:12:13,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713200843] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:13,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1563214013] [2022-11-18 20:12:13,669 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:12:13,669 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:13,669 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:13,672 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:13,673 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-18 20:12:13,771 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:12:13,771 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:13,772 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 20:12:13,774 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:13,940 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:14,083 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:14,084 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:12:14,107 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:14,107 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:12:14,165 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:14,165 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:12:14,461 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:12:14,493 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:14,493 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:14,882 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:12:14,887 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:12:14,927 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:12:14,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1563214013] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:14,927 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:14,927 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 15] total 32 [2022-11-18 20:12:14,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730290994] [2022-11-18 20:12:14,927 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:14,928 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:14,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:14,928 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-18 20:12:14,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:14,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530245412] [2022-11-18 20:12:14,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:14,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:14,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:14,933 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:14,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:14,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:15,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:15,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-11-18 20:12:15,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=924, Unknown=0, NotChecked=0, Total=1056 [2022-11-18 20:12:15,084 INFO L87 Difference]: Start difference. First operand 100 states and 135 transitions. cyclomatic complexity: 45 Second operand has 33 states, 32 states have (on average 2.1875) internal successors, (70), 33 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:15,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:15,842 INFO L93 Difference]: Finished difference Result 105 states and 135 transitions. [2022-11-18 20:12:15,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 135 transitions. [2022-11-18 20:12:15,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:15,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 103 states and 133 transitions. [2022-11-18 20:12:15,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:12:15,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:12:15,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 133 transitions. [2022-11-18 20:12:15,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:15,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-18 20:12:15,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 133 transitions. [2022-11-18 20:12:15,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 61. [2022-11-18 20:12:15,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.3114754098360655) internal successors, (80), 60 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:15,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 80 transitions. [2022-11-18 20:12:15,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61 states and 80 transitions. [2022-11-18 20:12:15,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-18 20:12:15,847 INFO L428 stractBuchiCegarLoop]: Abstraction has 61 states and 80 transitions. [2022-11-18 20:12:15,847 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-18 20:12:15,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 80 transitions. [2022-11-18 20:12:15,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:15,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:15,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:15,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:15,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:15,848 INFO L748 eck$LassoCheckResult]: Stem: 7387#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7398#L367 assume !(main_~length~0#1 < 1); 7389#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7390#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7391#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7399#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7441#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7440#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7439#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7438#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7436#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7435#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7434#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7433#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7432#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7430#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7418#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7392#L370-4 main_~j~0#1 := 0; 7393#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7417#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7396#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7397#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7416#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7411#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7408#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7407#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7394#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7395#L378-2 [2022-11-18 20:12:15,849 INFO L750 eck$LassoCheckResult]: Loop: 7395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7409#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7395#L378-2 [2022-11-18 20:12:15,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:15,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1201186386, now seen corresponding path program 15 times [2022-11-18 20:12:15,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:15,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181783411] [2022-11-18 20:12:15,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:15,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:15,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:16,114 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:16,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:16,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181783411] [2022-11-18 20:12:16,115 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181783411] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:16,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2010540202] [2022-11-18 20:12:16,115 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:12:16,115 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:16,115 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:16,119 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:16,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-18 20:12:16,308 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 20:12:16,308 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:16,309 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 20:12:16,310 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:16,506 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:16,506 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:16,674 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:16,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2010540202] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:16,675 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:16,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-18 20:12:16,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200927705] [2022-11-18 20:12:16,675 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:16,675 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:16,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:16,676 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-18 20:12:16,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:16,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914399160] [2022-11-18 20:12:16,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:16,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:16,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:16,679 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:16,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:16,683 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:16,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:16,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 20:12:16,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2022-11-18 20:12:16,748 INFO L87 Difference]: Start difference. First operand 61 states and 80 transitions. cyclomatic complexity: 24 Second operand has 23 states, 23 states have (on average 2.3043478260869565) internal successors, (53), 23 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:16,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:16,983 INFO L93 Difference]: Finished difference Result 79 states and 99 transitions. [2022-11-18 20:12:16,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 99 transitions. [2022-11-18 20:12:16,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:16,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 67 states and 87 transitions. [2022-11-18 20:12:16,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:12:16,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:12:16,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 87 transitions. [2022-11-18 20:12:16,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:16,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 87 transitions. [2022-11-18 20:12:16,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 87 transitions. [2022-11-18 20:12:16,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 63. [2022-11-18 20:12:16,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.3015873015873016) internal successors, (82), 62 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:16,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 82 transitions. [2022-11-18 20:12:16,987 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63 states and 82 transitions. [2022-11-18 20:12:16,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-18 20:12:16,988 INFO L428 stractBuchiCegarLoop]: Abstraction has 63 states and 82 transitions. [2022-11-18 20:12:16,988 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-18 20:12:16,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 82 transitions. [2022-11-18 20:12:16,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:16,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:16,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:16,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:16,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:16,990 INFO L748 eck$LassoCheckResult]: Stem: 7765#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7776#L367 assume !(main_~length~0#1 < 1); 7767#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7768#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7769#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7777#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7780#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7825#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7822#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7819#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7816#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7812#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7810#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7809#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7808#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7807#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 7805#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7784#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7770#L370-4 main_~j~0#1 := 0; 7771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7782#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7792#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7790#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7772#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 7773#L378-2 [2022-11-18 20:12:16,990 INFO L750 eck$LassoCheckResult]: Loop: 7773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7788#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 7773#L378-2 [2022-11-18 20:12:16,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:16,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1152648807, now seen corresponding path program 16 times [2022-11-18 20:12:16,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:16,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888143969] [2022-11-18 20:12:16,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:16,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:17,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:17,520 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:17,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:17,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888143969] [2022-11-18 20:12:17,524 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888143969] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:17,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1761090540] [2022-11-18 20:12:17,525 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:12:17,525 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:17,525 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:17,529 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:17,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-18 20:12:17,636 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:12:17,637 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:17,638 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-18 20:12:17,640 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:17,683 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:17,759 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:12:17,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:12:17,915 INFO L321 Elim1Store]: treesize reduction 61, result has 28.2 percent of original size [2022-11-18 20:12:17,916 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 41 [2022-11-18 20:12:18,727 INFO L321 Elim1Store]: treesize reduction 18, result has 14.3 percent of original size [2022-11-18 20:12:18,727 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 33 treesize of output 13 [2022-11-18 20:12:18,732 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:18,732 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:26,965 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 64 [2022-11-18 20:12:26,976 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:12:26,976 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 508 treesize of output 492 [2022-11-18 20:12:27,312 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:27,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1761090540] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:27,312 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:27,313 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 17] total 42 [2022-11-18 20:12:27,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9806586] [2022-11-18 20:12:27,313 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:27,313 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:27,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:27,314 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-18 20:12:27,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:27,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708630730] [2022-11-18 20:12:27,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:27,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:27,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:27,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:27,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:27,320 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:27,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:27,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-18 20:12:27,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=1616, Unknown=2, NotChecked=0, Total=1806 [2022-11-18 20:12:27,379 INFO L87 Difference]: Start difference. First operand 63 states and 82 transitions. cyclomatic complexity: 24 Second operand has 43 states, 42 states have (on average 2.0238095238095237) internal successors, (85), 43 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:28,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:28,796 INFO L93 Difference]: Finished difference Result 122 states and 149 transitions. [2022-11-18 20:12:28,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 149 transitions. [2022-11-18 20:12:28,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:28,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 120 states and 147 transitions. [2022-11-18 20:12:28,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-18 20:12:28,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-18 20:12:28,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 147 transitions. [2022-11-18 20:12:28,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:28,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 147 transitions. [2022-11-18 20:12:28,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 147 transitions. [2022-11-18 20:12:28,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 70. [2022-11-18 20:12:28,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.3285714285714285) internal successors, (93), 69 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:28,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 93 transitions. [2022-11-18 20:12:28,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 70 states and 93 transitions. [2022-11-18 20:12:28,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-18 20:12:28,807 INFO L428 stractBuchiCegarLoop]: Abstraction has 70 states and 93 transitions. [2022-11-18 20:12:28,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-18 20:12:28,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 93 transitions. [2022-11-18 20:12:28,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:28,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:28,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:28,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:28,809 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:28,809 INFO L748 eck$LassoCheckResult]: Stem: 8214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8225#L367 assume !(main_~length~0#1 < 1); 8216#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8217#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8218#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8226#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8228#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8282#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8280#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8278#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8277#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8275#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8264#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8261#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8260#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8248#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8247#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8245#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8244#L370-4 main_~j~0#1 := 0; 8243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8229#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8240#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8238#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8237#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8236#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8235#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8219#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8220#L378-2 [2022-11-18 20:12:28,809 INFO L750 eck$LassoCheckResult]: Loop: 8220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8234#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8220#L378-2 [2022-11-18 20:12:28,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:28,809 INFO L85 PathProgramCache]: Analyzing trace with hash 575418155, now seen corresponding path program 17 times [2022-11-18 20:12:28,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:28,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425506112] [2022-11-18 20:12:28,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:28,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:28,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:29,564 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:29,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:29,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425506112] [2022-11-18 20:12:29,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425506112] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:29,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1448777839] [2022-11-18 20:12:29,565 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:12:29,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:29,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:29,568 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:29,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-18 20:12:29,723 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-18 20:12:29,723 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:29,725 INFO L263 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-18 20:12:29,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:29,943 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:30,083 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:30,084 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:12:30,094 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:30,095 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:12:30,535 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:12:30,537 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:12:30,538 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-18 20:12:30,564 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:30,564 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:30,949 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:12:30,952 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:12:31,003 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:31,003 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1448777839] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:31,003 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:31,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 18, 17] total 36 [2022-11-18 20:12:31,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7080809] [2022-11-18 20:12:31,004 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:31,004 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:31,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:31,005 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-18 20:12:31,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:31,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179478060] [2022-11-18 20:12:31,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:31,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:31,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:31,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:31,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:31,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:31,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:31,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-18 20:12:31,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=1191, Unknown=0, NotChecked=0, Total=1332 [2022-11-18 20:12:31,087 INFO L87 Difference]: Start difference. First operand 70 states and 93 transitions. cyclomatic complexity: 29 Second operand has 37 states, 36 states have (on average 2.0) internal successors, (72), 37 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:31,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:31,888 INFO L93 Difference]: Finished difference Result 80 states and 103 transitions. [2022-11-18 20:12:31,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 103 transitions. [2022-11-18 20:12:31,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:31,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 79 states and 102 transitions. [2022-11-18 20:12:31,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:12:31,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:12:31,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 102 transitions. [2022-11-18 20:12:31,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:31,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79 states and 102 transitions. [2022-11-18 20:12:31,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 102 transitions. [2022-11-18 20:12:31,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 42. [2022-11-18 20:12:31,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 41 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:31,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 52 transitions. [2022-11-18 20:12:31,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 52 transitions. [2022-11-18 20:12:31,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 20:12:31,894 INFO L428 stractBuchiCegarLoop]: Abstraction has 42 states and 52 transitions. [2022-11-18 20:12:31,894 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-18 20:12:31,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 52 transitions. [2022-11-18 20:12:31,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:31,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:31,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:31,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:31,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:31,896 INFO L748 eck$LassoCheckResult]: Stem: 8620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8631#L367 assume !(main_~length~0#1 < 1); 8622#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8623#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8624#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8632#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8660#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8658#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8657#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8656#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8655#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8654#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8653#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8652#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8651#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8637#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8633#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8634#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 8648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8641#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8629#L370-4 main_~j~0#1 := 0; 8630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8627#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8635#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8647#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8646#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8645#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8644#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8643#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8639#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8638#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8625#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 8626#L378-2 [2022-11-18 20:12:31,896 INFO L750 eck$LassoCheckResult]: Loop: 8626#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8640#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 8626#L378-2 [2022-11-18 20:12:31,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:31,896 INFO L85 PathProgramCache]: Analyzing trace with hash -187204696, now seen corresponding path program 18 times [2022-11-18 20:12:31,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:31,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149128741] [2022-11-18 20:12:31,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:31,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:31,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:32,638 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:32,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:32,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149128741] [2022-11-18 20:12:32,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149128741] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:32,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1874726160] [2022-11-18 20:12:32,639 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:12:32,639 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:32,639 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:32,644 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:32,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-18 20:12:32,863 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-18 20:12:32,863 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:32,864 INFO L263 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 20:12:32,865 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:33,052 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:33,890 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 20:12:33,891 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-18 20:12:33,918 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:33,919 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:34,919 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-18 20:12:34,924 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-18 20:12:35,101 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:35,101 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1874726160] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:35,101 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:35,101 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2022-11-18 20:12:35,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228398592] [2022-11-18 20:12:35,102 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:35,102 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:35,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:35,103 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-18 20:12:35,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:35,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183282849] [2022-11-18 20:12:35,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:35,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:35,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:35,106 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:35,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:35,109 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:35,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:35,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-18 20:12:35,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=234, Invalid=1658, Unknown=0, NotChecked=0, Total=1892 [2022-11-18 20:12:35,166 INFO L87 Difference]: Start difference. First operand 42 states and 52 transitions. cyclomatic complexity: 14 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:36,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:36,963 INFO L93 Difference]: Finished difference Result 112 states and 134 transitions. [2022-11-18 20:12:36,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 134 transitions. [2022-11-18 20:12:36,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:36,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 96 states and 116 transitions. [2022-11-18 20:12:36,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:12:36,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:12:36,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 116 transitions. [2022-11-18 20:12:36,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:36,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 96 states and 116 transitions. [2022-11-18 20:12:36,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 116 transitions. [2022-11-18 20:12:36,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 63. [2022-11-18 20:12:36,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.253968253968254) internal successors, (79), 62 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:36,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 79 transitions. [2022-11-18 20:12:36,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63 states and 79 transitions. [2022-11-18 20:12:36,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-18 20:12:36,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 63 states and 79 transitions. [2022-11-18 20:12:36,970 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-18 20:12:36,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 79 transitions. [2022-11-18 20:12:36,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:36,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:36,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:36,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:36,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:36,972 INFO L748 eck$LassoCheckResult]: Stem: 9092#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9103#L367 assume !(main_~length~0#1 < 1); 9094#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9095#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9096#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9104#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9144#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9109#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9110#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9105#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9106#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9152#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9131#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9151#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9147#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9124#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9123#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9125#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9114#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9115#L370-4 main_~j~0#1 := 0; 9107#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9108#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9150#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9149#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9148#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9146#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9120#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9113#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9112#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9097#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9098#L378-2 [2022-11-18 20:12:36,972 INFO L750 eck$LassoCheckResult]: Loop: 9098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9111#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9098#L378-2 [2022-11-18 20:12:36,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:36,972 INFO L85 PathProgramCache]: Analyzing trace with hash -888804570, now seen corresponding path program 19 times [2022-11-18 20:12:36,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:36,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527525897] [2022-11-18 20:12:36,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:36,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:37,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:37,668 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:37,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:37,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527525897] [2022-11-18 20:12:37,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527525897] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:37,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [446984474] [2022-11-18 20:12:37,669 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:12:37,669 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:37,669 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:37,672 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:37,673 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-18 20:12:37,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:37,788 INFO L263 TraceCheckSpWp]: Trace formula consists of 208 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 20:12:37,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:38,094 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:12:38,584 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:12:38,614 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:38,614 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:38,799 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:12:38,802 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:12:38,867 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:38,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [446984474] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:38,867 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:38,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 16] total 34 [2022-11-18 20:12:38,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790061380] [2022-11-18 20:12:38,868 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:38,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:38,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:38,868 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-18 20:12:38,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:38,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459405933] [2022-11-18 20:12:38,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:38,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:38,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:38,873 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:38,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:38,876 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:38,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:38,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 20:12:38,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1067, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 20:12:38,936 INFO L87 Difference]: Start difference. First operand 63 states and 79 transitions. cyclomatic complexity: 20 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:40,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:40,428 INFO L93 Difference]: Finished difference Result 106 states and 130 transitions. [2022-11-18 20:12:40,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 130 transitions. [2022-11-18 20:12:40,429 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:12:40,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 105 states and 129 transitions. [2022-11-18 20:12:40,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:12:40,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:12:40,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 129 transitions. [2022-11-18 20:12:40,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:40,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105 states and 129 transitions. [2022-11-18 20:12:40,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 129 transitions. [2022-11-18 20:12:40,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 76. [2022-11-18 20:12:40,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.2763157894736843) internal successors, (97), 75 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:40,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 97 transitions. [2022-11-18 20:12:40,433 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-18 20:12:40,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-18 20:12:40,439 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-18 20:12:40,439 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-18 20:12:40,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 97 transitions. [2022-11-18 20:12:40,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:40,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:40,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:40,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:40,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:40,441 INFO L748 eck$LassoCheckResult]: Stem: 9523#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9534#L367 assume !(main_~length~0#1 < 1); 9525#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9526#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9527#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9535#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9593#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9587#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9583#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9581#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9574#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9572#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9567#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9543#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9532#L370-4 main_~j~0#1 := 0; 9533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9530#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9539#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9553#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9551#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9549#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9548#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9547#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9528#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9529#L378-2 [2022-11-18 20:12:40,441 INFO L750 eck$LassoCheckResult]: Loop: 9529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9545#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9529#L378-2 [2022-11-18 20:12:40,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:40,441 INFO L85 PathProgramCache]: Analyzing trace with hash 557299561, now seen corresponding path program 20 times [2022-11-18 20:12:40,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:40,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049960817] [2022-11-18 20:12:40,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:40,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:40,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:40,781 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:40,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:40,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049960817] [2022-11-18 20:12:40,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049960817] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:40,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1080328533] [2022-11-18 20:12:40,781 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:12:40,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:40,782 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:40,783 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:40,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-18 20:12:40,918 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:12:40,918 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:40,919 INFO L263 TraceCheckSpWp]: Trace formula consists of 220 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-18 20:12:40,920 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:41,218 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:41,218 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:41,426 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:41,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1080328533] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:41,427 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:41,427 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 26 [2022-11-18 20:12:41,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057563017] [2022-11-18 20:12:41,427 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:41,427 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:41,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:41,428 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-18 20:12:41,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:41,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492728921] [2022-11-18 20:12:41,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:41,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:41,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:41,431 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:41,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:41,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:41,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:41,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-18 20:12:41,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=493, Unknown=0, NotChecked=0, Total=650 [2022-11-18 20:12:41,494 INFO L87 Difference]: Start difference. First operand 76 states and 97 transitions. cyclomatic complexity: 26 Second operand has 26 states, 26 states have (on average 2.3076923076923075) internal successors, (60), 26 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:41,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:41,786 INFO L93 Difference]: Finished difference Result 96 states and 118 transitions. [2022-11-18 20:12:41,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96 states and 118 transitions. [2022-11-18 20:12:41,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:41,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96 states to 82 states and 104 transitions. [2022-11-18 20:12:41,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:12:41,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:12:41,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 104 transitions. [2022-11-18 20:12:41,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:41,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-18 20:12:41,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 104 transitions. [2022-11-18 20:12:41,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 58. [2022-11-18 20:12:41,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2586206896551724) internal successors, (73), 57 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:41,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 73 transitions. [2022-11-18 20:12:41,790 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 73 transitions. [2022-11-18 20:12:41,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 20:12:41,791 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 73 transitions. [2022-11-18 20:12:41,791 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-18 20:12:41,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 73 transitions. [2022-11-18 20:12:41,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:41,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:41,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:41,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:41,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:41,793 INFO L748 eck$LassoCheckResult]: Stem: 9968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9979#L367 assume !(main_~length~0#1 < 1); 9970#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9971#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9972#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9980#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 9983#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9981#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9982#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10025#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10024#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10023#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10021#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10020#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10018#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10015#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10013#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10012#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10010#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10001#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9997#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9985#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9973#L370-4 main_~j~0#1 := 0; 9974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9984#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9995#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9993#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9992#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9991#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9990#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9988#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9975#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 9976#L378-2 [2022-11-18 20:12:41,793 INFO L750 eck$LassoCheckResult]: Loop: 9976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9989#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 9976#L378-2 [2022-11-18 20:12:41,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:41,793 INFO L85 PathProgramCache]: Analyzing trace with hash -50400780, now seen corresponding path program 21 times [2022-11-18 20:12:41,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:41,794 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331176350] [2022-11-18 20:12:41,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:41,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:41,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:42,736 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:42,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:42,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331176350] [2022-11-18 20:12:42,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331176350] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:42,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1860844346] [2022-11-18 20:12:42,737 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:12:42,737 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:42,737 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:42,744 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:42,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-18 20:12:43,325 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-18 20:12:43,325 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:43,327 INFO L263 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-18 20:12:43,329 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:43,390 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:43,549 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:12:43,549 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:12:43,588 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:12:43,588 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:12:44,391 INFO L321 Elim1Store]: treesize reduction 30, result has 9.1 percent of original size [2022-11-18 20:12:44,391 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 17 [2022-11-18 20:12:44,395 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:44,396 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:44,670 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:12:44,675 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:12:44,741 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 98 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:12:44,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1860844346] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:44,742 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:44,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 17] total 30 [2022-11-18 20:12:44,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111219573] [2022-11-18 20:12:44,742 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:44,743 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:44,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:44,743 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-18 20:12:44,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:44,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557958460] [2022-11-18 20:12:44,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:44,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:44,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:44,746 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:44,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:44,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:44,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:44,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-11-18 20:12:44,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=814, Unknown=0, NotChecked=0, Total=930 [2022-11-18 20:12:44,823 INFO L87 Difference]: Start difference. First operand 58 states and 73 transitions. cyclomatic complexity: 20 Second operand has 31 states, 30 states have (on average 2.2333333333333334) internal successors, (67), 31 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:46,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:46,713 INFO L93 Difference]: Finished difference Result 109 states and 131 transitions. [2022-11-18 20:12:46,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 131 transitions. [2022-11-18 20:12:46,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:46,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 108 states and 129 transitions. [2022-11-18 20:12:46,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 20:12:46,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 20:12:46,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 129 transitions. [2022-11-18 20:12:46,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:46,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108 states and 129 transitions. [2022-11-18 20:12:46,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 129 transitions. [2022-11-18 20:12:46,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 65. [2022-11-18 20:12:46,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.3076923076923077) internal successors, (85), 64 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:46,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 85 transitions. [2022-11-18 20:12:46,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 65 states and 85 transitions. [2022-11-18 20:12:46,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 20:12:46,719 INFO L428 stractBuchiCegarLoop]: Abstraction has 65 states and 85 transitions. [2022-11-18 20:12:46,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-18 20:12:46,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 85 transitions. [2022-11-18 20:12:46,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:46,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:46,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:46,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:46,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:46,721 INFO L748 eck$LassoCheckResult]: Stem: 10413#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10424#L367 assume !(main_~length~0#1 < 1); 10415#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10416#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10425#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10428#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10426#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10427#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10470#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10469#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10468#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10467#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10466#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10465#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10464#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10463#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10461#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10462#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10477#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10476#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10474#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10473#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10418#L370-4 main_~j~0#1 := 0; 10419#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10422#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10423#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10429#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10439#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10438#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10437#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10436#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10435#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10434#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10433#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10431#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10420#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10421#L378-2 [2022-11-18 20:12:46,721 INFO L750 eck$LassoCheckResult]: Loop: 10421#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10432#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10421#L378-2 [2022-11-18 20:12:46,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:46,721 INFO L85 PathProgramCache]: Analyzing trace with hash 687610867, now seen corresponding path program 22 times [2022-11-18 20:12:46,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:46,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325078776] [2022-11-18 20:12:46,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:46,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:46,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:47,790 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:47,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:47,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325078776] [2022-11-18 20:12:47,791 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325078776] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:47,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [240626721] [2022-11-18 20:12:47,791 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:12:47,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:47,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:47,797 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:47,804 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-18 20:12:47,933 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:12:47,933 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:47,935 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-18 20:12:47,936 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:48,028 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:48,540 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:12:48,543 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:48,543 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:48,773 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:12:48,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:12:48,862 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:48,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [240626721] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:48,863 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:48,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18] total 28 [2022-11-18 20:12:48,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265124875] [2022-11-18 20:12:48,863 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:48,863 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:48,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:48,864 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-18 20:12:48,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:48,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911283089] [2022-11-18 20:12:48,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:48,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:48,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:48,867 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:48,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:48,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:48,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:48,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-18 20:12:48,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=730, Unknown=0, NotChecked=0, Total=812 [2022-11-18 20:12:48,932 INFO L87 Difference]: Start difference. First operand 65 states and 85 transitions. cyclomatic complexity: 26 Second operand has 29 states, 28 states have (on average 2.2142857142857144) internal successors, (62), 29 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:49,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:12:49,891 INFO L93 Difference]: Finished difference Result 86 states and 108 transitions. [2022-11-18 20:12:49,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 108 transitions. [2022-11-18 20:12:49,892 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:12:49,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 85 states and 107 transitions. [2022-11-18 20:12:49,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:12:49,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:12:49,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 107 transitions. [2022-11-18 20:12:49,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:12:49,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85 states and 107 transitions. [2022-11-18 20:12:49,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 107 transitions. [2022-11-18 20:12:49,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 69. [2022-11-18 20:12:49,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.289855072463768) internal successors, (89), 68 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:12:49,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 89 transitions. [2022-11-18 20:12:49,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69 states and 89 transitions. [2022-11-18 20:12:49,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 20:12:49,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 69 states and 89 transitions. [2022-11-18 20:12:49,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-18 20:12:49,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 89 transitions. [2022-11-18 20:12:49,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:12:49,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:12:49,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:12:49,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:12:49,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:12:49,899 INFO L748 eck$LassoCheckResult]: Stem: 10846#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10857#L367 assume !(main_~length~0#1 < 1); 10848#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10849#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10850#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10858#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10914#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10859#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10860#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10861#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10863#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10913#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10912#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10910#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10908#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10905#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10903#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10900#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 10897#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10895#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10893#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10864#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10851#L370-4 main_~j~0#1 := 0; 10852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10855#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10876#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10875#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10874#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10873#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10872#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10871#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10870#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10869#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10867#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10853#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 10854#L378-2 [2022-11-18 20:12:49,899 INFO L750 eck$LassoCheckResult]: Loop: 10854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10868#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 10854#L378-2 [2022-11-18 20:12:49,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:49,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1190509897, now seen corresponding path program 23 times [2022-11-18 20:12:49,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:49,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060364060] [2022-11-18 20:12:49,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:49,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:49,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:12:50,672 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:50,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:12:50,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060364060] [2022-11-18 20:12:50,673 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1060364060] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:12:50,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [803449256] [2022-11-18 20:12:50,673 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:12:50,673 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:12:50,673 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:12:50,674 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:12:50,677 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-18 20:12:50,894 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-18 20:12:50,894 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:12:50,897 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-18 20:12:50,899 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:12:51,122 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:12:51,216 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:12:51,277 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:12:51,291 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-18 20:12:52,103 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:12:52,104 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:12:52,107 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:12:52,107 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 13 [2022-11-18 20:12:52,111 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:52,111 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:12:53,847 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 72 [2022-11-18 20:12:53,859 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:12:53,860 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 1532 treesize of output 1462 [2022-11-18 20:12:54,482 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:12:54,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [803449256] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:12:54,482 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:12:54,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 21] total 57 [2022-11-18 20:12:54,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169955406] [2022-11-18 20:12:54,483 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:12:54,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:12:54,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:12:54,484 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-18 20:12:54,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:12:54,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620713] [2022-11-18 20:12:54,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:12:54,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:12:54,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:54,488 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:12:54,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:12:54,491 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:12:54,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:12:54,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2022-11-18 20:12:54,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=3023, Unknown=0, NotChecked=0, Total=3306 [2022-11-18 20:12:54,580 INFO L87 Difference]: Start difference. First operand 69 states and 89 transitions. cyclomatic complexity: 26 Second operand has 58 states, 57 states have (on average 2.0701754385964914) internal successors, (118), 58 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:00,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:13:00,342 INFO L93 Difference]: Finished difference Result 188 states and 227 transitions. [2022-11-18 20:13:00,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 188 states and 227 transitions. [2022-11-18 20:13:00,343 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 10 [2022-11-18 20:13:00,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 188 states to 184 states and 223 transitions. [2022-11-18 20:13:00,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-18 20:13:00,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-18 20:13:00,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 223 transitions. [2022-11-18 20:13:00,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:13:00,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 223 transitions. [2022-11-18 20:13:00,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 223 transitions. [2022-11-18 20:13:00,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 94. [2022-11-18 20:13:00,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.297872340425532) internal successors, (122), 93 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:00,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 122 transitions. [2022-11-18 20:13:00,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 122 transitions. [2022-11-18 20:13:00,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-18 20:13:00,350 INFO L428 stractBuchiCegarLoop]: Abstraction has 94 states and 122 transitions. [2022-11-18 20:13:00,350 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-18 20:13:00,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 122 transitions. [2022-11-18 20:13:00,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:13:00,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:13:00,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:13:00,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:13:00,352 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:13:00,352 INFO L748 eck$LassoCheckResult]: Stem: 11493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11504#L367 assume !(main_~length~0#1 < 1); 11495#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11496#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11505#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11544#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11543#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11542#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11541#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11539#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11536#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11534#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11532#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 11533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11524#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11507#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11508#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11516#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11586#L370-4 main_~j~0#1 := 0; 11585#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11575#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11574#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11573#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11571#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11518#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11520#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11500#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 11501#L378-2 [2022-11-18 20:13:00,352 INFO L750 eck$LassoCheckResult]: Loop: 11501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11519#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 11501#L378-2 [2022-11-18 20:13:00,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:13:00,353 INFO L85 PathProgramCache]: Analyzing trace with hash -1747225229, now seen corresponding path program 24 times [2022-11-18 20:13:00,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:13:00,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568004750] [2022-11-18 20:13:00,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:13:00,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:13:00,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:13:01,123 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:01,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:13:01,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568004750] [2022-11-18 20:13:01,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568004750] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:13:01,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [326464719] [2022-11-18 20:13:01,124 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:13:01,124 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:13:01,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:13:01,128 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:13:01,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-18 20:13:01,494 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2022-11-18 20:13:01,494 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:13:01,496 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 20:13:01,497 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:13:01,733 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:13:02,564 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 20:13:02,564 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-18 20:13:02,568 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:02,568 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:13:03,619 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-18 20:13:03,624 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 22 [2022-11-18 20:13:03,859 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:03,859 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [326464719] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:13:03,859 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:13:03,859 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 46 [2022-11-18 20:13:03,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713096109] [2022-11-18 20:13:03,859 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:13:03,860 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:13:03,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:13:03,860 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-18 20:13:03,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:13:03,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133679435] [2022-11-18 20:13:03,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:13:03,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:13:03,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:13:03,864 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:13:03,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:13:03,868 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:13:03,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:13:03,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-18 20:13:03,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=1901, Unknown=0, NotChecked=0, Total=2162 [2022-11-18 20:13:03,936 INFO L87 Difference]: Start difference. First operand 94 states and 122 transitions. cyclomatic complexity: 34 Second operand has 47 states, 46 states have (on average 2.108695652173913) internal successors, (97), 47 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:05,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:13:05,430 INFO L93 Difference]: Finished difference Result 139 states and 168 transitions. [2022-11-18 20:13:05,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 168 transitions. [2022-11-18 20:13:05,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:13:05,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 106 states and 133 transitions. [2022-11-18 20:13:05,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:13:05,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:13:05,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 133 transitions. [2022-11-18 20:13:05,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:13:05,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 133 transitions. [2022-11-18 20:13:05,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 133 transitions. [2022-11-18 20:13:05,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 96. [2022-11-18 20:13:05,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96 states, 96 states have (on average 1.28125) internal successors, (123), 95 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:05,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 123 transitions. [2022-11-18 20:13:05,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96 states and 123 transitions. [2022-11-18 20:13:05,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-18 20:13:05,437 INFO L428 stractBuchiCegarLoop]: Abstraction has 96 states and 123 transitions. [2022-11-18 20:13:05,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-18 20:13:05,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96 states and 123 transitions. [2022-11-18 20:13:05,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:13:05,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:13:05,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:13:05,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:13:05,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:13:05,440 INFO L748 eck$LassoCheckResult]: Stem: 12074#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12085#L367 assume !(main_~length~0#1 < 1); 12076#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12077#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12078#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12086#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12090#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12088#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12168#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12167#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12166#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12165#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12164#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12163#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12162#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12159#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12152#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12153#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12156#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12138#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12127#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12119#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12117#L370-4 main_~j~0#1 := 0; 12113#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12111#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12109#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12107#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12105#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12103#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12092#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12098#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12094#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12079#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12080#L378-2 [2022-11-18 20:13:05,440 INFO L750 eck$LassoCheckResult]: Loop: 12080#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12093#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12080#L378-2 [2022-11-18 20:13:05,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:13:05,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1688826200, now seen corresponding path program 25 times [2022-11-18 20:13:05,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:13:05,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335185865] [2022-11-18 20:13:05,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:13:05,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:13:05,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:13:06,367 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:06,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:13:06,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335185865] [2022-11-18 20:13:06,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335185865] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:13:06,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [793557551] [2022-11-18 20:13:06,368 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:13:06,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:13:06,368 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:13:06,375 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:13:06,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-18 20:13:06,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:13:06,541 INFO L263 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-18 20:13:06,544 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:13:06,549 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 9 [2022-11-18 20:13:06,633 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-11-18 20:13:06,856 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:13:06,981 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:13:06,993 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:13:07,114 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,118 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,120 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:13:07,121 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:13:07,145 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,147 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,150 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:13:07,150 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:13:07,230 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,232 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:13:07,234 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:13:07,234 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:13:07,787 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:13:07,788 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-18 20:13:07,790 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:07,791 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:13:55,540 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 78 [2022-11-18 20:13:55,566 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:13:55,567 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 2660 treesize of output 2624 [2022-11-18 20:13:56,566 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:56,567 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [793557551] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:13:56,567 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:13:56,567 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21, 22] total 58 [2022-11-18 20:13:56,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665862863] [2022-11-18 20:13:56,567 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:13:56,568 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:13:56,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:13:56,568 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-18 20:13:56,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:13:56,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386959547] [2022-11-18 20:13:56,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:13:56,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:13:56,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:13:56,571 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:13:56,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:13:56,573 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:13:56,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:13:56,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-18 20:13:56,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=3118, Unknown=3, NotChecked=0, Total=3422 [2022-11-18 20:13:56,636 INFO L87 Difference]: Start difference. First operand 96 states and 123 transitions. cyclomatic complexity: 33 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:58,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:13:58,526 INFO L93 Difference]: Finished difference Result 211 states and 258 transitions. [2022-11-18 20:13:58,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211 states and 258 transitions. [2022-11-18 20:13:58,527 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 20:13:58,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211 states to 209 states and 256 transitions. [2022-11-18 20:13:58,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2022-11-18 20:13:58,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2022-11-18 20:13:58,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209 states and 256 transitions. [2022-11-18 20:13:58,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:13:58,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 209 states and 256 transitions. [2022-11-18 20:13:58,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states and 256 transitions. [2022-11-18 20:13:58,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 102. [2022-11-18 20:13:58,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.303921568627451) internal successors, (133), 101 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:13:58,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 133 transitions. [2022-11-18 20:13:58,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102 states and 133 transitions. [2022-11-18 20:13:58,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-18 20:13:58,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 102 states and 133 transitions. [2022-11-18 20:13:58,537 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-18 20:13:58,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 133 transitions. [2022-11-18 20:13:58,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:13:58,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:13:58,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:13:58,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:13:58,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:13:58,539 INFO L748 eck$LassoCheckResult]: Stem: 12735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12746#L367 assume !(main_~length~0#1 < 1); 12737#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12738#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12739#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12747#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12802#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12801#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12800#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12799#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12798#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12797#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12795#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12794#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12793#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12791#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12790#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12789#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12788#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12787#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12786#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12784#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12783#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12782#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12780#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 12775#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12776#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12772#L370-4 main_~j~0#1 := 0; 12771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12770#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12768#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12766#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12764#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12762#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12756#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12742#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 12743#L378-2 [2022-11-18 20:13:58,539 INFO L750 eck$LassoCheckResult]: Loop: 12743#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12758#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 12743#L378-2 [2022-11-18 20:13:58,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:13:58,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1469971482, now seen corresponding path program 26 times [2022-11-18 20:13:58,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:13:58,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740596209] [2022-11-18 20:13:58,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:13:58,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:13:58,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:13:59,540 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:13:59,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:13:59,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740596209] [2022-11-18 20:13:59,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740596209] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:13:59,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [753588122] [2022-11-18 20:13:59,540 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:13:59,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:13:59,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:13:59,543 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:13:59,549 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-18 20:13:59,689 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:13:59,689 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:13:59,691 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-18 20:13:59,693 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:13:59,971 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:14:00,125 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:14:00,126 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:14:00,139 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:14:00,139 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:14:00,211 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:14:00,212 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:14:00,704 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:14:00,736 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:00,736 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:01,180 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:14:01,183 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:14:01,268 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 120 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:14:01,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [753588122] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:01,269 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:01,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 40 [2022-11-18 20:14:01,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792547071] [2022-11-18 20:14:01,269 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:01,269 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:01,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:01,270 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-18 20:14:01,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:01,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617293631] [2022-11-18 20:14:01,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:01,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:01,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:01,274 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:01,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:01,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:01,342 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:01,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 20:14:01,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=1480, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 20:14:01,343 INFO L87 Difference]: Start difference. First operand 102 states and 133 transitions. cyclomatic complexity: 39 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:02,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:02,577 INFO L93 Difference]: Finished difference Result 126 states and 157 transitions. [2022-11-18 20:14:02,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 157 transitions. [2022-11-18 20:14:02,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:02,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 125 states and 155 transitions. [2022-11-18 20:14:02,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:14:02,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:14:02,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125 states and 155 transitions. [2022-11-18 20:14:02,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:02,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125 states and 155 transitions. [2022-11-18 20:14:02,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states and 155 transitions. [2022-11-18 20:14:02,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 74. [2022-11-18 20:14:02,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2837837837837838) internal successors, (95), 73 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:02,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 95 transitions. [2022-11-18 20:14:02,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 95 transitions. [2022-11-18 20:14:02,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-18 20:14:02,584 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 95 transitions. [2022-11-18 20:14:02,584 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-18 20:14:02,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 95 transitions. [2022-11-18 20:14:02,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:02,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:02,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:02,585 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:02,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:02,586 INFO L748 eck$LassoCheckResult]: Stem: 13273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13284#L367 assume !(main_~length~0#1 < 1); 13275#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13276#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13285#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13343#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13342#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13341#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13340#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13339#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13338#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13336#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13335#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13333#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13332#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13330#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13328#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13325#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13293#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13278#L370-4 main_~j~0#1 := 0; 13279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13307#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13282#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13306#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13305#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13304#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13302#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13299#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13298#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13297#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13295#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13280#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 13281#L378-2 [2022-11-18 20:14:02,586 INFO L750 eck$LassoCheckResult]: Loop: 13281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13296#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13281#L378-2 [2022-11-18 20:14:02,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:02,587 INFO L85 PathProgramCache]: Analyzing trace with hash -630920970, now seen corresponding path program 27 times [2022-11-18 20:14:02,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:02,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673745550] [2022-11-18 20:14:02,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:02,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:02,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:03,020 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:03,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:03,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673745550] [2022-11-18 20:14:03,021 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673745550] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:03,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1909610811] [2022-11-18 20:14:03,021 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:14:03,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:03,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:03,026 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:03,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-18 20:14:03,582 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-18 20:14:03,582 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:03,584 INFO L263 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 20:14:03,585 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:03,888 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:03,888 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:04,118 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:04,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1909610811] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:04,118 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:04,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 29 [2022-11-18 20:14:04,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316219041] [2022-11-18 20:14:04,119 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:04,119 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:04,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:04,119 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-18 20:14:04,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:04,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539652752] [2022-11-18 20:14:04,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:04,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:04,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:04,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:04,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:04,127 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:04,188 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:04,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-18 20:14:04,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=618, Unknown=0, NotChecked=0, Total=812 [2022-11-18 20:14:04,188 INFO L87 Difference]: Start difference. First operand 74 states and 95 transitions. cyclomatic complexity: 26 Second operand has 29 states, 29 states have (on average 2.310344827586207) internal successors, (67), 29 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:04,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:04,493 INFO L93 Difference]: Finished difference Result 101 states and 125 transitions. [2022-11-18 20:14:04,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 125 transitions. [2022-11-18 20:14:04,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:04,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 85 states and 109 transitions. [2022-11-18 20:14:04,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:14:04,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:14:04,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 109 transitions. [2022-11-18 20:14:04,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:04,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 85 states and 109 transitions. [2022-11-18 20:14:04,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 109 transitions. [2022-11-18 20:14:04,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 76. [2022-11-18 20:14:04,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.2763157894736843) internal successors, (97), 75 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:04,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 97 transitions. [2022-11-18 20:14:04,497 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-18 20:14:04,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-18 20:14:04,498 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 97 transitions. [2022-11-18 20:14:04,498 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-18 20:14:04,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 97 transitions. [2022-11-18 20:14:04,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:04,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:04,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:04,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:04,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:04,500 INFO L748 eck$LassoCheckResult]: Stem: 13756#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13757#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13767#L367 assume !(main_~length~0#1 < 1); 13758#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13759#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13760#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13768#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13819#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13818#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13817#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13816#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13815#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13814#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13812#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13811#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13810#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13809#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13807#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13808#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13830#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13828#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13771#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13776#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13795#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 13793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13777#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13761#L370-4 main_~j~0#1 := 0; 13762#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13775#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13790#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13789#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13788#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13787#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13785#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13784#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13783#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13782#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13780#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13763#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 13764#L378-2 [2022-11-18 20:14:04,500 INFO L750 eck$LassoCheckResult]: Loop: 13764#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13781#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 13764#L378-2 [2022-11-18 20:14:04,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:04,500 INFO L85 PathProgramCache]: Analyzing trace with hash 535659115, now seen corresponding path program 28 times [2022-11-18 20:14:04,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:04,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233639046] [2022-11-18 20:14:04,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:04,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:04,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:05,258 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:05,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:05,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233639046] [2022-11-18 20:14:05,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233639046] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:05,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2081690470] [2022-11-18 20:14:05,259 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:14:05,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:05,260 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:05,262 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:05,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-18 20:14:05,402 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:14:05,402 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:05,404 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-18 20:14:05,407 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:05,470 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:14:05,557 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:14:05,569 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:14:05,725 INFO L321 Elim1Store]: treesize reduction 61, result has 28.2 percent of original size [2022-11-18 20:14:05,725 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 41 [2022-11-18 20:14:06,532 INFO L321 Elim1Store]: treesize reduction 18, result has 14.3 percent of original size [2022-11-18 20:14:06,533 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 33 treesize of output 13 [2022-11-18 20:14:06,536 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:06,536 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:22,890 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 64 [2022-11-18 20:14:22,903 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:14:22,904 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 508 treesize of output 492 [2022-11-18 20:14:23,575 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:23,575 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2081690470] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:23,575 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:23,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 21, 21] total 52 [2022-11-18 20:14:23,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672182089] [2022-11-18 20:14:23,576 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:23,576 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:23,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:23,577 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-18 20:14:23,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:23,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653658800] [2022-11-18 20:14:23,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:23,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:23,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:23,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:23,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:23,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:23,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:23,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-18 20:14:23,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=228, Invalid=2523, Unknown=5, NotChecked=0, Total=2756 [2022-11-18 20:14:23,676 INFO L87 Difference]: Start difference. First operand 76 states and 97 transitions. cyclomatic complexity: 26 Second operand has 53 states, 52 states have (on average 2.0961538461538463) internal successors, (109), 53 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:25,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:25,796 INFO L93 Difference]: Finished difference Result 153 states and 182 transitions. [2022-11-18 20:14:25,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153 states and 182 transitions. [2022-11-18 20:14:25,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:25,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153 states to 151 states and 180 transitions. [2022-11-18 20:14:25,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-18 20:14:25,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-18 20:14:25,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 180 transitions. [2022-11-18 20:14:25,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:25,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151 states and 180 transitions. [2022-11-18 20:14:25,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 180 transitions. [2022-11-18 20:14:25,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2022-11-18 20:14:25,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.3068181818181819) internal successors, (115), 87 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:25,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 115 transitions. [2022-11-18 20:14:25,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 88 states and 115 transitions. [2022-11-18 20:14:25,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-11-18 20:14:25,802 INFO L428 stractBuchiCegarLoop]: Abstraction has 88 states and 115 transitions. [2022-11-18 20:14:25,802 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-18 20:14:25,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 115 transitions. [2022-11-18 20:14:25,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:25,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:25,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:25,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:25,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:25,804 INFO L748 eck$LassoCheckResult]: Stem: 14318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14329#L367 assume !(main_~length~0#1 < 1); 14320#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14321#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14322#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14330#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14387#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14386#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14385#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14384#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14383#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14382#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14381#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14380#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14379#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14377#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14375#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14374#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14371#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14370#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14369#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14368#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14392#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14354#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14353#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14351#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14350#L370-4 main_~j~0#1 := 0; 14349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14335#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14348#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14347#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14345#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14344#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14343#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14342#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14341#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14338#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14325#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 14326#L378-2 [2022-11-18 20:14:25,804 INFO L750 eck$LassoCheckResult]: Loop: 14326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14339#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14326#L378-2 [2022-11-18 20:14:25,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:25,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1342461649, now seen corresponding path program 29 times [2022-11-18 20:14:25,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:25,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899625526] [2022-11-18 20:14:25,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:25,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:25,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:26,918 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:26,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:26,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899625526] [2022-11-18 20:14:26,918 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899625526] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:26,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [818931562] [2022-11-18 20:14:26,918 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:14:26,919 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:26,919 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:26,920 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:26,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-18 20:14:27,173 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2022-11-18 20:14:27,173 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:27,176 INFO L263 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-18 20:14:27,178 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:27,617 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:14:27,835 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:14:27,836 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:14:27,850 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:14:27,851 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:14:28,736 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:14:28,739 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:14:28,739 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-18 20:14:28,781 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:28,781 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:29,410 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:14:29,414 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:14:29,508 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:29,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [818931562] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:29,509 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:29,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 44 [2022-11-18 20:14:29,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737216258] [2022-11-18 20:14:29,509 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:29,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:29,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:29,510 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-18 20:14:29,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:29,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709117863] [2022-11-18 20:14:29,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:29,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:29,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:29,514 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:29,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:29,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:29,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-11-18 20:14:29,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=1810, Unknown=0, NotChecked=0, Total=1980 [2022-11-18 20:14:29,597 INFO L87 Difference]: Start difference. First operand 88 states and 115 transitions. cyclomatic complexity: 33 Second operand has 45 states, 44 states have (on average 2.090909090909091) internal successors, (92), 45 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:31,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:31,126 INFO L93 Difference]: Finished difference Result 102 states and 129 transitions. [2022-11-18 20:14:31,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 129 transitions. [2022-11-18 20:14:31,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:31,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 101 states and 128 transitions. [2022-11-18 20:14:31,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:14:31,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:14:31,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 128 transitions. [2022-11-18 20:14:31,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:31,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 128 transitions. [2022-11-18 20:14:31,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 128 transitions. [2022-11-18 20:14:31,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 58. [2022-11-18 20:14:31,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2413793103448276) internal successors, (72), 57 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:31,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 72 transitions. [2022-11-18 20:14:31,132 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-18 20:14:31,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 20:14:31,133 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-18 20:14:31,133 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-18 20:14:31,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 72 transitions. [2022-11-18 20:14:31,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:31,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:31,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:31,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:31,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:31,136 INFO L748 eck$LassoCheckResult]: Stem: 14836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14847#L367 assume !(main_~length~0#1 < 1); 14838#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14839#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14848#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14892#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14891#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14890#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14889#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14888#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14886#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14885#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14883#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14882#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14880#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14879#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14878#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14877#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14875#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14869#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 14868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14854#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14841#L370-4 main_~j~0#1 := 0; 14842#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14845#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14846#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14852#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14867#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14866#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14865#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14864#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14863#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14862#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14861#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14860#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14859#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14858#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14857#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14843#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 14844#L378-2 [2022-11-18 20:14:31,136 INFO L750 eck$LassoCheckResult]: Loop: 14844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14856#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 14844#L378-2 [2022-11-18 20:14:31,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:31,137 INFO L85 PathProgramCache]: Analyzing trace with hash -627666578, now seen corresponding path program 30 times [2022-11-18 20:14:31,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:31,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872740996] [2022-11-18 20:14:31,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:31,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:31,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:32,324 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:32,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:32,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872740996] [2022-11-18 20:14:32,324 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872740996] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:32,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1409097937] [2022-11-18 20:14:32,325 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:14:32,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:32,325 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:32,327 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:32,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-18 20:14:33,060 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-18 20:14:33,061 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:33,063 INFO L263 TraceCheckSpWp]: Trace formula consists of 269 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-18 20:14:33,065 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:33,456 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:14:34,797 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 20:14:34,798 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-18 20:14:34,840 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:34,840 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:36,613 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-18 20:14:36,618 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-18 20:14:36,994 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:36,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1409097937] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:36,994 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:36,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 53 [2022-11-18 20:14:36,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845288052] [2022-11-18 20:14:36,995 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:36,995 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:36,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:36,995 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-18 20:14:36,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:36,996 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012425161] [2022-11-18 20:14:36,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:36,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:37,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:37,000 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:37,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:37,005 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:37,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:37,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-18 20:14:37,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=2525, Unknown=0, NotChecked=0, Total=2862 [2022-11-18 20:14:37,090 INFO L87 Difference]: Start difference. First operand 58 states and 72 transitions. cyclomatic complexity: 18 Second operand has 54 states, 53 states have (on average 2.056603773584906) internal successors, (109), 54 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:41,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:41,304 INFO L93 Difference]: Finished difference Result 154 states and 187 transitions. [2022-11-18 20:14:41,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 187 transitions. [2022-11-18 20:14:41,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:41,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 135 states and 166 transitions. [2022-11-18 20:14:41,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 20:14:41,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 20:14:41,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 166 transitions. [2022-11-18 20:14:41,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:41,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 166 transitions. [2022-11-18 20:14:41,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 166 transitions. [2022-11-18 20:14:41,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 73. [2022-11-18 20:14:41,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 72 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:41,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 92 transitions. [2022-11-18 20:14:41,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 92 transitions. [2022-11-18 20:14:41,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-11-18 20:14:41,311 INFO L428 stractBuchiCegarLoop]: Abstraction has 73 states and 92 transitions. [2022-11-18 20:14:41,312 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-18 20:14:41,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 92 transitions. [2022-11-18 20:14:41,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:41,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:41,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:41,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:41,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:41,314 INFO L748 eck$LassoCheckResult]: Stem: 15469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15480#L367 assume !(main_~length~0#1 < 1); 15471#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15472#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15481#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15541#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15540#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15539#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15484#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15485#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15482#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15483#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15516#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15515#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15514#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15512#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15511#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15497#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15492#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15494#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15491#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 15490#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15488#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15474#L370-4 main_~j~0#1 := 0; 15475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15486#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15478#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15479#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15508#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15506#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15505#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15504#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15503#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15502#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15501#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15499#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15498#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15476#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 15477#L378-2 [2022-11-18 20:14:41,314 INFO L750 eck$LassoCheckResult]: Loop: 15477#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15500#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 15477#L378-2 [2022-11-18 20:14:41,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:41,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1051313300, now seen corresponding path program 31 times [2022-11-18 20:14:41,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:41,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376270961] [2022-11-18 20:14:41,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:41,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:41,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:42,516 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:42,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:42,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376270961] [2022-11-18 20:14:42,517 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376270961] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:42,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [706617247] [2022-11-18 20:14:42,517 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:14:42,517 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:42,517 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:42,520 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:42,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-18 20:14:42,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:42,715 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-18 20:14:42,717 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:43,306 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:14:44,239 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:14:44,297 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:44,298 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:44,656 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:14:44,660 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:14:44,791 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:44,792 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [706617247] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:44,792 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:44,792 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 20] total 42 [2022-11-18 20:14:44,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385456215] [2022-11-18 20:14:44,792 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:44,792 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:44,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:44,793 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-18 20:14:44,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:44,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399029779] [2022-11-18 20:14:44,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:44,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:44,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:44,798 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:44,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:44,803 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:44,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:44,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-18 20:14:44,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1653, Unknown=0, NotChecked=0, Total=1806 [2022-11-18 20:14:44,897 INFO L87 Difference]: Start difference. First operand 73 states and 92 transitions. cyclomatic complexity: 23 Second operand has 43 states, 42 states have (on average 2.2857142857142856) internal successors, (96), 43 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:46,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:46,411 INFO L93 Difference]: Finished difference Result 124 states and 155 transitions. [2022-11-18 20:14:46,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 155 transitions. [2022-11-18 20:14:46,412 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:14:46,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 123 states and 154 transitions. [2022-11-18 20:14:46,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-18 20:14:46,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-18 20:14:46,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 154 transitions. [2022-11-18 20:14:46,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:46,413 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 154 transitions. [2022-11-18 20:14:46,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 154 transitions. [2022-11-18 20:14:46,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 104. [2022-11-18 20:14:46,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.2788461538461537) internal successors, (133), 103 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:46,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 133 transitions. [2022-11-18 20:14:46,416 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-18 20:14:46,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 20:14:46,417 INFO L428 stractBuchiCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-18 20:14:46,417 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-18 20:14:46,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 133 transitions. [2022-11-18 20:14:46,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:46,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:46,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:46,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:46,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:46,419 INFO L748 eck$LassoCheckResult]: Stem: 15996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16007#L367 assume !(main_~length~0#1 < 1); 15998#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15999#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16000#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16008#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16010#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16011#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16060#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16050#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16059#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16057#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16093#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16092#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16091#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16089#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16086#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16063#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16062#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16019#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16017#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16015#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16001#L370-4 main_~j~0#1 := 0; 16002#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16077#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16005#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16006#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16076#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16075#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16074#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16073#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16072#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16071#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16070#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16069#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16068#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16067#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16065#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16064#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16003#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 16004#L378-2 [2022-11-18 20:14:46,419 INFO L750 eck$LassoCheckResult]: Loop: 16004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16066#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16004#L378-2 [2022-11-18 20:14:46,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:46,419 INFO L85 PathProgramCache]: Analyzing trace with hash -994767313, now seen corresponding path program 32 times [2022-11-18 20:14:46,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:46,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657155270] [2022-11-18 20:14:46,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:46,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:46,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:46,869 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:46,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:46,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657155270] [2022-11-18 20:14:46,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657155270] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:46,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1841263898] [2022-11-18 20:14:46,870 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:14:46,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:46,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:46,872 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:46,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-18 20:14:47,060 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:14:47,060 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:47,062 INFO L263 TraceCheckSpWp]: Trace formula consists of 288 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-18 20:14:47,064 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:47,497 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:47,497 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:14:47,813 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:47,814 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1841263898] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:14:47,814 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:14:47,814 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21] total 32 [2022-11-18 20:14:47,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139733692] [2022-11-18 20:14:47,815 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:14:47,815 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:14:47,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:47,815 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-18 20:14:47,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:47,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479301014] [2022-11-18 20:14:47,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:47,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:47,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:47,820 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:14:47,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:14:47,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:14:47,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:14:47,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-18 20:14:47,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2022-11-18 20:14:47,894 INFO L87 Difference]: Start difference. First operand 104 states and 133 transitions. cyclomatic complexity: 34 Second operand has 32 states, 32 states have (on average 2.3125) internal successors, (74), 32 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:48,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:14:48,308 INFO L93 Difference]: Finished difference Result 128 states and 158 transitions. [2022-11-18 20:14:48,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 158 transitions. [2022-11-18 20:14:48,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:48,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 110 states and 140 transitions. [2022-11-18 20:14:48,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:14:48,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:14:48,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110 states and 140 transitions. [2022-11-18 20:14:48,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:14:48,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 110 states and 140 transitions. [2022-11-18 20:14:48,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states and 140 transitions. [2022-11-18 20:14:48,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 74. [2022-11-18 20:14:48,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2567567567567568) internal successors, (93), 73 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:14:48,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 93 transitions. [2022-11-18 20:14:48,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-18 20:14:48,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-18 20:14:48,317 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-18 20:14:48,317 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-18 20:14:48,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 93 transitions. [2022-11-18 20:14:48,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:14:48,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:14:48,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:14:48,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:14:48,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:14:48,319 INFO L748 eck$LassoCheckResult]: Stem: 16571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16582#L367 assume !(main_~length~0#1 < 1); 16573#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16574#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16575#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16583#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16586#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16585#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16644#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16643#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16642#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16641#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16640#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16639#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16638#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16637#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16634#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16628#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16622#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16616#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 16617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16608#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16588#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16576#L370-4 main_~j~0#1 := 0; 16577#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16587#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16603#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16602#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16600#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16598#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16596#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16594#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16591#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16578#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 16579#L378-2 [2022-11-18 20:14:48,319 INFO L750 eck$LassoCheckResult]: Loop: 16579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16592#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 16579#L378-2 [2022-11-18 20:14:48,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:14:48,320 INFO L85 PathProgramCache]: Analyzing trace with hash 846855098, now seen corresponding path program 33 times [2022-11-18 20:14:48,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:14:48,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048572293] [2022-11-18 20:14:48,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:14:48,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:14:48,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:14:49,660 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:14:49,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:14:49,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048572293] [2022-11-18 20:14:49,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048572293] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:14:49,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [145421678] [2022-11-18 20:14:49,661 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:14:49,661 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:14:49,661 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:14:49,664 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:14:49,665 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-18 20:14:50,443 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-18 20:14:50,444 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:14:50,447 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-18 20:14:50,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:14:50,831 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:14:51,096 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 20:14:51,097 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 29 treesize of output 36 [2022-11-18 20:14:51,268 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-18 20:14:51,268 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 49 [2022-11-18 20:15:07,575 WARN L233 SmtUtils]: Spent 12.03s on a formula simplification that was a NOOP. DAG size: 37 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:15:15,008 WARN L233 SmtUtils]: Spent 7.26s on a formula simplification that was a NOOP. DAG size: 40 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:15:24,521 WARN L233 SmtUtils]: Spent 5.14s on a formula simplification that was a NOOP. DAG size: 40 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:15:30,750 WARN L233 SmtUtils]: Spent 6.00s on a formula simplification that was a NOOP. DAG size: 41 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:15:48,109 WARN L233 SmtUtils]: Spent 12.03s on a formula simplification that was a NOOP. DAG size: 41 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:16:00,373 WARN L233 SmtUtils]: Spent 12.03s on a formula simplification that was a NOOP. DAG size: 41 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:16:04,849 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:16:04,849 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 71 treesize of output 117 [2022-11-18 20:16:05,311 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 49 proven. 124 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:05,312 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:16:09,938 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-18 20:16:09,944 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-18 20:16:10,344 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 42 proven. 129 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 20:16:10,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [145421678] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:16:10,344 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:16:10,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25, 22] total 57 [2022-11-18 20:16:10,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586904393] [2022-11-18 20:16:10,345 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:16:10,345 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:16:10,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:10,345 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-18 20:16:10,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:10,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035480506] [2022-11-18 20:16:10,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:10,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:10,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:10,350 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:16:10,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:10,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:16:10,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:16:10,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2022-11-18 20:16:10,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=373, Invalid=2932, Unknown=1, NotChecked=0, Total=3306 [2022-11-18 20:16:10,449 INFO L87 Difference]: Start difference. First operand 74 states and 93 transitions. cyclomatic complexity: 24 Second operand has 58 states, 57 states have (on average 2.0526315789473686) internal successors, (117), 58 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:38,145 WARN L233 SmtUtils]: Spent 12.03s on a formula simplification that was a NOOP. DAG size: 45 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:16:38,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:16:38,563 INFO L93 Difference]: Finished difference Result 201 states and 233 transitions. [2022-11-18 20:16:38,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 233 transitions. [2022-11-18 20:16:38,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:16:38,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 144 states and 173 transitions. [2022-11-18 20:16:38,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:16:38,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:16:38,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 173 transitions. [2022-11-18 20:16:38,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:16:38,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 173 transitions. [2022-11-18 20:16:38,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 173 transitions. [2022-11-18 20:16:38,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 74. [2022-11-18 20:16:38,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2567567567567568) internal successors, (93), 73 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:38,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 93 transitions. [2022-11-18 20:16:38,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-18 20:16:38,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2022-11-18 20:16:38,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 93 transitions. [2022-11-18 20:16:38,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-18 20:16:38,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 93 transitions. [2022-11-18 20:16:38,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:16:38,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:16:38,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:16:38,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:16:38,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:16:38,570 INFO L748 eck$LassoCheckResult]: Stem: 17360#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17371#L367 assume !(main_~length~0#1 < 1); 17362#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17363#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17364#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17372#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17427#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17426#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17425#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17422#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17420#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17419#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17415#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17414#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17413#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17412#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17411#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17410#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17409#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17408#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17407#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17405#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17404#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17403#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17379#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17399#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17397#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17396#L370-4 main_~j~0#1 := 0; 17395#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17377#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17394#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17393#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17392#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17391#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17390#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17389#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17388#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17387#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17386#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17385#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17384#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17382#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17367#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 17368#L378-2 [2022-11-18 20:16:38,571 INFO L750 eck$LassoCheckResult]: Loop: 17368#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17383#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17368#L378-2 [2022-11-18 20:16:38,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:38,571 INFO L85 PathProgramCache]: Analyzing trace with hash -1999869190, now seen corresponding path program 34 times [2022-11-18 20:16:38,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:38,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409044345] [2022-11-18 20:16:38,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:38,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:38,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:16:39,825 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:39,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:16:39,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409044345] [2022-11-18 20:16:39,826 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409044345] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:16:39,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1751776448] [2022-11-18 20:16:39,826 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:16:39,826 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:16:39,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:16:39,828 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:16:39,831 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-18 20:16:39,993 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:16:39,993 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:16:39,995 INFO L263 TraceCheckSpWp]: Trace formula consists of 261 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-18 20:16:39,997 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:16:40,081 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:16:40,260 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:16:40,260 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:16:40,288 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:16:40,289 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:16:40,823 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:16:40,826 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:40,826 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:16:41,254 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:16:41,259 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:16:41,365 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:41,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1751776448] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:16:41,365 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:16:41,365 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-11-18 20:16:41,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471500877] [2022-11-18 20:16:41,366 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:16:41,366 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:16:41,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:41,366 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-18 20:16:41,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:41,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797887560] [2022-11-18 20:16:41,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:41,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:41,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:41,369 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:16:41,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:41,372 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:16:41,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:16:41,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 20:16:41,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=1092, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 20:16:41,447 INFO L87 Difference]: Start difference. First operand 74 states and 93 transitions. cyclomatic complexity: 24 Second operand has 35 states, 34 states have (on average 2.2058823529411766) internal successors, (75), 35 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:42,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:16:42,880 INFO L93 Difference]: Finished difference Result 146 states and 174 transitions. [2022-11-18 20:16:42,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146 states and 174 transitions. [2022-11-18 20:16:42,880 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-18 20:16:42,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146 states to 145 states and 173 transitions. [2022-11-18 20:16:42,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-18 20:16:42,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-18 20:16:42,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145 states and 173 transitions. [2022-11-18 20:16:42,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:16:42,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145 states and 173 transitions. [2022-11-18 20:16:42,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states and 173 transitions. [2022-11-18 20:16:42,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 80. [2022-11-18 20:16:42,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2875) internal successors, (103), 79 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:42,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 103 transitions. [2022-11-18 20:16:42,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 103 transitions. [2022-11-18 20:16:42,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-18 20:16:42,893 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 103 transitions. [2022-11-18 20:16:42,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-18 20:16:42,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 103 transitions. [2022-11-18 20:16:42,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:16:42,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:16:42,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:16:42,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:16:42,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:16:42,895 INFO L748 eck$LassoCheckResult]: Stem: 17932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17943#L367 assume !(main_~length~0#1 < 1); 17934#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17935#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17936#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17944#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17948#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18001#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18000#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17999#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17998#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17997#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17996#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17995#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17994#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17993#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17992#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17988#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17986#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17984#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17982#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17980#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17979#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17977#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17975#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17973#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17968#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 17952#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17950#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17941#L370-4 main_~j~0#1 := 0; 17942#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17939#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17940#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17947#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17966#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17965#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17964#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17963#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17962#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17961#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17960#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17959#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17957#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17956#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17955#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17954#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17937#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 17938#L378-2 [2022-11-18 20:16:42,895 INFO L750 eck$LassoCheckResult]: Loop: 17938#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17953#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 17938#L378-2 [2022-11-18 20:16:42,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:42,895 INFO L85 PathProgramCache]: Analyzing trace with hash -1295583043, now seen corresponding path program 35 times [2022-11-18 20:16:42,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:42,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136925332] [2022-11-18 20:16:42,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:42,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:42,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:16:44,303 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:44,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:16:44,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136925332] [2022-11-18 20:16:44,303 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136925332] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:16:44,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [334597981] [2022-11-18 20:16:44,304 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:16:44,304 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:16:44,304 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:16:44,313 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:16:44,337 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-18 20:16:44,654 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-18 20:16:44,654 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:16:44,657 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 49 conjunts are in the unsatisfiable core [2022-11-18 20:16:44,660 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:16:45,258 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:16:46,498 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:16:46,500 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:16:46,501 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-18 20:16:46,550 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:46,550 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:16:46,955 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:16:46,958 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:16:47,078 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:47,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [334597981] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:16:47,078 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:16:47,078 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 23] total 48 [2022-11-18 20:16:47,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630125314] [2022-11-18 20:16:47,079 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:16:47,079 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:16:47,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:47,079 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-18 20:16:47,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:47,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774973103] [2022-11-18 20:16:47,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:47,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:47,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:47,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:16:47,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:47,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:16:47,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:16:47,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 20:16:47,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=2171, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 20:16:47,182 INFO L87 Difference]: Start difference. First operand 80 states and 103 transitions. cyclomatic complexity: 28 Second operand has 49 states, 48 states have (on average 2.2083333333333335) internal successors, (106), 49 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:49,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:16:49,861 INFO L93 Difference]: Finished difference Result 149 states and 187 transitions. [2022-11-18 20:16:49,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 187 transitions. [2022-11-18 20:16:49,862 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21 [2022-11-18 20:16:49,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 148 states and 186 transitions. [2022-11-18 20:16:49,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-18 20:16:49,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-18 20:16:49,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 186 transitions. [2022-11-18 20:16:49,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:16:49,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148 states and 186 transitions. [2022-11-18 20:16:49,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 186 transitions. [2022-11-18 20:16:49,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 127. [2022-11-18 20:16:49,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.2834645669291338) internal successors, (163), 126 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:49,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 163 transitions. [2022-11-18 20:16:49,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 163 transitions. [2022-11-18 20:16:49,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 20:16:49,881 INFO L428 stractBuchiCegarLoop]: Abstraction has 127 states and 163 transitions. [2022-11-18 20:16:49,881 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-18 20:16:49,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 163 transitions. [2022-11-18 20:16:49,882 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2022-11-18 20:16:49,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:16:49,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:16:49,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 8, 7, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:16:49,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 20:16:49,883 INFO L748 eck$LassoCheckResult]: Stem: 18527#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18538#L367 assume !(main_~length~0#1 < 1); 18529#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18530#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18539#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18580#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18579#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18578#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18576#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18575#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18573#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18572#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18571#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18570#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18568#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18565#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18564#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18563#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18561#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18562#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18542#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18581#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18582#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18611#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 18610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18608#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18607#L370-4 main_~j~0#1 := 0; 18606#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18605#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18604#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18603#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18602#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18601#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18600#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18599#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18598#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18597#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18595#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18594#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18593#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18586#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18587#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 18639#L378-2 [2022-11-18 20:16:49,884 INFO L750 eck$LassoCheckResult]: Loop: 18639#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18641#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 18640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18638#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 18639#L378-2 [2022-11-18 20:16:49,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:49,884 INFO L85 PathProgramCache]: Analyzing trace with hash -1146287510, now seen corresponding path program 36 times [2022-11-18 20:16:49,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:49,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728911522] [2022-11-18 20:16:49,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:49,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:49,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:16:51,622 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 0 proven. 201 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:51,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:16:51,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728911522] [2022-11-18 20:16:51,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728911522] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:16:51,623 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [318477816] [2022-11-18 20:16:51,623 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:16:51,623 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:16:51,623 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:16:51,645 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:16:51,647 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-18 20:16:53,617 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-18 20:16:53,618 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:16:53,621 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-18 20:16:53,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:16:54,222 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:16:54,468 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:16:54,469 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:16:54,488 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:16:54,489 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:16:54,591 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:16:54,591 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:16:55,539 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:16:55,590 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:55,591 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:16:56,255 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:16:56,259 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:16:56,399 INFO L134 CoverageAnalysis]: Checked inductivity of 201 backedges. 1 proven. 199 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 20:16:56,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [318477816] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:16:56,400 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:16:56,400 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 23] total 48 [2022-11-18 20:16:56,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802580925] [2022-11-18 20:16:56,400 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:16:56,401 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:16:56,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:56,401 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 3 times [2022-11-18 20:16:56,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:56,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381046798] [2022-11-18 20:16:56,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:56,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:56,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:56,406 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:16:56,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:56,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:16:56,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:16:56,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 20:16:56,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=2164, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 20:16:56,578 INFO L87 Difference]: Start difference. First operand 127 states and 163 transitions. cyclomatic complexity: 43 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:58,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:16:58,398 INFO L93 Difference]: Finished difference Result 139 states and 166 transitions. [2022-11-18 20:16:58,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 166 transitions. [2022-11-18 20:16:58,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:16:58,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 137 states and 164 transitions. [2022-11-18 20:16:58,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-18 20:16:58,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-18 20:16:58,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 137 states and 164 transitions. [2022-11-18 20:16:58,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:16:58,399 INFO L218 hiAutomatonCegarLoop]: Abstraction has 137 states and 164 transitions. [2022-11-18 20:16:58,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states and 164 transitions. [2022-11-18 20:16:58,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 80. [2022-11-18 20:16:58,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2625) internal successors, (101), 79 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:16:58,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 101 transitions. [2022-11-18 20:16:58,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 101 transitions. [2022-11-18 20:16:58,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 20:16:58,413 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 101 transitions. [2022-11-18 20:16:58,413 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-18 20:16:58,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 101 transitions. [2022-11-18 20:16:58,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:16:58,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:16:58,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:16:58,414 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:16:58,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:16:58,415 INFO L748 eck$LassoCheckResult]: Stem: 19175#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19176#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19186#L367 assume !(main_~length~0#1 < 1); 19177#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19178#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19179#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19187#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19254#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19253#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19252#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19251#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19250#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19249#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19248#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19247#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19246#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19245#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19243#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19241#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19237#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19233#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19231#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19226#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19224#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19223#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19222#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19212#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19180#L370-4 main_~j~0#1 := 0; 19181#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19213#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19192#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19184#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19211#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19209#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19208#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19207#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19206#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19205#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19204#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19203#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19198#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19197#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19195#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19194#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19182#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 19183#L378-2 [2022-11-18 20:16:58,415 INFO L750 eck$LassoCheckResult]: Loop: 19183#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19196#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19183#L378-2 [2022-11-18 20:16:58,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:58,415 INFO L85 PathProgramCache]: Analyzing trace with hash 485210944, now seen corresponding path program 37 times [2022-11-18 20:16:58,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:58,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661584862] [2022-11-18 20:16:58,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:58,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:58,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:16:58,899 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:58,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:16:58,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [661584862] [2022-11-18 20:16:58,899 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [661584862] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:16:58,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1264403129] [2022-11-18 20:16:58,900 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:16:58,900 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:16:58,900 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:16:58,903 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:16:58,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-18 20:16:59,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:16:59,084 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 20:16:59,086 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:16:59,527 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:59,527 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:16:59,851 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:16:59,851 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1264403129] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:16:59,851 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:16:59,851 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-18 20:16:59,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653537644] [2022-11-18 20:16:59,852 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:16:59,852 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:16:59,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:16:59,852 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-18 20:16:59,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:16:59,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025122769] [2022-11-18 20:16:59,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:16:59,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:16:59,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:59,856 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:16:59,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:16:59,859 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:16:59,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:16:59,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-18 20:16:59,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-18 20:16:59,939 INFO L87 Difference]: Start difference. First operand 80 states and 101 transitions. cyclomatic complexity: 26 Second operand has 35 states, 35 states have (on average 2.3142857142857145) internal successors, (81), 35 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:00,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:17:00,446 INFO L93 Difference]: Finished difference Result 106 states and 128 transitions. [2022-11-18 20:17:00,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 128 transitions. [2022-11-18 20:17:00,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:00,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 86 states and 108 transitions. [2022-11-18 20:17:00,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:17:00,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:17:00,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 108 transitions. [2022-11-18 20:17:00,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:17:00,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86 states and 108 transitions. [2022-11-18 20:17:00,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 108 transitions. [2022-11-18 20:17:00,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 82. [2022-11-18 20:17:00,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:00,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-18 20:17:00,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 20:17:00,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-18 20:17:00,450 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-18 20:17:00,450 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-18 20:17:00,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-18 20:17:00,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:00,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:17:00,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:17:00,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:17:00,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:17:00,452 INFO L748 eck$LassoCheckResult]: Stem: 19739#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19740#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19750#L367 assume !(main_~length~0#1 < 1); 19741#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19742#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19743#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19751#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19814#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19813#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19812#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19811#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19810#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19809#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19808#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19807#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19806#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19805#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19804#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19802#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19803#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19818#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19817#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19815#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19794#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19792#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19791#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19788#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19787#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19786#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 19757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19752#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19753#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19779#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19776#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19775#L370-4 main_~j~0#1 := 0; 19754#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19746#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19747#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19772#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19771#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19770#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19769#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19768#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19767#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19766#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19765#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19764#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19763#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19762#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19761#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19759#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19758#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19744#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 19745#L378-2 [2022-11-18 20:17:00,452 INFO L750 eck$LassoCheckResult]: Loop: 19745#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19760#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 19745#L378-2 [2022-11-18 20:17:00,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:00,452 INFO L85 PathProgramCache]: Analyzing trace with hash 2145991281, now seen corresponding path program 38 times [2022-11-18 20:17:00,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:00,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536438029] [2022-11-18 20:17:00,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:00,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:00,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:17:01,980 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:01,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:17:01,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536438029] [2022-11-18 20:17:01,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536438029] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:17:01,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [624583689] [2022-11-18 20:17:01,981 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:17:01,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:17:01,982 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:17:01,985 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:17:01,996 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-18 20:17:02,171 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:17:02,171 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:17:02,174 INFO L263 TraceCheckSpWp]: Trace formula consists of 311 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-18 20:17:02,176 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:17:02,698 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:17:02,901 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:17:02,901 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:17:02,912 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:17:02,913 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:17:03,773 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:17:03,818 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:03,819 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:17:04,338 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:17:04,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:17:04,449 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:04,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [624583689] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:17:04,450 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:17:04,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 50 [2022-11-18 20:17:04,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125303879] [2022-11-18 20:17:04,450 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:17:04,450 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:17:04,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:04,451 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2022-11-18 20:17:04,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:04,451 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409042456] [2022-11-18 20:17:04,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:04,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:04,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:04,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:17:04,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:04,459 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:17:04,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:17:04,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-11-18 20:17:04,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=2365, Unknown=0, NotChecked=0, Total=2550 [2022-11-18 20:17:04,536 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 51 states, 50 states have (on average 2.24) internal successors, (112), 51 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:06,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:17:06,519 INFO L93 Difference]: Finished difference Result 100 states and 121 transitions. [2022-11-18 20:17:06,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 121 transitions. [2022-11-18 20:17:06,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:06,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 99 states and 120 transitions. [2022-11-18 20:17:06,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:17:06,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:17:06,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 120 transitions. [2022-11-18 20:17:06,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:17:06,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 120 transitions. [2022-11-18 20:17:06,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 120 transitions. [2022-11-18 20:17:06,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 74. [2022-11-18 20:17:06,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2432432432432432) internal successors, (92), 73 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:06,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 92 transitions. [2022-11-18 20:17:06,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-18 20:17:06,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 20:17:06,528 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-18 20:17:06,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 51 ============ [2022-11-18 20:17:06,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 92 transitions. [2022-11-18 20:17:06,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:06,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:17:06,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:17:06,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:17:06,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:17:06,530 INFO L748 eck$LassoCheckResult]: Stem: 20319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20330#L367 assume !(main_~length~0#1 < 1); 20321#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20322#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20331#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20334#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20383#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20382#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20381#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20380#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20379#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20378#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20377#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20376#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20375#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20374#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20373#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20371#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20369#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20367#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20365#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20363#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20361#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20360#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20358#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20356#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20354#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20352#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20350#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20337#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20333#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 20344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20338#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20324#L370-4 main_~j~0#1 := 0; 20325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20335#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20336#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20328#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20329#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20392#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20391#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20390#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20389#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20388#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20387#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20386#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20385#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20384#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20346#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20345#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20343#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20341#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20340#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20326#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 20327#L378-2 [2022-11-18 20:17:06,531 INFO L750 eck$LassoCheckResult]: Loop: 20327#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20342#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 20327#L378-2 [2022-11-18 20:17:06,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:06,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1343923152, now seen corresponding path program 39 times [2022-11-18 20:17:06,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:06,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420029885] [2022-11-18 20:17:06,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:06,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:06,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:17:08,007 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:08,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:17:08,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420029885] [2022-11-18 20:17:08,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420029885] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:17:08,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1079103619] [2022-11-18 20:17:08,008 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:17:08,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:17:08,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:17:08,016 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:17:08,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-18 20:17:08,778 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 20:17:08,778 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:17:08,782 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-18 20:17:08,783 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:17:09,275 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:17:10,909 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-18 20:17:10,909 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2022-11-18 20:17:10,953 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:10,953 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:17:12,949 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 37 [2022-11-18 20:17:12,958 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2022-11-18 20:17:13,410 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:13,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1079103619] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:17:13,411 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:17:13,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-18 20:17:13,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953844310] [2022-11-18 20:17:13,411 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:17:13,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:17:13,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:13,412 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2022-11-18 20:17:13,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:13,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401737212] [2022-11-18 20:17:13,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:13,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:13,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:13,415 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:17:13,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:13,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:17:13,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:17:13,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-18 20:17:13,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=460, Invalid=3572, Unknown=0, NotChecked=0, Total=4032 [2022-11-18 20:17:13,505 INFO L87 Difference]: Start difference. First operand 74 states and 92 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:17,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:17:17,410 INFO L93 Difference]: Finished difference Result 131 states and 154 transitions. [2022-11-18 20:17:17,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131 states and 154 transitions. [2022-11-18 20:17:17,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:17,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131 states to 107 states and 128 transitions. [2022-11-18 20:17:17,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:17:17,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:17:17,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 128 transitions. [2022-11-18 20:17:17,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:17:17,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 107 states and 128 transitions. [2022-11-18 20:17:17,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 128 transitions. [2022-11-18 20:17:17,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 86. [2022-11-18 20:17:17,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 86 states have (on average 1.244186046511628) internal successors, (107), 85 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:17,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 107 transitions. [2022-11-18 20:17:17,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86 states and 107 transitions. [2022-11-18 20:17:17,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-18 20:17:17,416 INFO L428 stractBuchiCegarLoop]: Abstraction has 86 states and 107 transitions. [2022-11-18 20:17:17,417 INFO L335 stractBuchiCegarLoop]: ======== Iteration 52 ============ [2022-11-18 20:17:17,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 107 transitions. [2022-11-18 20:17:17,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:17,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:17:17,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:17:17,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 7, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:17:17,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:17:17,418 INFO L748 eck$LassoCheckResult]: Stem: 21018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21029#L367 assume !(main_~length~0#1 < 1); 21020#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21021#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21030#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21083#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21082#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21081#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21080#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21079#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21078#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21077#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21076#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21075#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21071#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21072#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21087#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21086#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21085#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21084#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21063#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21062#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21060#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21058#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21057#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21056#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21036#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21052#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21047#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21045#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21042#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21027#L370-4 main_~j~0#1 := 0; 21028#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21101#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21034#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21025#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21026#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21100#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21099#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21098#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21097#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21096#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21094#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21093#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21092#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21091#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21090#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21089#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21046#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21040#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21023#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 21024#L378-2 [2022-11-18 20:17:17,419 INFO L750 eck$LassoCheckResult]: Loop: 21024#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21041#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21024#L378-2 [2022-11-18 20:17:17,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:17,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1695797065, now seen corresponding path program 40 times [2022-11-18 20:17:17,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:17,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564979265] [2022-11-18 20:17:17,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:17,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:17,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:17:17,972 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:17,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:17:17,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564979265] [2022-11-18 20:17:17,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564979265] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:17:17,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1461230205] [2022-11-18 20:17:17,972 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:17:17,973 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:17:17,973 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:17:17,976 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:17:17,976 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-18 20:17:18,168 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:17:18,168 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:17:18,170 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 20:17:18,172 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:17:18,668 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:18,669 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:17:19,154 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:19,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1461230205] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:17:19,155 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:17:19,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-18 20:17:19,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425212447] [2022-11-18 20:17:19,155 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:17:19,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:17:19,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:19,155 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2022-11-18 20:17:19,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:19,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613221292] [2022-11-18 20:17:19,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:19,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:19,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:19,159 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:17:19,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:19,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:17:19,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:17:19,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-18 20:17:19,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 20:17:19,233 INFO L87 Difference]: Start difference. First operand 86 states and 107 transitions. cyclomatic complexity: 25 Second operand has 38 states, 38 states have (on average 2.3157894736842106) internal successors, (88), 38 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:19,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:17:19,675 INFO L93 Difference]: Finished difference Result 110 states and 132 transitions. [2022-11-18 20:17:19,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 132 transitions. [2022-11-18 20:17:19,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:19,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 88 states and 110 transitions. [2022-11-18 20:17:19,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-18 20:17:19,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-18 20:17:19,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 110 transitions. [2022-11-18 20:17:19,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:17:19,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 110 transitions. [2022-11-18 20:17:19,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 110 transitions. [2022-11-18 20:17:19,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 80. [2022-11-18 20:17:19,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.25) internal successors, (100), 79 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:19,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 100 transitions. [2022-11-18 20:17:19,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-18 20:17:19,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 20:17:19,679 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-18 20:17:19,679 INFO L335 stractBuchiCegarLoop]: ======== Iteration 53 ============ [2022-11-18 20:17:19,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 100 transitions. [2022-11-18 20:17:19,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:17:19,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:17:19,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:17:19,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 7, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:17:19,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:17:19,681 INFO L748 eck$LassoCheckResult]: Stem: 21627#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21638#L367 assume !(main_~length~0#1 < 1); 21629#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21630#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21639#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21640#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21641#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21705#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21704#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21701#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21698#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21695#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21693#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21689#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21686#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21684#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21682#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21681#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21676#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21675#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21669#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21650#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21666#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21649#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 21647#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21645#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21632#L370-4 main_~j~0#1 := 0; 21633#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21643#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21644#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21636#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21664#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21662#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21660#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21659#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21658#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21657#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21656#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21654#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21653#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21652#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21651#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21634#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 21635#L378-2 [2022-11-18 20:17:19,681 INFO L750 eck$LassoCheckResult]: Loop: 21635#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21648#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 21635#L378-2 [2022-11-18 20:17:19,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:19,681 INFO L85 PathProgramCache]: Analyzing trace with hash 1467274560, now seen corresponding path program 41 times [2022-11-18 20:17:19,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:19,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184717650] [2022-11-18 20:17:19,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:19,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:19,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:17:20,943 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:20,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:17:20,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184717650] [2022-11-18 20:17:20,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184717650] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:17:20,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [835491753] [2022-11-18 20:17:20,944 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:17:20,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:17:20,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:17:20,948 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:17:20,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-18 20:17:21,597 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-18 20:17:21,597 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:17:21,600 INFO L263 TraceCheckSpWp]: Trace formula consists of 345 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-18 20:17:21,603 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:17:21,705 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:17:21,815 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:17:21,827 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-18 20:17:22,010 INFO L321 Elim1Store]: treesize reduction 61, result has 28.2 percent of original size [2022-11-18 20:17:22,011 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 39 treesize of output 41 [2022-11-18 20:17:23,427 INFO L321 Elim1Store]: treesize reduction 24, result has 11.1 percent of original size [2022-11-18 20:17:23,427 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-11-18 20:17:23,436 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:17:23,436 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:17:42,484 WARN L837 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_2074 Int) (|v_ULTIMATE.start_main_~i~0#1_639| Int) (|v_ULTIMATE.start_main_~j~0#1_679| Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_639| 4)) v_ArrVal_2074)) (.cse1 (* |v_ULTIMATE.start_main_~j~0#1_679| 4))) (or (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| .cse1 36)) 2) 0) (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_639|)) (not (<= 0 |v_ULTIMATE.start_main_~j~0#1_679|)) (not (<= |v_ULTIMATE.start_main_~j~0#1_679| 0)) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 32 .cse1)) 2) 0))))) is different from false [2022-11-18 20:17:48,262 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 70 [2022-11-18 20:17:48,274 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:17:48,274 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 560 treesize of output 539 [2022-11-18 20:17:49,266 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 21 not checked. [2022-11-18 20:17:49,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [835491753] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:17:49,267 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:17:49,267 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 28, 28] total 69 [2022-11-18 20:17:49,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969468012] [2022-11-18 20:17:49,267 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:17:49,268 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:17:49,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:17:49,268 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2022-11-18 20:17:49,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:17:49,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378569363] [2022-11-18 20:17:49,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:17:49,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:17:49,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:49,273 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:17:49,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:17:49,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:17:49,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:17:49,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2022-11-18 20:17:49,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=4389, Unknown=12, NotChecked=134, Total=4830 [2022-11-18 20:17:49,355 INFO L87 Difference]: Start difference. First operand 80 states and 100 transitions. cyclomatic complexity: 24 Second operand has 70 states, 69 states have (on average 2.101449275362319) internal successors, (145), 70 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:17:57,625 WARN L233 SmtUtils]: Spent 6.27s on a formula simplification that was a NOOP. DAG size: 54 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:18:16,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:18:16,925 INFO L93 Difference]: Finished difference Result 185 states and 220 transitions. [2022-11-18 20:18:16,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 185 states and 220 transitions. [2022-11-18 20:18:16,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:18:16,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 185 states to 183 states and 217 transitions. [2022-11-18 20:18:16,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 20:18:16,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 20:18:16,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183 states and 217 transitions. [2022-11-18 20:18:16,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:18:16,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183 states and 217 transitions. [2022-11-18 20:18:16,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states and 217 transitions. [2022-11-18 20:18:16,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 118. [2022-11-18 20:18:16,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.2796610169491525) internal successors, (151), 117 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:18:16,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 151 transitions. [2022-11-18 20:18:16,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-18 20:18:16,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2022-11-18 20:18:16,932 INFO L428 stractBuchiCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-18 20:18:16,933 INFO L335 stractBuchiCegarLoop]: ======== Iteration 54 ============ [2022-11-18 20:18:16,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 151 transitions. [2022-11-18 20:18:16,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:18:16,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:18:16,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:18:16,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:18:16,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:18:16,934 INFO L748 eck$LassoCheckResult]: Stem: 22345#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22346#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22356#L367 assume !(main_~length~0#1 < 1); 22347#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22348#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22349#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22357#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22449#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22448#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22447#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22443#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22441#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22439#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22437#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22435#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22433#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22428#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22429#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22427#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22424#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22414#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22413#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22412#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22411#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22363#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22358#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22359#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22361#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22457#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22392#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22454#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22391#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 22388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22386#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22385#L370-4 main_~j~0#1 := 0; 22384#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22360#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22381#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22380#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22379#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22378#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22376#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22375#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22374#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22373#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22372#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22371#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22370#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22369#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22368#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22367#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22366#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22365#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22350#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 22351#L378-2 [2022-11-18 20:18:16,935 INFO L750 eck$LassoCheckResult]: Loop: 22351#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22364#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 22351#L378-2 [2022-11-18 20:18:16,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:18:16,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1539661118, now seen corresponding path program 42 times [2022-11-18 20:18:16,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:18:16,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520862848] [2022-11-18 20:18:16,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:18:16,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:18:16,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:18:18,375 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:18:18,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:18:18,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520862848] [2022-11-18 20:18:18,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520862848] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:18:18,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1966528821] [2022-11-18 20:18:18,375 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:18:18,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:18:18,376 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:18:18,380 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:18:18,404 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-18 20:18:21,508 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-18 20:18:21,509 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:18:21,512 INFO L263 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 76 conjunts are in the unsatisfiable core [2022-11-18 20:18:21,515 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:18:22,001 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:18:22,143 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,145 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:18:22,164 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,165 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:18:22,363 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,364 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,367 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:18:22,368 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:18:22,389 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,391 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,393 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:18:22,393 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:18:22,582 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,583 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,584 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,586 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:22,588 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:18:22,588 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 46 treesize of output 51 [2022-11-18 20:18:24,270 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:18:24,271 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 29 treesize of output 13 [2022-11-18 20:18:24,274 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:18:24,275 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:18:27,014 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 82 [2022-11-18 20:18:27,024 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:18:27,024 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 1260 treesize of output 1240 [2022-11-18 20:18:28,034 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:18:28,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1966528821] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:18:28,035 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:18:28,035 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 30, 30] total 82 [2022-11-18 20:18:28,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687611998] [2022-11-18 20:18:28,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:18:28,036 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:18:28,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:18:28,036 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 49 times [2022-11-18 20:18:28,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:18:28,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145671786] [2022-11-18 20:18:28,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:18:28,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:18:28,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:18:28,041 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:18:28,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:18:28,047 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:18:28,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:18:28,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2022-11-18 20:18:28,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=755, Invalid=6051, Unknown=0, NotChecked=0, Total=6806 [2022-11-18 20:18:28,114 INFO L87 Difference]: Start difference. First operand 118 states and 151 transitions. cyclomatic complexity: 38 Second operand has 83 states, 82 states have (on average 2.097560975609756) internal successors, (172), 83 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:18:55,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:18:55,820 INFO L93 Difference]: Finished difference Result 435 states and 548 transitions. [2022-11-18 20:18:55,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 548 transitions. [2022-11-18 20:18:55,822 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 103 [2022-11-18 20:18:55,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 423 states and 536 transitions. [2022-11-18 20:18:55,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144 [2022-11-18 20:18:55,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144 [2022-11-18 20:18:55,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 423 states and 536 transitions. [2022-11-18 20:18:55,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:18:55,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 423 states and 536 transitions. [2022-11-18 20:18:55,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 423 states and 536 transitions. [2022-11-18 20:18:55,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 423 to 272. [2022-11-18 20:18:55,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 272 states, 272 states have (on average 1.349264705882353) internal successors, (367), 271 states have internal predecessors, (367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:18:55,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 367 transitions. [2022-11-18 20:18:55,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 272 states and 367 transitions. [2022-11-18 20:18:55,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2022-11-18 20:18:55,831 INFO L428 stractBuchiCegarLoop]: Abstraction has 272 states and 367 transitions. [2022-11-18 20:18:55,831 INFO L335 stractBuchiCegarLoop]: ======== Iteration 55 ============ [2022-11-18 20:18:55,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 272 states and 367 transitions. [2022-11-18 20:18:55,832 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 90 [2022-11-18 20:18:55,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:18:55,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:18:55,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 7, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:18:55,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:18:55,834 INFO L748 eck$LassoCheckResult]: Stem: 23572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 23573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 23583#L367 assume !(main_~length~0#1 < 1); 23574#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 23575#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 23576#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23584#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23637#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23634#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23631#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23628#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23624#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23622#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23616#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23610#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23605#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23603#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23709#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23697#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 23698#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23696#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 23695#L370-4 main_~j~0#1 := 0; 23694#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23587#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23692#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23691#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23690#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23688#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23686#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23684#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23683#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23682#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23680#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23646#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23647#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23577#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 23578#L378-2 [2022-11-18 20:18:55,834 INFO L750 eck$LassoCheckResult]: Loop: 23578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23643#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 23578#L378-2 [2022-11-18 20:18:55,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:18:55,834 INFO L85 PathProgramCache]: Analyzing trace with hash -832078144, now seen corresponding path program 43 times [2022-11-18 20:18:55,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:18:55,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217502046] [2022-11-18 20:18:55,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:18:55,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:18:55,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:18:57,344 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:18:57,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:18:57,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217502046] [2022-11-18 20:18:57,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217502046] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:18:57,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1217425285] [2022-11-18 20:18:57,345 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 20:18:57,345 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:18:57,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:18:57,352 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:18:57,354 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-18 20:18:57,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:18:57,566 INFO L263 TraceCheckSpWp]: Trace formula consists of 345 conjuncts, 56 conjunts are in the unsatisfiable core [2022-11-18 20:18:57,569 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:18:58,207 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:18:58,441 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:18:58,442 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2022-11-18 20:18:59,411 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:18:59,453 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:18:59,454 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:18:59,903 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:18:59,906 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:19:00,028 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:00,029 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1217425285] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:19:00,029 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:19:00,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27, 26] total 54 [2022-11-18 20:19:00,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850710252] [2022-11-18 20:19:00,029 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:19:00,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:19:00,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:00,030 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 50 times [2022-11-18 20:19:00,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:00,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876614774] [2022-11-18 20:19:00,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:00,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:00,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:00,034 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:19:00,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:00,037 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:19:00,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:19:00,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-18 20:19:00,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=200, Invalid=2770, Unknown=0, NotChecked=0, Total=2970 [2022-11-18 20:19:00,103 INFO L87 Difference]: Start difference. First operand 272 states and 367 transitions. cyclomatic complexity: 109 Second operand has 55 states, 54 states have (on average 2.259259259259259) internal successors, (122), 55 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:02,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:19:02,616 INFO L93 Difference]: Finished difference Result 310 states and 405 transitions. [2022-11-18 20:19:02,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 405 transitions. [2022-11-18 20:19:02,617 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 90 [2022-11-18 20:19:02,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 309 states and 404 transitions. [2022-11-18 20:19:02,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120 [2022-11-18 20:19:02,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120 [2022-11-18 20:19:02,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 404 transitions. [2022-11-18 20:19:02,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:19:02,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309 states and 404 transitions. [2022-11-18 20:19:02,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 404 transitions. [2022-11-18 20:19:02,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 220. [2022-11-18 20:19:02,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 220 states have (on average 1.3136363636363637) internal successors, (289), 219 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:02,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 289 transitions. [2022-11-18 20:19:02,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220 states and 289 transitions. [2022-11-18 20:19:02,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 20:19:02,626 INFO L428 stractBuchiCegarLoop]: Abstraction has 220 states and 289 transitions. [2022-11-18 20:19:02,626 INFO L335 stractBuchiCegarLoop]: ======== Iteration 56 ============ [2022-11-18 20:19:02,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220 states and 289 transitions. [2022-11-18 20:19:02,627 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 90 [2022-11-18 20:19:02,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:19:02,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:19:02,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:19:02,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 20:19:02,628 INFO L748 eck$LassoCheckResult]: Stem: 24588#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24599#L367 assume !(main_~length~0#1 < 1); 24590#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24591#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24592#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24600#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24648#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24646#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24645#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24644#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24643#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24642#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24640#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24636#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24635#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24634#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24633#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24632#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24631#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24629#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24652#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24650#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24649#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24622#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24618#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24688#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24687#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24686#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 24685#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24684#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24683#L370-4 main_~j~0#1 := 0; 24682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24681#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24679#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24678#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24677#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24675#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24673#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24671#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24670#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24669#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24668#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24667#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24666#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24665#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24663#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24659#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 24711#L378-2 [2022-11-18 20:19:02,629 INFO L750 eck$LassoCheckResult]: Loop: 24711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24799#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 24800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24710#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 24711#L378-2 [2022-11-18 20:19:02,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:02,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2145584001, now seen corresponding path program 44 times [2022-11-18 20:19:02,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:02,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776697921] [2022-11-18 20:19:02,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:02,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:02,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:19:04,262 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:04,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:19:04,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776697921] [2022-11-18 20:19:04,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776697921] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:19:04,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [54827539] [2022-11-18 20:19:04,263 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:19:04,263 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:19:04,263 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:19:04,267 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:19:04,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-18 20:19:04,486 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:19:04,486 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:19:04,489 INFO L263 TraceCheckSpWp]: Trace formula consists of 364 conjuncts, 57 conjunts are in the unsatisfiable core [2022-11-18 20:19:04,492 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:19:05,252 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:19:06,497 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2022-11-18 20:19:06,544 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:06,545 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:19:06,846 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:19:06,848 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:19:06,978 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:06,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [54827539] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:19:06,978 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:19:06,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 26] total 54 [2022-11-18 20:19:06,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409225295] [2022-11-18 20:19:06,979 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:19:06,979 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:19:06,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:06,979 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 4 times [2022-11-18 20:19:06,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:06,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202318655] [2022-11-18 20:19:06,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:06,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:06,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:06,984 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:19:06,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:06,987 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:19:07,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:19:07,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-18 20:19:07,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=198, Invalid=2772, Unknown=0, NotChecked=0, Total=2970 [2022-11-18 20:19:07,115 INFO L87 Difference]: Start difference. First operand 220 states and 289 transitions. cyclomatic complexity: 81 Second operand has 55 states, 54 states have (on average 2.3333333333333335) internal successors, (126), 55 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:09,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:19:09,314 INFO L93 Difference]: Finished difference Result 174 states and 205 transitions. [2022-11-18 20:19:09,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 205 transitions. [2022-11-18 20:19:09,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:19:09,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 172 states and 203 transitions. [2022-11-18 20:19:09,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-18 20:19:09,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-18 20:19:09,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 203 transitions. [2022-11-18 20:19:09,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:19:09,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 203 transitions. [2022-11-18 20:19:09,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 203 transitions. [2022-11-18 20:19:09,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 127. [2022-11-18 20:19:09,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.2283464566929134) internal successors, (156), 126 states have internal predecessors, (156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:09,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 156 transitions. [2022-11-18 20:19:09,319 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 156 transitions. [2022-11-18 20:19:09,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-18 20:19:09,325 INFO L428 stractBuchiCegarLoop]: Abstraction has 127 states and 156 transitions. [2022-11-18 20:19:09,325 INFO L335 stractBuchiCegarLoop]: ======== Iteration 57 ============ [2022-11-18 20:19:09,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 156 transitions. [2022-11-18 20:19:09,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:19:09,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:19:09,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:19:09,327 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 7, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:19:09,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:19:09,328 INFO L748 eck$LassoCheckResult]: Stem: 25414#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 25415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 25425#L367 assume !(main_~length~0#1 < 1); 25416#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 25417#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 25418#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25426#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25536#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25534#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25531#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25530#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25529#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25527#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25522#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25518#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25523#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25520#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25513#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25504#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25502#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25498#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25495#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25493#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25491#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25487#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25476#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25478#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25538#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25537#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 25436#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25434#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25423#L370-4 main_~j~0#1 := 0; 25424#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25475#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25458#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25457#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25456#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25455#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25454#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25453#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25452#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25451#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25450#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25449#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25448#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25447#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25446#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25445#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25444#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25443#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25442#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25441#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25440#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25439#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25438#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25419#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 25420#L378-2 [2022-11-18 20:19:09,328 INFO L750 eck$LassoCheckResult]: Loop: 25420#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25437#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 25420#L378-2 [2022-11-18 20:19:09,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:09,329 INFO L85 PathProgramCache]: Analyzing trace with hash 1023522182, now seen corresponding path program 45 times [2022-11-18 20:19:09,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:09,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662667687] [2022-11-18 20:19:09,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:09,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:09,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:19:09,962 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:09,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:19:09,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662667687] [2022-11-18 20:19:09,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662667687] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:19:09,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1713922791] [2022-11-18 20:19:09,963 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:19:09,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:19:09,964 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:19:09,975 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:19:09,980 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-11-18 20:19:10,777 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2022-11-18 20:19:10,777 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:19:10,781 INFO L263 TraceCheckSpWp]: Trace formula consists of 369 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-18 20:19:10,782 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:19:11,354 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:11,354 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:19:11,782 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:11,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1713922791] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:19:11,783 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:19:11,783 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 41 [2022-11-18 20:19:11,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860072727] [2022-11-18 20:19:11,783 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:19:11,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:19:11,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:11,784 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 51 times [2022-11-18 20:19:11,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:11,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713567287] [2022-11-18 20:19:11,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:11,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:11,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:11,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:19:11,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:11,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:19:11,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:19:11,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-18 20:19:11,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=1258, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 20:19:11,853 INFO L87 Difference]: Start difference. First operand 127 states and 156 transitions. cyclomatic complexity: 34 Second operand has 41 states, 41 states have (on average 2.317073170731707) internal successors, (95), 41 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:12,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:19:12,367 INFO L93 Difference]: Finished difference Result 161 states and 190 transitions. [2022-11-18 20:19:12,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161 states and 190 transitions. [2022-11-18 20:19:12,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:19:12,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161 states to 113 states and 142 transitions. [2022-11-18 20:19:12,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-18 20:19:12,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-18 20:19:12,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 142 transitions. [2022-11-18 20:19:12,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:19:12,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 113 states and 142 transitions. [2022-11-18 20:19:12,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 142 transitions. [2022-11-18 20:19:12,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 98. [2022-11-18 20:19:12,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.2551020408163265) internal successors, (123), 97 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:12,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 123 transitions. [2022-11-18 20:19:12,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 123 transitions. [2022-11-18 20:19:12,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-18 20:19:12,372 INFO L428 stractBuchiCegarLoop]: Abstraction has 98 states and 123 transitions. [2022-11-18 20:19:12,372 INFO L335 stractBuchiCegarLoop]: ======== Iteration 58 ============ [2022-11-18 20:19:12,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 123 transitions. [2022-11-18 20:19:12,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:19:12,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:19:12,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:19:12,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 7, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:19:12,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:19:12,374 INFO L748 eck$LassoCheckResult]: Stem: 26150#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26161#L367 assume !(main_~length~0#1 < 1); 26152#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26153#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26162#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26243#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26242#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26241#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26238#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26237#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26236#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26235#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26234#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26233#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26231#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26229#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26228#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26227#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26226#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26224#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26225#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26245#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26221#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26217#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26169#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26209#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26206#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26204#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26191#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26194#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26193#L370-4 main_~j~0#1 := 0; 26165#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26157#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26189#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26188#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26187#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26186#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26185#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26184#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26183#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26182#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26181#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26180#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26179#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26177#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26175#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26172#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26171#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26155#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 26156#L378-2 [2022-11-18 20:19:12,374 INFO L750 eck$LassoCheckResult]: Loop: 26156#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26173#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26156#L378-2 [2022-11-18 20:19:12,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:12,374 INFO L85 PathProgramCache]: Analyzing trace with hash -335325513, now seen corresponding path program 46 times [2022-11-18 20:19:12,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:12,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580422682] [2022-11-18 20:19:12,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:12,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:12,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:19:14,194 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:14,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:19:14,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580422682] [2022-11-18 20:19:14,195 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580422682] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:19:14,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1709157951] [2022-11-18 20:19:14,195 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:19:14,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:19:14,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:19:14,198 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:19:14,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2022-11-18 20:19:14,420 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:19:14,420 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:19:14,423 INFO L263 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-18 20:19:14,435 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:19:14,564 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:19:14,721 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:19:14,721 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:19:14,752 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-18 20:19:14,752 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-11-18 20:19:15,616 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 11 [2022-11-18 20:19:15,669 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:15,669 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:19:16,199 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:19:16,212 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:19:16,378 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:16,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1709157951] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:19:16,378 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:19:16,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 42 [2022-11-18 20:19:16,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108948971] [2022-11-18 20:19:16,379 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:19:16,379 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:19:16,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:16,379 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 52 times [2022-11-18 20:19:16,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:16,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127009720] [2022-11-18 20:19:16,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:16,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:16,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:16,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:19:16,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:16,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:19:16,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:19:16,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-18 20:19:16,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=1688, Unknown=0, NotChecked=0, Total=1806 [2022-11-18 20:19:16,464 INFO L87 Difference]: Start difference. First operand 98 states and 123 transitions. cyclomatic complexity: 30 Second operand has 43 states, 42 states have (on average 2.238095238095238) internal successors, (94), 43 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:18,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:19:18,362 INFO L93 Difference]: Finished difference Result 159 states and 191 transitions. [2022-11-18 20:19:18,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 159 states and 191 transitions. [2022-11-18 20:19:18,363 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-18 20:19:18,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 159 states to 158 states and 190 transitions. [2022-11-18 20:19:18,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-18 20:19:18,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-18 20:19:18,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 190 transitions. [2022-11-18 20:19:18,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:19:18,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 190 transitions. [2022-11-18 20:19:18,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 190 transitions. [2022-11-18 20:19:18,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 104. [2022-11-18 20:19:18,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.2788461538461537) internal successors, (133), 103 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:18,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 133 transitions. [2022-11-18 20:19:18,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-18 20:19:18,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-18 20:19:18,366 INFO L428 stractBuchiCegarLoop]: Abstraction has 104 states and 133 transitions. [2022-11-18 20:19:18,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 59 ============ [2022-11-18 20:19:18,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 133 transitions. [2022-11-18 20:19:18,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-18 20:19:18,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:19:18,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:19:18,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 7, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:19:18,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:19:18,368 INFO L748 eck$LassoCheckResult]: Stem: 26839#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26850#L367 assume !(main_~length~0#1 < 1); 26841#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26842#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26851#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26854#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26942#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26941#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26940#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26938#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26937#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26936#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26935#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26934#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26932#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26930#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26928#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26926#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26924#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26922#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26920#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26919#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26915#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26913#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26909#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26905#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26903#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26899#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26896#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26897#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26852#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26853#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 26856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26857#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26844#L370-4 main_~j~0#1 := 0; 26845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26848#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26849#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26855#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26878#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26877#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26876#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26875#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26874#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26873#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26872#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26871#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26870#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26869#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26868#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26867#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26866#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26865#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26863#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26861#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26846#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 26847#L378-2 [2022-11-18 20:19:18,369 INFO L750 eck$LassoCheckResult]: Loop: 26847#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26859#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 26847#L378-2 [2022-11-18 20:19:18,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:18,369 INFO L85 PathProgramCache]: Analyzing trace with hash -1336344330, now seen corresponding path program 47 times [2022-11-18 20:19:18,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:18,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099739539] [2022-11-18 20:19:18,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:18,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:18,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:19:19,843 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:19,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:19:19,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099739539] [2022-11-18 20:19:19,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099739539] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:19:19,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [707790021] [2022-11-18 20:19:19,844 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:19:19,844 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:19:19,844 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:19:19,847 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:19:19,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-11-18 20:19:20,364 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-11-18 20:19:20,364 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:19:20,369 INFO L263 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-18 20:19:20,370 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:19:21,199 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-18 20:19:23,005 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 20:19:23,007 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:19:23,008 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 12 [2022-11-18 20:19:23,057 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:23,057 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:19:23,517 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-11-18 20:19:23,520 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 20 [2022-11-18 20:19:23,669 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:23,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [707790021] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:19:23,669 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:19:23,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29] total 60 [2022-11-18 20:19:23,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334121067] [2022-11-18 20:19:23,669 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:19:23,670 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:19:23,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:23,670 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 53 times [2022-11-18 20:19:23,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:23,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563840577] [2022-11-18 20:19:23,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:23,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:23,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:23,674 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:19:23,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:19:23,677 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:19:23,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:19:23,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-11-18 20:19:23,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=226, Invalid=3434, Unknown=0, NotChecked=0, Total=3660 [2022-11-18 20:19:23,741 INFO L87 Difference]: Start difference. First operand 104 states and 133 transitions. cyclomatic complexity: 34 Second operand has 61 states, 60 states have (on average 2.2666666666666666) internal successors, (136), 61 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:27,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:19:27,026 INFO L93 Difference]: Finished difference Result 191 states and 238 transitions. [2022-11-18 20:19:27,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 238 transitions. [2022-11-18 20:19:27,026 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 27 [2022-11-18 20:19:27,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 190 states and 237 transitions. [2022-11-18 20:19:27,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-18 20:19:27,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-18 20:19:27,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190 states and 237 transitions. [2022-11-18 20:19:27,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-18 20:19:27,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190 states and 237 transitions. [2022-11-18 20:19:27,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states and 237 transitions. [2022-11-18 20:19:27,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 163. [2022-11-18 20:19:27,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.2760736196319018) internal successors, (208), 162 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:19:27,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 208 transitions. [2022-11-18 20:19:27,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163 states and 208 transitions. [2022-11-18 20:19:27,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-18 20:19:27,031 INFO L428 stractBuchiCegarLoop]: Abstraction has 163 states and 208 transitions. [2022-11-18 20:19:27,031 INFO L335 stractBuchiCegarLoop]: ======== Iteration 60 ============ [2022-11-18 20:19:27,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 208 transitions. [2022-11-18 20:19:27,031 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 24 [2022-11-18 20:19:27,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:19:27,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:19:27,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 11, 10, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:19:27,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-18 20:19:27,032 INFO L748 eck$LassoCheckResult]: Stem: 27602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 27603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 27613#L367 assume !(main_~length~0#1 < 1); 27604#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 27605#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 27606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27614#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27677#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27676#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27675#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27674#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27671#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27670#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27669#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27668#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27666#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27664#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27662#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27660#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27658#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27656#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27651#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27645#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27643#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27641#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27639#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27637#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27633#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27615#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27616#L372 assume 0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2);havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27713#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27711#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27710#L372 assume !(0 != (if main_#t~mem209#1 < 0 && 0 != main_#t~mem209#1 % 2 then main_#t~mem209#1 % 2 - 2 else main_#t~mem209#1 % 2));havoc main_#t~mem209#1; 27709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27707#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 27706#L370-4 main_~j~0#1 := 0; 27705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27704#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27703#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27702#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27700#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27699#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27698#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27697#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27696#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27695#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27694#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27693#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27692#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27691#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27690#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27688#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27686#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27682#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 27744#L378-2 [2022-11-18 20:19:27,032 INFO L750 eck$LassoCheckResult]: Loop: 27744#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27746#L378 assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1; 27745#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27743#L378 assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1; 27744#L378-2 [2022-11-18 20:19:27,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:19:27,033 INFO L85 PathProgramCache]: Analyzing trace with hash -496788221, now seen corresponding path program 48 times [2022-11-18 20:19:27,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:19:27,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162440772] [2022-11-18 20:19:27,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:19:27,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:19:27,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:19:28,471 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 0 proven. 357 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:28,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:19:28,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162440772] [2022-11-18 20:19:28,476 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162440772] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:19:28,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1803039097] [2022-11-18 20:19:28,476 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:19:28,477 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:19:28,477 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:19:28,481 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:19:28,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2022-11-18 20:19:30,560 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2022-11-18 20:19:30,560 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:19:30,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 401 conjuncts, 79 conjunts are in the unsatisfiable core [2022-11-18 20:19:30,568 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:19:31,115 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-18 20:19:31,249 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,249 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:19:31,264 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,264 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:19:31,352 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,352 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:19:31,361 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,361 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-18 20:19:31,510 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,512 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,514 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:19:31,514 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:19:31,528 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,529 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,532 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:19:31,532 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-18 20:19:31,744 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,746 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,750 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,752 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,754 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:31,756 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:19:31,757 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 45 treesize of output 50 [2022-11-18 20:19:52,826 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:52,827 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 20:19:52,829 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:19:52,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 31 treesize of output 13 [2022-11-18 20:19:52,833 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 1 proven. 356 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:19:52,833 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:22:12,740 WARN L837 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_802| Int) (v_ArrVal_2605 Int) (|v_ULTIMATE.start_main_~i~0#1_801| Int)) (let ((.cse0 (store (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4) 4) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_802| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_801| 4)) v_ArrVal_2605))) (or (not (<= (+ 2 |c_ULTIMATE.start_main_~i~0#1|) |v_ULTIMATE.start_main_~i~0#1_802|)) (= (mod (select .cse0 (+ 40 |c_ULTIMATE.start_main_~arr~0#1.offset|)) 2) 0) (not (<= (+ |v_ULTIMATE.start_main_~i~0#1_802| 1) |v_ULTIMATE.start_main_~i~0#1_801|)) (not (= (mod (select .cse0 (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 32)) 2) 0))))) is different from false [2022-11-18 20:23:12,733 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 94 [2022-11-18 20:23:12,761 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 20:23:12,762 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 12121 treesize of output 12025 [2022-11-18 20:23:22,272 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 12 not checked. [2022-11-18 20:23:22,272 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1803039097] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:23:22,273 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:23:22,273 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 32, 32] total 89 [2022-11-18 20:23:22,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686084352] [2022-11-18 20:23:22,273 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:23:22,273 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:23:22,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:23:22,274 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 5 times [2022-11-18 20:23:22,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:23:22,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585968083] [2022-11-18 20:23:22,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:23:22,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:23:22,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:23:22,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:23:22,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:23:22,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:23:22,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:23:22,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2022-11-18 20:23:22,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=443, Invalid=7363, Unknown=30, NotChecked=174, Total=8010 [2022-11-18 20:23:22,476 INFO L87 Difference]: Start difference. First operand 163 states and 208 transitions. cyclomatic complexity: 52 Second operand has 90 states, 89 states have (on average 2.202247191011236) internal successors, (196), 90 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:23:27,229 WARN L230 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) stderr output: (error "out of memory") [2022-11-18 20:23:27,230 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 101 [2022-11-18 20:23:27,231 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:243) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:262) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.smtlibutils.ManagedScript.checkSat(ManagedScript.java:139) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:85) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:898) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:772) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:346) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:391) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:230) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.getOrConstructPredicate(DeterministicInterpolantAutomaton.java:282) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.constructSuccessorsAndTransitions(DeterministicInterpolantAutomaton.java:304) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:79) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:233) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:246) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:218) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:210) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1058) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:960) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:182) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.cegar.BuchiAutomatonCegarLoop.refineFinite(BuchiAutomatonCegarLoop.java:177) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.cegar.BuchiAutomatonCegarLoop.refineFinite(BuchiAutomatonCegarLoop.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.cegar.AbstractBuchiCegarLoop.refineFiniteInternal(AbstractBuchiCegarLoop.java:472) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.cegar.AbstractBuchiCegarLoop.runCegarLoop(AbstractBuchiCegarLoop.java:401) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.runCegarLoops(BuchiAutomizerObserver.java:136) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:157) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:341) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1465) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:658) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:239) ... 43 more [2022-11-18 20:23:27,234 INFO L158 Benchmark]: Toolchain (without parser) took 777000.61ms. Allocated memory was 132.1MB in the beginning and 551.6MB in the end (delta: 419.4MB). Free memory was 95.9MB in the beginning and 313.7MB in the end (delta: -217.8MB). Peak memory consumption was 202.4MB. Max. memory is 16.1GB. [2022-11-18 20:23:27,234 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 132.1MB. Free memory was 105.1MB in the beginning and 105.1MB in the end (delta: 27.1kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 20:23:27,234 INFO L158 Benchmark]: CACSL2BoogieTranslator took 447.86ms. Allocated memory is still 132.1MB. Free memory was 95.6MB in the beginning and 98.9MB in the end (delta: -3.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-18 20:23:27,234 INFO L158 Benchmark]: Boogie Procedure Inliner took 42.55ms. Allocated memory is still 132.1MB. Free memory was 98.9MB in the beginning and 97.3MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-18 20:23:27,235 INFO L158 Benchmark]: Boogie Preprocessor took 44.03ms. Allocated memory is still 132.1MB. Free memory was 97.3MB in the beginning and 96.1MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 20:23:27,235 INFO L158 Benchmark]: RCFGBuilder took 382.36ms. Allocated memory is still 132.1MB. Free memory was 96.1MB in the beginning and 84.8MB in the end (delta: 11.3MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-18 20:23:27,235 INFO L158 Benchmark]: BuchiAutomizer took 776075.69ms. Allocated memory was 132.1MB in the beginning and 551.6MB in the end (delta: 419.4MB). Free memory was 84.8MB in the beginning and 313.7MB in the end (delta: -228.9MB). Peak memory consumption was 192.2MB. Max. memory is 16.1GB. [2022-11-18 20:23:27,237 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 132.1MB. Free memory was 105.1MB in the beginning and 105.1MB in the end (delta: 27.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 447.86ms. Allocated memory is still 132.1MB. Free memory was 95.6MB in the beginning and 98.9MB in the end (delta: -3.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 42.55ms. Allocated memory is still 132.1MB. Free memory was 98.9MB in the beginning and 97.3MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 44.03ms. Allocated memory is still 132.1MB. Free memory was 97.3MB in the beginning and 96.1MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 382.36ms. Allocated memory is still 132.1MB. Free memory was 96.1MB in the beginning and 84.8MB in the end (delta: 11.3MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 776075.69ms. Allocated memory was 132.1MB in the beginning and 551.6MB in the end (delta: 419.4MB). Free memory was 84.8MB in the beginning and 313.7MB in the end (delta: -228.9MB). Peak memory consumption was 192.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:243) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2022-11-18 20:23:27,255 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:27,461 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:27,659 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:27,860 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:28,061 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:28,261 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:28,461 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:28,661 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:28,860 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:29,062 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:29,261 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:29,460 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:29,661 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:29,862 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:30,062 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:30,262 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:30,462 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:30,662 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:30,863 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:31,075 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:31,263 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2022-11-18 20:23:31,463 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:31,666 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:31,863 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2022-11-18 20:23:32,064 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Ended with exit code 0 [2022-11-18 20:23:32,265 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2022-11-18 20:23:32,464 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Ended with exit code 0 [2022-11-18 20:23:32,664 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2022-11-18 20:23:32,864 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2022-11-18 20:23:33,064 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:33,265 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:33,464 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2022-11-18 20:23:33,665 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:33,865 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:34,065 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2022-11-18 20:23:34,266 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:34,465 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:34,665 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2022-11-18 20:23:34,865 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2022-11-18 20:23:35,066 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:35,266 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2022-11-18 20:23:35,465 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:35,666 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2022-11-18 20:23:35,866 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:36,066 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2022-11-18 20:23:36,266 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2022-11-18 20:23:36,466 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2022-11-18 20:23:36,666 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2022-11-18 20:23:36,866 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2022-11-18 20:23:37,067 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2022-11-18 20:23:37,267 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2022-11-18 20:23:37,467 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2022-11-18 20:23:37,667 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:37,867 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2022-11-18 20:23:38,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2022-11-18 20:23:38,267 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-11-18 20:23:38,468 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/config using search string *Termination*64bit*_Bitvector*.epf No suitable settings file found using Termination*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_030a65e4-c09e-4b7f-8019-86a409756758/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory")