./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_3-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_3-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42bdab47928922c9249a376933fe7b7a33d855d426cfe04eb271066ef5c44d0a --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 20:39:15,006 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 20:39:15,009 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 20:39:15,052 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 20:39:15,052 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 20:39:15,058 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 20:39:15,061 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 20:39:15,065 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 20:39:15,069 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 20:39:15,073 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 20:39:15,075 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 20:39:15,078 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 20:39:15,079 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 20:39:15,088 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 20:39:15,089 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 20:39:15,090 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 20:39:15,093 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 20:39:15,094 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 20:39:15,097 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 20:39:15,104 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 20:39:15,106 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 20:39:15,111 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 20:39:15,112 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 20:39:15,114 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 20:39:15,119 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 20:39:15,125 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 20:39:15,126 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 20:39:15,127 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 20:39:15,129 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 20:39:15,130 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 20:39:15,131 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 20:39:15,132 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 20:39:15,134 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 20:39:15,136 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 20:39:15,138 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 20:39:15,139 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 20:39:15,140 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 20:39:15,141 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 20:39:15,141 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 20:39:15,142 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 20:39:15,142 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 20:39:15,143 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-18 20:39:15,195 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 20:39:15,198 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 20:39:15,199 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 20:39:15,199 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 20:39:15,201 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 20:39:15,201 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 20:39:15,202 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 20:39:15,202 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 20:39:15,202 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 20:39:15,203 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 20:39:15,204 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 20:39:15,205 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 20:39:15,205 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 20:39:15,205 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 20:39:15,205 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 20:39:15,206 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 20:39:15,206 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 20:39:15,206 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 20:39:15,206 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 20:39:15,207 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 20:39:15,207 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 20:39:15,207 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 20:39:15,208 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 20:39:15,208 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 20:39:15,210 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 20:39:15,211 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 20:39:15,211 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 20:39:15,211 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 20:39:15,212 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 20:39:15,212 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 20:39:15,212 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 20:39:15,214 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 20:39:15,214 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42bdab47928922c9249a376933fe7b7a33d855d426cfe04eb271066ef5c44d0a [2022-11-18 20:39:15,560 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 20:39:15,600 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 20:39:15,603 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 20:39:15,604 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 20:39:15,608 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 20:39:15,610 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/loop-acceleration/array_3-2.i [2022-11-18 20:39:15,709 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/data/4d9af6b42/fa24aba4435e4020b46716af73efeab4/FLAG328ed82a3 [2022-11-18 20:39:16,312 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 20:39:16,314 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/sv-benchmarks/c/loop-acceleration/array_3-2.i [2022-11-18 20:39:16,321 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/data/4d9af6b42/fa24aba4435e4020b46716af73efeab4/FLAG328ed82a3 [2022-11-18 20:39:16,657 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/data/4d9af6b42/fa24aba4435e4020b46716af73efeab4 [2022-11-18 20:39:16,661 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 20:39:16,662 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 20:39:16,664 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 20:39:16,664 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 20:39:16,669 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 20:39:16,670 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:16,671 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@19408818 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16, skipping insertion in model container [2022-11-18 20:39:16,672 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:16,680 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 20:39:16,698 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 20:39:16,893 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/sv-benchmarks/c/loop-acceleration/array_3-2.i[809,822] [2022-11-18 20:39:16,916 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:39:16,926 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 20:39:16,942 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/sv-benchmarks/c/loop-acceleration/array_3-2.i[809,822] [2022-11-18 20:39:16,955 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:39:16,970 INFO L208 MainTranslator]: Completed translation [2022-11-18 20:39:16,970 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16 WrapperNode [2022-11-18 20:39:16,971 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 20:39:16,972 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 20:39:16,972 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 20:39:16,972 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 20:39:16,981 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:16,990 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,009 INFO L138 Inliner]: procedures = 16, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 46 [2022-11-18 20:39:17,010 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 20:39:17,010 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 20:39:17,010 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 20:39:17,010 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 20:39:17,017 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,018 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,019 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,019 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,024 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,029 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,030 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,031 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,033 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 20:39:17,034 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 20:39:17,041 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 20:39:17,042 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 20:39:17,043 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (1/1) ... [2022-11-18 20:39:17,051 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:17,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:17,081 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:17,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 20:39:17,125 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-18 20:39:17,125 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-18 20:39:17,125 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 20:39:17,125 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 20:39:17,125 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 20:39:17,125 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 20:39:17,126 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 20:39:17,126 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 20:39:17,197 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 20:39:17,199 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 20:39:17,342 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 20:39:17,349 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 20:39:17,349 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 20:39:17,351 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:39:17 BoogieIcfgContainer [2022-11-18 20:39:17,352 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 20:39:17,353 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 20:39:17,353 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 20:39:17,358 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 20:39:17,358 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:39:17,359 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 08:39:16" (1/3) ... [2022-11-18 20:39:17,360 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ee03423 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:39:17, skipping insertion in model container [2022-11-18 20:39:17,360 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:39:17,360 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:39:16" (2/3) ... [2022-11-18 20:39:17,361 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ee03423 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:39:17, skipping insertion in model container [2022-11-18 20:39:17,361 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 20:39:17,361 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:39:17" (3/3) ... [2022-11-18 20:39:17,362 INFO L332 chiAutomizerObserver]: Analyzing ICFG array_3-2.i [2022-11-18 20:39:17,426 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 20:39:17,427 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 20:39:17,427 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 20:39:17,427 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 20:39:17,427 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 20:39:17,427 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 20:39:17,428 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 20:39:17,428 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 20:39:17,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:17,475 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-11-18 20:39:17,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:17,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:17,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 20:39:17,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:39:17,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 20:39:17,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:17,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-11-18 20:39:17,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:17,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:17,496 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 20:39:17,496 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 20:39:17,521 INFO L748 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 13#L23-3true [2022-11-18 20:39:17,521 INFO L750 eck$LassoCheckResult]: Loop: 13#L23-3true assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 11#L23-2true main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 13#L23-3true [2022-11-18 20:39:17,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:17,529 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-18 20:39:17,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:17,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324041421] [2022-11-18 20:39:17,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:17,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:17,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:17,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:17,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:17,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-11-18 20:39:17,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:17,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271027255] [2022-11-18 20:39:17,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:17,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:17,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,879 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:17,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:17,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:17,892 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-11-18 20:39:17,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:17,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082102043] [2022-11-18 20:39:17,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:17,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:17,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:17,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:17,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:18,470 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 20:39:18,471 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 20:39:18,471 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 20:39:18,472 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 20:39:18,472 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 20:39:18,472 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:18,473 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 20:39:18,473 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 20:39:18,473 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_3-2.i_Iteration1_Lasso [2022-11-18 20:39:18,474 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 20:39:18,474 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 20:39:18,497 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,507 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,512 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,750 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,753 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,757 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,760 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:18,763 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 20:39:19,047 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 20:39:19,052 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 20:39:19,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,060 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,062 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 20:39:19,063 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,079 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,080 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:39:19,080 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,080 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,081 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,083 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:39:19,083 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:39:19,094 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:39:19,100 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:19,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,103 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 20:39:19,109 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,125 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,126 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,126 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,126 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,130 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:39:19,130 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:39:19,142 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:39:19,152 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:19,153 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,153 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,155 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,166 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 20:39:19,166 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,182 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,182 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,182 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,182 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,186 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:39:19,186 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:39:19,208 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:39:19,217 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:19,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,219 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 20:39:19,224 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,237 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,237 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 20:39:19,238 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,238 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,238 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,239 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 20:39:19,239 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 20:39:19,248 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:39:19,256 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:19,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,257 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,258 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,268 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 20:39:19,283 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,283 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,283 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,283 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,288 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:39:19,288 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:39:19,306 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 20:39:19,320 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:19,320 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,320 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,322 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 20:39:19,331 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 20:39:19,346 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 20:39:19,346 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 20:39:19,346 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 20:39:19,346 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 20:39:19,353 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 20:39:19,354 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 20:39:19,369 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 20:39:19,410 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2022-11-18 20:39:19,410 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2022-11-18 20:39:19,412 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 20:39:19,413 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:19,436 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 20:39:19,446 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 20:39:19,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 20:39:19,496 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 20:39:19,496 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 20:39:19,496 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1) = -8*ULTIMATE.start_main_~i~0#1 + 2047*v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1 Supporting invariants [] [2022-11-18 20:39:19,505 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-11-18 20:39:19,533 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-11-18 20:39:19,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:19,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:19,591 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 20:39:19,592 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:19,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:19,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 20:39:19,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:19,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:19,722 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 20:39:19,724 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:19,771 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 16 states, 15 states have (on average 1.4) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 31 states and 43 transitions. Complement of second has 8 states. [2022-11-18 20:39:19,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 20:39:19,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:19,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 21 transitions. [2022-11-18 20:39:19,790 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 2 letters. Loop has 2 letters. [2022-11-18 20:39:19,790 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:39:19,791 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 4 letters. Loop has 2 letters. [2022-11-18 20:39:19,791 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:39:19,791 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 21 transitions. Stem has 2 letters. Loop has 4 letters. [2022-11-18 20:39:19,791 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 20:39:19,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 43 transitions. [2022-11-18 20:39:19,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:19,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 10 states and 13 transitions. [2022-11-18 20:39:19,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-11-18 20:39:19,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-11-18 20:39:19,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 13 transitions. [2022-11-18 20:39:19,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:19,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2022-11-18 20:39:19,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 13 transitions. [2022-11-18 20:39:19,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2022-11-18 20:39:19,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:19,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2022-11-18 20:39:19,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2022-11-18 20:39:19,837 INFO L428 stractBuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2022-11-18 20:39:19,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 20:39:19,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2022-11-18 20:39:19,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:19,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:19,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:19,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-18 20:39:19,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:19,840 INFO L748 eck$LassoCheckResult]: Stem: 108#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 109#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 115#L23-3 assume !(main_~i~0#1 < 1024); 114#L23-4 main_~i~0#1 := 0; 106#L26-6 [2022-11-18 20:39:19,840 INFO L750 eck$LassoCheckResult]: Loop: 106#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 107#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 112#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 113#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 106#L26-6 [2022-11-18 20:39:19,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:19,841 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-11-18 20:39:19,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:19,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660681402] [2022-11-18 20:39:19,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:19,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:19,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:19,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:19,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:19,908 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660681402] [2022-11-18 20:39:19,908 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1660681402] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 20:39:19,909 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 20:39:19,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 20:39:19,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241553644] [2022-11-18 20:39:19,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 20:39:19,912 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:19,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:19,913 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 1 times [2022-11-18 20:39:19,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:19,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840162396] [2022-11-18 20:39:19,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:19,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:19,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:19,922 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:19,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:19,928 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:20,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:20,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 20:39:20,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 20:39:20,034 INFO L87 Difference]: Start difference. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:20,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:20,062 INFO L93 Difference]: Finished difference Result 15 states and 18 transitions. [2022-11-18 20:39:20,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 18 transitions. [2022-11-18 20:39:20,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:20,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 18 transitions. [2022-11-18 20:39:20,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-18 20:39:20,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-18 20:39:20,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 18 transitions. [2022-11-18 20:39:20,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:20,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 18 transitions. [2022-11-18 20:39:20,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 18 transitions. [2022-11-18 20:39:20,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 10. [2022-11-18 20:39:20,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.2) internal successors, (12), 9 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:20,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 12 transitions. [2022-11-18 20:39:20,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 12 transitions. [2022-11-18 20:39:20,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 20:39:20,069 INFO L428 stractBuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2022-11-18 20:39:20,069 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 20:39:20,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 12 transitions. [2022-11-18 20:39:20,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:20,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:20,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:20,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-11-18 20:39:20,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:20,071 INFO L748 eck$LassoCheckResult]: Stem: 139#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 146#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 141#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 142#L23-3 assume !(main_~i~0#1 < 1024); 145#L23-4 main_~i~0#1 := 0; 137#L26-6 [2022-11-18 20:39:20,071 INFO L750 eck$LassoCheckResult]: Loop: 137#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 138#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 143#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 144#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 137#L26-6 [2022-11-18 20:39:20,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:20,072 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2022-11-18 20:39:20,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:20,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102037529] [2022-11-18 20:39:20,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:20,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:20,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:20,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-18 20:39:20,176 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:20,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102037529] [2022-11-18 20:39:20,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102037529] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:20,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [183219154] [2022-11-18 20:39:20,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:20,178 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:20,178 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:20,180 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:20,208 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-18 20:39:20,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:20,252 INFO L263 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-18 20:39:20,253 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:20,270 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,271 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:39:20,298 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,299 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [183219154] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:39:20,299 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:39:20,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2022-11-18 20:39:20,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062733939] [2022-11-18 20:39:20,300 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:39:20,300 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:20,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:20,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 2 times [2022-11-18 20:39:20,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:20,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065941708] [2022-11-18 20:39:20,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:20,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:20,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:20,320 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:20,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:20,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:20,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:20,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-18 20:39:20,438 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-18 20:39:20,439 INFO L87 Difference]: Start difference. First operand 10 states and 12 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:20,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:20,510 INFO L93 Difference]: Finished difference Result 32 states and 38 transitions. [2022-11-18 20:39:20,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 38 transitions. [2022-11-18 20:39:20,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:20,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 32 states and 38 transitions. [2022-11-18 20:39:20,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2022-11-18 20:39:20,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24 [2022-11-18 20:39:20,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2022-11-18 20:39:20,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:20,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2022-11-18 20:39:20,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2022-11-18 20:39:20,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 16. [2022-11-18 20:39:20,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.125) internal successors, (18), 15 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:20,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 18 transitions. [2022-11-18 20:39:20,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 18 transitions. [2022-11-18 20:39:20,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 20:39:20,524 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2022-11-18 20:39:20,525 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 20:39:20,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 18 transitions. [2022-11-18 20:39:20,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:20,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:20,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:20,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2022-11-18 20:39:20,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:20,528 INFO L748 eck$LassoCheckResult]: Stem: 221#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 222#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 228#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 223#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 224#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 229#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 234#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 233#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 232#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 231#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 230#L23-3 assume !(main_~i~0#1 < 1024); 227#L23-4 main_~i~0#1 := 0; 219#L26-6 [2022-11-18 20:39:20,529 INFO L750 eck$LassoCheckResult]: Loop: 219#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 220#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 225#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 226#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 219#L26-6 [2022-11-18 20:39:20,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:20,529 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 2 times [2022-11-18 20:39:20,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:20,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864882398] [2022-11-18 20:39:20,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:20,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:20,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:20,660 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:20,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864882398] [2022-11-18 20:39:20,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864882398] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:20,661 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1386915951] [2022-11-18 20:39:20,661 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:39:20,662 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:20,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:20,663 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:20,705 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-18 20:39:20,768 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:39:20,768 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:39:20,769 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 20:39:20,771 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:20,809 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,809 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:39:20,898 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:20,899 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1386915951] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:39:20,899 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:39:20,899 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2022-11-18 20:39:20,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119402532] [2022-11-18 20:39:20,900 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:39:20,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:20,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:20,902 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 3 times [2022-11-18 20:39:20,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:20,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122215590] [2022-11-18 20:39:20,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:20,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:20,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:20,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:20,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:20,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:21,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:21,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-18 20:39:21,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-18 20:39:21,033 INFO L87 Difference]: Start difference. First operand 16 states and 18 transitions. cyclomatic complexity: 4 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:21,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:21,174 INFO L93 Difference]: Finished difference Result 68 states and 80 transitions. [2022-11-18 20:39:21,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 80 transitions. [2022-11-18 20:39:21,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:21,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 68 states and 80 transitions. [2022-11-18 20:39:21,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48 [2022-11-18 20:39:21,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48 [2022-11-18 20:39:21,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 80 transitions. [2022-11-18 20:39:21,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:21,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68 states and 80 transitions. [2022-11-18 20:39:21,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 80 transitions. [2022-11-18 20:39:21,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 28. [2022-11-18 20:39:21,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0714285714285714) internal successors, (30), 27 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:21,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 30 transitions. [2022-11-18 20:39:21,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 30 transitions. [2022-11-18 20:39:21,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 20:39:21,182 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2022-11-18 20:39:21,182 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 20:39:21,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 30 transitions. [2022-11-18 20:39:21,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:21,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:21,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:21,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2022-11-18 20:39:21,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:21,184 INFO L748 eck$LassoCheckResult]: Stem: 387#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 394#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 389#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 390#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 395#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 412#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 411#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 410#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 409#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 408#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 407#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 406#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 405#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 404#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 403#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 402#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 401#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 400#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 399#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 398#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 397#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 396#L23-3 assume !(main_~i~0#1 < 1024); 393#L23-4 main_~i~0#1 := 0; 385#L26-6 [2022-11-18 20:39:21,185 INFO L750 eck$LassoCheckResult]: Loop: 385#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 386#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 391#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 392#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 385#L26-6 [2022-11-18 20:39:21,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:21,185 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 3 times [2022-11-18 20:39:21,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:21,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394612712] [2022-11-18 20:39:21,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:21,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:21,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:21,508 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:21,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:21,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394612712] [2022-11-18 20:39:21,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394612712] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:21,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [807904211] [2022-11-18 20:39:21,509 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:39:21,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:21,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:21,516 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:21,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-18 20:39:21,657 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 20:39:21,657 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:39:21,659 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 20:39:21,661 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:21,752 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:21,752 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:39:22,018 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:22,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [807904211] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:39:22,019 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:39:22,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2022-11-18 20:39:22,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96516285] [2022-11-18 20:39:22,020 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:39:22,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:22,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:22,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 4 times [2022-11-18 20:39:22,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:22,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852183719] [2022-11-18 20:39:22,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:22,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:22,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:22,032 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:22,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:22,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:22,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:22,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-18 20:39:22,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-18 20:39:22,127 INFO L87 Difference]: Start difference. First operand 28 states and 30 transitions. cyclomatic complexity: 4 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:22,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:22,408 INFO L93 Difference]: Finished difference Result 140 states and 164 transitions. [2022-11-18 20:39:22,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 164 transitions. [2022-11-18 20:39:22,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:22,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 140 states and 164 transitions. [2022-11-18 20:39:22,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96 [2022-11-18 20:39:22,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96 [2022-11-18 20:39:22,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 164 transitions. [2022-11-18 20:39:22,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:22,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 164 transitions. [2022-11-18 20:39:22,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 164 transitions. [2022-11-18 20:39:22,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 52. [2022-11-18 20:39:22,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0384615384615385) internal successors, (54), 51 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:22,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 54 transitions. [2022-11-18 20:39:22,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 54 transitions. [2022-11-18 20:39:22,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 20:39:22,437 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2022-11-18 20:39:22,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 20:39:22,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 54 transitions. [2022-11-18 20:39:22,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:22,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:22,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:22,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2022-11-18 20:39:22,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:22,443 INFO L748 eck$LassoCheckResult]: Stem: 721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 728#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 723#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 724#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 729#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 770#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 769#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 768#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 767#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 766#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 765#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 764#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 763#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 762#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 761#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 760#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 759#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 758#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 757#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 756#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 755#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 754#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 753#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 752#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 751#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 750#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 749#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 748#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 747#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 746#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 745#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 744#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 743#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 742#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 741#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 740#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 739#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 738#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 737#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 736#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 735#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 734#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 733#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 732#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 731#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 730#L23-3 assume !(main_~i~0#1 < 1024); 727#L23-4 main_~i~0#1 := 0; 719#L26-6 [2022-11-18 20:39:22,443 INFO L750 eck$LassoCheckResult]: Loop: 719#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 720#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 725#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 726#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 719#L26-6 [2022-11-18 20:39:22,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:22,445 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 4 times [2022-11-18 20:39:22,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:22,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754483673] [2022-11-18 20:39:22,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:22,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:22,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:23,153 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:23,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:23,153 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754483673] [2022-11-18 20:39:23,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754483673] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:23,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [857348415] [2022-11-18 20:39:23,154 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:39:23,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:23,154 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:23,158 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:23,180 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-18 20:39:23,286 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:39:23,286 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:39:23,288 INFO L263 TraceCheckSpWp]: Trace formula consists of 280 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 20:39:23,291 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:23,402 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:23,402 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:39:24,359 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:24,360 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [857348415] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:39:24,360 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:39:24,360 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2022-11-18 20:39:24,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472747461] [2022-11-18 20:39:24,361 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:39:24,361 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:24,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:24,362 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 5 times [2022-11-18 20:39:24,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:24,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174866108] [2022-11-18 20:39:24,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:24,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:24,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:24,367 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:24,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:24,371 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:24,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:24,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 20:39:24,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 20:39:24,454 INFO L87 Difference]: Start difference. First operand 52 states and 54 transitions. cyclomatic complexity: 4 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:25,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:25,091 INFO L93 Difference]: Finished difference Result 284 states and 332 transitions. [2022-11-18 20:39:25,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 332 transitions. [2022-11-18 20:39:25,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:25,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 332 transitions. [2022-11-18 20:39:25,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192 [2022-11-18 20:39:25,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192 [2022-11-18 20:39:25,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 332 transitions. [2022-11-18 20:39:25,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:25,098 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 332 transitions. [2022-11-18 20:39:25,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 332 transitions. [2022-11-18 20:39:25,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 100. [2022-11-18 20:39:25,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.02) internal successors, (102), 99 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:25,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 102 transitions. [2022-11-18 20:39:25,128 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 102 transitions. [2022-11-18 20:39:25,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-18 20:39:25,130 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2022-11-18 20:39:25,131 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 20:39:25,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 102 transitions. [2022-11-18 20:39:25,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:25,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:25,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:25,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2022-11-18 20:39:25,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:25,136 INFO L748 eck$LassoCheckResult]: Stem: 1391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 1392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 1398#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1393#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1394#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1399#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1488#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1487#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1486#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1485#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1484#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1483#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1482#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1481#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1480#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1479#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1478#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1477#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1476#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1475#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1474#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1473#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1472#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1471#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1470#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1469#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1468#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1467#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1466#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1465#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1464#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1463#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1462#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1461#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1460#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1459#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1458#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1457#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1456#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1455#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1454#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1453#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1452#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1451#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1450#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1449#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1448#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1447#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1446#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1445#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1444#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1443#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1442#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1441#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1440#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1439#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1438#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1437#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1436#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1435#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1434#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1433#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1432#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1431#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1430#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1429#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1428#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1427#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1426#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1425#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1424#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1423#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1422#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1421#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1420#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1419#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1418#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1417#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1416#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1415#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1414#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1413#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1412#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1411#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1410#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1409#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1408#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1407#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1406#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1405#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1404#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1403#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1402#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1401#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1400#L23-3 assume !(main_~i~0#1 < 1024); 1397#L23-4 main_~i~0#1 := 0; 1389#L26-6 [2022-11-18 20:39:25,140 INFO L750 eck$LassoCheckResult]: Loop: 1389#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 1390#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 1395#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 1396#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1389#L26-6 [2022-11-18 20:39:25,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:25,141 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 5 times [2022-11-18 20:39:25,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:25,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661986101] [2022-11-18 20:39:25,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:25,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:25,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:27,878 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:27,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:27,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661986101] [2022-11-18 20:39:27,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661986101] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:27,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [902438293] [2022-11-18 20:39:27,879 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:39:27,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:27,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:27,883 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:27,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-18 20:39:32,326 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-11-18 20:39:32,326 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:39:32,336 INFO L263 TraceCheckSpWp]: Trace formula consists of 544 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-18 20:39:32,341 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:39:32,627 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:32,627 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:39:36,300 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:36,303 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [902438293] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:39:36,303 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 20:39:36,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2022-11-18 20:39:36,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526210008] [2022-11-18 20:39:36,304 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 20:39:36,309 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 20:39:36,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:36,310 INFO L85 PathProgramCache]: Analyzing trace with hash 1542438, now seen corresponding path program 6 times [2022-11-18 20:39:36,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:36,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925757986] [2022-11-18 20:39:36,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:36,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:36,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:36,337 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:39:36,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:39:36,340 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:39:36,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:39:36,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-18 20:39:36,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-18 20:39:36,433 INFO L87 Difference]: Start difference. First operand 100 states and 102 transitions. cyclomatic complexity: 4 Second operand has 97 states, 97 states have (on average 1.9896907216494846) internal successors, (193), 97 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:38,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:39:38,875 INFO L93 Difference]: Finished difference Result 572 states and 668 transitions. [2022-11-18 20:39:38,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 572 states and 668 transitions. [2022-11-18 20:39:38,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:38,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 572 states to 572 states and 668 transitions. [2022-11-18 20:39:38,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2022-11-18 20:39:38,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-11-18 20:39:38,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 572 states and 668 transitions. [2022-11-18 20:39:38,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 20:39:38,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 572 states and 668 transitions. [2022-11-18 20:39:38,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states and 668 transitions. [2022-11-18 20:39:38,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 196. [2022-11-18 20:39:38,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.010204081632653) internal successors, (198), 195 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:39:38,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 198 transitions. [2022-11-18 20:39:38,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 198 transitions. [2022-11-18 20:39:38,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-18 20:39:38,899 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 198 transitions. [2022-11-18 20:39:38,899 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 20:39:38,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 198 transitions. [2022-11-18 20:39:38,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2022-11-18 20:39:38,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 20:39:38,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 20:39:38,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1] [2022-11-18 20:39:38,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-11-18 20:39:38,925 INFO L748 eck$LassoCheckResult]: Stem: 2733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2); 2734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_#t~short5#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 2740#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2735#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2736#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2741#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2926#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2925#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2924#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2923#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2922#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2921#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2920#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2919#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2918#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2917#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2916#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2915#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2914#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2913#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2912#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2911#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2910#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2909#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2908#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2907#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2906#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2905#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2904#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2903#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2902#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2901#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2900#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2899#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2898#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2897#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2896#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2895#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2894#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2893#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2892#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2891#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2890#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2889#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2888#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2887#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2886#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2885#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2884#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2883#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2882#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2881#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2880#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2879#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2878#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2877#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2876#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2875#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2874#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2873#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2872#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2871#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2870#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2869#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2868#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2867#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2866#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2865#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2864#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2863#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2862#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2861#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2860#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2859#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2858#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2857#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2856#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2855#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2854#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2853#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2852#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2851#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2850#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2849#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2848#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2847#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2846#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2845#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2844#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2843#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2842#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2841#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2840#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2839#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2838#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2837#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2836#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2835#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2834#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2833#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2832#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2831#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2830#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2829#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2828#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2827#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2826#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2825#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2824#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2823#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2822#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2821#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2820#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2819#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2818#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2817#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2816#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2815#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2814#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2813#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2812#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2811#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2810#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2809#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2808#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2807#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2806#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2805#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2804#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2803#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2802#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2801#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2800#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2799#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2798#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2797#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2796#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2795#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2794#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2793#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2792#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2791#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2790#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2789#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2788#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2787#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2786#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2785#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2784#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2783#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2782#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2781#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2780#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2779#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2778#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2777#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2776#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2775#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2774#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2773#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2772#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2771#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2770#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2769#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2768#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2767#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2766#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2765#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2764#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2763#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2762#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2761#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2760#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2759#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2758#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2757#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2756#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2755#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2754#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2753#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2752#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2751#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2750#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2749#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2748#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2747#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2746#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2745#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2744#L23-3 assume !!(main_~i~0#1 < 1024);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2743#L23-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2742#L23-3 assume !(main_~i~0#1 < 1024); 2739#L23-4 main_~i~0#1 := 0; 2731#L26-6 [2022-11-18 20:39:38,925 INFO L750 eck$LassoCheckResult]: Loop: 2731#L26-6 main_#t~short5#1 := main_~i~0#1 < 1024; 2732#L26-1 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);main_#t~short5#1 := 0 != main_#t~mem4#1; 2737#L26-3 assume !!main_#t~short5#1;havoc main_#t~mem4#1;havoc main_#t~short5#1; 2738#L26-5 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2731#L26-6 [2022-11-18 20:39:38,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:39:38,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1165371207, now seen corresponding path program 6 times [2022-11-18 20:39:38,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:39:38,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631822056] [2022-11-18 20:39:38,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:39:38,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:39:39,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:39:47,046 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:39:47,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:39:47,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631822056] [2022-11-18 20:39:47,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631822056] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 20:39:47,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [699318267] [2022-11-18 20:39:47,047 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:39:47,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 20:39:47,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:39:47,049 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 20:39:47,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_20f2ef0b-bd0e-4ec1-8303-2cae9da3b1e2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process