./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_4.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_4.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e8c27e61ac5d5a22c0e00a5dbac1b872460567877a501387ed9d5bda89096498 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 18:32:01,387 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 18:32:01,389 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 18:32:01,420 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 18:32:01,424 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 18:32:01,429 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 18:32:01,432 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 18:32:01,434 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 18:32:01,436 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 18:32:01,437 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 18:32:01,438 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 18:32:01,439 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 18:32:01,440 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 18:32:01,441 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 18:32:01,442 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 18:32:01,444 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 18:32:01,444 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 18:32:01,446 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 18:32:01,447 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 18:32:01,450 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 18:32:01,451 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 18:32:01,453 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 18:32:01,454 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 18:32:01,455 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 18:32:01,459 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 18:32:01,459 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 18:32:01,460 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 18:32:01,461 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 18:32:01,461 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 18:32:01,462 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 18:32:01,462 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 18:32:01,463 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 18:32:01,464 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 18:32:01,465 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 18:32:01,466 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 18:32:01,466 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 18:32:01,467 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 18:32:01,468 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 18:32:01,468 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 18:32:01,469 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 18:32:01,470 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 18:32:01,476 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-18 18:32:01,515 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 18:32:01,518 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 18:32:01,519 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 18:32:01,520 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 18:32:01,521 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 18:32:01,521 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 18:32:01,522 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 18:32:01,522 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-18 18:32:01,522 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-18 18:32:01,522 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-18 18:32:01,524 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-18 18:32:01,524 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-18 18:32:01,524 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-18 18:32:01,524 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 18:32:01,525 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 18:32:01,525 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 18:32:01,525 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 18:32:01,525 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 18:32:01,526 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 18:32:01,526 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-18 18:32:01,526 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-18 18:32:01,526 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-18 18:32:01,526 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 18:32:01,527 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 18:32:01,527 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-18 18:32:01,527 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 18:32:01,527 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-18 18:32:01,528 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 18:32:01,528 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 18:32:01,528 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 18:32:01,528 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 18:32:01,530 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-18 18:32:01,530 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e8c27e61ac5d5a22c0e00a5dbac1b872460567877a501387ed9d5bda89096498 [2022-11-18 18:32:01,846 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 18:32:01,882 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 18:32:01,884 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 18:32:01,886 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 18:32:01,886 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 18:32:01,888 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/loop-acceleration/array_4.i [2022-11-18 18:32:01,972 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/data/513fb216b/8f049d189c304f89bf634d0758827a25/FLAGb881eb852 [2022-11-18 18:32:02,475 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 18:32:02,476 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/sv-benchmarks/c/loop-acceleration/array_4.i [2022-11-18 18:32:02,483 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/data/513fb216b/8f049d189c304f89bf634d0758827a25/FLAGb881eb852 [2022-11-18 18:32:02,826 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/data/513fb216b/8f049d189c304f89bf634d0758827a25 [2022-11-18 18:32:02,829 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 18:32:02,831 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 18:32:02,833 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 18:32:02,833 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 18:32:02,836 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 18:32:02,837 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:32:02" (1/1) ... [2022-11-18 18:32:02,838 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b8384e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:02, skipping insertion in model container [2022-11-18 18:32:02,839 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:32:02" (1/1) ... [2022-11-18 18:32:02,850 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 18:32:02,868 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 18:32:03,164 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/sv-benchmarks/c/loop-acceleration/array_4.i[848,861] [2022-11-18 18:32:03,183 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:32:03,203 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 18:32:03,225 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/sv-benchmarks/c/loop-acceleration/array_4.i[848,861] [2022-11-18 18:32:03,235 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:32:03,255 INFO L208 MainTranslator]: Completed translation [2022-11-18 18:32:03,256 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03 WrapperNode [2022-11-18 18:32:03,257 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 18:32:03,258 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 18:32:03,258 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 18:32:03,258 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 18:32:03,272 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,282 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,310 INFO L138 Inliner]: procedures = 16, calls = 12, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 42 [2022-11-18 18:32:03,310 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 18:32:03,311 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 18:32:03,311 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 18:32:03,311 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 18:32:03,319 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,319 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,321 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,321 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,327 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,331 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,332 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,333 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,335 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 18:32:03,336 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 18:32:03,336 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 18:32:03,336 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 18:32:03,337 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (1/1) ... [2022-11-18 18:32:03,355 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:03,367 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:03,379 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:03,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-18 18:32:03,427 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-18 18:32:03,427 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-18 18:32:03,427 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 18:32:03,427 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 18:32:03,428 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 18:32:03,428 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 18:32:03,428 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 18:32:03,428 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 18:32:03,499 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 18:32:03,501 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 18:32:03,636 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 18:32:03,643 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 18:32:03,643 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 18:32:03,645 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:32:03 BoogieIcfgContainer [2022-11-18 18:32:03,645 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 18:32:03,646 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-18 18:32:03,646 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-18 18:32:03,664 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-18 18:32:03,665 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:03,666 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 06:32:02" (1/3) ... [2022-11-18 18:32:03,667 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b1b2d11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:32:03, skipping insertion in model container [2022-11-18 18:32:03,667 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:03,667 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:32:03" (2/3) ... [2022-11-18 18:32:03,667 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b1b2d11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 06:32:03, skipping insertion in model container [2022-11-18 18:32:03,667 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-18 18:32:03,668 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:32:03" (3/3) ... [2022-11-18 18:32:03,669 INFO L332 chiAutomizerObserver]: Analyzing ICFG array_4.i [2022-11-18 18:32:03,739 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-18 18:32:03,740 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-18 18:32:03,740 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-18 18:32:03,740 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-18 18:32:03,740 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-18 18:32:03,740 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-18 18:32:03,741 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-18 18:32:03,741 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-18 18:32:03,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:03,767 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:32:03,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:03,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:03,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 18:32:03,774 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:03,774 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-18 18:32:03,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:03,776 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-18 18:32:03,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:03,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:03,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-11-18 18:32:03,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-18 18:32:03,786 INFO L748 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 6#L25-3true [2022-11-18 18:32:03,786 INFO L750 eck$LassoCheckResult]: Loop: 6#L25-3true assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 9#L25-2true main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 6#L25-3true [2022-11-18 18:32:03,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:03,793 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-11-18 18:32:03,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:03,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502834576] [2022-11-18 18:32:03,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:03,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:03,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:03,913 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:03,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:03,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:03,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:03,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-11-18 18:32:03,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:03,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458653329] [2022-11-18 18:32:03,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:03,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:03,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:03,971 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:03,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:03,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:03,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:03,983 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-11-18 18:32:03,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:03,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725625336] [2022-11-18 18:32:03,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:03,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:04,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:04,054 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:04,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:04,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:04,525 INFO L210 LassoAnalysis]: Preferences: [2022-11-18 18:32:04,526 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-18 18:32:04,526 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-18 18:32:04,526 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-18 18:32:04,527 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-18 18:32:04,527 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:04,527 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-18 18:32:04,527 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-18 18:32:04,528 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_4.i_Iteration1_Lasso [2022-11-18 18:32:04,528 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-18 18:32:04,528 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-18 18:32:04,559 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,571 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,574 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,910 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,914 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,919 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:04,922 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-18 18:32:05,216 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-18 18:32:05,222 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-18 18:32:05,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,231 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-18 18:32:05,251 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,267 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,267 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,267 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,268 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,276 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,278 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,303 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,312 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,315 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,325 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-18 18:32:05,340 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,340 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:05,341 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,341 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,341 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,342 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:05,343 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:05,371 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,376 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2022-11-18 18:32:05,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,376 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,380 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,388 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-18 18:32:05,402 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,402 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,402 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,402 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,406 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,407 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,419 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,428 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,429 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,429 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,431 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,435 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-18 18:32:05,436 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,451 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,451 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:05,451 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,451 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,452 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,453 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:05,453 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:05,467 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,478 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,478 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,478 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,480 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,493 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-18 18:32:05,508 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,509 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,509 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,509 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,513 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,513 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,535 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,544 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,545 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,545 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,547 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,551 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-18 18:32:05,551 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,565 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,566 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,566 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,566 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,573 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,573 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,590 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,595 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,595 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,602 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,608 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,623 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-18 18:32:05,623 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,627 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,628 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,640 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,649 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,650 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,652 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,661 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-18 18:32:05,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,676 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,676 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,676 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,684 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,684 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,703 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,711 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,712 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,714 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,725 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-18 18:32:05,739 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,740 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,740 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,740 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,743 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,743 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,763 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,772 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,774 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,779 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-18 18:32:05,793 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,793 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,794 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,794 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,797 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,797 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,810 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,823 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,826 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,831 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-11-18 18:32:05,846 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,846 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-18 18:32:05,846 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,846 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,846 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,847 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-18 18:32:05,847 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-18 18:32:05,856 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,870 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,871 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,872 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,876 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-11-18 18:32:05,893 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,894 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,894 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,894 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,902 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,903 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,914 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,931 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,933 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,943 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:05,945 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-11-18 18:32:05,954 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:05,954 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:05,955 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:05,955 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:05,959 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:05,959 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:05,972 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-18 18:32:05,981 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:05,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:05,981 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:05,982 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:05,997 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-18 18:32:06,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2022-11-18 18:32:06,011 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-18 18:32:06,011 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-18 18:32:06,011 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-18 18:32:06,011 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-18 18:32:06,025 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-18 18:32:06,025 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-18 18:32:06,047 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-18 18:32:06,112 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-11-18 18:32:06,112 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2022-11-18 18:32:06,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-18 18:32:06,114 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:06,115 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-18 18:32:06,140 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2022-11-18 18:32:06,140 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-18 18:32:06,176 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-18 18:32:06,176 INFO L513 LassoAnalysis]: Proved termination. [2022-11-18 18:32:06,177 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1) = -8*ULTIMATE.start_main_~i~0#1 + 2045*v_rep(select #length ULTIMATE.start_main_~#A~0#1.base)_1 Supporting invariants [] [2022-11-18 18:32:06,186 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:06,216 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-11-18 18:32:06,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:06,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:06,272 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 18:32:06,274 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:06,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:06,293 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 18:32:06,295 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:06,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:06,409 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-18 18:32:06,412 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:06,477 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 29 states and 39 transitions. Complement of second has 8 states. [2022-11-18 18:32:06,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-18 18:32:06,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:06,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 19 transitions. [2022-11-18 18:32:06,491 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 2 letters. Loop has 2 letters. [2022-11-18 18:32:06,491 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:06,491 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 4 letters. Loop has 2 letters. [2022-11-18 18:32:06,492 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:06,492 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 2 letters. Loop has 4 letters. [2022-11-18 18:32:06,492 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-18 18:32:06,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 39 transitions. [2022-11-18 18:32:06,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:06,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 9 states and 11 transitions. [2022-11-18 18:32:06,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-11-18 18:32:06,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-11-18 18:32:06,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2022-11-18 18:32:06,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:06,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 11 transitions. [2022-11-18 18:32:06,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2022-11-18 18:32:06,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2022-11-18 18:32:06,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:06,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2022-11-18 18:32:06,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 11 transitions. [2022-11-18 18:32:06,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2022-11-18 18:32:06,533 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-18 18:32:06,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 11 transitions. [2022-11-18 18:32:06,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:06,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:06,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:06,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-11-18 18:32:06,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:06,535 INFO L748 eck$LassoCheckResult]: Stem: 107#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 109#L25-3 assume !(main_~i~0#1 < 1023); 110#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 111#L30-4 [2022-11-18 18:32:06,535 INFO L750 eck$LassoCheckResult]: Loop: 111#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 103#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 104#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 111#L30-4 [2022-11-18 18:32:06,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:06,536 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-11-18 18:32:06,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:06,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145733104] [2022-11-18 18:32:06,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:06,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:06,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:06,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:06,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:06,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145733104] [2022-11-18 18:32:06,611 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145733104] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:32:06,611 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:32:06,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 18:32:06,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [582015626] [2022-11-18 18:32:06,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:32:06,614 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:06,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:06,615 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 1 times [2022-11-18 18:32:06,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:06,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777874222] [2022-11-18 18:32:06,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:06,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:06,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:06,622 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:06,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:06,628 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:06,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:06,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 18:32:06,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:32:06,674 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. cyclomatic complexity: 4 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:06,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:06,695 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2022-11-18 18:32:06,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2022-11-18 18:32:06,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:06,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 14 transitions. [2022-11-18 18:32:06,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2022-11-18 18:32:06,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2022-11-18 18:32:06,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 14 transitions. [2022-11-18 18:32:06,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:06,699 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-11-18 18:32:06,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 14 transitions. [2022-11-18 18:32:06,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 9. [2022-11-18 18:32:06,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:06,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2022-11-18 18:32:06,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-11-18 18:32:06,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 18:32:06,707 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-11-18 18:32:06,707 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-18 18:32:06,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2022-11-18 18:32:06,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:06,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:06,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:06,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-11-18 18:32:06,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:06,709 INFO L748 eck$LassoCheckResult]: Stem: 135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 137#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 133#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 134#L25-3 assume !(main_~i~0#1 < 1023); 138#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 139#L30-4 [2022-11-18 18:32:06,709 INFO L750 eck$LassoCheckResult]: Loop: 139#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 131#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 132#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 139#L30-4 [2022-11-18 18:32:06,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:06,710 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2022-11-18 18:32:06,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:06,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584780274] [2022-11-18 18:32:06,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:06,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:06,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:06,821 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:06,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:06,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584780274] [2022-11-18 18:32:06,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584780274] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:06,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1313863053] [2022-11-18 18:32:06,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:06,823 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:06,823 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:06,824 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:06,855 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-18 18:32:06,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:06,895 INFO L263 TraceCheckSpWp]: Trace formula consists of 57 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-18 18:32:06,895 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:06,908 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:06,908 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:06,938 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:06,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1313863053] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:06,939 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:06,939 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2022-11-18 18:32:06,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334734975] [2022-11-18 18:32:06,939 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:06,940 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:06,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:06,940 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 2 times [2022-11-18 18:32:06,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:06,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963050569] [2022-11-18 18:32:06,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:06,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:06,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:06,972 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:06,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:06,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:06,997 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2022-11-18 18:32:07,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:07,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-18 18:32:07,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:32:07,058 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:07,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:07,168 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2022-11-18 18:32:07,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2022-11-18 18:32:07,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:07,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2022-11-18 18:32:07,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-18 18:32:07,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-18 18:32:07,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2022-11-18 18:32:07,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:07,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-18 18:32:07,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2022-11-18 18:32:07,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 15. [2022-11-18 18:32:07,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:07,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2022-11-18 18:32:07,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-11-18 18:32:07,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 18:32:07,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-11-18 18:32:07,179 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-18 18:32:07,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2022-11-18 18:32:07,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:07,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:07,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:07,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2022-11-18 18:32:07,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:07,184 INFO L748 eck$LassoCheckResult]: Stem: 211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 213#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 209#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 210#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 214#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 221#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 220#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 219#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 218#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 217#L25-3 assume !(main_~i~0#1 < 1023); 215#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 216#L30-4 [2022-11-18 18:32:07,184 INFO L750 eck$LassoCheckResult]: Loop: 216#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 207#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 208#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 216#L30-4 [2022-11-18 18:32:07,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:07,186 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 2 times [2022-11-18 18:32:07,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:07,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062976856] [2022-11-18 18:32:07,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:07,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:07,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:07,347 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:07,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:07,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062976856] [2022-11-18 18:32:07,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2062976856] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:07,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1458140189] [2022-11-18 18:32:07,348 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:32:07,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:07,348 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:07,349 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:07,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-18 18:32:07,427 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:32:07,427 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:32:07,429 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-18 18:32:07,430 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:07,458 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:07,458 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:07,530 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:07,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1458140189] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:07,530 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:07,530 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2022-11-18 18:32:07,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369710485] [2022-11-18 18:32:07,531 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:07,531 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:07,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:07,532 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 3 times [2022-11-18 18:32:07,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:07,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707343225] [2022-11-18 18:32:07,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:07,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:07,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:07,538 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:07,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:07,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:07,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:07,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-18 18:32:07,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-11-18 18:32:07,586 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:07,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:07,701 INFO L93 Difference]: Finished difference Result 57 states and 58 transitions. [2022-11-18 18:32:07,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 58 transitions. [2022-11-18 18:32:07,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:07,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 58 transitions. [2022-11-18 18:32:07,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2022-11-18 18:32:07,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2022-11-18 18:32:07,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 58 transitions. [2022-11-18 18:32:07,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:07,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 58 transitions. [2022-11-18 18:32:07,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 58 transitions. [2022-11-18 18:32:07,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 27. [2022-11-18 18:32:07,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:07,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2022-11-18 18:32:07,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-18 18:32:07,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 18:32:07,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-11-18 18:32:07,711 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-18 18:32:07,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2022-11-18 18:32:07,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:07,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:07,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:07,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2022-11-18 18:32:07,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:07,714 INFO L748 eck$LassoCheckResult]: Stem: 365#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 367#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 363#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 364#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 368#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 387#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 386#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 385#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 384#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 383#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 382#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 381#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 380#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 379#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 378#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 377#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 376#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 375#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 374#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 373#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 372#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 371#L25-3 assume !(main_~i~0#1 < 1023); 369#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 370#L30-4 [2022-11-18 18:32:07,714 INFO L750 eck$LassoCheckResult]: Loop: 370#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 361#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 362#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 370#L30-4 [2022-11-18 18:32:07,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:07,715 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 3 times [2022-11-18 18:32:07,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:07,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572129762] [2022-11-18 18:32:07,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:07,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:07,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:07,998 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:07,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:07,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572129762] [2022-11-18 18:32:07,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572129762] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:07,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1982139231] [2022-11-18 18:32:07,999 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:32:08,000 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:08,000 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:08,034 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:08,042 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-18 18:32:08,269 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-18 18:32:08,270 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:32:08,272 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 18:32:08,274 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:08,346 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:08,347 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:08,684 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:08,684 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1982139231] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:08,685 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:08,685 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2022-11-18 18:32:08,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359031886] [2022-11-18 18:32:08,685 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:08,686 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:08,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:08,686 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 4 times [2022-11-18 18:32:08,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:08,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922030423] [2022-11-18 18:32:08,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:08,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:08,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:08,693 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:08,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:08,698 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:08,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:08,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-11-18 18:32:08,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-11-18 18:32:08,756 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:09,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:09,012 INFO L93 Difference]: Finished difference Result 117 states and 118 transitions. [2022-11-18 18:32:09,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 118 transitions. [2022-11-18 18:32:09,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:09,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 118 transitions. [2022-11-18 18:32:09,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2022-11-18 18:32:09,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2022-11-18 18:32:09,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 118 transitions. [2022-11-18 18:32:09,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:09,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 118 transitions. [2022-11-18 18:32:09,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 118 transitions. [2022-11-18 18:32:09,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 51. [2022-11-18 18:32:09,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:09,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2022-11-18 18:32:09,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-11-18 18:32:09,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 18:32:09,043 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-11-18 18:32:09,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-18 18:32:09,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2022-11-18 18:32:09,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:09,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:09,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:09,049 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2022-11-18 18:32:09,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:09,050 INFO L748 eck$LassoCheckResult]: Stem: 675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 677#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 673#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 674#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 678#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 721#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 720#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 719#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 718#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 717#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 716#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 715#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 714#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 713#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 712#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 711#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 710#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 709#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 708#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 707#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 706#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 705#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 704#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 703#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 702#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 701#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 700#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 699#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 698#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 697#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 696#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 695#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 694#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 693#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 692#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 691#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 690#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 689#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 688#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 687#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 686#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 685#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 684#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 683#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 682#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 681#L25-3 assume !(main_~i~0#1 < 1023); 679#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 680#L30-4 [2022-11-18 18:32:09,050 INFO L750 eck$LassoCheckResult]: Loop: 680#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 671#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 672#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 680#L30-4 [2022-11-18 18:32:09,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:09,050 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 4 times [2022-11-18 18:32:09,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:09,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158206033] [2022-11-18 18:32:09,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:09,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:09,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:09,925 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:09,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:09,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158206033] [2022-11-18 18:32:09,926 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158206033] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:09,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [99619254] [2022-11-18 18:32:09,926 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:32:09,926 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:09,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:09,931 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:09,943 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-18 18:32:10,061 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:32:10,061 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:32:10,063 INFO L263 TraceCheckSpWp]: Trace formula consists of 288 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 18:32:10,065 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:32:10,178 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:10,179 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:32:11,102 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:11,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [99619254] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:32:11,103 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:32:11,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2022-11-18 18:32:11,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028037931] [2022-11-18 18:32:11,103 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:32:11,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:32:11,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:11,104 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 5 times [2022-11-18 18:32:11,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:11,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380805058] [2022-11-18 18:32:11,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:11,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:11,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:11,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:32:11,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:32:11,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:32:11,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:32:11,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-18 18:32:11,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-11-18 18:32:11,165 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:11,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:32:11,791 INFO L93 Difference]: Finished difference Result 237 states and 238 transitions. [2022-11-18 18:32:11,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 237 states and 238 transitions. [2022-11-18 18:32:11,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:11,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 237 states to 237 states and 238 transitions. [2022-11-18 18:32:11,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145 [2022-11-18 18:32:11,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145 [2022-11-18 18:32:11,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 237 states and 238 transitions. [2022-11-18 18:32:11,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:32:11,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 237 states and 238 transitions. [2022-11-18 18:32:11,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states and 238 transitions. [2022-11-18 18:32:11,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 99. [2022-11-18 18:32:11,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:32:11,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2022-11-18 18:32:11,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-11-18 18:32:11,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-11-18 18:32:11,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-11-18 18:32:11,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-18 18:32:11,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2022-11-18 18:32:11,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:32:11,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:32:11,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:32:11,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2022-11-18 18:32:11,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:32:11,815 INFO L748 eck$LassoCheckResult]: Stem: 1297#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 1298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 1299#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1295#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1296#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1300#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1391#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1390#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1389#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1388#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1387#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1386#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1385#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1384#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1383#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1382#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1381#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1380#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1379#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1378#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1377#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1376#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1375#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1374#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1373#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1372#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1371#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1370#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1369#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1368#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1367#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1366#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1365#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1364#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1363#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1362#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1361#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1360#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1359#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1358#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1357#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1356#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1355#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1354#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1353#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1352#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1351#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1350#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1349#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1348#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1347#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1346#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1345#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1344#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1343#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1342#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1341#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1340#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1339#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1338#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1337#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1336#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1335#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1334#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1333#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1332#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1331#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1330#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1329#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1328#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1327#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1326#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1325#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1324#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1323#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1322#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1321#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1320#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1319#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1318#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1317#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1316#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1315#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1314#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1313#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1312#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1311#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1310#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1309#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1308#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1307#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1306#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1305#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1304#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1303#L25-3 assume !(main_~i~0#1 < 1023); 1301#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 1302#L30-4 [2022-11-18 18:32:11,816 INFO L750 eck$LassoCheckResult]: Loop: 1302#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 1293#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 1294#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 1302#L30-4 [2022-11-18 18:32:11,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:32:11,817 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 5 times [2022-11-18 18:32:11,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:32:11,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288513737] [2022-11-18 18:32:11,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:32:11,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:32:11,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:32:14,140 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:32:14,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:32:14,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288513737] [2022-11-18 18:32:14,140 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288513737] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:32:14,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [16121003] [2022-11-18 18:32:14,141 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:32:14,141 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:32:14,141 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:32:14,147 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:32:14,173 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-18 18:33:11,653 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-11-18 18:33:11,653 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:33:11,683 INFO L263 TraceCheckSpWp]: Trace formula consists of 552 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-18 18:33:11,688 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:33:11,911 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:11,911 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:33:15,239 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:15,239 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [16121003] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:33:15,239 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:33:15,239 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2022-11-18 18:33:15,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563029685] [2022-11-18 18:33:15,240 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:33:15,241 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-18 18:33:15,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:15,241 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 6 times [2022-11-18 18:33:15,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:15,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764101760] [2022-11-18 18:33:15,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:15,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:15,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:15,261 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 18:33:15,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 18:33:15,268 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 18:33:15,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:33:15,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-11-18 18:33:15,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-11-18 18:33:15,314 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 1.9896907216494846) internal successors, (193), 97 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:17,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:33:17,484 INFO L93 Difference]: Finished difference Result 477 states and 478 transitions. [2022-11-18 18:33:17,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 477 states and 478 transitions. [2022-11-18 18:33:17,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:33:17,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 477 states to 477 states and 478 transitions. [2022-11-18 18:33:17,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 289 [2022-11-18 18:33:17,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 289 [2022-11-18 18:33:17,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 477 states and 478 transitions. [2022-11-18 18:33:17,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-18 18:33:17,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 477 states and 478 transitions. [2022-11-18 18:33:17,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states and 478 transitions. [2022-11-18 18:33:17,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 195. [2022-11-18 18:33:17,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:33:17,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2022-11-18 18:33:17,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-11-18 18:33:17,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-11-18 18:33:17,506 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-11-18 18:33:17,506 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-18 18:33:17,506 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2022-11-18 18:33:17,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-11-18 18:33:17,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-18 18:33:17,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-18 18:33:17,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1] [2022-11-18 18:33:17,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-18 18:33:17,514 INFO L748 eck$LassoCheckResult]: Stem: 2543#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(10, 2); 2544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet2#1, main_#t~post1#1, main_#t~post3#1, main_#t~mem4#1, main_~#A~0#1.base, main_~#A~0#1.offset, main_~i~0#1;call main_~#A~0#1.base, main_~#A~0#1.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0#1;main_~i~0#1 := 0; 2545#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2541#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2542#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2546#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2733#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2732#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2731#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2730#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2729#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2728#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2727#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2726#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2725#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2724#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2723#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2722#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2721#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2720#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2719#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2718#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2717#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2716#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2715#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2714#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2713#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2712#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2711#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2710#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2709#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2708#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2707#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2706#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2705#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2704#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2703#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2702#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2701#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2700#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2699#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2698#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2697#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2696#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2695#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2694#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2693#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2692#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2691#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2690#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2689#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2688#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2687#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2686#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2685#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2684#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2683#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2682#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2681#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2680#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2679#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2678#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2677#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2676#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2675#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2674#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2673#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2672#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2671#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2670#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2669#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2668#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2667#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2666#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2665#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2664#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2663#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2662#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2661#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2660#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2659#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2658#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2657#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2656#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2655#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2654#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2653#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2652#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2651#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2650#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2649#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2648#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2647#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2646#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2645#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2644#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2643#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2642#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2641#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2640#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2639#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2638#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2637#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2636#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2635#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2634#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2633#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2632#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2631#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2630#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2629#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2628#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2627#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2626#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2625#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2624#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2623#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2622#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2621#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2620#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2619#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2618#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2617#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2616#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2615#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2614#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2613#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2612#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2611#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2610#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2609#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2608#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2607#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2606#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2605#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2604#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2603#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2602#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2601#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2600#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2599#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2598#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2597#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2596#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2595#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2594#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2593#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2592#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2591#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2590#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2589#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2588#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2587#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2586#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2585#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2584#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2583#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2582#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2581#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2580#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2579#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2578#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2577#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2576#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2575#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2574#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2573#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2572#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2571#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2570#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2569#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2568#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2567#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2566#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2565#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2564#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2563#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2562#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2561#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2560#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2559#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2558#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2557#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2556#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2555#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2554#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2553#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2552#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2551#L25-3 assume !!(main_~i~0#1 < 1023);call write~int(main_#t~nondet2#1, main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2550#L25-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2549#L25-3 assume !(main_~i~0#1 < 1023); 2547#L25-4 call write~int(0, main_~#A~0#1.base, 4092 + main_~#A~0#1.offset, 4);main_~i~0#1 := 0; 2548#L30-4 [2022-11-18 18:33:17,514 INFO L750 eck$LassoCheckResult]: Loop: 2548#L30-4 call main_#t~mem4#1 := read~int(main_~#A~0#1.base, main_~#A~0#1.offset + 4 * main_~i~0#1, 4); 2539#L30-1 assume !!(0 != main_#t~mem4#1);havoc main_#t~mem4#1; 2540#L30-3 main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1; 2548#L30-4 [2022-11-18 18:33:17,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:33:17,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1165371207, now seen corresponding path program 6 times [2022-11-18 18:33:17,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:33:17,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490560831] [2022-11-18 18:33:17,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:33:17,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:33:17,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:33:25,288 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:33:25,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:33:25,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490560831] [2022-11-18 18:33:25,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490560831] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:33:25,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1355828734] [2022-11-18 18:33:25,289 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:33:25,289 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:33:25,289 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:33:25,290 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:33:25,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6030e221-796b-45a8-9e09-365c0d540bc2/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process