./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 8730d6ec4fcbc5f6df390d4be768126ffa92771ead17d97dfd39e0d222630fca --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 20:49:47,476 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 20:49:47,478 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 20:49:47,498 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 20:49:47,499 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 20:49:47,500 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 20:49:47,501 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 20:49:47,503 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 20:49:47,505 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 20:49:47,506 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 20:49:47,507 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 20:49:47,509 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 20:49:47,509 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 20:49:47,510 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 20:49:47,512 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 20:49:47,513 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 20:49:47,514 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 20:49:47,515 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 20:49:47,517 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 20:49:47,519 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 20:49:47,520 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 20:49:47,524 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 20:49:47,525 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 20:49:47,526 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 20:49:47,529 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 20:49:47,530 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 20:49:47,530 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 20:49:47,531 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 20:49:47,532 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 20:49:47,533 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 20:49:47,533 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 20:49:47,534 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 20:49:47,535 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 20:49:47,536 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 20:49:47,537 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 20:49:47,537 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 20:49:47,538 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 20:49:47,539 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 20:49:47,539 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 20:49:47,540 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 20:49:47,541 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 20:49:47,542 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-11-18 20:49:47,563 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 20:49:47,563 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 20:49:47,563 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 20:49:47,564 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 20:49:47,564 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-18 20:49:47,565 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-18 20:49:47,565 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 20:49:47,565 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 20:49:47,566 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 20:49:47,566 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 20:49:47,566 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 20:49:47,566 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 20:49:47,566 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-18 20:49:47,567 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-18 20:49:47,567 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-18 20:49:47,567 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 20:49:47,567 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 20:49:47,567 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-18 20:49:47,568 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 20:49:47,568 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 20:49:47,568 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-18 20:49:47,568 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 20:49:47,569 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 20:49:47,569 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-18 20:49:47,569 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-18 20:49:47,569 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 20:49:47,569 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-18 20:49:47,570 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-11-18 20:49:47,570 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-11-18 20:49:47,570 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-18 20:49:47,570 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8730d6ec4fcbc5f6df390d4be768126ffa92771ead17d97dfd39e0d222630fca [2022-11-18 20:49:47,800 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 20:49:47,821 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 20:49:47,823 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 20:49:47,825 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 20:49:47,825 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 20:49:47,827 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:47,898 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/9710886f3/fc98ae324e5248788b117f31a8e32fda/FLAG9943baa7c [2022-11-18 20:49:48,375 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 20:49:48,375 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:48,385 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/9710886f3/fc98ae324e5248788b117f31a8e32fda/FLAG9943baa7c [2022-11-18 20:49:48,727 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/9710886f3/fc98ae324e5248788b117f31a8e32fda [2022-11-18 20:49:48,729 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 20:49:48,731 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 20:49:48,732 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 20:49:48,735 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 20:49:48,746 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 20:49:48,746 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:49:48" (1/1) ... [2022-11-18 20:49:48,749 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@279242a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:48, skipping insertion in model container [2022-11-18 20:49:48,749 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:49:48" (1/1) ... [2022-11-18 20:49:48,757 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 20:49:48,815 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 20:49:49,051 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c[1107,1120] [2022-11-18 20:49:49,277 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:49:49,288 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 20:49:49,298 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c[1107,1120] [2022-11-18 20:49:49,414 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:49:49,441 INFO L208 MainTranslator]: Completed translation [2022-11-18 20:49:49,442 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49 WrapperNode [2022-11-18 20:49:49,443 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 20:49:49,445 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 20:49:49,445 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 20:49:49,445 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 20:49:49,453 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,478 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,562 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 604 [2022-11-18 20:49:49,562 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 20:49:49,574 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 20:49:49,575 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 20:49:49,575 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 20:49:49,584 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,584 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,590 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,590 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,606 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,610 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,615 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,619 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,626 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 20:49:49,626 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 20:49:49,627 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 20:49:49,627 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 20:49:49,647 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (1/1) ... [2022-11-18 20:49:49,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 20:49:49,666 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:49:49,695 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-18 20:49:49,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-18 20:49:49,750 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 20:49:49,750 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 20:49:49,981 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 20:49:49,983 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 20:49:53,019 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 20:49:53,030 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 20:49:53,030 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-18 20:49:53,032 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:53 BoogieIcfgContainer [2022-11-18 20:49:53,033 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 20:49:53,037 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-18 20:49:53,037 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-18 20:49:53,041 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-18 20:49:53,041 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 08:49:48" (1/3) ... [2022-11-18 20:49:53,042 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73f960f9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 08:49:53, skipping insertion in model container [2022-11-18 20:49:53,042 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:49" (2/3) ... [2022-11-18 20:49:53,043 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73f960f9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 08:49:53, skipping insertion in model container [2022-11-18 20:49:53,043 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:53" (3/3) ... [2022-11-18 20:49:53,051 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:53,073 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-18 20:49:53,073 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-18 20:49:53,144 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-18 20:49:53,153 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@1e12a171, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-18 20:49:53,154 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-18 20:49:53,158 INFO L276 IsEmpty]: Start isEmpty. Operand has 41 states, 39 states have (on average 1.6153846153846154) internal successors, (63), 40 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:49:53,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-11-18 20:49:53,168 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:49:53,169 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:49:53,170 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:49:53,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:49:53,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1428179117, now seen corresponding path program 1 times [2022-11-18 20:49:53,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:49:53,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708531415] [2022-11-18 20:49:53,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:49:53,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:49:53,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:49:53,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:49:53,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 20:49:53,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708531415] [2022-11-18 20:49:53,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1708531415] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 20:49:53,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 20:49:53,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 20:49:53,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336861770] [2022-11-18 20:49:53,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 20:49:53,658 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 20:49:53,658 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 20:49:53,687 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 20:49:53,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 20:49:53,693 INFO L87 Difference]: Start difference. First operand has 41 states, 39 states have (on average 1.6153846153846154) internal successors, (63), 40 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:49:53,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:49:53,799 INFO L93 Difference]: Finished difference Result 121 states and 197 transitions. [2022-11-18 20:49:53,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 20:49:53,801 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 13 [2022-11-18 20:49:53,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:49:53,810 INFO L225 Difference]: With dead ends: 121 [2022-11-18 20:49:53,810 INFO L226 Difference]: Without dead ends: 82 [2022-11-18 20:49:53,813 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 20:49:53,817 INFO L413 NwaCegarLoop]: 75 mSDtfsCounter, 147 mSDsluCounter, 88 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 147 SdHoareTripleChecker+Valid, 163 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 20:49:53,818 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [147 Valid, 163 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-18 20:49:53,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2022-11-18 20:49:53,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 39. [2022-11-18 20:49:53,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 38 states have (on average 1.5526315789473684) internal successors, (59), 38 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:49:53,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 59 transitions. [2022-11-18 20:49:53,853 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 59 transitions. Word has length 13 [2022-11-18 20:49:53,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:49:53,854 INFO L495 AbstractCegarLoop]: Abstraction has 39 states and 59 transitions. [2022-11-18 20:49:53,854 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:49:53,855 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 59 transitions. [2022-11-18 20:49:53,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-11-18 20:49:53,855 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:49:53,856 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 20:49:53,856 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-18 20:49:53,856 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:49:53,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:49:53,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1325604663, now seen corresponding path program 1 times [2022-11-18 20:49:53,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 20:49:53,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468816157] [2022-11-18 20:49:53,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:49:53,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 20:49:53,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:49:53,877 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:49:53,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:49:53,919 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-18 20:49:53,919 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-18 20:49:53,921 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-18 20:49:53,923 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-18 20:49:53,927 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-18 20:49:53,931 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-18 20:49:53,955 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:49:53,964 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 08:49:53 BoogieIcfgContainer [2022-11-18 20:49:53,964 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-18 20:49:53,965 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-18 20:49:53,965 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-18 20:49:53,965 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-18 20:49:53,966 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:53" (3/4) ... [2022-11-18 20:49:53,969 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-18 20:49:53,970 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-18 20:49:53,971 INFO L158 Benchmark]: Toolchain (without parser) took 5239.70ms. Allocated memory was 157.3MB in the beginning and 199.2MB in the end (delta: 41.9MB). Free memory was 127.3MB in the beginning and 96.9MB in the end (delta: 30.3MB). Peak memory consumption was 71.0MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,971 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 100.7MB. Free memory is still 56.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 20:49:53,972 INFO L158 Benchmark]: CACSL2BoogieTranslator took 711.51ms. Allocated memory is still 157.3MB. Free memory was 127.3MB in the beginning and 121.1MB in the end (delta: 6.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,972 INFO L158 Benchmark]: Boogie Procedure Inliner took 118.00ms. Allocated memory is still 157.3MB. Free memory was 120.6MB in the beginning and 114.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,973 INFO L158 Benchmark]: Boogie Preprocessor took 51.47ms. Allocated memory is still 157.3MB. Free memory was 114.3MB in the beginning and 110.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,974 INFO L158 Benchmark]: RCFGBuilder took 3406.33ms. Allocated memory was 157.3MB in the beginning and 199.2MB in the end (delta: 41.9MB). Free memory was 110.6MB in the beginning and 145.2MB in the end (delta: -34.6MB). Peak memory consumption was 108.3MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,974 INFO L158 Benchmark]: TraceAbstraction took 927.71ms. Allocated memory is still 199.2MB. Free memory was 145.2MB in the beginning and 96.9MB in the end (delta: 48.2MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. [2022-11-18 20:49:53,975 INFO L158 Benchmark]: Witness Printer took 4.73ms. Allocated memory is still 199.2MB. Free memory is still 96.9MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 20:49:53,977 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 100.7MB. Free memory is still 56.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 711.51ms. Allocated memory is still 157.3MB. Free memory was 127.3MB in the beginning and 121.1MB in the end (delta: 6.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 118.00ms. Allocated memory is still 157.3MB. Free memory was 120.6MB in the beginning and 114.3MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 51.47ms. Allocated memory is still 157.3MB. Free memory was 114.3MB in the beginning and 110.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 3406.33ms. Allocated memory was 157.3MB in the beginning and 199.2MB in the end (delta: 41.9MB). Free memory was 110.6MB in the beginning and 145.2MB in the end (delta: -34.6MB). Peak memory consumption was 108.3MB. Max. memory is 16.1GB. * TraceAbstraction took 927.71ms. Allocated memory is still 199.2MB. Free memory was 145.2MB in the beginning and 96.9MB in the end (delta: 48.2MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. * Witness Printer took 4.73ms. Allocated memory is still 199.2MB. Free memory is still 96.9MB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 92, overapproximation of bitwiseAnd at line 97. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 8); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (8 - 1); [L28] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 1); [L29] const SORT_5 msb_SORT_5 = (SORT_5)1 << (1 - 1); [L31] const SORT_5 var_7 = 0; [L32] const SORT_5 var_13 = 1; [L33] const SORT_1 var_33 = 0; [L34] const SORT_1 var_42 = 4; [L35] const SORT_1 var_54 = 5; [L36] const SORT_1 var_193 = 3; [L37] const SORT_1 var_199 = 2; [L39] SORT_1 input_2; [L40] SORT_1 input_3; [L41] SORT_1 input_4; [L42] SORT_5 input_6; [L43] SORT_1 input_38; [L45] SORT_5 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L46] SORT_5 state_17 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L47] SORT_5 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L48] SORT_5 state_21 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L49] SORT_5 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L50] SORT_5 state_25 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L51] SORT_5 state_27 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L52] SORT_5 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L53] SORT_5 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L54] SORT_1 state_34 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L55] SORT_1 state_36 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L57] SORT_5 init_9_arg_1 = var_7; [L58] state_8 = init_9_arg_1 [L59] SORT_5 init_18_arg_1 = var_13; [L60] state_17 = init_18_arg_1 [L61] SORT_5 init_20_arg_1 = var_7; [L62] state_19 = init_20_arg_1 [L63] SORT_5 init_22_arg_1 = var_7; [L64] state_21 = init_22_arg_1 [L65] SORT_5 init_24_arg_1 = var_7; [L66] state_23 = init_24_arg_1 [L67] SORT_5 init_26_arg_1 = var_7; [L68] state_25 = init_26_arg_1 [L69] SORT_5 init_28_arg_1 = var_7; [L70] state_27 = init_28_arg_1 [L71] SORT_5 init_30_arg_1 = var_7; [L72] state_29 = init_30_arg_1 [L73] SORT_5 init_32_arg_1 = var_13; [L74] state_31 = init_32_arg_1 [L75] SORT_1 init_35_arg_1 = var_33; [L76] state_34 = init_35_arg_1 [L77] SORT_1 init_37_arg_1 = var_33; [L78] state_36 = init_37_arg_1 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_13=1, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_13=1, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_13=1, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_4=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_13=1, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=2, input_4=0, input_6=1, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_10=0, var_10_arg_0=0, var_13=1, var_14=255, var_14_arg_0=0, var_15=1, var_15_arg_0=1, var_15_arg_1=255, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L98] var_15 = var_15 & mask_SORT_5 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=2, input_4=0, input_6=1, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_10=0, var_10_arg_0=0, var_13=1, var_14=255, var_14_arg_0=0, var_15=1, var_15_arg_0=1, var_15_arg_1=255, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 41 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 0.8s, OverallIterations: 2, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 0.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 147 SdHoareTripleChecker+Valid, 0.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 147 mSDsluCounter, 163 SdHoareTripleChecker+Invalid, 0.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 88 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 17 IncrementalHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 75 mSDtfsCounter, 17 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=41occurred in iteration=0, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 43 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.3s InterpolantComputationTime, 27 NumberOfCodeBlocks, 27 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 12 ConstructedInterpolants, 0 QuantifiedInterpolants, 17 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-18 20:49:54,004 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 8730d6ec4fcbc5f6df390d4be768126ffa92771ead17d97dfd39e0d222630fca --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 20:49:56,342 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 20:49:56,345 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 20:49:56,378 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 20:49:56,379 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 20:49:56,380 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 20:49:56,382 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 20:49:56,384 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 20:49:56,386 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 20:49:56,387 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 20:49:56,388 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 20:49:56,389 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 20:49:56,390 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 20:49:56,391 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 20:49:56,392 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 20:49:56,394 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 20:49:56,395 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 20:49:56,396 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 20:49:56,398 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 20:49:56,400 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 20:49:56,402 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 20:49:56,403 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 20:49:56,405 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 20:49:56,406 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 20:49:56,410 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 20:49:56,410 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 20:49:56,411 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 20:49:56,412 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 20:49:56,412 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 20:49:56,414 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 20:49:56,414 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 20:49:56,415 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 20:49:56,416 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 20:49:56,417 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 20:49:56,418 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 20:49:56,419 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 20:49:56,420 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 20:49:56,420 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 20:49:56,421 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 20:49:56,422 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 20:49:56,423 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 20:49:56,424 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2022-11-18 20:49:56,447 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 20:49:56,447 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 20:49:56,448 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 20:49:56,448 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 20:49:56,449 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-18 20:49:56,450 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-18 20:49:56,450 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 20:49:56,451 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 20:49:56,451 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 20:49:56,452 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 20:49:56,452 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 20:49:56,452 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-18 20:49:56,453 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-18 20:49:56,453 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-18 20:49:56,453 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-18 20:49:56,454 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-18 20:49:56,454 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-18 20:49:56,454 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-18 20:49:56,454 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 20:49:56,455 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-18 20:49:56,455 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 20:49:56,455 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 20:49:56,456 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-18 20:49:56,456 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 20:49:56,456 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 20:49:56,457 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-18 20:49:56,457 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-18 20:49:56,457 INFO L138 SettingsManager]: * Trace refinement strategy=WOLF [2022-11-18 20:49:56,457 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-18 20:49:56,458 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-11-18 20:49:56,458 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-11-18 20:49:56,458 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-18 20:49:56,458 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-18 20:49:56,459 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8730d6ec4fcbc5f6df390d4be768126ffa92771ead17d97dfd39e0d222630fca [2022-11-18 20:49:56,799 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 20:49:56,821 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 20:49:56,824 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 20:49:56,825 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 20:49:56,826 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 20:49:56,828 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:56,901 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/93a030093/b0b1c31933fb4cf78d2d61e89e9c4f72/FLAG2d34584e8 [2022-11-18 20:49:57,430 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 20:49:57,431 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:57,441 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/93a030093/b0b1c31933fb4cf78d2d61e89e9c4f72/FLAG2d34584e8 [2022-11-18 20:49:57,734 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/data/93a030093/b0b1c31933fb4cf78d2d61e89e9c4f72 [2022-11-18 20:49:57,736 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 20:49:57,739 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 20:49:57,741 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 20:49:57,743 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 20:49:57,747 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 20:49:57,748 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:49:57" (1/1) ... [2022-11-18 20:49:57,750 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1416806e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:57, skipping insertion in model container [2022-11-18 20:49:57,751 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:49:57" (1/1) ... [2022-11-18 20:49:57,758 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 20:49:57,800 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 20:49:57,963 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c[1107,1120] [2022-11-18 20:49:58,159 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:49:58,163 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 20:49:58,176 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.sw_sym_ex_v.c[1107,1120] [2022-11-18 20:49:58,269 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 20:49:58,281 INFO L208 MainTranslator]: Completed translation [2022-11-18 20:49:58,282 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58 WrapperNode [2022-11-18 20:49:58,282 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 20:49:58,283 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 20:49:58,283 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 20:49:58,283 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 20:49:58,293 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,312 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,361 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 534 [2022-11-18 20:49:58,361 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 20:49:58,362 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 20:49:58,362 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 20:49:58,362 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 20:49:58,374 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,374 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,380 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,380 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,394 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,398 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,402 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,405 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,410 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 20:49:58,411 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 20:49:58,411 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 20:49:58,411 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 20:49:58,412 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (1/1) ... [2022-11-18 20:49:58,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 20:49:58,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 20:49:58,453 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-18 20:49:58,457 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-18 20:49:58,496 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 20:49:58,496 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 20:49:58,730 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 20:49:58,745 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 20:49:59,469 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 20:49:59,483 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 20:49:59,483 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-18 20:49:59,487 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:59 BoogieIcfgContainer [2022-11-18 20:49:59,487 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 20:49:59,490 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-18 20:49:59,492 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-18 20:49:59,495 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-18 20:49:59,495 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 08:49:57" (1/3) ... [2022-11-18 20:49:59,496 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c7fb4c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 08:49:59, skipping insertion in model container [2022-11-18 20:49:59,496 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:49:58" (2/3) ... [2022-11-18 20:49:59,497 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c7fb4c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 08:49:59, skipping insertion in model container [2022-11-18 20:49:59,498 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:59" (3/3) ... [2022-11-18 20:49:59,499 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.sw_sym_ex_v.c [2022-11-18 20:49:59,520 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-18 20:49:59,521 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-18 20:49:59,576 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-18 20:49:59,583 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@508be4d9, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-18 20:49:59,584 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-18 20:49:59,588 INFO L276 IsEmpty]: Start isEmpty. Operand has 11 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:49:59,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-18 20:49:59,594 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:49:59,595 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-18 20:49:59,595 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:49:59,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:49:59,600 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-18 20:49:59,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:49:59,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [959750451] [2022-11-18 20:49:59,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:49:59,614 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:49:59,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:49:59,620 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:49:59,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-18 20:49:59,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:49:59,832 INFO L263 TraceCheckSpWp]: Trace formula consists of 53 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 20:49:59,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:49:59,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:49:59,968 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 20:49:59,969 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:49:59,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [959750451] [2022-11-18 20:49:59,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [959750451] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 20:49:59,970 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 20:49:59,970 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 20:49:59,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919747357] [2022-11-18 20:49:59,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 20:49:59,978 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 20:49:59,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:50:00,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 20:50:00,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 20:50:00,019 INFO L87 Difference]: Start difference. First operand has 11 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:00,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:50:00,125 INFO L93 Difference]: Finished difference Result 20 states and 30 transitions. [2022-11-18 20:50:00,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 20:50:00,128 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-18 20:50:00,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:50:00,139 INFO L225 Difference]: With dead ends: 20 [2022-11-18 20:50:00,140 INFO L226 Difference]: Without dead ends: 11 [2022-11-18 20:50:00,143 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 20:50:00,147 INFO L413 NwaCegarLoop]: 5 mSDtfsCounter, 4 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 13 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 20:50:00,149 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 13 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 20:50:00,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2022-11-18 20:50:00,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 9. [2022-11-18 20:50:00,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:00,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 9 transitions. [2022-11-18 20:50:00,181 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 9 transitions. Word has length 5 [2022-11-18 20:50:00,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:50:00,182 INFO L495 AbstractCegarLoop]: Abstraction has 9 states and 9 transitions. [2022-11-18 20:50:00,182 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:00,182 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 9 transitions. [2022-11-18 20:50:00,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2022-11-18 20:50:00,183 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:50:00,183 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1] [2022-11-18 20:50:00,200 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-18 20:50:00,394 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:00,395 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:50:00,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:50:00,395 INFO L85 PathProgramCache]: Analyzing trace with hash 271073635, now seen corresponding path program 1 times [2022-11-18 20:50:00,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:50:00,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [339857954] [2022-11-18 20:50:00,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 20:50:00,399 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:00,399 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:50:00,405 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:50:00,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-18 20:50:00,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 20:50:00,762 INFO L263 TraceCheckSpWp]: Trace formula consists of 501 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 20:50:00,768 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:50:00,905 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:50:00,905 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:50:01,264 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:50:01,265 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:50:01,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [339857954] [2022-11-18 20:50:01,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [339857954] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:50:01,266 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 20:50:01,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 8 [2022-11-18 20:50:01,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627807164] [2022-11-18 20:50:01,271 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 20:50:01,273 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 20:50:01,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:50:01,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 20:50:01,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2022-11-18 20:50:01,276 INFO L87 Difference]: Start difference. First operand 9 states and 9 transitions. Second operand has 8 states, 8 states have (on average 1.75) internal successors, (14), 8 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:01,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:50:01,388 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-11-18 20:50:01,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 20:50:01,390 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 8 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 8 [2022-11-18 20:50:01,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:50:01,390 INFO L225 Difference]: With dead ends: 16 [2022-11-18 20:50:01,390 INFO L226 Difference]: Without dead ends: 14 [2022-11-18 20:50:01,391 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=34, Invalid=56, Unknown=0, NotChecked=0, Total=90 [2022-11-18 20:50:01,392 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 13 mSDsluCounter, 11 mSDsCounter, 0 mSdLazyCounter, 13 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 15 SdHoareTripleChecker+Invalid, 21 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 13 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 20:50:01,392 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 15 Invalid, 21 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 13 Invalid, 0 Unknown, 7 Unchecked, 0.1s Time] [2022-11-18 20:50:01,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2022-11-18 20:50:01,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-18 20:50:01,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:01,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 12 transitions. [2022-11-18 20:50:01,401 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 12 transitions. Word has length 8 [2022-11-18 20:50:01,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:50:01,403 INFO L495 AbstractCegarLoop]: Abstraction has 12 states and 12 transitions. [2022-11-18 20:50:01,404 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 8 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:01,404 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2022-11-18 20:50:01,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-11-18 20:50:01,408 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:50:01,409 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1] [2022-11-18 20:50:01,427 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-18 20:50:01,628 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:01,628 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:50:01,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:50:01,629 INFO L85 PathProgramCache]: Analyzing trace with hash 1020920393, now seen corresponding path program 2 times [2022-11-18 20:50:01,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:50:01,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1299919370] [2022-11-18 20:50:01,631 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 20:50:01,631 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:01,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:50:01,632 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:50:01,639 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-18 20:50:02,099 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 20:50:02,100 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:50:02,119 INFO L263 TraceCheckSpWp]: Trace formula consists of 949 conjuncts, 112 conjunts are in the unsatisfiable core [2022-11-18 20:50:02,129 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:50:02,638 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:50:02,638 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:50:03,798 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:50:03,798 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:50:03,798 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1299919370] [2022-11-18 20:50:03,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1299919370] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:50:03,798 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 20:50:03,799 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 20:50:03,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438956174] [2022-11-18 20:50:03,799 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 20:50:03,799 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 20:50:03,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:50:03,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 20:50:03,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-11-18 20:50:03,800 INFO L87 Difference]: Start difference. First operand 12 states and 12 transitions. Second operand has 10 states, 10 states have (on average 2.0) internal successors, (20), 10 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:03,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:50:03,981 INFO L93 Difference]: Finished difference Result 19 states and 19 transitions. [2022-11-18 20:50:03,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 20:50:03,983 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.0) internal successors, (20), 10 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-11-18 20:50:03,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:50:03,983 INFO L225 Difference]: With dead ends: 19 [2022-11-18 20:50:03,983 INFO L226 Difference]: Without dead ends: 17 [2022-11-18 20:50:03,984 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=57, Invalid=99, Unknown=0, NotChecked=0, Total=156 [2022-11-18 20:50:03,985 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 10 mSDsluCounter, 18 mSDsCounter, 0 mSdLazyCounter, 9 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 22 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 9 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 15 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 20:50:03,985 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 22 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 9 Invalid, 0 Unknown, 15 Unchecked, 0.1s Time] [2022-11-18 20:50:03,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-11-18 20:50:03,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 15. [2022-11-18 20:50:03,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 14 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:03,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2022-11-18 20:50:03,995 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2022-11-18 20:50:03,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:50:03,995 INFO L495 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2022-11-18 20:50:03,996 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.0) internal successors, (20), 10 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:50:03,996 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-11-18 20:50:03,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-11-18 20:50:03,997 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:50:03,997 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1] [2022-11-18 20:50:04,017 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-18 20:50:04,197 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:04,198 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:50:04,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:50:04,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1580781475, now seen corresponding path program 3 times [2022-11-18 20:50:04,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:50:04,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1042896007] [2022-11-18 20:50:04,201 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 20:50:04,201 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:50:04,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:50:04,202 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:50:04,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-18 20:50:04,839 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-11-18 20:50:04,839 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:50:04,870 INFO L263 TraceCheckSpWp]: Trace formula consists of 1397 conjuncts, 215 conjunts are in the unsatisfiable core [2022-11-18 20:50:04,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:50:13,109 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:50:13,109 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:50:36,302 WARN L233 SmtUtils]: Spent 6.26s on a formula simplification that was a NOOP. DAG size: 397 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:51:49,782 WARN L233 SmtUtils]: Spent 54.35s on a formula simplification. DAG size of input: 634 DAG size of output: 634 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:51:51,132 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:51:51,132 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:51:51,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1042896007] [2022-11-18 20:51:51,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1042896007] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:51:51,133 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 20:51:51,133 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2022-11-18 20:51:51,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461320562] [2022-11-18 20:51:51,133 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 20:51:51,133 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-11-18 20:51:51,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:51:51,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-18 20:51:51,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=186, Unknown=13, NotChecked=0, Total=240 [2022-11-18 20:51:51,135 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand has 16 states, 16 states have (on average 1.625) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:51:52,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:51:52,083 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2022-11-18 20:51:52,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 20:51:52,084 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.625) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 14 [2022-11-18 20:51:52,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:51:52,084 INFO L225 Difference]: With dead ends: 22 [2022-11-18 20:51:52,085 INFO L226 Difference]: Without dead ends: 20 [2022-11-18 20:51:52,085 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 101.3s TimeCoverageRelationStatistics Valid=56, Invalid=273, Unknown=13, NotChecked=0, Total=342 [2022-11-18 20:51:52,086 INFO L413 NwaCegarLoop]: 8 mSDtfsCounter, 5 mSDsluCounter, 45 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 53 SdHoareTripleChecker+Invalid, 78 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 52 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 20:51:52,086 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 53 Invalid, 78 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 23 Invalid, 0 Unknown, 52 Unchecked, 0.2s Time] [2022-11-18 20:51:52,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2022-11-18 20:51:52,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 18. [2022-11-18 20:51:52,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:51:52,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2022-11-18 20:51:52,093 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2022-11-18 20:51:52,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:51:52,093 INFO L495 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2022-11-18 20:51:52,093 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.625) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:51:52,093 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2022-11-18 20:51:52,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 20:51:52,094 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:51:52,094 INFO L195 NwaCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1] [2022-11-18 20:51:52,121 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-18 20:51:52,294 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:51:52,295 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:51:52,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:51:52,295 INFO L85 PathProgramCache]: Analyzing trace with hash -1250702327, now seen corresponding path program 4 times [2022-11-18 20:51:52,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:51:52,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1303244099] [2022-11-18 20:51:52,297 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 20:51:52,297 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:51:52,298 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:51:52,303 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:51:52,304 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-18 20:51:52,927 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 20:51:52,927 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:51:52,957 INFO L263 TraceCheckSpWp]: Trace formula consists of 1845 conjuncts, 382 conjunts are in the unsatisfiable core [2022-11-18 20:51:52,970 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:51:56,052 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:51:56,053 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:52:15,790 WARN L233 SmtUtils]: Spent 17.88s on a formula simplification. DAG size of input: 334 DAG size of output: 260 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:54:39,080 WARN L233 SmtUtils]: Spent 2.28m on a formula simplification. DAG size of input: 744 DAG size of output: 365 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:54:49,188 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse53 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_17~0#1|)) (.cse50 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_21~0#1|)) (.cse51 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_25~0#1|)) (.cse42 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_27~0#1|)) (.cse43 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_29~0#1|)) (.cse49 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_8~0#1|)) (.cse55 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_19~0#1|)) (.cse54 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_23~0#1|)) (.cse56 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_7~0#1|)))) (.cse32 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_5~0#1|))) (let ((.cse40 ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) .cse56)) .cse32))) (.cse33 ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse56)))) (.cse48 ((_ zero_extend 24) ((_ extract 7 0) .cse54))) (.cse46 ((_ zero_extend 24) ((_ extract 7 0) .cse55))) (.cse7 ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_42~0#1|)) (.cse8 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|)) (.cse19 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_193~0#1|)))))))))))) (.cse35 (forall ((|v_ULTIMATE.start_main_~var_65_arg_2~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_46_arg_2~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_14|))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_65_arg_2~0#1_14|))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_14|))))))))))))))))))))))) .cse32)) (_ bv0 8)))) (.cse36 (forall ((|v_ULTIMATE.start_main_~var_146_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_116_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_131_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_176_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_161_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_191_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_101_arg_1~0#1_16| (_ BitVec 8))) (not (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_176_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_146_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse54))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse55))) .cse53))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse50))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse51)))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse42)))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse43)))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse49)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_101_arg_1~0#1_16|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_116_arg_1~0#1_17|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_131_arg_1~0#1_17|))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_161_arg_1~0#1_17|))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_191_arg_1~0#1_17|)))))) (_ bv0 8)))))) (let ((.cse21 (= |c_ULTIMATE.start_main_~state_31~0#1| (_ bv0 8))) (.cse13 (or .cse35 .cse36)) (.cse27 (forall ((|v_ULTIMATE.start_main_~var_204_arg_1~0#1_14| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_204_arg_1~0#1_14|))))))))) .cse19)))))))))) (.cse10 (forall ((|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_0~0#1_12| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_16| (_ BitVec 8))) (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_16|)))) .cse51))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_16|)))) .cse49)))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor .cse48 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_14|))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_0~0#1_12|) (_ bv1 32))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|)))) .cse32)) (_ bv0 8)))) (.cse41 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_16| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_16|)))))))) (_ bv0 8)))) (.cse15 (forall ((|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_16| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_16|)))) .cse51))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_16|)))) .cse49)))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor .cse48 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_14|))))))))) (_ bv0 32))))))))))))))))) (_ bv0 8)))) (.cse29 (forall ((|v_ULTIMATE.start_main_~var_46_arg_2~0#1_12| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_12|)))))))))))) .cse32)) (_ bv0 8)))) (.cse45 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) .cse40)))) .cse33))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) .cse53)) .cse32))))))))) (.cse2 (= (_ bv0 8) |c_ULTIMATE.start_main_~state_19~0#1|))) (let ((.cse18 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_34~0#1|)))))))))))))))) (.cse1 (not .cse2)) (.cse14 (or .cse29 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_146_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_161_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_191_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_176_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_116_arg_0~0#1_13| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_131_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_16| (_ BitVec 8))) (not (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_191_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_176_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_131_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse52 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_16|)))) .cse51))))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse52 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_16|)))) .cse49))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse45 ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_15|)))))) .cse32))))))))) (_ bv255 32)))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor .cse48 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_16|)))) .cse43))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse52 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_15|))))))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_116_arg_0~0#1_13|))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_146_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_161_arg_1~0#1_15|)))))))))) .cse32)) (_ bv0 8)))))) (.cse16 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_16| (_ BitVec 8))) (not (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_16|)))))))) (_ bv0 8))))) (.cse4 (or .cse41 .cse15)) (.cse5 (or .cse29 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_56_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_146_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_161_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_191_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_176_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_116_arg_0~0#1_13| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_131_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_16| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_16| (_ BitVec 8))) (let ((.cse47 ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_16|)))))))))) (or (not (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_191_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_116_arg_0~0#1_13|) ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse44 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse50 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_16|)))) .cse51))))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_16|)))) .cse43))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse44 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_15|)))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse45 ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_15|)))))) .cse32))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) .cse47))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor .cse48 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse46 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|)))))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse44 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse42 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_16|)))) .cse49)))))))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_131_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_146_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_161_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_176_arg_1~0#1_15|))))))) .cse32)) (_ bv0 8))) (= .cse47 (_ bv0 8))))))) (.cse6 (or .cse35 .cse41 .cse36)) (.cse17 (or .cse27 .cse41 .cse10)) (.cse20 (= (_ bv0 8) .cse40)) (.cse0 (let ((.cse26 (forall ((|v_ULTIMATE.start_main_~var_57_arg_2~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_57_arg_2~0#1_15|))))) (_ bv0 8)))) (.cse28 (forall ((|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_59_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_65_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_46_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_0~0#1_12| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_52_arg_2~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_0~0#1_12|) (_ bv1 32)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_65_arg_2~0#1_15|))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_15|)))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_52_arg_2~0#1_15|)))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_59_arg_2~0#1_15|)))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_14|)))))))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|)))))) (_ bv0 8)))) (.cse37 (forall ((|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_59_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_65_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_46_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_14| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_15_arg_0~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_52_arg_2~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_65_arg_2~0#1_15|))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_15|)))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_52_arg_2~0#1_15|)))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_59_arg_2~0#1_15|)))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_14|))))))))) (_ bv0 32)))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_15_arg_0~0#1_15|)))))) (_ bv0 8))))) (and (or .cse26 .cse27 .cse28) (or .cse29 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_71_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_59_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_65_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_146_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_161_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_48_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_57_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_191_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_176_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_116_arg_0~0#1_13| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_46_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_131_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_50_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_52_arg_2~0#1_15| (_ BitVec 8))) (let ((.cse34 ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_57_arg_2~0#1_15|))))))) (or (not (= (_ bv0 8) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_191_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_176_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_131_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse30 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_65_arg_2~0#1_15|))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse30 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_71_arg_2~0#1_15|))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse31 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_52_arg_2~0#1_15|))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse31 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_15|)))))) .cse32)))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_50_arg_2~0#1_15|))) .cse32))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_48_arg_2~0#1_15|))))) .cse32)))))) .cse33))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) .cse34))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|) .cse31))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_59_arg_2~0#1_15|)))))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse30 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_15|))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_116_arg_0~0#1_13|))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_146_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_161_arg_1~0#1_15|)))))))))) .cse32)))) (= .cse34 (_ bv0 8)))))) (or .cse35 .cse26 .cse36) (or .cse26 .cse37) (or (and (or (forall ((|v_ULTIMATE.start_main_~var_205_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_197_arg_2~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_205_arg_2~0#1_15|))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_197_arg_2~0#1_15|)))))))))))))))))))))) .cse28) (or .cse29 (forall ((|v_ULTIMATE.start_main_~var_56_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_71_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_63_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_59_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_65_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_146_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_161_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_48_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_191_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_176_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_116_arg_0~0#1_13| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_46_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_131_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_50_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_44_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_69_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_52_arg_2~0#1_15| (_ BitVec 8))) (not (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_191_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_176_arg_1~0#1_15|) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_116_arg_0~0#1_13|) ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse39 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_65_arg_2~0#1_15|))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (let ((.cse38 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_52_arg_2~0#1_15|))))) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse38 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_56_arg_1~0#1_15|)))))) .cse32)))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_50_arg_2~0#1_15|))) .cse32))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_48_arg_2~0#1_15|))))) .cse32)))))) .cse33))))))))) (_ bv255 32)))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_63_arg_1~0#1_15|) .cse38))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_59_arg_2~0#1_15|))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse39 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_69_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_71_arg_2~0#1_15|)))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse39 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_44_arg_1~0#1_15|)))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_46_arg_2~0#1_15|)))))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_131_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_146_arg_1~0#1_15|)))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_161_arg_1~0#1_15|)))))))))))) (_ bv0 8))))) (or (forall ((|v_ULTIMATE.start_main_~var_205_arg_2~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_196_arg_1~0#1_13| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_205_arg_2~0#1_15|))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_196_arg_1~0#1_13|)))))))))))))) .cse28 (forall ((|v_ULTIMATE.start_main_~var_48_arg_2~0#1_15| (_ BitVec 8))) (= ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_48_arg_2~0#1_15|))))) .cse32)) (_ bv0 8)))) (or .cse28 (forall ((|v_ULTIMATE.start_main_~var_205_arg_2~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_205_arg_2~0#1_15|))))))))))) .cse19)))))))))) .cse13 .cse37) (forall ((|v_ULTIMATE.start_main_~var_57_arg_2~0#1_15| (_ BitVec 8))) (not (= ((_ extract 7 0) (bvand .cse32 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_57_arg_2~0#1_15|))))) (_ bv0 8)))))))) (.cse3 (not .cse21)) (.cse22 (= |c_ULTIMATE.start_main_~state_23~0#1| (_ bv0 8)))) (and (or (and (or (and (or .cse0 .cse1) (or .cse0 .cse2)) .cse3) (or (let ((.cse9 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_36~0#1|))))))))))))))) (let ((.cse11 (or (forall ((|v_ULTIMATE.start_main_~var_196_arg_1~0#1_13| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse9 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_196_arg_1~0#1_13|)))))))))))))) .cse10 .cse20)) (.cse12 (or .cse10 (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse9 .cse19))))))))))) (and (or (and .cse4 .cse5 .cse6 (or (and (or (forall ((|v_ULTIMATE.start_main_~var_196_arg_1~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse9 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_196_arg_1~0#1_15|)))))))))))))))))))))))) .cse10) .cse11 .cse12 .cse13 .cse14 .cse15) .cse16) .cse17) .cse2) (or (and .cse4 .cse5 .cse6 (or .cse16 (and (or .cse10 (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse9 .cse18))))))))) .cse11 .cse12 .cse13 .cse14 .cse15)) .cse17) .cse1)))) .cse21)) (not .cse22)) (or (let ((.cse25 (or .cse0 .cse3)) (.cse23 (or .cse10 (forall ((|v_ULTIMATE.start_main_~var_204_arg_1~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse19 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_204_arg_1~0#1_15|)))))))))))))))) .cse8)))))))) (.cse24 (or .cse10 (forall ((|v_ULTIMATE.start_main_~var_204_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_196_arg_1~0#1_13| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_204_arg_1~0#1_15|))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_196_arg_1~0#1_13|)))))))))))))) .cse20))) (and (or (and (or (and (or (and (or .cse10 (forall ((|v_ULTIMATE.start_main_~var_204_arg_1~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse8 ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse18 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_204_arg_1~0#1_15|))))))))))))))))))))))) .cse23 .cse13 .cse14 .cse15 .cse24) .cse16) .cse4 .cse5 .cse6 .cse17) .cse21) .cse25) .cse1) (or (and .cse25 (or (and (or (and (or .cse10 (forall ((|v_ULTIMATE.start_main_~var_204_arg_1~0#1_15| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_196_arg_1~0#1_15| (_ BitVec 8))) (not (= .cse7 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_204_arg_1~0#1_15|))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_196_arg_1~0#1_15|)))))))))))))))))) .cse8))))))) .cse23 .cse13 .cse14 .cse15 .cse24) .cse16) .cse4 .cse5 .cse6 .cse17) .cse21)) .cse2))) .cse22)))))) is different from false [2022-11-18 20:54:53,431 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 11 not checked. [2022-11-18 20:54:53,431 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:54:53,431 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1303244099] [2022-11-18 20:54:53,432 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1303244099] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:54:53,432 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 20:54:53,432 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2022-11-18 20:54:53,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163333865] [2022-11-18 20:54:53,432 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 20:54:53,433 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 20:54:53,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:54:53,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 20:54:53,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=110, Unknown=1, NotChecked=22, Total=182 [2022-11-18 20:54:53,434 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:55:14,619 WARN L233 SmtUtils]: Spent 14.93s on a formula simplification. DAG size of input: 965 DAG size of output: 41 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:55:15,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:55:15,030 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2022-11-18 20:55:15,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 20:55:15,030 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 20:55:15,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:55:15,031 INFO L225 Difference]: With dead ends: 25 [2022-11-18 20:55:15,031 INFO L226 Difference]: Without dead ends: 23 [2022-11-18 20:55:15,032 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 179.9s TimeCoverageRelationStatistics Valid=99, Invalid=208, Unknown=3, NotChecked=32, Total=342 [2022-11-18 20:55:15,032 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 10 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 29 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 20:55:15,033 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 24 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 29 Unchecked, 0.0s Time] [2022-11-18 20:55:15,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2022-11-18 20:55:15,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 21. [2022-11-18 20:55:15,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 20 states have (on average 1.05) internal successors, (21), 20 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:55:15,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2022-11-18 20:55:15,042 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2022-11-18 20:55:15,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:55:15,043 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2022-11-18 20:55:15,043 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:55:15,043 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-11-18 20:55:15,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-11-18 20:55:15,043 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:55:15,044 INFO L195 NwaCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1] [2022-11-18 20:55:15,062 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-18 20:55:15,244 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:55:15,245 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:55:15,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:55:15,245 INFO L85 PathProgramCache]: Analyzing trace with hash -826954269, now seen corresponding path program 5 times [2022-11-18 20:55:15,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:55:15,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [685268671] [2022-11-18 20:55:15,246 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 20:55:15,247 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:55:15,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:55:15,248 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:55:15,250 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-18 20:55:16,075 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-18 20:55:16,075 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 20:55:16,113 INFO L263 TraceCheckSpWp]: Trace formula consists of 2293 conjuncts, 339 conjunts are in the unsatisfiable core [2022-11-18 20:55:16,126 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 20:55:18,817 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:55:18,818 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 20:55:30,842 WARN L233 SmtUtils]: Spent 6.42s on a formula simplification. DAG size of input: 241 DAG size of output: 240 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:55:50,178 WARN L233 SmtUtils]: Spent 6.30s on a formula simplification. DAG size of input: 253 DAG size of output: 251 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:56:41,157 WARN L233 SmtUtils]: Spent 37.78s on a formula simplification. DAG size of input: 517 DAG size of output: 339 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:56:57,392 WARN L233 SmtUtils]: Spent 13.21s on a formula simplification that was a NOOP. DAG size: 342 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:57:31,246 WARN L233 SmtUtils]: Spent 16.56s on a formula simplification that was a NOOP. DAG size: 350 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:59:06,686 WARN L233 SmtUtils]: Spent 1.10m on a formula simplification. DAG size of input: 773 DAG size of output: 702 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 20:59:07,321 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 20:59:07,322 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 20:59:07,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [685268671] [2022-11-18 20:59:07,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [685268671] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 20:59:07,322 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 20:59:07,322 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 28 [2022-11-18 20:59:07,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244226116] [2022-11-18 20:59:07,323 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 20:59:07,323 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-11-18 20:59:07,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 20:59:07,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-18 20:59:07,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=600, Unknown=32, NotChecked=0, Total=756 [2022-11-18 20:59:07,325 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand has 28 states, 28 states have (on average 1.3571428571428572) internal successors, (38), 28 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:59:08,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 20:59:08,912 INFO L93 Difference]: Finished difference Result 28 states and 28 transitions. [2022-11-18 20:59:08,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-18 20:59:08,913 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 1.3571428571428572) internal successors, (38), 28 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 20 [2022-11-18 20:59:08,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 20:59:08,914 INFO L225 Difference]: With dead ends: 28 [2022-11-18 20:59:08,914 INFO L226 Difference]: Without dead ends: 26 [2022-11-18 20:59:08,915 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 12 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 223.7s TimeCoverageRelationStatistics Valid=205, Invalid=885, Unknown=32, NotChecked=0, Total=1122 [2022-11-18 20:59:08,917 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 16 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 61 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 20:59:08,918 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 38 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 8 Invalid, 0 Unknown, 61 Unchecked, 0.1s Time] [2022-11-18 20:59:08,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-11-18 20:59:08,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2022-11-18 20:59:08,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:59:08,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2022-11-18 20:59:08,932 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2022-11-18 20:59:08,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 20:59:08,933 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2022-11-18 20:59:08,933 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 1.3571428571428572) internal successors, (38), 28 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 20:59:08,933 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2022-11-18 20:59:08,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-11-18 20:59:08,934 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 20:59:08,934 INFO L195 NwaCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1] [2022-11-18 20:59:08,956 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-18 20:59:09,143 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:59:09,144 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-18 20:59:09,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 20:59:09,144 INFO L85 PathProgramCache]: Analyzing trace with hash 142558665, now seen corresponding path program 6 times [2022-11-18 20:59:09,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 20:59:09,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1271970816] [2022-11-18 20:59:09,146 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 20:59:09,146 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:59:09,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 20:59:09,147 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 20:59:09,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-18 20:59:10,591 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-18 20:59:10,591 INFO L229 tOrderPrioritization]: Conjunction of SSA is sat [2022-11-18 20:59:10,591 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-18 20:59:11,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-18 20:59:11,975 INFO L130 FreeRefinementEngine]: Strategy WOLF found a feasible trace [2022-11-18 20:59:11,975 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-18 20:59:11,976 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-18 20:59:12,021 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-18 20:59:12,199 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 20:59:12,203 INFO L444 BasicCegarLoop]: Path program histogram: [6, 1] [2022-11-18 20:59:12,212 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-18 20:59:12,415 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,415 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,416 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,416 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,416 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,417 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,417 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,514 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 18.11 08:59:12 BoogieIcfgContainer [2022-11-18 20:59:12,514 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-18 20:59:12,515 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-18 20:59:12,515 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-18 20:59:12,515 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-18 20:59:12,516 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:49:59" (3/4) ... [2022-11-18 20:59:12,518 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-18 20:59:12,605 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,606 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,606 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,606 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,607 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,607 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,607 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-18 20:59:12,943 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/witness.graphml [2022-11-18 20:59:12,943 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-18 20:59:12,944 INFO L158 Benchmark]: Toolchain (without parser) took 555205.27ms. Allocated memory was 67.1MB in the beginning and 425.7MB in the end (delta: 358.6MB). Free memory was 47.2MB in the beginning and 203.5MB in the end (delta: -156.4MB). Peak memory consumption was 201.4MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,944 INFO L158 Benchmark]: CDTParser took 0.34ms. Allocated memory is still 67.1MB. Free memory was 49.3MB in the beginning and 49.3MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 20:59:12,945 INFO L158 Benchmark]: CACSL2BoogieTranslator took 540.82ms. Allocated memory is still 67.1MB. Free memory was 46.8MB in the beginning and 41.6MB in the end (delta: 5.2MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,945 INFO L158 Benchmark]: Boogie Procedure Inliner took 78.47ms. Allocated memory is still 67.1MB. Free memory was 41.6MB in the beginning and 36.9MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,946 INFO L158 Benchmark]: Boogie Preprocessor took 48.59ms. Allocated memory is still 67.1MB. Free memory was 36.9MB in the beginning and 33.9MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,946 INFO L158 Benchmark]: RCFGBuilder took 1076.29ms. Allocated memory was 67.1MB in the beginning and 90.2MB in the end (delta: 23.1MB). Free memory was 33.9MB in the beginning and 47.2MB in the end (delta: -13.3MB). Peak memory consumption was 22.0MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,947 INFO L158 Benchmark]: TraceAbstraction took 553023.82ms. Allocated memory was 90.2MB in the beginning and 425.7MB in the end (delta: 335.5MB). Free memory was 46.1MB in the beginning and 266.1MB in the end (delta: -220.0MB). Peak memory consumption was 114.7MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,948 INFO L158 Benchmark]: Witness Printer took 428.61ms. Allocated memory is still 425.7MB. Free memory was 266.1MB in the beginning and 203.5MB in the end (delta: 62.6MB). Peak memory consumption was 62.9MB. Max. memory is 16.1GB. [2022-11-18 20:59:12,951 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34ms. Allocated memory is still 67.1MB. Free memory was 49.3MB in the beginning and 49.3MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 540.82ms. Allocated memory is still 67.1MB. Free memory was 46.8MB in the beginning and 41.6MB in the end (delta: 5.2MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 78.47ms. Allocated memory is still 67.1MB. Free memory was 41.6MB in the beginning and 36.9MB in the end (delta: 4.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 48.59ms. Allocated memory is still 67.1MB. Free memory was 36.9MB in the beginning and 33.9MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1076.29ms. Allocated memory was 67.1MB in the beginning and 90.2MB in the end (delta: 23.1MB). Free memory was 33.9MB in the beginning and 47.2MB in the end (delta: -13.3MB). Peak memory consumption was 22.0MB. Max. memory is 16.1GB. * TraceAbstraction took 553023.82ms. Allocated memory was 90.2MB in the beginning and 425.7MB in the end (delta: 335.5MB). Free memory was 46.1MB in the beginning and 266.1MB in the end (delta: -220.0MB). Peak memory consumption was 114.7MB. Max. memory is 16.1GB. * Witness Printer took 428.61ms. Allocated memory is still 425.7MB. Free memory was 266.1MB in the beginning and 203.5MB in the end (delta: 62.6MB). Peak memory consumption was 62.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 20]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 8); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (8 - 1); [L28] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 1); [L29] const SORT_5 msb_SORT_5 = (SORT_5)1 << (1 - 1); [L31] const SORT_5 var_7 = 0; [L32] const SORT_5 var_13 = 1; [L33] const SORT_1 var_33 = 0; [L34] const SORT_1 var_42 = 4; [L35] const SORT_1 var_54 = 5; [L36] const SORT_1 var_193 = 3; [L37] const SORT_1 var_199 = 2; [L39] SORT_1 input_2; [L40] SORT_1 input_3; [L41] SORT_1 input_4; [L42] SORT_5 input_6; [L43] SORT_1 input_38; [L45] SORT_5 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L46] SORT_5 state_17 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L47] SORT_5 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L48] SORT_5 state_21 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L49] SORT_5 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L50] SORT_5 state_25 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L51] SORT_5 state_27 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L52] SORT_5 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L53] SORT_5 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L54] SORT_1 state_34 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L55] SORT_1 state_36 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L57] SORT_5 init_9_arg_1 = var_7; [L58] state_8 = init_9_arg_1 [L59] SORT_5 init_18_arg_1 = var_13; [L60] state_17 = init_18_arg_1 [L61] SORT_5 init_20_arg_1 = var_7; [L62] state_19 = init_20_arg_1 [L63] SORT_5 init_22_arg_1 = var_7; [L64] state_21 = init_22_arg_1 [L65] SORT_5 init_24_arg_1 = var_7; [L66] state_23 = init_24_arg_1 [L67] SORT_5 init_26_arg_1 = var_7; [L68] state_25 = init_26_arg_1 [L69] SORT_5 init_28_arg_1 = var_7; [L70] state_27 = init_28_arg_1 [L71] SORT_5 init_30_arg_1 = var_7; [L72] state_29 = init_30_arg_1 [L73] SORT_5 init_32_arg_1 = var_13; [L74] state_31 = init_32_arg_1 [L75] SORT_1 init_35_arg_1 = var_33; [L76] state_34 = init_35_arg_1 [L77] SORT_1 init_37_arg_1 = var_33; [L78] state_36 = init_37_arg_1 VAL [init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_17=1, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_13=1, var_193=3, var_199=2, var_33=0, var_42=4, var_54=5, var_7=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=0, input_4=0, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=0, next_47_arg_1=0, next_49_arg_1=0, next_51_arg_1=1, next_53_arg_1=0, next_58_arg_1=0, next_60_arg_1=0, next_66_arg_1=0, next_72_arg_1=0, state_17=0, state_19=1, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_10=255, var_100=0, var_100_arg_0=0, var_100_arg_1=255, var_101=1, var_101_arg_0=1, var_101_arg_1=0, var_102=254, var_102_arg_0=1, var_103=255, var_103_arg_0=0, var_104=254, var_104_arg_0=254, var_104_arg_1=255, var_105=0, var_105_arg_0=254, var_105_arg_1=0, var_106=255, var_106_arg_0=0, var_107=0, var_107_arg_0=0, var_107_arg_1=255, var_108=255, var_108_arg_0=0, var_109=0, var_109_arg_0=0, var_109_arg_1=255, var_10_arg_0=0, var_110=255, var_110_arg_0=0, var_111=0, var_111_arg_0=0, var_111_arg_1=255, var_112=255, var_112_arg_0=0, var_113=0, var_113_arg_0=0, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=0, var_115_arg_0=0, var_115_arg_1=255, var_116=1, var_116_arg_0=1, var_116_arg_1=0, var_117=254, var_117_arg_0=1, var_118=255, var_118_arg_0=0, var_119=254, var_119_arg_0=254, var_119_arg_1=255, var_120=255, var_120_arg_0=0, var_121=254, var_121_arg_0=254, var_121_arg_1=255, var_122=0, var_122_arg_0=254, var_122_arg_1=0, var_123=255, var_123_arg_0=0, var_124=0, var_124_arg_0=0, var_124_arg_1=255, var_125=255, var_125_arg_0=0, var_126=0, var_126_arg_0=0, var_126_arg_1=255, var_127=255, var_127_arg_0=0, var_128=0, var_128_arg_0=0, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=0, var_130_arg_0=0, var_130_arg_1=255, var_131=1, var_131_arg_0=1, var_131_arg_1=0, var_132=254, var_132_arg_0=1, var_133=255, var_133_arg_0=0, var_134=254, var_134_arg_0=254, var_134_arg_1=255, var_135=255, var_135_arg_0=0, var_136=254, var_136_arg_0=254, var_136_arg_1=255, var_137=255, var_137_arg_0=0, var_138=254, var_138_arg_0=254, var_138_arg_1=255, var_139=0, var_139_arg_0=254, var_139_arg_1=0, var_14=0, var_140=255, var_140_arg_0=0, var_141=0, var_141_arg_0=0, var_141_arg_1=255, var_142=255, var_142_arg_0=0, var_143=0, var_143_arg_0=0, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=0, var_145_arg_0=0, var_145_arg_1=255, var_146=1, var_146_arg_0=1, var_146_arg_1=0, var_147=254, var_147_arg_0=1, var_148=255, var_148_arg_0=0, var_149=254, var_149_arg_0=254, var_149_arg_1=255, var_14_arg_0=255, var_15=0, var_150=255, var_150_arg_0=0, var_151=254, var_151_arg_0=254, var_151_arg_1=255, var_152=255, var_152_arg_0=0, var_153=254, var_153_arg_0=254, var_153_arg_1=255, var_154=255, var_154_arg_0=0, var_155=254, var_155_arg_0=254, var_155_arg_1=255, var_156=0, var_156_arg_0=254, var_156_arg_1=0, var_157=255, var_157_arg_0=0, var_158=0, var_158_arg_0=0, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=0, var_160_arg_0=0, var_160_arg_1=255, var_161=1, var_161_arg_0=1, var_161_arg_1=0, var_162=254, var_162_arg_0=1, var_163=255, var_163_arg_0=0, var_164=254, var_164_arg_0=254, var_164_arg_1=255, var_165=255, var_165_arg_0=0, var_166=254, var_166_arg_0=254, var_166_arg_1=255, var_167=255, var_167_arg_0=0, var_168=254, var_168_arg_0=254, var_168_arg_1=255, var_169=255, var_169_arg_0=0, var_170=254, var_170_arg_0=254, var_170_arg_1=255, var_171=255, var_171_arg_0=0, var_172=254, var_172_arg_0=254, var_172_arg_1=255, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=254, var_177_arg_0=1, var_178=255, var_178_arg_0=0, var_179=254, var_179_arg_0=254, var_179_arg_1=255, var_180=255, var_180_arg_0=0, var_181=254, var_181_arg_0=254, var_181_arg_1=255, var_182=255, var_182_arg_0=0, var_183=254, var_183_arg_0=254, var_183_arg_1=255, var_184=255, var_184_arg_0=0, var_185=254, var_185_arg_0=254, var_185_arg_1=255, var_186=255, var_186_arg_0=0, var_187=254, var_187_arg_0=254, var_187_arg_1=255, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=0, var_196_arg_1=0, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=1, var_200_arg_0=0, var_200_arg_1=0, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=1, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=0, var_204=0, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=0, var_205=0, var_205_arg_0=1, var_205_arg_1=0, var_205_arg_2=0, var_33=0, var_41=0, var_41_arg_0=0, var_41_arg_1=0, var_42=4, var_43=0, var_43_arg_0=0, var_43_arg_1=4, var_44=0, var_44_arg_0=0, var_44_arg_1=0, var_45=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_46_arg_0=1, var_46_arg_1=0, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=1, var_50=1, var_50_arg_0=1, var_50_arg_1=1, var_50_arg_2=0, var_52=0, var_52_arg_0=1, var_52_arg_1=0, var_52_arg_2=0, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=0, var_56_arg_0=0, var_56_arg_1=1, var_57=0, var_57_arg_0=1, var_57_arg_1=0, var_57_arg_2=0, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_59_arg_2=0, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=0, var_63_arg_1=254, var_64=0, var_64_arg_0=0, var_64_arg_1=0, var_65=0, var_65_arg_0=1, var_65_arg_1=0, var_65_arg_2=0, var_67=0, var_67_arg_0=0, var_67_arg_1=0, var_68=1, var_68_arg_0=0, var_68_arg_1=4, var_69=0, var_69_arg_0=0, var_69_arg_1=1, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=255, var_73_arg_0=0, var_74=1, var_74_arg_0=1, var_74_arg_1=255, var_75=255, var_75_arg_0=0, var_76=1, var_76_arg_0=1, var_76_arg_1=255, var_77=255, var_77_arg_0=0, var_78=1, var_78_arg_0=1, var_78_arg_1=255, var_79=255, var_79_arg_0=0, var_80=1, var_80_arg_0=1, var_80_arg_1=255, var_81=255, var_81_arg_0=0, var_82=1, var_82_arg_0=1, var_82_arg_1=255, var_83=255, var_83_arg_0=0, var_84=1, var_84_arg_0=1, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=1, var_86_arg_0=1, var_86_arg_1=255, var_87=254, var_87_arg_0=1, var_88=0, var_88_arg_0=254, var_88_arg_1=0, var_89=255, var_89_arg_0=0, var_90=0, var_90_arg_0=0, var_90_arg_1=255, var_91=255, var_91_arg_0=0, var_92=0, var_92_arg_0=0, var_92_arg_1=255, var_93=255, var_93_arg_0=0, var_94=0, var_94_arg_0=0, var_94_arg_1=255, var_95=255, var_95_arg_0=0, var_96=0, var_96_arg_0=0, var_96_arg_1=255, var_97=255, var_97_arg_0=0, var_98=0, var_98_arg_0=0, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=0, input_4=0, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=0, next_47_arg_1=0, next_49_arg_1=0, next_51_arg_1=0, next_53_arg_1=1, next_58_arg_1=0, next_60_arg_1=0, next_66_arg_1=0, next_72_arg_1=0, state_17=0, state_19=0, state_21=1, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_10=255, var_100=1, var_100_arg_0=1, var_100_arg_1=255, var_101=1, var_101_arg_0=0, var_101_arg_1=1, var_102=255, var_102_arg_0=0, var_103=254, var_103_arg_0=1, var_104=254, var_104_arg_0=255, var_104_arg_1=254, var_105=0, var_105_arg_0=254, var_105_arg_1=0, var_106=255, var_106_arg_0=0, var_107=0, var_107_arg_0=0, var_107_arg_1=255, var_108=255, var_108_arg_0=0, var_109=0, var_109_arg_0=0, var_109_arg_1=255, var_10_arg_0=0, var_110=255, var_110_arg_0=0, var_111=0, var_111_arg_0=0, var_111_arg_1=255, var_112=255, var_112_arg_0=0, var_113=0, var_113_arg_0=0, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=0, var_115_arg_0=0, var_115_arg_1=255, var_116=1, var_116_arg_0=1, var_116_arg_1=0, var_117=255, var_117_arg_0=0, var_118=254, var_118_arg_0=1, var_119=254, var_119_arg_0=255, var_119_arg_1=254, var_120=255, var_120_arg_0=0, var_121=254, var_121_arg_0=254, var_121_arg_1=255, var_122=0, var_122_arg_0=254, var_122_arg_1=0, var_123=255, var_123_arg_0=0, var_124=0, var_124_arg_0=0, var_124_arg_1=255, var_125=255, var_125_arg_0=0, var_126=0, var_126_arg_0=0, var_126_arg_1=255, var_127=255, var_127_arg_0=0, var_128=0, var_128_arg_0=0, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=0, var_130_arg_0=0, var_130_arg_1=255, var_131=1, var_131_arg_0=1, var_131_arg_1=0, var_132=255, var_132_arg_0=0, var_133=254, var_133_arg_0=1, var_134=254, var_134_arg_0=255, var_134_arg_1=254, var_135=255, var_135_arg_0=0, var_136=254, var_136_arg_0=254, var_136_arg_1=255, var_137=255, var_137_arg_0=0, var_138=254, var_138_arg_0=254, var_138_arg_1=255, var_139=0, var_139_arg_0=254, var_139_arg_1=0, var_14=0, var_140=255, var_140_arg_0=0, var_141=0, var_141_arg_0=0, var_141_arg_1=255, var_142=255, var_142_arg_0=0, var_143=0, var_143_arg_0=0, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=0, var_145_arg_0=0, var_145_arg_1=255, var_146=1, var_146_arg_0=1, var_146_arg_1=0, var_147=255, var_147_arg_0=0, var_148=254, var_148_arg_0=1, var_149=254, var_149_arg_0=255, var_149_arg_1=254, var_14_arg_0=255, var_15=0, var_150=255, var_150_arg_0=0, var_151=254, var_151_arg_0=254, var_151_arg_1=255, var_152=255, var_152_arg_0=0, var_153=254, var_153_arg_0=254, var_153_arg_1=255, var_154=255, var_154_arg_0=0, var_155=254, var_155_arg_0=254, var_155_arg_1=255, var_156=0, var_156_arg_0=254, var_156_arg_1=0, var_157=255, var_157_arg_0=0, var_158=0, var_158_arg_0=0, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=0, var_160_arg_0=0, var_160_arg_1=255, var_161=1, var_161_arg_0=1, var_161_arg_1=0, var_162=255, var_162_arg_0=0, var_163=254, var_163_arg_0=1, var_164=254, var_164_arg_0=255, var_164_arg_1=254, var_165=255, var_165_arg_0=0, var_166=254, var_166_arg_0=254, var_166_arg_1=255, var_167=255, var_167_arg_0=0, var_168=254, var_168_arg_0=254, var_168_arg_1=255, var_169=255, var_169_arg_0=0, var_170=254, var_170_arg_0=254, var_170_arg_1=255, var_171=255, var_171_arg_0=0, var_172=254, var_172_arg_0=254, var_172_arg_1=255, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=255, var_177_arg_0=0, var_178=254, var_178_arg_0=1, var_179=254, var_179_arg_0=255, var_179_arg_1=254, var_180=255, var_180_arg_0=0, var_181=254, var_181_arg_0=254, var_181_arg_1=255, var_182=255, var_182_arg_0=0, var_183=254, var_183_arg_0=254, var_183_arg_1=255, var_184=255, var_184_arg_0=0, var_185=254, var_185_arg_0=254, var_185_arg_1=255, var_186=255, var_186_arg_0=0, var_187=254, var_187_arg_0=254, var_187_arg_1=255, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=1, var_196_arg_1=0, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=1, var_200_arg_0=0, var_200_arg_1=0, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=1, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=0, var_204=0, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=0, var_205=0, var_205_arg_0=1, var_205_arg_1=0, var_205_arg_2=0, var_33=0, var_41=0, var_41_arg_0=0, var_41_arg_1=0, var_42=4, var_43=0, var_43_arg_0=0, var_43_arg_1=4, var_44=0, var_44_arg_0=0, var_44_arg_1=0, var_45=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_46_arg_0=1, var_46_arg_1=0, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=0, var_50=0, var_50_arg_0=1, var_50_arg_1=0, var_50_arg_2=1, var_52=1, var_52_arg_0=1, var_52_arg_1=1, var_52_arg_2=0, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=0, var_56_arg_0=0, var_56_arg_1=1, var_57=0, var_57_arg_0=1, var_57_arg_1=0, var_57_arg_2=0, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_59_arg_2=0, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=0, var_63_arg_1=254, var_64=0, var_64_arg_0=0, var_64_arg_1=0, var_65=0, var_65_arg_0=1, var_65_arg_1=0, var_65_arg_2=0, var_67=0, var_67_arg_0=0, var_67_arg_1=0, var_68=1, var_68_arg_0=0, var_68_arg_1=4, var_69=0, var_69_arg_0=0, var_69_arg_1=1, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=254, var_73_arg_0=1, var_74=0, var_74_arg_0=0, var_74_arg_1=254, var_75=255, var_75_arg_0=0, var_76=0, var_76_arg_0=0, var_76_arg_1=255, var_77=255, var_77_arg_0=0, var_78=0, var_78_arg_0=0, var_78_arg_1=255, var_79=255, var_79_arg_0=0, var_80=0, var_80_arg_0=0, var_80_arg_1=255, var_81=255, var_81_arg_0=0, var_82=0, var_82_arg_0=0, var_82_arg_1=255, var_83=255, var_83_arg_0=0, var_84=0, var_84_arg_0=0, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=0, var_86_arg_0=0, var_86_arg_1=255, var_87=255, var_87_arg_0=0, var_88=1, var_88_arg_0=255, var_88_arg_1=1, var_89=255, var_89_arg_0=0, var_90=1, var_90_arg_0=1, var_90_arg_1=255, var_91=255, var_91_arg_0=0, var_92=1, var_92_arg_0=1, var_92_arg_1=255, var_93=255, var_93_arg_0=0, var_94=1, var_94_arg_0=1, var_94_arg_1=255, var_95=255, var_95_arg_0=0, var_96=1, var_96_arg_0=1, var_96_arg_1=255, var_97=255, var_97_arg_0=0, var_98=1, var_98_arg_0=1, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=0, input_4=0, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=0, next_47_arg_1=0, next_49_arg_1=0, next_51_arg_1=0, next_53_arg_1=0, next_58_arg_1=1, next_60_arg_1=0, next_66_arg_1=0, next_72_arg_1=0, state_17=0, state_19=0, state_21=0, state_23=1, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=0, state_8=0, var_10=255, var_100=0, var_100_arg_0=0, var_100_arg_1=255, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_102=255, var_102_arg_0=0, var_103=255, var_103_arg_0=0, var_104=255, var_104_arg_0=255, var_104_arg_1=255, var_105=1, var_105_arg_0=255, var_105_arg_1=1, var_106=255, var_106_arg_0=0, var_107=1, var_107_arg_0=1, var_107_arg_1=255, var_108=255, var_108_arg_0=0, var_109=1, var_109_arg_0=1, var_109_arg_1=255, var_10_arg_0=0, var_110=255, var_110_arg_0=0, var_111=1, var_111_arg_0=1, var_111_arg_1=255, var_112=255, var_112_arg_0=0, var_113=1, var_113_arg_0=1, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=1, var_115_arg_0=1, var_115_arg_1=255, var_116=1, var_116_arg_0=0, var_116_arg_1=1, var_117=255, var_117_arg_0=0, var_118=255, var_118_arg_0=0, var_119=255, var_119_arg_0=255, var_119_arg_1=255, var_120=254, var_120_arg_0=1, var_121=254, var_121_arg_0=255, var_121_arg_1=254, var_122=0, var_122_arg_0=254, var_122_arg_1=0, var_123=255, var_123_arg_0=0, var_124=0, var_124_arg_0=0, var_124_arg_1=255, var_125=255, var_125_arg_0=0, var_126=0, var_126_arg_0=0, var_126_arg_1=255, var_127=255, var_127_arg_0=0, var_128=0, var_128_arg_0=0, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=0, var_130_arg_0=0, var_130_arg_1=255, var_131=1, var_131_arg_0=1, var_131_arg_1=0, var_132=255, var_132_arg_0=0, var_133=255, var_133_arg_0=0, var_134=255, var_134_arg_0=255, var_134_arg_1=255, var_135=254, var_135_arg_0=1, var_136=254, var_136_arg_0=255, var_136_arg_1=254, var_137=255, var_137_arg_0=0, var_138=254, var_138_arg_0=254, var_138_arg_1=255, var_139=0, var_139_arg_0=254, var_139_arg_1=0, var_14=0, var_140=255, var_140_arg_0=0, var_141=0, var_141_arg_0=0, var_141_arg_1=255, var_142=255, var_142_arg_0=0, var_143=0, var_143_arg_0=0, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=0, var_145_arg_0=0, var_145_arg_1=255, var_146=1, var_146_arg_0=1, var_146_arg_1=0, var_147=255, var_147_arg_0=0, var_148=255, var_148_arg_0=0, var_149=255, var_149_arg_0=255, var_149_arg_1=255, var_14_arg_0=255, var_15=0, var_150=254, var_150_arg_0=1, var_151=254, var_151_arg_0=255, var_151_arg_1=254, var_152=255, var_152_arg_0=0, var_153=254, var_153_arg_0=254, var_153_arg_1=255, var_154=255, var_154_arg_0=0, var_155=254, var_155_arg_0=254, var_155_arg_1=255, var_156=0, var_156_arg_0=254, var_156_arg_1=0, var_157=255, var_157_arg_0=0, var_158=0, var_158_arg_0=0, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=0, var_160_arg_0=0, var_160_arg_1=255, var_161=1, var_161_arg_0=1, var_161_arg_1=0, var_162=255, var_162_arg_0=0, var_163=255, var_163_arg_0=0, var_164=255, var_164_arg_0=255, var_164_arg_1=255, var_165=254, var_165_arg_0=1, var_166=254, var_166_arg_0=255, var_166_arg_1=254, var_167=255, var_167_arg_0=0, var_168=254, var_168_arg_0=254, var_168_arg_1=255, var_169=255, var_169_arg_0=0, var_170=254, var_170_arg_0=254, var_170_arg_1=255, var_171=255, var_171_arg_0=0, var_172=254, var_172_arg_0=254, var_172_arg_1=255, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=255, var_177_arg_0=0, var_178=255, var_178_arg_0=0, var_179=255, var_179_arg_0=255, var_179_arg_1=255, var_180=254, var_180_arg_0=1, var_181=254, var_181_arg_0=255, var_181_arg_1=254, var_182=255, var_182_arg_0=0, var_183=254, var_183_arg_0=254, var_183_arg_1=255, var_184=255, var_184_arg_0=0, var_185=254, var_185_arg_0=254, var_185_arg_1=255, var_186=255, var_186_arg_0=0, var_187=254, var_187_arg_0=254, var_187_arg_1=255, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=0, var_196_arg_1=0, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=1, var_200_arg_0=0, var_200_arg_1=0, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=1, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=0, var_204=0, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=0, var_205=0, var_205_arg_0=1, var_205_arg_1=0, var_205_arg_2=0, var_33=0, var_41=0, var_41_arg_0=0, var_41_arg_1=0, var_42=4, var_43=0, var_43_arg_0=0, var_43_arg_1=4, var_44=0, var_44_arg_0=0, var_44_arg_1=0, var_45=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_46_arg_0=1, var_46_arg_1=0, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=0, var_50=0, var_50_arg_0=1, var_50_arg_1=0, var_50_arg_2=0, var_52=0, var_52_arg_0=1, var_52_arg_1=0, var_52_arg_2=1, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=1, var_56_arg_0=1, var_56_arg_1=1, var_57=1, var_57_arg_0=1, var_57_arg_1=1, var_57_arg_2=0, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_59_arg_2=0, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=1, var_63_arg_1=254, var_64=0, var_64_arg_0=0, var_64_arg_1=0, var_65=0, var_65_arg_0=1, var_65_arg_1=0, var_65_arg_2=0, var_67=0, var_67_arg_0=0, var_67_arg_1=0, var_68=1, var_68_arg_0=0, var_68_arg_1=4, var_69=0, var_69_arg_0=0, var_69_arg_1=1, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=255, var_73_arg_0=0, var_74=0, var_74_arg_0=0, var_74_arg_1=255, var_75=254, var_75_arg_0=1, var_76=0, var_76_arg_0=0, var_76_arg_1=254, var_77=255, var_77_arg_0=0, var_78=0, var_78_arg_0=0, var_78_arg_1=255, var_79=255, var_79_arg_0=0, var_80=0, var_80_arg_0=0, var_80_arg_1=255, var_81=255, var_81_arg_0=0, var_82=0, var_82_arg_0=0, var_82_arg_1=255, var_83=255, var_83_arg_0=0, var_84=0, var_84_arg_0=0, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=0, var_86_arg_0=0, var_86_arg_1=255, var_87=255, var_87_arg_0=0, var_88=0, var_88_arg_0=255, var_88_arg_1=0, var_89=254, var_89_arg_0=1, var_90=0, var_90_arg_0=0, var_90_arg_1=254, var_91=255, var_91_arg_0=0, var_92=0, var_92_arg_0=0, var_92_arg_1=255, var_93=255, var_93_arg_0=0, var_94=0, var_94_arg_0=0, var_94_arg_1=255, var_95=255, var_95_arg_0=0, var_96=0, var_96_arg_0=0, var_96_arg_1=255, var_97=255, var_97_arg_0=0, var_98=0, var_98_arg_0=0, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=128, input_3=0, input_38=0, input_4=4, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=4, next_47_arg_1=0, next_49_arg_1=0, next_51_arg_1=0, next_53_arg_1=0, next_58_arg_1=0, next_60_arg_1=1, next_66_arg_1=0, next_72_arg_1=0, state_17=0, state_19=0, state_21=0, state_23=0, state_25=1, state_27=0, state_29=0, state_31=1, state_34=0, state_36=4, state_8=0, var_10=255, var_100=0, var_100_arg_0=0, var_100_arg_1=255, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_102=255, var_102_arg_0=0, var_103=255, var_103_arg_0=0, var_104=255, var_104_arg_0=255, var_104_arg_1=255, var_105=0, var_105_arg_0=255, var_105_arg_1=0, var_106=254, var_106_arg_0=1, var_107=0, var_107_arg_0=0, var_107_arg_1=254, var_108=255, var_108_arg_0=0, var_109=0, var_109_arg_0=0, var_109_arg_1=255, var_10_arg_0=0, var_110=255, var_110_arg_0=0, var_111=0, var_111_arg_0=0, var_111_arg_1=255, var_112=255, var_112_arg_0=0, var_113=0, var_113_arg_0=0, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=0, var_115_arg_0=0, var_115_arg_1=255, var_116=0, var_116_arg_0=0, var_116_arg_1=0, var_117=255, var_117_arg_0=0, var_118=255, var_118_arg_0=0, var_119=255, var_119_arg_0=255, var_119_arg_1=255, var_120=255, var_120_arg_0=0, var_121=255, var_121_arg_0=255, var_121_arg_1=255, var_122=1, var_122_arg_0=255, var_122_arg_1=1, var_123=255, var_123_arg_0=0, var_124=1, var_124_arg_0=1, var_124_arg_1=255, var_125=255, var_125_arg_0=0, var_126=1, var_126_arg_0=1, var_126_arg_1=255, var_127=255, var_127_arg_0=0, var_128=1, var_128_arg_0=1, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=1, var_130_arg_0=1, var_130_arg_1=255, var_131=1, var_131_arg_0=0, var_131_arg_1=1, var_132=255, var_132_arg_0=0, var_133=255, var_133_arg_0=0, var_134=255, var_134_arg_0=255, var_134_arg_1=255, var_135=255, var_135_arg_0=0, var_136=255, var_136_arg_0=255, var_136_arg_1=255, var_137=254, var_137_arg_0=1, var_138=254, var_138_arg_0=255, var_138_arg_1=254, var_139=0, var_139_arg_0=254, var_139_arg_1=0, var_14=0, var_140=255, var_140_arg_0=0, var_141=0, var_141_arg_0=0, var_141_arg_1=255, var_142=255, var_142_arg_0=0, var_143=0, var_143_arg_0=0, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=0, var_145_arg_0=0, var_145_arg_1=255, var_146=1, var_146_arg_0=1, var_146_arg_1=0, var_147=255, var_147_arg_0=0, var_148=255, var_148_arg_0=0, var_149=255, var_149_arg_0=255, var_149_arg_1=255, var_14_arg_0=255, var_15=0, var_150=255, var_150_arg_0=0, var_151=255, var_151_arg_0=255, var_151_arg_1=255, var_152=254, var_152_arg_0=1, var_153=254, var_153_arg_0=255, var_153_arg_1=254, var_154=255, var_154_arg_0=0, var_155=254, var_155_arg_0=254, var_155_arg_1=255, var_156=0, var_156_arg_0=254, var_156_arg_1=0, var_157=255, var_157_arg_0=0, var_158=0, var_158_arg_0=0, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=0, var_160_arg_0=0, var_160_arg_1=255, var_161=1, var_161_arg_0=1, var_161_arg_1=0, var_162=255, var_162_arg_0=0, var_163=255, var_163_arg_0=0, var_164=255, var_164_arg_0=255, var_164_arg_1=255, var_165=255, var_165_arg_0=0, var_166=255, var_166_arg_0=255, var_166_arg_1=255, var_167=254, var_167_arg_0=1, var_168=254, var_168_arg_0=255, var_168_arg_1=254, var_169=255, var_169_arg_0=0, var_170=254, var_170_arg_0=254, var_170_arg_1=255, var_171=255, var_171_arg_0=0, var_172=254, var_172_arg_0=254, var_172_arg_1=255, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=255, var_177_arg_0=0, var_178=255, var_178_arg_0=0, var_179=255, var_179_arg_0=255, var_179_arg_1=255, var_180=255, var_180_arg_0=0, var_181=255, var_181_arg_0=255, var_181_arg_1=255, var_182=254, var_182_arg_0=1, var_183=254, var_183_arg_0=255, var_183_arg_1=254, var_184=255, var_184_arg_0=0, var_185=254, var_185_arg_0=254, var_185_arg_1=255, var_186=255, var_186_arg_0=0, var_187=254, var_187_arg_0=254, var_187_arg_1=255, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=1, var_194_arg_0=128, var_194_arg_1=0, var_195=3, var_195_arg_0=1, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=0, var_196_arg_1=3, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=0, var_200_arg_0=128, var_200_arg_1=0, var_201=1, var_201_arg_0=4, var_201_arg_1=0, var_202=0, var_202_arg_0=0, var_202_arg_1=1, var_203=4, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=4, var_204=4, var_204_arg_0=1, var_204_arg_1=4, var_204_arg_2=0, var_205=4, var_205_arg_0=1, var_205_arg_1=4, var_205_arg_2=0, var_33=0, var_41=0, var_41_arg_0=0, var_41_arg_1=0, var_42=4, var_43=0, var_43_arg_0=0, var_43_arg_1=4, var_44=0, var_44_arg_0=0, var_44_arg_1=0, var_45=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_46_arg_0=1, var_46_arg_1=0, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=0, var_50=0, var_50_arg_0=1, var_50_arg_1=0, var_50_arg_2=0, var_52=0, var_52_arg_0=1, var_52_arg_1=0, var_52_arg_2=0, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=0, var_56_arg_0=0, var_56_arg_1=1, var_57=0, var_57_arg_0=1, var_57_arg_1=0, var_57_arg_2=1, var_59=1, var_59_arg_0=1, var_59_arg_1=1, var_59_arg_2=0, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=0, var_63_arg_1=254, var_64=0, var_64_arg_0=0, var_64_arg_1=0, var_65=0, var_65_arg_0=1, var_65_arg_1=0, var_65_arg_2=0, var_67=0, var_67_arg_0=0, var_67_arg_1=0, var_68=1, var_68_arg_0=0, var_68_arg_1=4, var_69=0, var_69_arg_0=0, var_69_arg_1=1, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=255, var_73_arg_0=0, var_74=0, var_74_arg_0=0, var_74_arg_1=255, var_75=255, var_75_arg_0=0, var_76=0, var_76_arg_0=0, var_76_arg_1=255, var_77=254, var_77_arg_0=1, var_78=0, var_78_arg_0=0, var_78_arg_1=254, var_79=255, var_79_arg_0=0, var_80=0, var_80_arg_0=0, var_80_arg_1=255, var_81=255, var_81_arg_0=0, var_82=0, var_82_arg_0=0, var_82_arg_1=255, var_83=255, var_83_arg_0=0, var_84=0, var_84_arg_0=0, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=0, var_86_arg_0=0, var_86_arg_1=255, var_87=255, var_87_arg_0=0, var_88=0, var_88_arg_0=255, var_88_arg_1=0, var_89=255, var_89_arg_0=0, var_90=0, var_90_arg_0=0, var_90_arg_1=255, var_91=254, var_91_arg_0=1, var_92=0, var_92_arg_0=0, var_92_arg_1=254, var_93=255, var_93_arg_0=0, var_94=0, var_94_arg_0=0, var_94_arg_1=255, var_95=255, var_95_arg_0=0, var_96=0, var_96_arg_0=0, var_96_arg_1=255, var_97=255, var_97_arg_0=0, var_98=0, var_98_arg_0=0, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=0, input_4=0, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=4, next_47_arg_1=0, next_49_arg_1=0, next_51_arg_1=0, next_53_arg_1=0, next_58_arg_1=0, next_60_arg_1=0, next_66_arg_1=1, next_72_arg_1=0, state_17=0, state_19=0, state_21=0, state_23=0, state_25=0, state_27=1, state_29=0, state_31=1, state_34=0, state_36=4, state_8=0, var_10=255, var_100=0, var_100_arg_0=0, var_100_arg_1=255, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_102=255, var_102_arg_0=0, var_103=255, var_103_arg_0=0, var_104=255, var_104_arg_0=255, var_104_arg_1=255, var_105=0, var_105_arg_0=255, var_105_arg_1=0, var_106=255, var_106_arg_0=0, var_107=0, var_107_arg_0=0, var_107_arg_1=255, var_108=254, var_108_arg_0=1, var_109=0, var_109_arg_0=0, var_109_arg_1=254, var_10_arg_0=0, var_110=255, var_110_arg_0=0, var_111=0, var_111_arg_0=0, var_111_arg_1=255, var_112=255, var_112_arg_0=0, var_113=0, var_113_arg_0=0, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=0, var_115_arg_0=0, var_115_arg_1=255, var_116=0, var_116_arg_0=0, var_116_arg_1=0, var_117=255, var_117_arg_0=0, var_118=255, var_118_arg_0=0, var_119=255, var_119_arg_0=255, var_119_arg_1=255, var_120=255, var_120_arg_0=0, var_121=255, var_121_arg_0=255, var_121_arg_1=255, var_122=0, var_122_arg_0=255, var_122_arg_1=0, var_123=254, var_123_arg_0=1, var_124=0, var_124_arg_0=0, var_124_arg_1=254, var_125=255, var_125_arg_0=0, var_126=0, var_126_arg_0=0, var_126_arg_1=255, var_127=255, var_127_arg_0=0, var_128=0, var_128_arg_0=0, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=0, var_130_arg_0=0, var_130_arg_1=255, var_131=0, var_131_arg_0=0, var_131_arg_1=0, var_132=255, var_132_arg_0=0, var_133=255, var_133_arg_0=0, var_134=255, var_134_arg_0=255, var_134_arg_1=255, var_135=255, var_135_arg_0=0, var_136=255, var_136_arg_0=255, var_136_arg_1=255, var_137=255, var_137_arg_0=0, var_138=255, var_138_arg_0=255, var_138_arg_1=255, var_139=1, var_139_arg_0=255, var_139_arg_1=1, var_14=0, var_140=255, var_140_arg_0=0, var_141=1, var_141_arg_0=1, var_141_arg_1=255, var_142=255, var_142_arg_0=0, var_143=1, var_143_arg_0=1, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=1, var_145_arg_0=1, var_145_arg_1=255, var_146=1, var_146_arg_0=0, var_146_arg_1=1, var_147=255, var_147_arg_0=0, var_148=255, var_148_arg_0=0, var_149=255, var_149_arg_0=255, var_149_arg_1=255, var_14_arg_0=255, var_15=0, var_150=255, var_150_arg_0=0, var_151=255, var_151_arg_0=255, var_151_arg_1=255, var_152=255, var_152_arg_0=0, var_153=255, var_153_arg_0=255, var_153_arg_1=255, var_154=254, var_154_arg_0=1, var_155=254, var_155_arg_0=255, var_155_arg_1=254, var_156=0, var_156_arg_0=254, var_156_arg_1=0, var_157=255, var_157_arg_0=0, var_158=0, var_158_arg_0=0, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=0, var_160_arg_0=0, var_160_arg_1=255, var_161=1, var_161_arg_0=1, var_161_arg_1=0, var_162=255, var_162_arg_0=0, var_163=255, var_163_arg_0=0, var_164=255, var_164_arg_0=255, var_164_arg_1=255, var_165=255, var_165_arg_0=0, var_166=255, var_166_arg_0=255, var_166_arg_1=255, var_167=255, var_167_arg_0=0, var_168=255, var_168_arg_0=255, var_168_arg_1=255, var_169=254, var_169_arg_0=1, var_170=254, var_170_arg_0=255, var_170_arg_1=254, var_171=255, var_171_arg_0=0, var_172=254, var_172_arg_0=254, var_172_arg_1=255, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=255, var_177_arg_0=0, var_178=255, var_178_arg_0=0, var_179=255, var_179_arg_0=255, var_179_arg_1=255, var_180=255, var_180_arg_0=0, var_181=255, var_181_arg_0=255, var_181_arg_1=255, var_182=255, var_182_arg_0=0, var_183=255, var_183_arg_0=255, var_183_arg_1=255, var_184=254, var_184_arg_0=1, var_185=254, var_185_arg_0=255, var_185_arg_1=254, var_186=255, var_186_arg_0=0, var_187=254, var_187_arg_0=254, var_187_arg_1=255, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=0, var_196_arg_1=0, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=1, var_200_arg_0=0, var_200_arg_1=0, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=1, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=0, var_204=4, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=4, var_205=4, var_205_arg_0=1, var_205_arg_1=4, var_205_arg_2=4, var_33=0, var_41=4, var_41_arg_0=0, var_41_arg_1=4, var_42=4, var_43=1, var_43_arg_0=4, var_43_arg_1=4, var_44=0, var_44_arg_0=0, var_44_arg_1=1, var_45=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_46_arg_0=1, var_46_arg_1=0, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=0, var_50=0, var_50_arg_0=1, var_50_arg_1=0, var_50_arg_2=0, var_52=0, var_52_arg_0=1, var_52_arg_1=0, var_52_arg_2=0, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=0, var_56_arg_0=0, var_56_arg_1=1, var_57=0, var_57_arg_0=1, var_57_arg_1=0, var_57_arg_2=0, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_59_arg_2=1, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=0, var_63_arg_1=254, var_64=1, var_64_arg_0=1, var_64_arg_1=0, var_65=1, var_65_arg_0=1, var_65_arg_1=1, var_65_arg_2=0, var_67=4, var_67_arg_0=0, var_67_arg_1=4, var_68=0, var_68_arg_0=4, var_68_arg_1=4, var_69=0, var_69_arg_0=0, var_69_arg_1=0, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=255, var_73_arg_0=0, var_74=0, var_74_arg_0=0, var_74_arg_1=255, var_75=255, var_75_arg_0=0, var_76=0, var_76_arg_0=0, var_76_arg_1=255, var_77=255, var_77_arg_0=0, var_78=0, var_78_arg_0=0, var_78_arg_1=255, var_79=254, var_79_arg_0=1, var_80=0, var_80_arg_0=0, var_80_arg_1=254, var_81=255, var_81_arg_0=0, var_82=0, var_82_arg_0=0, var_82_arg_1=255, var_83=255, var_83_arg_0=0, var_84=0, var_84_arg_0=0, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=0, var_86_arg_0=0, var_86_arg_1=255, var_87=255, var_87_arg_0=0, var_88=0, var_88_arg_0=255, var_88_arg_1=0, var_89=255, var_89_arg_0=0, var_90=0, var_90_arg_0=0, var_90_arg_1=255, var_91=255, var_91_arg_0=0, var_92=0, var_92_arg_0=0, var_92_arg_1=255, var_93=254, var_93_arg_0=1, var_94=0, var_94_arg_0=0, var_94_arg_1=254, var_95=255, var_95_arg_0=0, var_96=0, var_96_arg_0=0, var_96_arg_1=255, var_97=255, var_97_arg_0=0, var_98=0, var_98_arg_0=0, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L100] RET __VERIFIER_assert(!(bad_16_arg_0)) [L102] SORT_1 var_41_arg_0 = state_34; [L103] SORT_1 var_41_arg_1 = state_36; [L104] SORT_1 var_41 = var_41_arg_0 + var_41_arg_1; [L105] var_41 = var_41 & mask_SORT_1 [L106] SORT_1 var_43_arg_0 = var_41; [L107] SORT_1 var_43_arg_1 = var_42; [L108] SORT_5 var_43 = var_43_arg_0 == var_43_arg_1; [L109] SORT_5 var_44_arg_0 = state_27; [L110] SORT_5 var_44_arg_1 = var_43; [L111] SORT_5 var_44 = var_44_arg_0 & var_44_arg_1; [L112] SORT_5 var_45_arg_0 = state_8; [L113] SORT_5 var_45_arg_1 = var_44; [L114] SORT_5 var_45 = var_45_arg_0 | var_45_arg_1; [L115] SORT_5 var_46_arg_0 = state_31; [L116] SORT_5 var_46_arg_1 = var_45; [L117] SORT_5 var_46_arg_2 = state_8; [L118] SORT_5 var_46 = var_46_arg_0 ? var_46_arg_1 : var_46_arg_2; [L119] SORT_5 next_47_arg_1 = var_46; [L120] SORT_5 var_48_arg_0 = state_31; [L121] SORT_5 var_48_arg_1 = var_7; [L122] SORT_5 var_48_arg_2 = state_17; [L123] SORT_5 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L124] SORT_5 next_49_arg_1 = var_48; [L125] SORT_5 var_50_arg_0 = state_31; [L126] SORT_5 var_50_arg_1 = state_17; [L127] SORT_5 var_50_arg_2 = state_19; [L128] SORT_5 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; [L129] var_50 = var_50 & mask_SORT_5 [L130] SORT_5 next_51_arg_1 = var_50; [L131] SORT_5 var_52_arg_0 = state_31; [L132] SORT_5 var_52_arg_1 = state_19; [L133] SORT_5 var_52_arg_2 = state_21; [L134] SORT_5 var_52 = var_52_arg_0 ? var_52_arg_1 : var_52_arg_2; [L135] SORT_5 next_53_arg_1 = var_52; [L136] SORT_1 var_55_arg_0 = input_3; [L137] SORT_1 var_55_arg_1 = var_54; [L138] SORT_5 var_55 = var_55_arg_0 < var_55_arg_1; [L139] SORT_5 var_56_arg_0 = state_21; [L140] SORT_5 var_56_arg_1 = var_55; [L141] SORT_5 var_56 = var_56_arg_0 & var_56_arg_1; [L142] SORT_5 var_57_arg_0 = state_31; [L143] SORT_5 var_57_arg_1 = var_56; [L144] SORT_5 var_57_arg_2 = state_23; [L145] SORT_5 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L146] var_57 = var_57 & mask_SORT_5 [L147] SORT_5 next_58_arg_1 = var_57; [L148] SORT_5 var_59_arg_0 = state_31; [L149] SORT_5 var_59_arg_1 = state_23; [L150] SORT_5 var_59_arg_2 = state_25; [L151] SORT_5 var_59 = var_59_arg_0 ? var_59_arg_1 : var_59_arg_2; [L152] SORT_5 next_60_arg_1 = var_59; [L153] SORT_1 var_61_arg_0 = input_3; [L154] SORT_1 var_61_arg_1 = var_54; [L155] SORT_5 var_61 = var_61_arg_0 < var_61_arg_1; [L156] SORT_5 var_62_arg_0 = var_61; [L157] SORT_5 var_62 = ~var_62_arg_0; [L158] SORT_5 var_63_arg_0 = state_21; [L159] SORT_5 var_63_arg_1 = var_62; [L160] SORT_5 var_63 = var_63_arg_0 & var_63_arg_1; [L161] SORT_5 var_64_arg_0 = state_25; [L162] SORT_5 var_64_arg_1 = var_63; [L163] SORT_5 var_64 = var_64_arg_0 | var_64_arg_1; [L164] SORT_5 var_65_arg_0 = state_31; [L165] SORT_5 var_65_arg_1 = var_64; [L166] SORT_5 var_65_arg_2 = state_27; [L167] SORT_5 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L168] SORT_5 next_66_arg_1 = var_65; [L169] SORT_1 var_67_arg_0 = state_34; [L170] SORT_1 var_67_arg_1 = state_36; [L171] SORT_1 var_67 = var_67_arg_0 + var_67_arg_1; [L172] var_67 = var_67 & mask_SORT_1 [L173] SORT_1 var_68_arg_0 = var_67; [L174] SORT_1 var_68_arg_1 = var_42; [L175] SORT_5 var_68 = var_68_arg_0 != var_68_arg_1; [L176] SORT_5 var_69_arg_0 = state_27; [L177] SORT_5 var_69_arg_1 = var_68; [L178] SORT_5 var_69 = var_69_arg_0 & var_69_arg_1; [L179] SORT_5 var_70_arg_0 = state_29; [L180] SORT_5 var_70_arg_1 = var_69; [L181] SORT_5 var_70 = var_70_arg_0 | var_70_arg_1; [L182] SORT_5 var_71_arg_0 = state_31; [L183] SORT_5 var_71_arg_1 = var_70; [L184] SORT_5 var_71_arg_2 = state_29; [L185] SORT_5 var_71 = var_71_arg_0 ? var_71_arg_1 : var_71_arg_2; [L186] SORT_5 next_72_arg_1 = var_71; [L187] SORT_5 var_73_arg_0 = state_19; [L188] SORT_5 var_73 = ~var_73_arg_0; [L189] SORT_5 var_74_arg_0 = state_17; [L190] SORT_5 var_74_arg_1 = var_73; [L191] SORT_5 var_74 = var_74_arg_0 & var_74_arg_1; [L192] SORT_5 var_75_arg_0 = state_21; [L193] SORT_5 var_75 = ~var_75_arg_0; [L194] SORT_5 var_76_arg_0 = var_74; [L195] SORT_5 var_76_arg_1 = var_75; [L196] SORT_5 var_76 = var_76_arg_0 & var_76_arg_1; [L197] SORT_5 var_77_arg_0 = state_23; [L198] SORT_5 var_77 = ~var_77_arg_0; [L199] SORT_5 var_78_arg_0 = var_76; [L200] SORT_5 var_78_arg_1 = var_77; [L201] SORT_5 var_78 = var_78_arg_0 & var_78_arg_1; [L202] SORT_5 var_79_arg_0 = state_25; [L203] SORT_5 var_79 = ~var_79_arg_0; [L204] SORT_5 var_80_arg_0 = var_78; [L205] SORT_5 var_80_arg_1 = var_79; [L206] SORT_5 var_80 = var_80_arg_0 & var_80_arg_1; [L207] SORT_5 var_81_arg_0 = state_27; [L208] SORT_5 var_81 = ~var_81_arg_0; [L209] SORT_5 var_82_arg_0 = var_80; [L210] SORT_5 var_82_arg_1 = var_81; [L211] SORT_5 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_5 var_83_arg_0 = state_29; [L213] SORT_5 var_83 = ~var_83_arg_0; [L214] SORT_5 var_84_arg_0 = var_82; [L215] SORT_5 var_84_arg_1 = var_83; [L216] SORT_5 var_84 = var_84_arg_0 & var_84_arg_1; [L217] SORT_5 var_85_arg_0 = state_8; [L218] SORT_5 var_85 = ~var_85_arg_0; [L219] SORT_5 var_86_arg_0 = var_84; [L220] SORT_5 var_86_arg_1 = var_85; [L221] SORT_5 var_86 = var_86_arg_0 & var_86_arg_1; [L222] SORT_5 var_87_arg_0 = state_17; [L223] SORT_5 var_87 = ~var_87_arg_0; [L224] SORT_5 var_88_arg_0 = var_87; [L225] SORT_5 var_88_arg_1 = state_19; [L226] SORT_5 var_88 = var_88_arg_0 & var_88_arg_1; [L227] SORT_5 var_89_arg_0 = state_21; [L228] SORT_5 var_89 = ~var_89_arg_0; [L229] SORT_5 var_90_arg_0 = var_88; [L230] SORT_5 var_90_arg_1 = var_89; [L231] SORT_5 var_90 = var_90_arg_0 & var_90_arg_1; [L232] SORT_5 var_91_arg_0 = state_23; [L233] SORT_5 var_91 = ~var_91_arg_0; [L234] SORT_5 var_92_arg_0 = var_90; [L235] SORT_5 var_92_arg_1 = var_91; [L236] SORT_5 var_92 = var_92_arg_0 & var_92_arg_1; [L237] SORT_5 var_93_arg_0 = state_25; [L238] SORT_5 var_93 = ~var_93_arg_0; [L239] SORT_5 var_94_arg_0 = var_92; [L240] SORT_5 var_94_arg_1 = var_93; [L241] SORT_5 var_94 = var_94_arg_0 & var_94_arg_1; [L242] SORT_5 var_95_arg_0 = state_27; [L243] SORT_5 var_95 = ~var_95_arg_0; [L244] SORT_5 var_96_arg_0 = var_94; [L245] SORT_5 var_96_arg_1 = var_95; [L246] SORT_5 var_96 = var_96_arg_0 & var_96_arg_1; [L247] SORT_5 var_97_arg_0 = state_29; [L248] SORT_5 var_97 = ~var_97_arg_0; [L249] SORT_5 var_98_arg_0 = var_96; [L250] SORT_5 var_98_arg_1 = var_97; [L251] SORT_5 var_98 = var_98_arg_0 & var_98_arg_1; [L252] SORT_5 var_99_arg_0 = state_8; [L253] SORT_5 var_99 = ~var_99_arg_0; [L254] SORT_5 var_100_arg_0 = var_98; [L255] SORT_5 var_100_arg_1 = var_99; [L256] SORT_5 var_100 = var_100_arg_0 & var_100_arg_1; [L257] SORT_5 var_101_arg_0 = var_86; [L258] SORT_5 var_101_arg_1 = var_100; [L259] SORT_5 var_101 = var_101_arg_0 | var_101_arg_1; [L260] SORT_5 var_102_arg_0 = state_17; [L261] SORT_5 var_102 = ~var_102_arg_0; [L262] SORT_5 var_103_arg_0 = state_19; [L263] SORT_5 var_103 = ~var_103_arg_0; [L264] SORT_5 var_104_arg_0 = var_102; [L265] SORT_5 var_104_arg_1 = var_103; [L266] SORT_5 var_104 = var_104_arg_0 & var_104_arg_1; [L267] SORT_5 var_105_arg_0 = var_104; [L268] SORT_5 var_105_arg_1 = state_21; [L269] SORT_5 var_105 = var_105_arg_0 & var_105_arg_1; [L270] SORT_5 var_106_arg_0 = state_23; [L271] SORT_5 var_106 = ~var_106_arg_0; [L272] SORT_5 var_107_arg_0 = var_105; [L273] SORT_5 var_107_arg_1 = var_106; [L274] SORT_5 var_107 = var_107_arg_0 & var_107_arg_1; [L275] SORT_5 var_108_arg_0 = state_25; [L276] SORT_5 var_108 = ~var_108_arg_0; [L277] SORT_5 var_109_arg_0 = var_107; [L278] SORT_5 var_109_arg_1 = var_108; [L279] SORT_5 var_109 = var_109_arg_0 & var_109_arg_1; [L280] SORT_5 var_110_arg_0 = state_27; [L281] SORT_5 var_110 = ~var_110_arg_0; [L282] SORT_5 var_111_arg_0 = var_109; [L283] SORT_5 var_111_arg_1 = var_110; [L284] SORT_5 var_111 = var_111_arg_0 & var_111_arg_1; [L285] SORT_5 var_112_arg_0 = state_29; [L286] SORT_5 var_112 = ~var_112_arg_0; [L287] SORT_5 var_113_arg_0 = var_111; [L288] SORT_5 var_113_arg_1 = var_112; [L289] SORT_5 var_113 = var_113_arg_0 & var_113_arg_1; [L290] SORT_5 var_114_arg_0 = state_8; [L291] SORT_5 var_114 = ~var_114_arg_0; [L292] SORT_5 var_115_arg_0 = var_113; [L293] SORT_5 var_115_arg_1 = var_114; [L294] SORT_5 var_115 = var_115_arg_0 & var_115_arg_1; [L295] SORT_5 var_116_arg_0 = var_101; [L296] SORT_5 var_116_arg_1 = var_115; [L297] SORT_5 var_116 = var_116_arg_0 | var_116_arg_1; [L298] SORT_5 var_117_arg_0 = state_17; [L299] SORT_5 var_117 = ~var_117_arg_0; [L300] SORT_5 var_118_arg_0 = state_19; [L301] SORT_5 var_118 = ~var_118_arg_0; [L302] SORT_5 var_119_arg_0 = var_117; [L303] SORT_5 var_119_arg_1 = var_118; [L304] SORT_5 var_119 = var_119_arg_0 & var_119_arg_1; [L305] SORT_5 var_120_arg_0 = state_21; [L306] SORT_5 var_120 = ~var_120_arg_0; [L307] SORT_5 var_121_arg_0 = var_119; [L308] SORT_5 var_121_arg_1 = var_120; [L309] SORT_5 var_121 = var_121_arg_0 & var_121_arg_1; [L310] SORT_5 var_122_arg_0 = var_121; [L311] SORT_5 var_122_arg_1 = state_23; [L312] SORT_5 var_122 = var_122_arg_0 & var_122_arg_1; [L313] SORT_5 var_123_arg_0 = state_25; [L314] SORT_5 var_123 = ~var_123_arg_0; [L315] SORT_5 var_124_arg_0 = var_122; [L316] SORT_5 var_124_arg_1 = var_123; [L317] SORT_5 var_124 = var_124_arg_0 & var_124_arg_1; [L318] SORT_5 var_125_arg_0 = state_27; [L319] SORT_5 var_125 = ~var_125_arg_0; [L320] SORT_5 var_126_arg_0 = var_124; [L321] SORT_5 var_126_arg_1 = var_125; [L322] SORT_5 var_126 = var_126_arg_0 & var_126_arg_1; [L323] SORT_5 var_127_arg_0 = state_29; [L324] SORT_5 var_127 = ~var_127_arg_0; [L325] SORT_5 var_128_arg_0 = var_126; [L326] SORT_5 var_128_arg_1 = var_127; [L327] SORT_5 var_128 = var_128_arg_0 & var_128_arg_1; [L328] SORT_5 var_129_arg_0 = state_8; [L329] SORT_5 var_129 = ~var_129_arg_0; [L330] SORT_5 var_130_arg_0 = var_128; [L331] SORT_5 var_130_arg_1 = var_129; [L332] SORT_5 var_130 = var_130_arg_0 & var_130_arg_1; [L333] SORT_5 var_131_arg_0 = var_116; [L334] SORT_5 var_131_arg_1 = var_130; [L335] SORT_5 var_131 = var_131_arg_0 | var_131_arg_1; [L336] SORT_5 var_132_arg_0 = state_17; [L337] SORT_5 var_132 = ~var_132_arg_0; [L338] SORT_5 var_133_arg_0 = state_19; [L339] SORT_5 var_133 = ~var_133_arg_0; [L340] SORT_5 var_134_arg_0 = var_132; [L341] SORT_5 var_134_arg_1 = var_133; [L342] SORT_5 var_134 = var_134_arg_0 & var_134_arg_1; [L343] SORT_5 var_135_arg_0 = state_21; [L344] SORT_5 var_135 = ~var_135_arg_0; [L345] SORT_5 var_136_arg_0 = var_134; [L346] SORT_5 var_136_arg_1 = var_135; [L347] SORT_5 var_136 = var_136_arg_0 & var_136_arg_1; [L348] SORT_5 var_137_arg_0 = state_23; [L349] SORT_5 var_137 = ~var_137_arg_0; [L350] SORT_5 var_138_arg_0 = var_136; [L351] SORT_5 var_138_arg_1 = var_137; [L352] SORT_5 var_138 = var_138_arg_0 & var_138_arg_1; [L353] SORT_5 var_139_arg_0 = var_138; [L354] SORT_5 var_139_arg_1 = state_25; [L355] SORT_5 var_139 = var_139_arg_0 & var_139_arg_1; [L356] SORT_5 var_140_arg_0 = state_27; [L357] SORT_5 var_140 = ~var_140_arg_0; [L358] SORT_5 var_141_arg_0 = var_139; [L359] SORT_5 var_141_arg_1 = var_140; [L360] SORT_5 var_141 = var_141_arg_0 & var_141_arg_1; [L361] SORT_5 var_142_arg_0 = state_29; [L362] SORT_5 var_142 = ~var_142_arg_0; [L363] SORT_5 var_143_arg_0 = var_141; [L364] SORT_5 var_143_arg_1 = var_142; [L365] SORT_5 var_143 = var_143_arg_0 & var_143_arg_1; [L366] SORT_5 var_144_arg_0 = state_8; [L367] SORT_5 var_144 = ~var_144_arg_0; [L368] SORT_5 var_145_arg_0 = var_143; [L369] SORT_5 var_145_arg_1 = var_144; [L370] SORT_5 var_145 = var_145_arg_0 & var_145_arg_1; [L371] SORT_5 var_146_arg_0 = var_131; [L372] SORT_5 var_146_arg_1 = var_145; [L373] SORT_5 var_146 = var_146_arg_0 | var_146_arg_1; [L374] SORT_5 var_147_arg_0 = state_17; [L375] SORT_5 var_147 = ~var_147_arg_0; [L376] SORT_5 var_148_arg_0 = state_19; [L377] SORT_5 var_148 = ~var_148_arg_0; [L378] SORT_5 var_149_arg_0 = var_147; [L379] SORT_5 var_149_arg_1 = var_148; [L380] SORT_5 var_149 = var_149_arg_0 & var_149_arg_1; [L381] SORT_5 var_150_arg_0 = state_21; [L382] SORT_5 var_150 = ~var_150_arg_0; [L383] SORT_5 var_151_arg_0 = var_149; [L384] SORT_5 var_151_arg_1 = var_150; [L385] SORT_5 var_151 = var_151_arg_0 & var_151_arg_1; [L386] SORT_5 var_152_arg_0 = state_23; [L387] SORT_5 var_152 = ~var_152_arg_0; [L388] SORT_5 var_153_arg_0 = var_151; [L389] SORT_5 var_153_arg_1 = var_152; [L390] SORT_5 var_153 = var_153_arg_0 & var_153_arg_1; [L391] SORT_5 var_154_arg_0 = state_25; [L392] SORT_5 var_154 = ~var_154_arg_0; [L393] SORT_5 var_155_arg_0 = var_153; [L394] SORT_5 var_155_arg_1 = var_154; [L395] SORT_5 var_155 = var_155_arg_0 & var_155_arg_1; [L396] SORT_5 var_156_arg_0 = var_155; [L397] SORT_5 var_156_arg_1 = state_27; [L398] SORT_5 var_156 = var_156_arg_0 & var_156_arg_1; [L399] SORT_5 var_157_arg_0 = state_29; [L400] SORT_5 var_157 = ~var_157_arg_0; [L401] SORT_5 var_158_arg_0 = var_156; [L402] SORT_5 var_158_arg_1 = var_157; [L403] SORT_5 var_158 = var_158_arg_0 & var_158_arg_1; [L404] SORT_5 var_159_arg_0 = state_8; [L405] SORT_5 var_159 = ~var_159_arg_0; [L406] SORT_5 var_160_arg_0 = var_158; [L407] SORT_5 var_160_arg_1 = var_159; [L408] SORT_5 var_160 = var_160_arg_0 & var_160_arg_1; [L409] SORT_5 var_161_arg_0 = var_146; [L410] SORT_5 var_161_arg_1 = var_160; [L411] SORT_5 var_161 = var_161_arg_0 | var_161_arg_1; [L412] SORT_5 var_162_arg_0 = state_17; [L413] SORT_5 var_162 = ~var_162_arg_0; [L414] SORT_5 var_163_arg_0 = state_19; [L415] SORT_5 var_163 = ~var_163_arg_0; [L416] SORT_5 var_164_arg_0 = var_162; [L417] SORT_5 var_164_arg_1 = var_163; [L418] SORT_5 var_164 = var_164_arg_0 & var_164_arg_1; [L419] SORT_5 var_165_arg_0 = state_21; [L420] SORT_5 var_165 = ~var_165_arg_0; [L421] SORT_5 var_166_arg_0 = var_164; [L422] SORT_5 var_166_arg_1 = var_165; [L423] SORT_5 var_166 = var_166_arg_0 & var_166_arg_1; [L424] SORT_5 var_167_arg_0 = state_23; [L425] SORT_5 var_167 = ~var_167_arg_0; [L426] SORT_5 var_168_arg_0 = var_166; [L427] SORT_5 var_168_arg_1 = var_167; [L428] SORT_5 var_168 = var_168_arg_0 & var_168_arg_1; [L429] SORT_5 var_169_arg_0 = state_25; [L430] SORT_5 var_169 = ~var_169_arg_0; [L431] SORT_5 var_170_arg_0 = var_168; [L432] SORT_5 var_170_arg_1 = var_169; [L433] SORT_5 var_170 = var_170_arg_0 & var_170_arg_1; [L434] SORT_5 var_171_arg_0 = state_27; [L435] SORT_5 var_171 = ~var_171_arg_0; [L436] SORT_5 var_172_arg_0 = var_170; [L437] SORT_5 var_172_arg_1 = var_171; [L438] SORT_5 var_172 = var_172_arg_0 & var_172_arg_1; [L439] SORT_5 var_173_arg_0 = var_172; [L440] SORT_5 var_173_arg_1 = state_29; [L441] SORT_5 var_173 = var_173_arg_0 & var_173_arg_1; [L442] SORT_5 var_174_arg_0 = state_8; [L443] SORT_5 var_174 = ~var_174_arg_0; [L444] SORT_5 var_175_arg_0 = var_173; [L445] SORT_5 var_175_arg_1 = var_174; [L446] SORT_5 var_175 = var_175_arg_0 & var_175_arg_1; [L447] SORT_5 var_176_arg_0 = var_161; [L448] SORT_5 var_176_arg_1 = var_175; [L449] SORT_5 var_176 = var_176_arg_0 | var_176_arg_1; [L450] SORT_5 var_177_arg_0 = state_17; [L451] SORT_5 var_177 = ~var_177_arg_0; [L452] SORT_5 var_178_arg_0 = state_19; [L453] SORT_5 var_178 = ~var_178_arg_0; [L454] SORT_5 var_179_arg_0 = var_177; [L455] SORT_5 var_179_arg_1 = var_178; [L456] SORT_5 var_179 = var_179_arg_0 & var_179_arg_1; [L457] SORT_5 var_180_arg_0 = state_21; [L458] SORT_5 var_180 = ~var_180_arg_0; [L459] SORT_5 var_181_arg_0 = var_179; [L460] SORT_5 var_181_arg_1 = var_180; [L461] SORT_5 var_181 = var_181_arg_0 & var_181_arg_1; [L462] SORT_5 var_182_arg_0 = state_23; [L463] SORT_5 var_182 = ~var_182_arg_0; [L464] SORT_5 var_183_arg_0 = var_181; [L465] SORT_5 var_183_arg_1 = var_182; [L466] SORT_5 var_183 = var_183_arg_0 & var_183_arg_1; [L467] SORT_5 var_184_arg_0 = state_25; [L468] SORT_5 var_184 = ~var_184_arg_0; [L469] SORT_5 var_185_arg_0 = var_183; [L470] SORT_5 var_185_arg_1 = var_184; [L471] SORT_5 var_185 = var_185_arg_0 & var_185_arg_1; [L472] SORT_5 var_186_arg_0 = state_27; [L473] SORT_5 var_186 = ~var_186_arg_0; [L474] SORT_5 var_187_arg_0 = var_185; [L475] SORT_5 var_187_arg_1 = var_186; [L476] SORT_5 var_187 = var_187_arg_0 & var_187_arg_1; [L477] SORT_5 var_188_arg_0 = state_29; [L478] SORT_5 var_188 = ~var_188_arg_0; [L479] SORT_5 var_189_arg_0 = var_187; [L480] SORT_5 var_189_arg_1 = var_188; [L481] SORT_5 var_189 = var_189_arg_0 & var_189_arg_1; [L482] SORT_5 var_190_arg_0 = var_189; [L483] SORT_5 var_190_arg_1 = state_8; [L484] SORT_5 var_190 = var_190_arg_0 & var_190_arg_1; [L485] SORT_5 var_191_arg_0 = var_176; [L486] SORT_5 var_191_arg_1 = var_190; [L487] SORT_5 var_191 = var_191_arg_0 | var_191_arg_1; [L488] var_191 = var_191 & mask_SORT_5 [L489] SORT_5 next_192_arg_1 = var_191; [L490] SORT_1 var_194_arg_0 = input_2; [L491] SORT_1 var_194_arg_1 = var_33; [L492] SORT_5 var_194 = var_194_arg_0 != var_194_arg_1; [L493] SORT_5 var_195_arg_0 = var_194; [L494] SORT_1 var_195_arg_1 = var_193; [L495] SORT_1 var_195_arg_2 = state_34; [L496] SORT_1 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L497] SORT_5 var_196_arg_0 = state_19; [L498] SORT_1 var_196_arg_1 = var_195; [L499] SORT_1 var_196_arg_2 = state_34; [L500] SORT_1 var_196 = var_196_arg_0 ? var_196_arg_1 : var_196_arg_2; [L501] SORT_5 var_197_arg_0 = state_31; [L502] SORT_1 var_197_arg_1 = var_196; [L503] SORT_1 var_197_arg_2 = state_34; [L504] SORT_1 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L505] SORT_1 next_198_arg_1 = var_197; [L506] SORT_1 var_200_arg_0 = input_2; [L507] SORT_1 var_200_arg_1 = var_33; [L508] SORT_5 var_200 = var_200_arg_0 == var_200_arg_1; [L509] SORT_1 var_201_arg_0 = input_4; [L510] SORT_1 var_201_arg_1 = var_33; [L511] SORT_5 var_201 = var_201_arg_0 != var_201_arg_1; [L512] SORT_5 var_202_arg_0 = var_200; [L513] SORT_5 var_202_arg_1 = var_201; [L514] SORT_5 var_202 = var_202_arg_0 & var_202_arg_1; [L515] var_202 = var_202 & mask_SORT_5 [L516] SORT_5 var_203_arg_0 = var_202; [L517] SORT_1 var_203_arg_1 = var_199; [L518] SORT_1 var_203_arg_2 = input_4; [L519] SORT_1 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L520] SORT_5 var_204_arg_0 = state_23; [L521] SORT_1 var_204_arg_1 = var_203; [L522] SORT_1 var_204_arg_2 = state_36; [L523] SORT_1 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L524] SORT_5 var_205_arg_0 = state_31; [L525] SORT_1 var_205_arg_1 = var_204; [L526] SORT_1 var_205_arg_2 = state_36; [L527] SORT_1 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L528] SORT_1 next_206_arg_1 = var_205; [L530] state_8 = next_47_arg_1 [L531] state_17 = next_49_arg_1 [L532] state_19 = next_51_arg_1 [L533] state_21 = next_53_arg_1 [L534] state_23 = next_58_arg_1 [L535] state_25 = next_60_arg_1 [L536] state_27 = next_66_arg_1 [L537] state_29 = next_72_arg_1 [L538] state_31 = next_192_arg_1 [L539] state_34 = next_198_arg_1 [L540] state_36 = next_206_arg_1 VAL [bad_16_arg_0=0, init_18_arg_1=1, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=1, init_35_arg_1=0, init_37_arg_1=0, init_9_arg_1=0, input_2=0, input_3=0, input_38=0, input_4=0, input_6=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_192_arg_1=1, next_198_arg_1=0, next_206_arg_1=4, next_47_arg_1=1, next_49_arg_1=0, next_51_arg_1=0, next_53_arg_1=0, next_58_arg_1=0, next_60_arg_1=0, next_66_arg_1=0, next_72_arg_1=0, state_17=0, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=1, state_34=0, state_36=4, state_8=1, var_10=255, var_100=0, var_100_arg_0=0, var_100_arg_1=255, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_102=255, var_102_arg_0=0, var_103=255, var_103_arg_0=0, var_104=255, var_104_arg_0=255, var_104_arg_1=255, var_105=0, var_105_arg_0=255, var_105_arg_1=0, var_106=255, var_106_arg_0=0, var_107=0, var_107_arg_0=0, var_107_arg_1=255, var_108=255, var_108_arg_0=0, var_109=0, var_109_arg_0=0, var_109_arg_1=255, var_10_arg_0=0, var_110=254, var_110_arg_0=1, var_111=0, var_111_arg_0=0, var_111_arg_1=254, var_112=255, var_112_arg_0=0, var_113=0, var_113_arg_0=0, var_113_arg_1=255, var_114=255, var_114_arg_0=0, var_115=0, var_115_arg_0=0, var_115_arg_1=255, var_116=0, var_116_arg_0=0, var_116_arg_1=0, var_117=255, var_117_arg_0=0, var_118=255, var_118_arg_0=0, var_119=255, var_119_arg_0=255, var_119_arg_1=255, var_120=255, var_120_arg_0=0, var_121=255, var_121_arg_0=255, var_121_arg_1=255, var_122=0, var_122_arg_0=255, var_122_arg_1=0, var_123=255, var_123_arg_0=0, var_124=0, var_124_arg_0=0, var_124_arg_1=255, var_125=254, var_125_arg_0=1, var_126=0, var_126_arg_0=0, var_126_arg_1=254, var_127=255, var_127_arg_0=0, var_128=0, var_128_arg_0=0, var_128_arg_1=255, var_129=255, var_129_arg_0=0, var_13=1, var_130=0, var_130_arg_0=0, var_130_arg_1=255, var_131=0, var_131_arg_0=0, var_131_arg_1=0, var_132=255, var_132_arg_0=0, var_133=255, var_133_arg_0=0, var_134=255, var_134_arg_0=255, var_134_arg_1=255, var_135=255, var_135_arg_0=0, var_136=255, var_136_arg_0=255, var_136_arg_1=255, var_137=255, var_137_arg_0=0, var_138=255, var_138_arg_0=255, var_138_arg_1=255, var_139=0, var_139_arg_0=255, var_139_arg_1=0, var_14=0, var_140=254, var_140_arg_0=1, var_141=0, var_141_arg_0=0, var_141_arg_1=254, var_142=255, var_142_arg_0=0, var_143=0, var_143_arg_0=0, var_143_arg_1=255, var_144=255, var_144_arg_0=0, var_145=0, var_145_arg_0=0, var_145_arg_1=255, var_146=0, var_146_arg_0=0, var_146_arg_1=0, var_147=255, var_147_arg_0=0, var_148=255, var_148_arg_0=0, var_149=255, var_149_arg_0=255, var_149_arg_1=255, var_14_arg_0=255, var_15=0, var_150=255, var_150_arg_0=0, var_151=255, var_151_arg_0=255, var_151_arg_1=255, var_152=255, var_152_arg_0=0, var_153=255, var_153_arg_0=255, var_153_arg_1=255, var_154=255, var_154_arg_0=0, var_155=255, var_155_arg_0=255, var_155_arg_1=255, var_156=1, var_156_arg_0=255, var_156_arg_1=1, var_157=255, var_157_arg_0=0, var_158=1, var_158_arg_0=1, var_158_arg_1=255, var_159=255, var_159_arg_0=0, var_15_arg_0=1, var_15_arg_1=0, var_160=1, var_160_arg_0=1, var_160_arg_1=255, var_161=1, var_161_arg_0=0, var_161_arg_1=1, var_162=255, var_162_arg_0=0, var_163=255, var_163_arg_0=0, var_164=255, var_164_arg_0=255, var_164_arg_1=255, var_165=255, var_165_arg_0=0, var_166=255, var_166_arg_0=255, var_166_arg_1=255, var_167=255, var_167_arg_0=0, var_168=255, var_168_arg_0=255, var_168_arg_1=255, var_169=255, var_169_arg_0=0, var_170=255, var_170_arg_0=255, var_170_arg_1=255, var_171=254, var_171_arg_0=1, var_172=254, var_172_arg_0=255, var_172_arg_1=254, var_173=0, var_173_arg_0=254, var_173_arg_1=0, var_174=255, var_174_arg_0=0, var_175=0, var_175_arg_0=0, var_175_arg_1=255, var_176=1, var_176_arg_0=1, var_176_arg_1=0, var_177=255, var_177_arg_0=0, var_178=255, var_178_arg_0=0, var_179=255, var_179_arg_0=255, var_179_arg_1=255, var_180=255, var_180_arg_0=0, var_181=255, var_181_arg_0=255, var_181_arg_1=255, var_182=255, var_182_arg_0=0, var_183=255, var_183_arg_0=255, var_183_arg_1=255, var_184=255, var_184_arg_0=0, var_185=255, var_185_arg_0=255, var_185_arg_1=255, var_186=254, var_186_arg_0=1, var_187=254, var_187_arg_0=255, var_187_arg_1=254, var_188=255, var_188_arg_0=0, var_189=254, var_189_arg_0=254, var_189_arg_1=255, var_190=0, var_190_arg_0=254, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_193=3, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_195_arg_1=3, var_195_arg_2=0, var_196=0, var_196_arg_0=0, var_196_arg_1=0, var_196_arg_2=0, var_197=0, var_197_arg_0=1, var_197_arg_1=0, var_197_arg_2=0, var_199=2, var_200=1, var_200_arg_0=0, var_200_arg_1=0, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=1, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=2, var_203_arg_2=0, var_204=4, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=4, var_205=4, var_205_arg_0=1, var_205_arg_1=4, var_205_arg_2=4, var_33=0, var_41=4, var_41_arg_0=0, var_41_arg_1=4, var_42=4, var_43=1, var_43_arg_0=4, var_43_arg_1=4, var_44=1, var_44_arg_0=1, var_44_arg_1=1, var_45=1, var_45_arg_0=0, var_45_arg_1=1, var_46=1, var_46_arg_0=1, var_46_arg_1=1, var_46_arg_2=0, var_48=0, var_48_arg_0=1, var_48_arg_1=0, var_48_arg_2=0, var_50=0, var_50_arg_0=1, var_50_arg_1=0, var_50_arg_2=0, var_52=0, var_52_arg_0=1, var_52_arg_1=0, var_52_arg_2=0, var_54=5, var_55=1, var_55_arg_0=0, var_55_arg_1=5, var_56=0, var_56_arg_0=0, var_56_arg_1=1, var_57=0, var_57_arg_0=1, var_57_arg_1=0, var_57_arg_2=0, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_59_arg_2=0, var_61=1, var_61_arg_0=0, var_61_arg_1=5, var_62=254, var_62_arg_0=1, var_63=0, var_63_arg_0=0, var_63_arg_1=254, var_64=0, var_64_arg_0=0, var_64_arg_1=0, var_65=0, var_65_arg_0=1, var_65_arg_1=0, var_65_arg_2=1, var_67=4, var_67_arg_0=0, var_67_arg_1=4, var_68=0, var_68_arg_0=4, var_68_arg_1=4, var_69=0, var_69_arg_0=1, var_69_arg_1=0, var_7=0, var_70=0, var_70_arg_0=0, var_70_arg_1=0, var_71=0, var_71_arg_0=1, var_71_arg_1=0, var_71_arg_2=0, var_73=255, var_73_arg_0=0, var_74=0, var_74_arg_0=0, var_74_arg_1=255, var_75=255, var_75_arg_0=0, var_76=0, var_76_arg_0=0, var_76_arg_1=255, var_77=255, var_77_arg_0=0, var_78=0, var_78_arg_0=0, var_78_arg_1=255, var_79=255, var_79_arg_0=0, var_80=0, var_80_arg_0=0, var_80_arg_1=255, var_81=254, var_81_arg_0=1, var_82=0, var_82_arg_0=0, var_82_arg_1=254, var_83=255, var_83_arg_0=0, var_84=0, var_84_arg_0=0, var_84_arg_1=255, var_85=255, var_85_arg_0=0, var_86=0, var_86_arg_0=0, var_86_arg_1=255, var_87=255, var_87_arg_0=0, var_88=0, var_88_arg_0=255, var_88_arg_1=0, var_89=255, var_89_arg_0=0, var_90=0, var_90_arg_0=0, var_90_arg_1=255, var_91=255, var_91_arg_0=0, var_92=0, var_92_arg_0=0, var_92_arg_1=255, var_93=255, var_93_arg_0=0, var_94=0, var_94_arg_0=0, var_94_arg_1=255, var_95=254, var_95_arg_0=1, var_96=0, var_96_arg_0=0, var_96_arg_1=254, var_97=255, var_97_arg_0=0, var_98=0, var_98_arg_0=0, var_98_arg_1=255, var_99=255, var_99_arg_0=0] [L81] input_2 = __VERIFIER_nondet_uchar() [L82] input_2 = input_2 & mask_SORT_1 [L83] input_3 = __VERIFIER_nondet_uchar() [L84] input_3 = input_3 & mask_SORT_1 [L85] input_4 = __VERIFIER_nondet_uchar() [L86] input_4 = input_4 & mask_SORT_1 [L87] input_6 = __VERIFIER_nondet_uchar() [L88] input_38 = __VERIFIER_nondet_uchar() [L91] SORT_5 var_10_arg_0 = state_8; [L92] SORT_5 var_10 = ~var_10_arg_0; [L93] SORT_5 var_14_arg_0 = var_10; [L94] SORT_5 var_14 = ~var_14_arg_0; [L95] SORT_5 var_15_arg_0 = var_13; [L96] SORT_5 var_15_arg_1 = var_14; [L97] SORT_5 var_15 = var_15_arg_0 & var_15_arg_1; [L98] var_15 = var_15 & mask_SORT_5 [L99] SORT_5 bad_16_arg_0 = var_15; [L100] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 11 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 552.6s, OverallIterations: 7, TraceHistogramMax: 7, PathProgramHistogramMax: 6, EmptinessCheckTime: 0.0s, AutomataDifference: 24.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 58 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 58 mSDsluCounter, 165 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 164 IncrementalHoareTripleChecker+Unchecked, 136 mSDsCounter, 9 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 68 IncrementalHoareTripleChecker+Invalid, 241 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 9 mSolverCounterUnsat, 29 mSDtfsCounter, 68 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 160 GetRequests, 69 SyntacticMatches, 3 SemanticMatches, 88 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 398 ImplicationChecksByTransitivity, 505.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=24occurred in iteration=6, InterpolantAutomatonStates: 61, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 6 MinimizatonAttempts, 12 StatesRemovedByMinimization, 6 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.9s SsaConstructionTime, 2.8s SatisfiabilityAnalysisTime, 520.4s InterpolantComputationTime, 98 NumberOfCodeBlocks, 98 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 134 ConstructedInterpolants, 76 QuantifiedInterpolants, 61625 SizeOfPredicates, 1168 NumberOfNonLiveVariables, 7038 ConjunctsInSsa, 1091 ConjunctsInUnsatCore, 11 InterpolantComputations, 1 PerfectInterpolantSequences, 0/180 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-18 20:59:13,218 WARN L435 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forcibly destroying the process [2022-11-18 20:59:13,235 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4156bdd8-abb8-49de-9f4c-4178762262df/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE