./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/memsafety/20051113-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety/20051113-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 18:29:43,105 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 18:29:43,108 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 18:29:43,150 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 18:29:43,155 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 18:29:43,157 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 18:29:43,160 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 18:29:43,165 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 18:29:43,168 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 18:29:43,170 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 18:29:43,172 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 18:29:43,174 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 18:29:43,176 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 18:29:43,179 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 18:29:43,181 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 18:29:43,183 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 18:29:43,186 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 18:29:43,191 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 18:29:43,193 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 18:29:43,195 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 18:29:43,201 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 18:29:43,203 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 18:29:43,204 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 18:29:43,207 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 18:29:43,212 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 18:29:43,217 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 18:29:43,217 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 18:29:43,218 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 18:29:43,220 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 18:29:43,221 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 18:29:43,222 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 18:29:43,223 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 18:29:43,225 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 18:29:43,227 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 18:29:43,230 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 18:29:43,230 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 18:29:43,231 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 18:29:43,231 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 18:29:43,232 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 18:29:43,232 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 18:29:43,233 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 18:29:43,234 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2022-11-18 18:29:43,277 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 18:29:43,278 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 18:29:43,278 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 18:29:43,279 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 18:29:43,280 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-18 18:29:43,280 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-18 18:29:43,281 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 18:29:43,281 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 18:29:43,282 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 18:29:43,282 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 18:29:43,284 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 18:29:43,284 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 18:29:43,285 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 18:29:43,285 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 18:29:43,285 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 18:29:43,285 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2022-11-18 18:29:43,286 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2022-11-18 18:29:43,286 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2022-11-18 18:29:43,286 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-18 18:29:43,287 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-18 18:29:43,287 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 18:29:43,287 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 18:29:43,288 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 18:29:43,288 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 18:29:43,288 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-18 18:29:43,289 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 18:29:43,291 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 18:29:43,291 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-18 18:29:43,292 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 18:29:43,292 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-18 18:29:43,293 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 [2022-11-18 18:29:43,651 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 18:29:43,680 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 18:29:43,685 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 18:29:43,687 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 18:29:43,687 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 18:29:43,689 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/memsafety/20051113-1.i [2022-11-18 18:29:43,784 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/data/30cae2727/3891a2716eac44729910eaa4980c0579/FLAGdb92d8878 [2022-11-18 18:29:44,345 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 18:29:44,363 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/sv-benchmarks/c/memsafety/20051113-1.i [2022-11-18 18:29:44,380 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/data/30cae2727/3891a2716eac44729910eaa4980c0579/FLAGdb92d8878 [2022-11-18 18:29:44,670 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/data/30cae2727/3891a2716eac44729910eaa4980c0579 [2022-11-18 18:29:44,673 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 18:29:44,675 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 18:29:44,679 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 18:29:44,679 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 18:29:44,683 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 18:29:44,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:29:44" (1/1) ... [2022-11-18 18:29:44,685 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@10210ee1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:44, skipping insertion in model container [2022-11-18 18:29:44,685 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 06:29:44" (1/1) ... [2022-11-18 18:29:44,692 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 18:29:44,749 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 18:29:45,196 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:29:45,215 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 18:29:45,286 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 18:29:45,313 INFO L208 MainTranslator]: Completed translation [2022-11-18 18:29:45,313 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45 WrapperNode [2022-11-18 18:29:45,313 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 18:29:45,314 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 18:29:45,315 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 18:29:45,315 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 18:29:45,323 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,341 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,379 INFO L138 Inliner]: procedures = 125, calls = 23, calls flagged for inlining = 5, calls inlined = 5, statements flattened = 77 [2022-11-18 18:29:45,380 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 18:29:45,382 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 18:29:45,382 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 18:29:45,382 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 18:29:45,392 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,392 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,412 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,412 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,422 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,426 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,427 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,428 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,431 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 18:29:45,432 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 18:29:45,432 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 18:29:45,432 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 18:29:45,445 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (1/1) ... [2022-11-18 18:29:45,451 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 18:29:45,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:45,477 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-18 18:29:45,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-18 18:29:45,514 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-18 18:29:45,514 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-18 18:29:45,515 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-18 18:29:45,515 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-18 18:29:45,515 INFO L130 BoogieDeclarations]: Found specification of procedure dummy_abort [2022-11-18 18:29:45,515 INFO L138 BoogieDeclarations]: Found implementation of procedure dummy_abort [2022-11-18 18:29:45,515 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-18 18:29:45,516 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 18:29:45,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 18:29:45,639 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 18:29:45,642 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 18:29:46,060 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 18:29:46,067 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 18:29:46,068 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-18 18:29:46,070 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:29:46 BoogieIcfgContainer [2022-11-18 18:29:46,071 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 18:29:46,074 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-18 18:29:46,074 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-18 18:29:46,079 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-18 18:29:46,079 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 06:29:44" (1/3) ... [2022-11-18 18:29:46,080 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb92b6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 06:29:46, skipping insertion in model container [2022-11-18 18:29:46,080 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 06:29:45" (2/3) ... [2022-11-18 18:29:46,081 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cb92b6d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 06:29:46, skipping insertion in model container [2022-11-18 18:29:46,081 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 06:29:46" (3/3) ... [2022-11-18 18:29:46,083 INFO L112 eAbstractionObserver]: Analyzing ICFG 20051113-1.i [2022-11-18 18:29:46,107 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-18 18:29:46,108 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 25 error locations. [2022-11-18 18:29:46,167 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-18 18:29:46,175 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@c8ae696, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-18 18:29:46,176 INFO L358 AbstractCegarLoop]: Starting to check reachability of 25 error locations. [2022-11-18 18:29:46,181 INFO L276 IsEmpty]: Start isEmpty. Operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:46,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-11-18 18:29:46,189 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:46,190 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-11-18 18:29:46,191 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:46,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:46,198 INFO L85 PathProgramCache]: Analyzing trace with hash 30849, now seen corresponding path program 1 times [2022-11-18 18:29:46,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:46,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616420968] [2022-11-18 18:29:46,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:46,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:46,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:46,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:46,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:46,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616420968] [2022-11-18 18:29:46,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616420968] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:46,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:46,499 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 18:29:46,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290521627] [2022-11-18 18:29:46,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:46,508 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 18:29:46,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:46,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 18:29:46,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:46,556 INFO L87 Difference]: Start difference. First operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:46,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:46,767 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2022-11-18 18:29:46,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 18:29:46,770 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-11-18 18:29:46,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:46,777 INFO L225 Difference]: With dead ends: 63 [2022-11-18 18:29:46,778 INFO L226 Difference]: Without dead ends: 61 [2022-11-18 18:29:46,780 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:46,784 INFO L413 NwaCegarLoop]: 39 mSDtfsCounter, 61 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:46,785 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 40 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:46,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-11-18 18:29:46,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2022-11-18 18:29:46,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 34 states have (on average 1.8235294117647058) internal successors, (62), 59 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:46,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2022-11-18 18:29:46,836 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 3 [2022-11-18 18:29:46,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:46,838 INFO L495 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2022-11-18 18:29:46,838 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:46,838 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2022-11-18 18:29:46,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-18 18:29:46,839 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:46,839 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-18 18:29:46,840 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-18 18:29:46,841 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:46,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:46,841 INFO L85 PathProgramCache]: Analyzing trace with hash 956356, now seen corresponding path program 1 times [2022-11-18 18:29:46,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:46,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108110157] [2022-11-18 18:29:46,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:46,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:46,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:47,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:47,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:47,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108110157] [2022-11-18 18:29:47,058 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108110157] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:47,058 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:47,058 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 18:29:47,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166184371] [2022-11-18 18:29:47,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:47,060 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 18:29:47,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:47,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 18:29:47,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:47,061 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:47,143 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2022-11-18 18:29:47,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 18:29:47,144 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-18 18:29:47,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:47,146 INFO L225 Difference]: With dead ends: 60 [2022-11-18 18:29:47,147 INFO L226 Difference]: Without dead ends: 60 [2022-11-18 18:29:47,147 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:47,148 INFO L413 NwaCegarLoop]: 38 mSDtfsCounter, 57 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:47,149 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 39 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:47,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2022-11-18 18:29:47,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2022-11-18 18:29:47,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 34 states have (on average 1.7941176470588236) internal successors, (61), 58 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:47,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 65 transitions. [2022-11-18 18:29:47,156 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 65 transitions. Word has length 4 [2022-11-18 18:29:47,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:47,156 INFO L495 AbstractCegarLoop]: Abstraction has 60 states and 65 transitions. [2022-11-18 18:29:47,157 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,157 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 65 transitions. [2022-11-18 18:29:47,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 18:29:47,157 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:47,158 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:47,158 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-18 18:29:47,158 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:47,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:47,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926710, now seen corresponding path program 1 times [2022-11-18 18:29:47,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:47,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245552532] [2022-11-18 18:29:47,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:47,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:47,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:47,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:47,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:47,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245552532] [2022-11-18 18:29:47,311 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245552532] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:47,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:47,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 18:29:47,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853620771] [2022-11-18 18:29:47,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:47,313 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 18:29:47,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:47,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:29:47,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:47,314 INFO L87 Difference]: Start difference. First operand 60 states and 65 transitions. Second operand has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:47,423 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2022-11-18 18:29:47,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 18:29:47,424 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 18:29:47,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:47,425 INFO L225 Difference]: With dead ends: 53 [2022-11-18 18:29:47,425 INFO L226 Difference]: Without dead ends: 53 [2022-11-18 18:29:47,426 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:47,427 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 98 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 100 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:47,428 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [100 Valid, 32 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:47,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2022-11-18 18:29:47,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2022-11-18 18:29:47,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 34 states have (on average 1.588235294117647) internal successors, (54), 51 states have internal predecessors, (54), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:47,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2022-11-18 18:29:47,435 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 7 [2022-11-18 18:29:47,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:47,435 INFO L495 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2022-11-18 18:29:47,436 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,436 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2022-11-18 18:29:47,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 18:29:47,436 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:47,437 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:47,437 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-11-18 18:29:47,437 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:47,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:47,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926709, now seen corresponding path program 1 times [2022-11-18 18:29:47,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:47,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493986150] [2022-11-18 18:29:47,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:47,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:47,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:47,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:47,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:47,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493986150] [2022-11-18 18:29:47,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493986150] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:47,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:47,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 18:29:47,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727556946] [2022-11-18 18:29:47,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:47,569 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 18:29:47,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:47,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 18:29:47,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:47,571 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:47,641 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2022-11-18 18:29:47,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 18:29:47,641 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 18:29:47,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:47,642 INFO L225 Difference]: With dead ends: 46 [2022-11-18 18:29:47,642 INFO L226 Difference]: Without dead ends: 46 [2022-11-18 18:29:47,643 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 18:29:47,644 INFO L413 NwaCegarLoop]: 33 mSDtfsCounter, 38 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:47,644 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 35 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 22 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:47,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2022-11-18 18:29:47,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2022-11-18 18:29:47,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 34 states have (on average 1.3823529411764706) internal successors, (47), 44 states have internal predecessors, (47), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:47,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 51 transitions. [2022-11-18 18:29:47,649 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 51 transitions. Word has length 7 [2022-11-18 18:29:47,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:47,650 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 51 transitions. [2022-11-18 18:29:47,650 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,650 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2022-11-18 18:29:47,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-18 18:29:47,651 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:47,651 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:47,651 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-11-18 18:29:47,651 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr16REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:47,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:47,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553495, now seen corresponding path program 1 times [2022-11-18 18:29:47,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:47,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709377927] [2022-11-18 18:29:47,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:47,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:47,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:47,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:47,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:47,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709377927] [2022-11-18 18:29:47,795 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709377927] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:47,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:47,796 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-18 18:29:47,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724673781] [2022-11-18 18:29:47,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:47,797 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-18 18:29:47,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:47,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-18 18:29:47,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-18 18:29:47,798 INFO L87 Difference]: Start difference. First operand 46 states and 51 transitions. Second operand has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:47,890 INFO L93 Difference]: Finished difference Result 44 states and 49 transitions. [2022-11-18 18:29:47,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:47,891 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-18 18:29:47,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:47,896 INFO L225 Difference]: With dead ends: 44 [2022-11-18 18:29:47,896 INFO L226 Difference]: Without dead ends: 44 [2022-11-18 18:29:47,897 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:47,903 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 72 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 72 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:47,904 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [72 Valid, 35 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:47,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2022-11-18 18:29:47,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2022-11-18 18:29:47,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 42 states have internal predecessors, (45), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:47,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 49 transitions. [2022-11-18 18:29:47,938 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 49 transitions. Word has length 15 [2022-11-18 18:29:47,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:47,938 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 49 transitions. [2022-11-18 18:29:47,938 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:47,939 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 49 transitions. [2022-11-18 18:29:47,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-18 18:29:47,939 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:47,939 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:47,939 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-11-18 18:29:47,940 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr17REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:47,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:47,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553496, now seen corresponding path program 1 times [2022-11-18 18:29:47,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:47,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095833644] [2022-11-18 18:29:47,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:47,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:47,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:48,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:48,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:48,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095833644] [2022-11-18 18:29:48,272 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095833644] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:48,273 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:48,273 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 18:29:48,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889823900] [2022-11-18 18:29:48,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:48,275 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 18:29:48,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:48,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:29:48,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:29:48,277 INFO L87 Difference]: Start difference. First operand 44 states and 49 transitions. Second operand has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:48,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:48,349 INFO L93 Difference]: Finished difference Result 43 states and 48 transitions. [2022-11-18 18:29:48,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:48,350 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-18 18:29:48,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:48,353 INFO L225 Difference]: With dead ends: 43 [2022-11-18 18:29:48,353 INFO L226 Difference]: Without dead ends: 43 [2022-11-18 18:29:48,353 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:48,356 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 56 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:48,359 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [56 Valid, 38 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:48,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2022-11-18 18:29:48,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2022-11-18 18:29:48,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 34 states have (on average 1.2941176470588236) internal successors, (44), 41 states have internal predecessors, (44), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:48,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 48 transitions. [2022-11-18 18:29:48,369 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 48 transitions. Word has length 15 [2022-11-18 18:29:48,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:48,369 INFO L495 AbstractCegarLoop]: Abstraction has 43 states and 48 transitions. [2022-11-18 18:29:48,370 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:48,370 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 48 transitions. [2022-11-18 18:29:48,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 18:29:48,371 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:48,371 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:48,371 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-11-18 18:29:48,372 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:48,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:48,372 INFO L85 PathProgramCache]: Analyzing trace with hash -1963083303, now seen corresponding path program 1 times [2022-11-18 18:29:48,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:48,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659609343] [2022-11-18 18:29:48,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:48,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:48,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:48,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:48,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:48,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659609343] [2022-11-18 18:29:48,608 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659609343] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:48,608 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:48,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 18:29:48,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168904360] [2022-11-18 18:29:48,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:48,609 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 18:29:48,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:48,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:29:48,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:29:48,611 INFO L87 Difference]: Start difference. First operand 43 states and 48 transitions. Second operand has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:48,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:48,758 INFO L93 Difference]: Finished difference Result 69 states and 79 transitions. [2022-11-18 18:29:48,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:48,761 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 18:29:48,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:48,764 INFO L225 Difference]: With dead ends: 69 [2022-11-18 18:29:48,764 INFO L226 Difference]: Without dead ends: 69 [2022-11-18 18:29:48,765 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:48,769 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 77 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 79 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:48,770 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [79 Valid, 54 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:48,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2022-11-18 18:29:48,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 46. [2022-11-18 18:29:48,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 37 states have (on average 1.2972972972972974) internal successors, (48), 44 states have internal predecessors, (48), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:48,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2022-11-18 18:29:48,792 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 17 [2022-11-18 18:29:48,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:48,793 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2022-11-18 18:29:48,794 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:48,794 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2022-11-18 18:29:48,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-11-18 18:29:48,795 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:48,795 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:48,796 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-11-18 18:29:48,797 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr20REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:48,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:48,799 INFO L85 PathProgramCache]: Analyzing trace with hash -58695891, now seen corresponding path program 1 times [2022-11-18 18:29:48,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:48,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101818674] [2022-11-18 18:29:48,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:48,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:48,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:48,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:48,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101818674] [2022-11-18 18:29:48,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101818674] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:48,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:48,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-18 18:29:48,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537224436] [2022-11-18 18:29:48,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:48,980 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 18:29:48,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:48,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:29:48,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:48,982 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:49,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:49,084 INFO L93 Difference]: Finished difference Result 44 states and 50 transitions. [2022-11-18 18:29:49,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 18:29:49,085 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-11-18 18:29:49,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:49,086 INFO L225 Difference]: With dead ends: 44 [2022-11-18 18:29:49,086 INFO L226 Difference]: Without dead ends: 44 [2022-11-18 18:29:49,087 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:49,088 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 70 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:49,089 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [70 Valid, 47 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:49,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2022-11-18 18:29:49,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2022-11-18 18:29:49,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 42 states have internal predecessors, (46), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:49,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 50 transitions. [2022-11-18 18:29:49,103 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 50 transitions. Word has length 21 [2022-11-18 18:29:49,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:49,104 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 50 transitions. [2022-11-18 18:29:49,104 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:49,104 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 50 transitions. [2022-11-18 18:29:49,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-11-18 18:29:49,105 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:49,105 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:49,106 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-11-18 18:29:49,106 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:49,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:49,107 INFO L85 PathProgramCache]: Analyzing trace with hash -58695890, now seen corresponding path program 1 times [2022-11-18 18:29:49,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:49,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829142972] [2022-11-18 18:29:49,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:49,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:49,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:49,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:49,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:49,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829142972] [2022-11-18 18:29:49,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829142972] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:49,259 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:49,260 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-18 18:29:49,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626517273] [2022-11-18 18:29:49,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:49,261 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 18:29:49,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:49,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:29:49,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:49,264 INFO L87 Difference]: Start difference. First operand 44 states and 50 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:49,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:49,315 INFO L93 Difference]: Finished difference Result 64 states and 73 transitions. [2022-11-18 18:29:49,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:49,317 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-11-18 18:29:49,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:49,318 INFO L225 Difference]: With dead ends: 64 [2022-11-18 18:29:49,318 INFO L226 Difference]: Without dead ends: 64 [2022-11-18 18:29:49,319 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:49,324 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 37 mSDsluCounter, 127 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 171 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:49,324 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [37 Valid, 171 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-18 18:29:49,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2022-11-18 18:29:49,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 47. [2022-11-18 18:29:49,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.225) internal successors, (49), 45 states have internal predecessors, (49), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:49,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 53 transitions. [2022-11-18 18:29:49,332 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 53 transitions. Word has length 21 [2022-11-18 18:29:49,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:49,332 INFO L495 AbstractCegarLoop]: Abstraction has 47 states and 53 transitions. [2022-11-18 18:29:49,333 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:49,333 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 53 transitions. [2022-11-18 18:29:49,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-11-18 18:29:49,334 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:49,334 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:49,334 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2022-11-18 18:29:49,334 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:49,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:49,335 INFO L85 PathProgramCache]: Analyzing trace with hash -309999949, now seen corresponding path program 1 times [2022-11-18 18:29:49,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:49,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478137516] [2022-11-18 18:29:49,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:49,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:49,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:49,595 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:49,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:49,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478137516] [2022-11-18 18:29:49,596 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478137516] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:29:49,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [157591347] [2022-11-18 18:29:49,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:49,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:29:49,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:49,603 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:29:49,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-18 18:29:49,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:49,712 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:29:49,718 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:29:50,051 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:50,051 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:29:50,373 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:29:50,374 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2022-11-18 18:29:50,446 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:50,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [157591347] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:29:50,447 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:29:50,447 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 6] total 13 [2022-11-18 18:29:50,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985769577] [2022-11-18 18:29:50,448 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:29:50,448 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 18:29:50,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:50,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 18:29:50,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2022-11-18 18:29:50,450 INFO L87 Difference]: Start difference. First operand 47 states and 53 transitions. Second operand has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:50,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:50,893 INFO L93 Difference]: Finished difference Result 111 states and 130 transitions. [2022-11-18 18:29:50,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 18:29:50,894 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 22 [2022-11-18 18:29:50,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:50,896 INFO L225 Difference]: With dead ends: 111 [2022-11-18 18:29:50,896 INFO L226 Difference]: Without dead ends: 111 [2022-11-18 18:29:50,896 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 33 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=86, Invalid=220, Unknown=0, NotChecked=0, Total=306 [2022-11-18 18:29:50,897 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 431 mSDsluCounter, 104 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 42 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 431 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 224 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 42 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:50,898 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [431 Valid, 148 Invalid, 224 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [42 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:29:50,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2022-11-18 18:29:50,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 57. [2022-11-18 18:29:50,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 50 states have (on average 1.22) internal successors, (61), 55 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:50,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2022-11-18 18:29:50,903 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 22 [2022-11-18 18:29:50,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:50,903 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2022-11-18 18:29:50,904 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:50,904 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2022-11-18 18:29:50,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2022-11-18 18:29:50,905 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:50,905 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:50,919 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-11-18 18:29:51,119 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-11-18 18:29:51,119 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:51,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:51,120 INFO L85 PathProgramCache]: Analyzing trace with hash -612311662, now seen corresponding path program 1 times [2022-11-18 18:29:51,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:51,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800779510] [2022-11-18 18:29:51,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:51,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:51,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,372 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-18 18:29:51,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:51,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:51,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800779510] [2022-11-18 18:29:51,383 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800779510] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:51,383 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:51,387 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 18:29:51,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439585822] [2022-11-18 18:29:51,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:51,389 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 18:29:51,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:51,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:29:51,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:29:51,391 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:51,474 INFO L93 Difference]: Finished difference Result 56 states and 64 transitions. [2022-11-18 18:29:51,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:51,476 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 24 [2022-11-18 18:29:51,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:51,478 INFO L225 Difference]: With dead ends: 56 [2022-11-18 18:29:51,478 INFO L226 Difference]: Without dead ends: 56 [2022-11-18 18:29:51,479 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:51,480 INFO L413 NwaCegarLoop]: 29 mSDtfsCounter, 32 mSDsluCounter, 15 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 44 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:51,481 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 44 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:51,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2022-11-18 18:29:51,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2022-11-18 18:29:51,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.2) internal successors, (60), 54 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:51,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 64 transitions. [2022-11-18 18:29:51,495 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 64 transitions. Word has length 24 [2022-11-18 18:29:51,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:51,496 INFO L495 AbstractCegarLoop]: Abstraction has 56 states and 64 transitions. [2022-11-18 18:29:51,496 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,496 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 64 transitions. [2022-11-18 18:29:51,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-11-18 18:29:51,498 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:51,498 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:51,498 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2022-11-18 18:29:51,499 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:51,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:51,500 INFO L85 PathProgramCache]: Analyzing trace with hash -20987021, now seen corresponding path program 1 times [2022-11-18 18:29:51,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:51,500 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066980098] [2022-11-18 18:29:51,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:51,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:51,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,691 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-18 18:29:51,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:51,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:51,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066980098] [2022-11-18 18:29:51,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066980098] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:51,698 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:51,698 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 18:29:51,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90769402] [2022-11-18 18:29:51,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:51,699 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 18:29:51,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:51,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:29:51,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 18:29:51,700 INFO L87 Difference]: Start difference. First operand 56 states and 64 transitions. Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:51,808 INFO L93 Difference]: Finished difference Result 68 states and 78 transitions. [2022-11-18 18:29:51,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:51,809 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 26 [2022-11-18 18:29:51,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:51,811 INFO L225 Difference]: With dead ends: 68 [2022-11-18 18:29:51,811 INFO L226 Difference]: Without dead ends: 68 [2022-11-18 18:29:51,811 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:51,812 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 38 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:51,812 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 49 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 47 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:51,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2022-11-18 18:29:51,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 59. [2022-11-18 18:29:51,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 53 states have (on average 1.2075471698113207) internal successors, (64), 57 states have internal predecessors, (64), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:51,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 68 transitions. [2022-11-18 18:29:51,821 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 68 transitions. Word has length 26 [2022-11-18 18:29:51,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:51,822 INFO L495 AbstractCegarLoop]: Abstraction has 59 states and 68 transitions. [2022-11-18 18:29:51,822 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,822 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 68 transitions. [2022-11-18 18:29:51,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-11-18 18:29:51,830 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:51,830 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:51,830 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2022-11-18 18:29:51,831 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:51,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:51,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1184799620, now seen corresponding path program 1 times [2022-11-18 18:29:51,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:51,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195935121] [2022-11-18 18:29:51,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:51,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:51,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,930 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-18 18:29:51,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:51,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:51,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:51,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195935121] [2022-11-18 18:29:51,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195935121] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:51,934 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:51,934 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-18 18:29:51,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42966009] [2022-11-18 18:29:51,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:51,936 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 18:29:51,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:51,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:29:51,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:51,938 INFO L87 Difference]: Start difference. First operand 59 states and 68 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:51,978 INFO L93 Difference]: Finished difference Result 67 states and 76 transitions. [2022-11-18 18:29:51,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:51,979 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-11-18 18:29:51,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:51,982 INFO L225 Difference]: With dead ends: 67 [2022-11-18 18:29:51,982 INFO L226 Difference]: Without dead ends: 67 [2022-11-18 18:29:51,983 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:51,984 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 11 mSDsluCounter, 125 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11 SdHoareTripleChecker+Valid, 169 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:51,984 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [11 Valid, 169 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-18 18:29:51,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2022-11-18 18:29:51,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2022-11-18 18:29:51,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 56 states have (on average 1.1964285714285714) internal successors, (67), 60 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:51,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 71 transitions. [2022-11-18 18:29:51,994 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 71 transitions. Word has length 30 [2022-11-18 18:29:51,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:51,994 INFO L495 AbstractCegarLoop]: Abstraction has 62 states and 71 transitions. [2022-11-18 18:29:51,995 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:51,995 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 71 transitions. [2022-11-18 18:29:51,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-11-18 18:29:51,997 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:51,998 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:51,998 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2022-11-18 18:29:51,998 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:51,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:51,999 INFO L85 PathProgramCache]: Analyzing trace with hash -416344648, now seen corresponding path program 1 times [2022-11-18 18:29:52,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:52,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487742161] [2022-11-18 18:29:52,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:52,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:52,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:52,260 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-18 18:29:52,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:52,267 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:52,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:52,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487742161] [2022-11-18 18:29:52,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487742161] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:52,270 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:52,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-18 18:29:52,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284837946] [2022-11-18 18:29:52,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:52,272 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-18 18:29:52,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:52,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-18 18:29:52,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:52,274 INFO L87 Difference]: Start difference. First operand 62 states and 71 transitions. Second operand has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:52,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:52,484 INFO L93 Difference]: Finished difference Result 73 states and 83 transitions. [2022-11-18 18:29:52,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 18:29:52,485 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-11-18 18:29:52,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:52,486 INFO L225 Difference]: With dead ends: 73 [2022-11-18 18:29:52,486 INFO L226 Difference]: Without dead ends: 73 [2022-11-18 18:29:52,487 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2022-11-18 18:29:52,487 INFO L413 NwaCegarLoop]: 41 mSDtfsCounter, 27 mSDsluCounter, 134 mSDsCounter, 0 mSdLazyCounter, 111 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 175 SdHoareTripleChecker+Invalid, 115 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 111 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:52,488 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 175 Invalid, 115 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 111 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:52,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2022-11-18 18:29:52,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 66. [2022-11-18 18:29:52,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 59 states have (on average 1.1864406779661016) internal successors, (70), 63 states have internal predecessors, (70), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-18 18:29:52,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 76 transitions. [2022-11-18 18:29:52,492 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 76 transitions. Word has length 31 [2022-11-18 18:29:52,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:52,492 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 76 transitions. [2022-11-18 18:29:52,492 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-11-18 18:29:52,493 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 76 transitions. [2022-11-18 18:29:52,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-11-18 18:29:52,493 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:52,494 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:52,494 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2022-11-18 18:29:52,494 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:52,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:52,495 INFO L85 PathProgramCache]: Analyzing trace with hash 241915192, now seen corresponding path program 1 times [2022-11-18 18:29:52,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:52,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138739561] [2022-11-18 18:29:52,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:52,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:52,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:52,861 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2022-11-18 18:29:52,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:52,865 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 28 [2022-11-18 18:29:52,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:52,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-18 18:29:52,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:52,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138739561] [2022-11-18 18:29:52,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138739561] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:52,869 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 18:29:52,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-18 18:29:52,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272485695] [2022-11-18 18:29:52,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:52,873 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 18:29:52,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:52,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 18:29:52,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-18 18:29:52,874 INFO L87 Difference]: Start difference. First operand 66 states and 76 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:52,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:52,978 INFO L93 Difference]: Finished difference Result 65 states and 73 transitions. [2022-11-18 18:29:52,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 18:29:52,979 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 33 [2022-11-18 18:29:52,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:52,981 INFO L225 Difference]: With dead ends: 65 [2022-11-18 18:29:52,982 INFO L226 Difference]: Without dead ends: 58 [2022-11-18 18:29:52,984 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-18 18:29:52,986 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 27 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 88 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:52,987 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 88 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:29:52,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2022-11-18 18:29:52,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2022-11-18 18:29:52,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.18) internal successors, (59), 54 states have internal predecessors, (59), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:52,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 63 transitions. [2022-11-18 18:29:52,991 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 63 transitions. Word has length 33 [2022-11-18 18:29:52,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:52,991 INFO L495 AbstractCegarLoop]: Abstraction has 56 states and 63 transitions. [2022-11-18 18:29:52,992 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:52,992 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 63 transitions. [2022-11-18 18:29:52,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-11-18 18:29:52,993 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:52,993 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:52,993 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2022-11-18 18:29:52,993 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:52,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:52,994 INFO L85 PathProgramCache]: Analyzing trace with hash 701429363, now seen corresponding path program 2 times [2022-11-18 18:29:52,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:52,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037512613] [2022-11-18 18:29:52,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:52,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:53,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:53,650 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 18:29:53,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:53,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037512613] [2022-11-18 18:29:53,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037512613] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:29:53,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2018932044] [2022-11-18 18:29:53,651 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:29:53,652 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:29:53,652 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:53,653 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:29:53,678 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-18 18:29:53,782 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-11-18 18:29:53,782 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:29:53,784 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 18:29:53,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:29:53,856 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2022-11-18 18:29:53,856 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 18:29:53,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2018932044] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 18:29:53,857 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-18 18:29:53,857 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2022-11-18 18:29:53,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950589717] [2022-11-18 18:29:53,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 18:29:53,858 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 18:29:53,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:53,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 18:29:53,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2022-11-18 18:29:53,860 INFO L87 Difference]: Start difference. First operand 56 states and 63 transitions. Second operand has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:53,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:53,878 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2022-11-18 18:29:53,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 18:29:53,879 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 32 [2022-11-18 18:29:53,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:53,895 INFO L225 Difference]: With dead ends: 57 [2022-11-18 18:29:53,895 INFO L226 Difference]: Without dead ends: 57 [2022-11-18 18:29:53,896 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2022-11-18 18:29:53,897 INFO L413 NwaCegarLoop]: 42 mSDtfsCounter, 38 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:53,897 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 81 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-18 18:29:53,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-11-18 18:29:53,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2022-11-18 18:29:53,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 51 states have (on average 1.1764705882352942) internal successors, (60), 55 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:53,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 64 transitions. [2022-11-18 18:29:53,901 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 64 transitions. Word has length 32 [2022-11-18 18:29:53,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:53,901 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 64 transitions. [2022-11-18 18:29:53,902 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:53,902 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 64 transitions. [2022-11-18 18:29:53,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-11-18 18:29:53,903 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:53,903 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:53,923 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-11-18 18:29:54,110 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-11-18 18:29:54,110 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:54,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:54,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1203352596, now seen corresponding path program 1 times [2022-11-18 18:29:54,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:54,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324156681] [2022-11-18 18:29:54,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:54,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:54,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:54,591 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:54,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:54,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324156681] [2022-11-18 18:29:54,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324156681] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:29:54,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [830505256] [2022-11-18 18:29:54,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:54,593 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:29:54,593 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:54,594 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:29:54,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-18 18:29:54,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:54,716 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-18 18:29:54,721 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:29:54,758 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-18 18:29:54,792 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,793 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:54,813 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,814 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:54,837 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,838 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:54,864 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:54,919 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,920 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:54,940 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:29:54,942 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:29:55,206 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:29:55,232 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:55,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:29:55,381 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:55,382 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [830505256] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:29:55,382 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:29:55,382 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 17 [2022-11-18 18:29:55,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442018257] [2022-11-18 18:29:55,383 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:29:55,384 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-11-18 18:29:55,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:55,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-18 18:29:55,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2022-11-18 18:29:55,386 INFO L87 Difference]: Start difference. First operand 57 states and 64 transitions. Second operand has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:55,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:55,862 INFO L93 Difference]: Finished difference Result 97 states and 111 transitions. [2022-11-18 18:29:55,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:29:55,863 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-11-18 18:29:55,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:55,863 INFO L225 Difference]: With dead ends: 97 [2022-11-18 18:29:55,864 INFO L226 Difference]: Without dead ends: 97 [2022-11-18 18:29:55,864 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 59 SyntacticMatches, 5 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 136 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=170, Invalid=480, Unknown=0, NotChecked=0, Total=650 [2022-11-18 18:29:55,865 INFO L413 NwaCegarLoop]: 68 mSDtfsCounter, 133 mSDsluCounter, 333 mSDsCounter, 0 mSdLazyCounter, 300 mSolverCounterSat, 25 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 133 SdHoareTripleChecker+Valid, 401 SdHoareTripleChecker+Invalid, 325 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 25 IncrementalHoareTripleChecker+Valid, 300 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:55,865 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [133 Valid, 401 Invalid, 325 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [25 Valid, 300 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:29:55,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2022-11-18 18:29:55,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 55. [2022-11-18 18:29:55,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 50 states have (on average 1.14) internal successors, (57), 53 states have internal predecessors, (57), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:55,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2022-11-18 18:29:55,868 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 33 [2022-11-18 18:29:55,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:55,868 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2022-11-18 18:29:55,868 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:55,868 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2022-11-18 18:29:55,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-11-18 18:29:55,869 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:55,869 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:55,881 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-11-18 18:29:56,069 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-11-18 18:29:56,070 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:56,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:56,070 INFO L85 PathProgramCache]: Analyzing trace with hash -149943807, now seen corresponding path program 1 times [2022-11-18 18:29:56,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:56,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172317857] [2022-11-18 18:29:56,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:56,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:56,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:56,652 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-18 18:29:56,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:56,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172317857] [2022-11-18 18:29:56,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1172317857] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:29:56,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1741598157] [2022-11-18 18:29:56,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:56,654 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:29:56,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:56,655 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:29:56,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-18 18:29:56,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:56,782 INFO L263 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-18 18:29:56,786 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:29:57,081 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-18 18:29:57,081 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:29:57,392 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 18:29:57,393 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2022-11-18 18:29:57,460 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-18 18:29:57,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1741598157] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:29:57,461 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:29:57,461 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 18 [2022-11-18 18:29:57,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126779527] [2022-11-18 18:29:57,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:29:57,462 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-18 18:29:57,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:57,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-18 18:29:57,463 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=255, Unknown=0, NotChecked=0, Total=306 [2022-11-18 18:29:57,463 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:58,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:29:58,040 INFO L93 Difference]: Finished difference Result 79 states and 88 transitions. [2022-11-18 18:29:58,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-18 18:29:58,041 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2022-11-18 18:29:58,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:29:58,041 INFO L225 Difference]: With dead ends: 79 [2022-11-18 18:29:58,042 INFO L226 Difference]: Without dead ends: 79 [2022-11-18 18:29:58,042 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=168, Invalid=588, Unknown=0, NotChecked=0, Total=756 [2022-11-18 18:29:58,043 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 211 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 217 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 211 SdHoareTripleChecker+Valid, 126 SdHoareTripleChecker+Invalid, 238 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 217 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 18:29:58,043 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [211 Valid, 126 Invalid, 238 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [21 Valid, 217 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 18:29:58,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2022-11-18 18:29:58,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 65. [2022-11-18 18:29:58,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1333333333333333) internal successors, (68), 63 states have internal predecessors, (68), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:29:58,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 72 transitions. [2022-11-18 18:29:58,047 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 72 transitions. Word has length 34 [2022-11-18 18:29:58,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:29:58,047 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 72 transitions. [2022-11-18 18:29:58,047 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:29:58,047 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 72 transitions. [2022-11-18 18:29:58,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2022-11-18 18:29:58,048 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:29:58,048 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:29:58,061 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-11-18 18:29:58,255 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2022-11-18 18:29:58,255 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:29:58,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:29:58,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1336889422, now seen corresponding path program 1 times [2022-11-18 18:29:58,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:29:58,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063758060] [2022-11-18 18:29:58,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:58,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:29:58,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:58,832 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-18 18:29:58,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:29:58,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063758060] [2022-11-18 18:29:58,833 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063758060] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:29:58,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [403799625] [2022-11-18 18:29:58,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:29:58,833 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:29:58,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:29:58,835 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:29:58,841 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-18 18:29:58,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:29:58,978 INFO L263 TraceCheckSpWp]: Trace formula consists of 228 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-18 18:29:58,983 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:29:59,022 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-18 18:29:59,308 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:29:59,333 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:59,333 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:29:59,578 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:29:59,578 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [403799625] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:29:59,578 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:29:59,579 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 9] total 24 [2022-11-18 18:29:59,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027322109] [2022-11-18 18:29:59,581 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:29:59,582 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2022-11-18 18:29:59,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:29:59,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-18 18:29:59,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2022-11-18 18:29:59,584 INFO L87 Difference]: Start difference. First operand 65 states and 72 transitions. Second operand has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:00,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:00,505 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2022-11-18 18:30:00,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-18 18:30:00,506 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 43 [2022-11-18 18:30:00,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:00,507 INFO L225 Difference]: With dead ends: 65 [2022-11-18 18:30:00,507 INFO L226 Difference]: Without dead ends: 65 [2022-11-18 18:30:00,508 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 236 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=293, Invalid=1039, Unknown=0, NotChecked=0, Total=1332 [2022-11-18 18:30:00,509 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 185 mSDsluCounter, 192 mSDsCounter, 0 mSdLazyCounter, 266 mSolverCounterSat, 30 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 185 SdHoareTripleChecker+Valid, 219 SdHoareTripleChecker+Invalid, 296 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 30 IncrementalHoareTripleChecker+Valid, 266 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:00,509 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [185 Valid, 219 Invalid, 296 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [30 Valid, 266 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:30:00,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2022-11-18 18:30:00,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2022-11-18 18:30:00,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1) internal successors, (66), 63 states have internal predecessors, (66), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:00,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 70 transitions. [2022-11-18 18:30:00,513 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 70 transitions. Word has length 43 [2022-11-18 18:30:00,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:00,513 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 70 transitions. [2022-11-18 18:30:00,513 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:00,514 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 70 transitions. [2022-11-18 18:30:00,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2022-11-18 18:30:00,515 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:00,515 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:00,530 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-18 18:30:00,722 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:00,723 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:00,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:00,724 INFO L85 PathProgramCache]: Analyzing trace with hash -990509317, now seen corresponding path program 2 times [2022-11-18 18:30:00,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:00,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312115456] [2022-11-18 18:30:00,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:00,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:00,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:01,444 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-11-18 18:30:01,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:01,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312115456] [2022-11-18 18:30:01,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312115456] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:01,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [407532503] [2022-11-18 18:30:01,445 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:30:01,445 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:01,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:01,447 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:01,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-18 18:30:01,628 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:30:01,629 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:01,631 INFO L263 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-18 18:30:01,634 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:01,675 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-11-18 18:30:02,082 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:30:02,105 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 7 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:30:02,105 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:02,358 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:30:02,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [407532503] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:02,358 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:02,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 11] total 27 [2022-11-18 18:30:02,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992891853] [2022-11-18 18:30:02,361 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:02,362 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2022-11-18 18:30:02,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:02,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-18 18:30:02,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=577, Unknown=0, NotChecked=0, Total=702 [2022-11-18 18:30:02,363 INFO L87 Difference]: Start difference. First operand 65 states and 70 transitions. Second operand has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:03,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:03,188 INFO L93 Difference]: Finished difference Result 67 states and 71 transitions. [2022-11-18 18:30:03,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-18 18:30:03,189 INFO L78 Accepts]: Start accepts. Automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 53 [2022-11-18 18:30:03,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:03,190 INFO L225 Difference]: With dead ends: 67 [2022-11-18 18:30:03,190 INFO L226 Difference]: Without dead ends: 67 [2022-11-18 18:30:03,191 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 93 SyntacticMatches, 4 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 432 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=421, Invalid=1219, Unknown=0, NotChecked=0, Total=1640 [2022-11-18 18:30:03,192 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 204 mSDsluCounter, 154 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 34 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 204 SdHoareTripleChecker+Valid, 182 SdHoareTripleChecker+Invalid, 303 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 34 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:03,192 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [204 Valid, 182 Invalid, 303 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [34 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:30:03,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2022-11-18 18:30:03,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2022-11-18 18:30:03,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 63 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:03,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2022-11-18 18:30:03,195 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 53 [2022-11-18 18:30:03,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:03,195 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2022-11-18 18:30:03,196 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:03,196 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2022-11-18 18:30:03,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-18 18:30:03,196 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:03,196 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:03,210 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-11-18 18:30:03,397 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable19 [2022-11-18 18:30:03,397 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:03,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:03,398 INFO L85 PathProgramCache]: Analyzing trace with hash 868555041, now seen corresponding path program 2 times [2022-11-18 18:30:03,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:03,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398357804] [2022-11-18 18:30:03,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:03,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:03,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:03,957 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 10 proven. 35 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 18:30:03,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:03,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398357804] [2022-11-18 18:30:03,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398357804] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:03,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [445295842] [2022-11-18 18:30:03,958 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 18:30:03,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:03,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:03,960 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:03,978 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-18 18:30:04,127 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 18:30:04,128 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:04,130 INFO L263 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-18 18:30:04,135 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:04,179 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-18 18:30:04,228 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,229 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,242 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,243 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,257 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,271 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,272 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,283 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,285 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,308 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 18:30:04,315 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-11-18 18:30:04,727 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-18 18:30:04,770 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-11-18 18:30:04,770 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:04,986 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-11-18 18:30:04,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [445295842] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:04,986 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:04,987 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 9, 8] total 23 [2022-11-18 18:30:04,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160640965] [2022-11-18 18:30:04,987 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:04,988 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-11-18 18:30:04,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:04,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-18 18:30:04,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=424, Unknown=0, NotChecked=0, Total=506 [2022-11-18 18:30:04,990 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:05,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:05,761 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2022-11-18 18:30:05,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-18 18:30:05,762 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-18 18:30:05,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:05,763 INFO L225 Difference]: With dead ends: 63 [2022-11-18 18:30:05,763 INFO L226 Difference]: Without dead ends: 63 [2022-11-18 18:30:05,764 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 96 SyntacticMatches, 5 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=266, Invalid=1140, Unknown=0, NotChecked=0, Total=1406 [2022-11-18 18:30:05,765 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 137 mSDsluCounter, 232 mSDsCounter, 0 mSdLazyCounter, 370 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 137 SdHoareTripleChecker+Valid, 258 SdHoareTripleChecker+Invalid, 385 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 370 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:05,765 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [137 Valid, 258 Invalid, 385 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 370 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:30:05,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2022-11-18 18:30:05,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2022-11-18 18:30:05,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 59 states have (on average 1.0508474576271187) internal successors, (62), 61 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:05,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 66 transitions. [2022-11-18 18:30:05,768 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 66 transitions. Word has length 54 [2022-11-18 18:30:05,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:05,768 INFO L495 AbstractCegarLoop]: Abstraction has 63 states and 66 transitions. [2022-11-18 18:30:05,769 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:05,769 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 66 transitions. [2022-11-18 18:30:05,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2022-11-18 18:30:05,769 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:05,770 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:05,782 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-11-18 18:30:05,970 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:05,970 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:05,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:05,971 INFO L85 PathProgramCache]: Analyzing trace with hash 679832114, now seen corresponding path program 3 times [2022-11-18 18:30:05,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:05,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180207209] [2022-11-18 18:30:05,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:05,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:06,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:06,208 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:06,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:06,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180207209] [2022-11-18 18:30:06,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180207209] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:06,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [538469068] [2022-11-18 18:30:06,209 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 18:30:06,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:06,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:06,211 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:06,242 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-18 18:30:06,622 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 18:30:06,622 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:06,624 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 18:30:06,627 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:06,687 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:06,687 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:06,770 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:06,770 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [538469068] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:06,771 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:06,771 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2022-11-18 18:30:06,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009505399] [2022-11-18 18:30:06,771 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:06,772 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-18 18:30:06,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:06,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-18 18:30:06,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-11-18 18:30:06,773 INFO L87 Difference]: Start difference. First operand 63 states and 66 transitions. Second operand has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:06,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:06,912 INFO L93 Difference]: Finished difference Result 66 states and 69 transitions. [2022-11-18 18:30:06,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 18:30:06,913 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 58 [2022-11-18 18:30:06,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:06,914 INFO L225 Difference]: With dead ends: 66 [2022-11-18 18:30:06,914 INFO L226 Difference]: Without dead ends: 66 [2022-11-18 18:30:06,914 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=79, Unknown=0, NotChecked=0, Total=132 [2022-11-18 18:30:06,915 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 71 mSDsluCounter, 50 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 71 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:06,915 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [71 Valid, 90 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-18 18:30:06,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2022-11-18 18:30:06,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2022-11-18 18:30:06,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 62 states have (on average 1.0483870967741935) internal successors, (65), 64 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:06,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 69 transitions. [2022-11-18 18:30:06,919 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 69 transitions. Word has length 58 [2022-11-18 18:30:06,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:06,919 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 69 transitions. [2022-11-18 18:30:06,919 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:06,919 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 69 transitions. [2022-11-18 18:30:06,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2022-11-18 18:30:06,920 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:06,920 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:06,937 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-11-18 18:30:07,127 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:07,127 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:07,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:07,128 INFO L85 PathProgramCache]: Analyzing trace with hash -220059533, now seen corresponding path program 4 times [2022-11-18 18:30:07,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:07,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779399189] [2022-11-18 18:30:07,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:07,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:07,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:07,490 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:07,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:07,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779399189] [2022-11-18 18:30:07,490 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779399189] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:07,491 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [682773291] [2022-11-18 18:30:07,491 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 18:30:07,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:07,491 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:07,492 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:07,510 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-18 18:30:07,963 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 18:30:07,963 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:07,965 INFO L263 TraceCheckSpWp]: Trace formula consists of 300 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-18 18:30:07,967 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:08,105 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:08,106 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:08,284 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:08,284 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [682773291] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:08,285 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:08,285 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 18 [2022-11-18 18:30:08,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585645368] [2022-11-18 18:30:08,285 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:08,285 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-18 18:30:08,286 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:08,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-18 18:30:08,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=202, Unknown=0, NotChecked=0, Total=306 [2022-11-18 18:30:08,287 INFO L87 Difference]: Start difference. First operand 66 states and 69 transitions. Second operand has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:08,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:08,898 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2022-11-18 18:30:08,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 18:30:08,899 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 61 [2022-11-18 18:30:08,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:08,900 INFO L225 Difference]: With dead ends: 72 [2022-11-18 18:30:08,900 INFO L226 Difference]: Without dead ends: 72 [2022-11-18 18:30:08,900 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=174, Invalid=332, Unknown=0, NotChecked=0, Total=506 [2022-11-18 18:30:08,901 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 45 mSDsluCounter, 230 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 47 SdHoareTripleChecker+Valid, 270 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:08,901 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [47 Valid, 270 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 18:30:08,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2022-11-18 18:30:08,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2022-11-18 18:30:08,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 68 states have (on average 1.0441176470588236) internal successors, (71), 70 states have internal predecessors, (71), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:08,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 75 transitions. [2022-11-18 18:30:08,906 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 75 transitions. Word has length 61 [2022-11-18 18:30:08,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:08,906 INFO L495 AbstractCegarLoop]: Abstraction has 72 states and 75 transitions. [2022-11-18 18:30:08,906 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:08,906 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 75 transitions. [2022-11-18 18:30:08,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-18 18:30:08,907 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:08,907 INFO L195 NwaCegarLoop]: trace histogram [10, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:08,921 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-18 18:30:09,115 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:09,116 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:09,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:09,116 INFO L85 PathProgramCache]: Analyzing trace with hash -179470317, now seen corresponding path program 5 times [2022-11-18 18:30:09,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:09,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552953534] [2022-11-18 18:30:09,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:09,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:09,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:09,811 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:09,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:09,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552953534] [2022-11-18 18:30:09,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552953534] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:09,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1658393012] [2022-11-18 18:30:09,812 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 18:30:09,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:09,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:09,816 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:09,829 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-18 18:30:10,943 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-18 18:30:10,943 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:10,949 INFO L263 TraceCheckSpWp]: Trace formula consists of 342 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-18 18:30:10,953 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:11,330 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:11,331 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:11,876 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:11,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1658393012] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:11,876 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:11,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 36 [2022-11-18 18:30:11,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731547445] [2022-11-18 18:30:11,876 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:11,877 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-11-18 18:30:11,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:11,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-11-18 18:30:11,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=898, Unknown=0, NotChecked=0, Total=1260 [2022-11-18 18:30:11,879 INFO L87 Difference]: Start difference. First operand 72 states and 75 transitions. Second operand has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:19,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:30:19,011 INFO L93 Difference]: Finished difference Result 84 states and 87 transitions. [2022-11-18 18:30:19,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-18 18:30:19,012 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 67 [2022-11-18 18:30:19,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:30:19,013 INFO L225 Difference]: With dead ends: 84 [2022-11-18 18:30:19,013 INFO L226 Difference]: Without dead ends: 84 [2022-11-18 18:30:19,014 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 493 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=648, Invalid=1514, Unknown=0, NotChecked=0, Total=2162 [2022-11-18 18:30:19,015 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 57 mSDsluCounter, 415 mSDsCounter, 0 mSdLazyCounter, 253 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 455 SdHoareTripleChecker+Invalid, 280 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 253 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 18:30:19,015 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 455 Invalid, 280 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 253 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 18:30:19,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2022-11-18 18:30:19,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2022-11-18 18:30:19,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 80 states have (on average 1.0375) internal successors, (83), 82 states have internal predecessors, (83), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:30:19,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 87 transitions. [2022-11-18 18:30:19,018 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 87 transitions. Word has length 67 [2022-11-18 18:30:19,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:30:19,018 INFO L495 AbstractCegarLoop]: Abstraction has 84 states and 87 transitions. [2022-11-18 18:30:19,019 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:30:19,019 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 87 transitions. [2022-11-18 18:30:19,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2022-11-18 18:30:19,019 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:30:19,020 INFO L195 NwaCegarLoop]: trace histogram [22, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:30:19,027 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-18 18:30:19,226 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2022-11-18 18:30:19,226 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:30:19,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:30:19,227 INFO L85 PathProgramCache]: Analyzing trace with hash -595228845, now seen corresponding path program 6 times [2022-11-18 18:30:19,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:30:19,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409484871] [2022-11-18 18:30:19,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:30:19,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:30:19,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:30:20,697 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:20,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:30:20,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409484871] [2022-11-18 18:30:20,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409484871] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:30:20,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1917882479] [2022-11-18 18:30:20,698 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 18:30:20,698 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:30:20,698 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:30:20,703 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:30:20,708 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-18 18:30:51,275 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-18 18:30:51,275 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 18:30:51,292 INFO L263 TraceCheckSpWp]: Trace formula consists of 426 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-18 18:30:51,297 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:30:52,527 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:52,527 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:30:54,963 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:30:54,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1917882479] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:30:54,963 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:30:54,964 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 72 [2022-11-18 18:30:54,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150873994] [2022-11-18 18:30:54,964 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:30:54,965 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2022-11-18 18:30:54,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:30:54,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2022-11-18 18:30:54,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1310, Invalid=3802, Unknown=0, NotChecked=0, Total=5112 [2022-11-18 18:30:54,968 INFO L87 Difference]: Start difference. First operand 84 states and 87 transitions. Second operand has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:31:11,249 WARN L233 SmtUtils]: Spent 8.72s on a formula simplification. DAG size of input: 120 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:31:25,264 WARN L233 SmtUtils]: Spent 5.37s on a formula simplification. DAG size of input: 114 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:31:39,699 WARN L233 SmtUtils]: Spent 5.05s on a formula simplification. DAG size of input: 108 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:32:05,960 WARN L233 SmtUtils]: Spent 5.42s on a formula simplification. DAG size of input: 96 DAG size of output: 14 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:34:09,271 WARN L233 SmtUtils]: Spent 21.29s on a formula simplification. DAG size of input: 116 DAG size of output: 26 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:34:11,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 18:34:11,528 INFO L93 Difference]: Finished difference Result 108 states and 111 transitions. [2022-11-18 18:34:11,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-11-18 18:34:11,529 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 79 [2022-11-18 18:34:11,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 18:34:11,530 INFO L225 Difference]: With dead ends: 108 [2022-11-18 18:34:11,530 INFO L226 Difference]: Without dead ends: 108 [2022-11-18 18:34:11,533 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2186 ImplicationChecksByTransitivity, 197.4s TimeCoverageRelationStatistics Valid=2494, Invalid=6621, Unknown=5, NotChecked=0, Total=9120 [2022-11-18 18:34:11,534 INFO L413 NwaCegarLoop]: 40 mSDtfsCounter, 514 mSDsluCounter, 688 mSDsCounter, 0 mSdLazyCounter, 1022 mSolverCounterSat, 103 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 514 SdHoareTripleChecker+Valid, 728 SdHoareTripleChecker+Invalid, 1125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 103 IncrementalHoareTripleChecker+Valid, 1022 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.1s IncrementalHoareTripleChecker+Time [2022-11-18 18:34:11,534 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [514 Valid, 728 Invalid, 1125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [103 Valid, 1022 Invalid, 0 Unknown, 0 Unchecked, 3.1s Time] [2022-11-18 18:34:11,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2022-11-18 18:34:11,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2022-11-18 18:34:11,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 104 states have (on average 1.0288461538461537) internal successors, (107), 106 states have internal predecessors, (107), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-11-18 18:34:11,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 111 transitions. [2022-11-18 18:34:11,538 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 111 transitions. Word has length 79 [2022-11-18 18:34:11,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 18:34:11,538 INFO L495 AbstractCegarLoop]: Abstraction has 108 states and 111 transitions. [2022-11-18 18:34:11,539 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:11,539 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 111 transitions. [2022-11-18 18:34:11,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2022-11-18 18:34:11,540 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 18:34:11,540 INFO L195 NwaCegarLoop]: trace histogram [46, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 18:34:11,552 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-18 18:34:11,752 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2022-11-18 18:34:11,752 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 22 more)] === [2022-11-18 18:34:11,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 18:34:11,753 INFO L85 PathProgramCache]: Analyzing trace with hash 51574227, now seen corresponding path program 7 times [2022-11-18 18:34:11,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-18 18:34:11,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100815343] [2022-11-18 18:34:11,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 18:34:11,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-18 18:34:11,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:15,587 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:34:15,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-18 18:34:15,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100815343] [2022-11-18 18:34:15,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100815343] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-18 18:34:15,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1407131134] [2022-11-18 18:34:15,588 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 18:34:15,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-18 18:34:15,588 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 18:34:15,595 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-18 18:34:15,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7359c37f-743b-4ebf-99d5-b24f745edec1/bin/uautomizer-TMbwUNV5ro/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-18 18:34:16,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 18:34:16,661 INFO L263 TraceCheckSpWp]: Trace formula consists of 594 conjuncts, 97 conjunts are in the unsatisfiable core [2022-11-18 18:34:16,664 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 18:34:20,814 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:34:20,814 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 18:34:27,459 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-18 18:34:27,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1407131134] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 18:34:27,459 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-18 18:34:27,460 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 144 [2022-11-18 18:34:27,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725489309] [2022-11-18 18:34:27,460 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-18 18:34:27,461 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 144 states [2022-11-18 18:34:27,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-18 18:34:27,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2022-11-18 18:34:27,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4934, Invalid=15658, Unknown=0, NotChecked=0, Total=20592 [2022-11-18 18:34:27,468 INFO L87 Difference]: Start difference. First operand 108 states and 111 transitions. Second operand has 144 states, 144 states have (on average 1.2361111111111112) internal successors, (178), 144 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 18:34:31,513 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 45 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (<= |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 94) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 46 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (<= 94 |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1|) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:33,538 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 45 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:35,557 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 44 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:37,582 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:39,612 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 42 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:41,637 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 41 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:43,653 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 40 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:45,667 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 39 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:47,691 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 38 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:49,707 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:34:51,728 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 36 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 35 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:09,971 WARN L233 SmtUtils]: Spent 2.37m on a formula simplification that was a NOOP. DAG size: 147 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:39:11,980 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:14,538 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:16,542 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:18,550 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:20,586 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.03s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:22,590 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:24,593 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:26,598 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:28,608 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:31,409 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:33,415 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:35,426 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:39:37,443 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 34 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:39,460 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ 33 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:41,472 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 32 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:43,485 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 31 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:45,509 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ 30 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0))) is different from false [2022-11-18 18:39:47,520 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 29 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-18 18:39:49,530 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-18 18:39:51,545 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0))) is different from false [2022-11-18 18:39:53,557 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:39:55,570 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:39:57,585 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:39:59,597 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 23 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 22 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:42:57,927 WARN L233 SmtUtils]: Spent 1.25m on a formula simplification that was a NOOP. DAG size: 95 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 18:43:00,879 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:03,523 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:05,227 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.70s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:07,231 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:08,831 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.60s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:10,836 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:12,460 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.51s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:13,760 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.22s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:15,825 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:17,830 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:19,008 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.18s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:20,965 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.05s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:23,503 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:25,662 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.43s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 18:43:27,673 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 21 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:43:29,684 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ 20 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false [2022-11-18 18:43:31,701 WARN L837 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ 18 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 8 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 3 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 19 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 5 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 9 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ 7 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 2 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ 15 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 14 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod (+ 12 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 16 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod (+ 6 |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1|) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0))) is different from false