./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/weaver/unroll-cond-2.wvr.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 8393723b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/weaver/unroll-cond-2.wvr.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 99c42ba3d1f6c70520bbcf0a3136609166f98fb21063bda215f7779ff0bb27ca --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 21:10:19,887 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 21:10:19,889 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 21:10:19,915 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 21:10:19,915 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 21:10:19,916 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 21:10:19,918 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 21:10:19,919 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 21:10:19,921 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 21:10:19,922 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 21:10:19,923 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 21:10:19,924 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 21:10:19,925 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 21:10:19,926 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 21:10:19,927 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 21:10:19,928 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 21:10:19,929 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 21:10:19,930 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 21:10:19,932 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 21:10:19,934 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 21:10:19,935 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 21:10:19,936 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 21:10:19,938 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 21:10:19,939 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 21:10:19,942 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 21:10:19,943 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 21:10:19,943 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 21:10:19,944 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 21:10:19,945 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 21:10:19,946 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 21:10:19,946 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 21:10:19,947 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 21:10:19,948 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 21:10:19,948 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 21:10:19,949 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 21:10:19,950 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 21:10:19,951 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 21:10:19,951 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 21:10:19,952 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 21:10:19,953 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 21:10:19,953 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 21:10:19,954 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2022-11-18 21:10:19,978 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 21:10:19,978 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 21:10:19,979 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 21:10:19,979 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 21:10:19,980 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-18 21:10:19,980 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-18 21:10:19,980 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 21:10:19,981 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 21:10:19,981 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 21:10:19,981 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 21:10:19,981 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 21:10:19,982 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 21:10:19,982 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 21:10:19,982 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 21:10:19,982 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 21:10:19,982 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2022-11-18 21:10:19,983 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2022-11-18 21:10:19,983 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2022-11-18 21:10:19,983 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-18 21:10:19,983 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-18 21:10:19,983 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 21:10:19,984 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 21:10:19,984 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 21:10:19,984 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 21:10:19,984 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-18 21:10:19,985 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 21:10:19,985 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 21:10:19,985 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-18 21:10:19,985 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-18 21:10:19,985 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-18 21:10:19,986 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 99c42ba3d1f6c70520bbcf0a3136609166f98fb21063bda215f7779ff0bb27ca [2022-11-18 21:10:20,276 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 21:10:20,298 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 21:10:20,301 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 21:10:20,306 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 21:10:20,307 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 21:10:20,308 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/weaver/unroll-cond-2.wvr.c [2022-11-18 21:10:20,392 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/8f02809a3/6d88a0241b704538b895353fd4dc976f/FLAG85ac66c46 [2022-11-18 21:10:20,967 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 21:10:20,968 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c [2022-11-18 21:10:20,976 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/8f02809a3/6d88a0241b704538b895353fd4dc976f/FLAG85ac66c46 [2022-11-18 21:10:21,324 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/8f02809a3/6d88a0241b704538b895353fd4dc976f [2022-11-18 21:10:21,330 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 21:10:21,335 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 21:10:21,339 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 21:10:21,339 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 21:10:21,343 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 21:10:21,344 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:10:21" (1/1) ... [2022-11-18 21:10:21,347 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7a88af27 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:21, skipping insertion in model container [2022-11-18 21:10:21,347 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:10:21" (1/1) ... [2022-11-18 21:10:21,356 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 21:10:21,380 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 21:10:21,670 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c[2474,2487] [2022-11-18 21:10:21,687 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:10:21,703 ERROR L326 MainTranslator]: Unsupported Syntax: Found a cast between two array/pointer types of different sizes while using memory model HoenickeLindenmann_Original (while Not using bitvector translation) [2022-11-18 21:10:21,706 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieTranslatorObserver@2992d90b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:21, skipping insertion in model container [2022-11-18 21:10:21,706 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 21:10:21,707 INFO L184 ToolchainWalker]: Toolchain execution was canceled (user or tool) before executing de.uni_freiburg.informatik.ultimate.boogie.procedureinliner [2022-11-18 21:10:21,709 INFO L158 Benchmark]: Toolchain (without parser) took 372.91ms. Allocated memory is still 109.1MB. Free memory was 67.7MB in the beginning and 85.2MB in the end (delta: -17.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-18 21:10:21,711 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 109.1MB. Free memory is still 84.6MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-18 21:10:21,713 INFO L158 Benchmark]: CACSL2BoogieTranslator took 367.99ms. Allocated memory is still 109.1MB. Free memory was 67.5MB in the beginning and 85.2MB in the end (delta: -17.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-18 21:10:21,715 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 109.1MB. Free memory is still 84.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 367.99ms. Allocated memory is still 109.1MB. Free memory was 67.5MB in the beginning and 85.2MB in the end (delta: -17.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - UnsupportedSyntaxResult [Line: 100]: Unsupported Syntax Found a cast between two array/pointer types of different sizes while using memory model HoenickeLindenmann_Original (while Not using bitvector translation) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/weaver/unroll-cond-2.wvr.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 99c42ba3d1f6c70520bbcf0a3136609166f98fb21063bda215f7779ff0bb27ca --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-8393723 [2022-11-18 21:10:23,803 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-18 21:10:23,806 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-18 21:10:23,827 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-18 21:10:23,827 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-18 21:10:23,829 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-18 21:10:23,830 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-18 21:10:23,832 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-18 21:10:23,834 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-18 21:10:23,835 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-18 21:10:23,836 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-18 21:10:23,837 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-18 21:10:23,838 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-18 21:10:23,839 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-18 21:10:23,840 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-18 21:10:23,841 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-18 21:10:23,842 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-18 21:10:23,843 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-18 21:10:23,845 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-18 21:10:23,847 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-18 21:10:23,848 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-18 21:10:23,854 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-18 21:10:23,855 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-18 21:10:23,856 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-18 21:10:23,859 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-18 21:10:23,859 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-18 21:10:23,860 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-18 21:10:23,861 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-18 21:10:23,861 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-18 21:10:23,862 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-18 21:10:23,863 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-18 21:10:23,864 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-18 21:10:23,864 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-18 21:10:23,865 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-18 21:10:23,874 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-18 21:10:23,875 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-18 21:10:23,877 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-18 21:10:23,877 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-18 21:10:23,877 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-18 21:10:23,879 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-18 21:10:23,880 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-18 21:10:23,881 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Bitvector.epf [2022-11-18 21:10:23,926 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-18 21:10:23,926 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-18 21:10:23,927 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-18 21:10:23,928 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-18 21:10:23,929 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-18 21:10:23,929 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-18 21:10:23,930 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-18 21:10:23,931 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-18 21:10:23,931 INFO L138 SettingsManager]: * Use SBE=true [2022-11-18 21:10:23,931 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-18 21:10:23,932 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-18 21:10:23,932 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-18 21:10:23,933 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-18 21:10:23,933 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-18 21:10:23,933 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-18 21:10:23,933 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2022-11-18 21:10:23,934 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2022-11-18 21:10:23,934 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2022-11-18 21:10:23,934 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-18 21:10:23,934 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-18 21:10:23,934 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-18 21:10:23,935 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-18 21:10:23,935 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-18 21:10:23,935 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-18 21:10:23,936 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-18 21:10:23,936 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-18 21:10:23,936 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-18 21:10:23,936 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 21:10:23,937 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-18 21:10:23,937 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-18 21:10:23,937 INFO L138 SettingsManager]: * Trace refinement strategy=WOLF [2022-11-18 21:10:23,937 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-18 21:10:23,938 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-18 21:10:23,938 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 99c42ba3d1f6c70520bbcf0a3136609166f98fb21063bda215f7779ff0bb27ca [2022-11-18 21:10:24,310 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-18 21:10:24,342 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-18 21:10:24,347 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-18 21:10:24,348 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-18 21:10:24,351 INFO L275 PluginConnector]: CDTParser initialized [2022-11-18 21:10:24,352 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/../../sv-benchmarks/c/weaver/unroll-cond-2.wvr.c [2022-11-18 21:10:24,435 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/c5e98ee86/aafb080732ea4dadabb535fbf1828a2c/FLAG5d71ac78e [2022-11-18 21:10:24,939 INFO L306 CDTParser]: Found 1 translation units. [2022-11-18 21:10:24,940 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c [2022-11-18 21:10:24,953 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/c5e98ee86/aafb080732ea4dadabb535fbf1828a2c/FLAG5d71ac78e [2022-11-18 21:10:25,300 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/data/c5e98ee86/aafb080732ea4dadabb535fbf1828a2c [2022-11-18 21:10:25,304 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-18 21:10:25,308 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-18 21:10:25,310 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-18 21:10:25,310 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-18 21:10:25,314 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-18 21:10:25,315 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,317 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@577c9f43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25, skipping insertion in model container [2022-11-18 21:10:25,317 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,325 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-18 21:10:25,348 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 21:10:25,611 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c[2474,2487] [2022-11-18 21:10:25,640 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:10:25,679 INFO L200 MainTranslator]: Restarting translation with changed settings: SettingsChange [mNewPreferredMemoryModel=HoenickeLindenmann_1ByteResolution] [2022-11-18 21:10:25,683 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-18 21:10:25,698 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c[2474,2487] [2022-11-18 21:10:25,701 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:10:25,707 INFO L203 MainTranslator]: Completed pre-run [2022-11-18 21:10:25,732 WARN L234 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/sv-benchmarks/c/weaver/unroll-cond-2.wvr.c[2474,2487] [2022-11-18 21:10:25,736 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-18 21:10:25,753 INFO L208 MainTranslator]: Completed translation [2022-11-18 21:10:25,754 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25 WrapperNode [2022-11-18 21:10:25,754 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-18 21:10:25,755 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-18 21:10:25,755 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-18 21:10:25,756 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-18 21:10:25,763 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,789 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,828 INFO L138 Inliner]: procedures = 26, calls = 33, calls flagged for inlining = 11, calls inlined = 11, statements flattened = 139 [2022-11-18 21:10:25,828 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-18 21:10:25,829 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-18 21:10:25,829 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-18 21:10:25,829 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-18 21:10:25,842 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,842 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,866 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,866 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,879 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,890 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,895 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,897 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,900 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-18 21:10:25,901 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-18 21:10:25,901 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-18 21:10:25,901 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-18 21:10:25,902 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (1/1) ... [2022-11-18 21:10:25,914 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-18 21:10:25,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/z3 [2022-11-18 21:10:25,938 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-18 21:10:25,941 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-18 21:10:25,988 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-18 21:10:25,988 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1 [2022-11-18 21:10:25,989 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-18 21:10:25,991 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2022-11-18 21:10:25,991 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2022-11-18 21:10:25,991 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2022-11-18 21:10:25,991 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2022-11-18 21:10:25,992 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2022-11-18 21:10:25,992 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-11-18 21:10:25,992 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-18 21:10:25,992 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-18 21:10:25,992 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-18 21:10:25,993 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2022-11-18 21:10:25,994 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-11-18 21:10:26,154 INFO L235 CfgBuilder]: Building ICFG [2022-11-18 21:10:26,157 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-18 21:10:26,785 INFO L276 CfgBuilder]: Performing block encoding [2022-11-18 21:10:26,794 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-18 21:10:26,794 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-11-18 21:10:26,796 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:10:26 BoogieIcfgContainer [2022-11-18 21:10:26,796 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-18 21:10:26,799 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-18 21:10:26,799 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-18 21:10:26,802 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-18 21:10:26,802 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 18.11 09:10:25" (1/3) ... [2022-11-18 21:10:26,803 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f482ddf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:10:26, skipping insertion in model container [2022-11-18 21:10:26,803 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:10:25" (2/3) ... [2022-11-18 21:10:26,803 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3f482ddf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 18.11 09:10:26, skipping insertion in model container [2022-11-18 21:10:26,803 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:10:26" (3/3) ... [2022-11-18 21:10:26,805 INFO L112 eAbstractionObserver]: Analyzing ICFG unroll-cond-2.wvr.c [2022-11-18 21:10:26,840 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-18 21:10:26,840 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 20 error locations. [2022-11-18 21:10:26,840 INFO L515 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2022-11-18 21:10:26,994 INFO L144 ThreadInstanceAdder]: Constructed 2 joinOtherThreadTransitions. [2022-11-18 21:10:27,049 INFO L115 etLargeBlockEncoding]: Petri net LBE is using semantic-based independence relation. [2022-11-18 21:10:27,067 INFO L131 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 191 places, 199 transitions, 414 flow [2022-11-18 21:10:27,073 INFO L113 LiptonReduction]: Starting Lipton reduction on Petri net that has 191 places, 199 transitions, 414 flow [2022-11-18 21:10:27,075 INFO L73 FinitePrefix]: Start finitePrefix. Operand has 191 places, 199 transitions, 414 flow [2022-11-18 21:10:27,206 INFO L130 PetriNetUnfolder]: 15/197 cut-off events. [2022-11-18 21:10:27,207 INFO L131 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2022-11-18 21:10:27,214 INFO L83 FinitePrefix]: Finished finitePrefix Result has 206 conditions, 197 events. 15/197 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 319 event pairs, 0 based on Foata normal form. 0/162 useless extension candidates. Maximal degree in co-relation 109. Up to 2 conditions per place. [2022-11-18 21:10:27,219 INFO L119 LiptonReduction]: Number of co-enabled transitions 4156 [2022-11-18 21:10:54,048 INFO L134 LiptonReduction]: Checked pairs total: 4096 [2022-11-18 21:10:54,049 INFO L136 LiptonReduction]: Total number of compositions: 225 [2022-11-18 21:10:54,056 INFO L113 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 43 places, 39 transitions, 94 flow [2022-11-18 21:10:54,087 INFO L135 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result has 246 states, 158 states have (on average 3.911392405063291) internal successors, (618), 245 states have internal predecessors, (618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:54,106 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-18 21:10:54,112 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@8660f38, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-18 21:10:54,112 INFO L358 AbstractCegarLoop]: Starting to check reachability of 30 error locations. [2022-11-18 21:10:54,115 INFO L276 IsEmpty]: Start isEmpty. Operand has 246 states, 158 states have (on average 3.911392405063291) internal successors, (618), 245 states have internal predecessors, (618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:54,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2022-11-18 21:10:54,120 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:54,121 INFO L195 NwaCegarLoop]: trace histogram [1, 1] [2022-11-18 21:10:54,121 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:54,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:54,127 INFO L85 PathProgramCache]: Analyzing trace with hash 25397, now seen corresponding path program 1 times [2022-11-18 21:10:54,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:54,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [313497257] [2022-11-18 21:10:54,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:54,138 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:54,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:54,139 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:54,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-18 21:10:54,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:54,258 INFO L263 TraceCheckSpWp]: Trace formula consists of 46 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-18 21:10:54,263 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:54,410 INFO L321 Elim1Store]: treesize reduction 39, result has 40.0 percent of original size [2022-11-18 21:10:54,411 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 33 [2022-11-18 21:10:54,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:10:54,442 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:10:54,443 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:54,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [313497257] [2022-11-18 21:10:54,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [313497257] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:10:54,444 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:10:54,444 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:10:54,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24583818] [2022-11-18 21:10:54,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:10:54,451 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:10:54,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:54,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:10:54,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:54,508 INFO L87 Difference]: Start difference. First operand has 246 states, 158 states have (on average 3.911392405063291) internal successors, (618), 245 states have internal predecessors, (618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:54,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:54,807 INFO L93 Difference]: Finished difference Result 220 states and 553 transitions. [2022-11-18 21:10:54,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:10:54,811 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 2 [2022-11-18 21:10:54,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:54,828 INFO L225 Difference]: With dead ends: 220 [2022-11-18 21:10:54,829 INFO L226 Difference]: Without dead ends: 220 [2022-11-18 21:10:54,830 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:54,836 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 32 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:54,842 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 2 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 21:10:54,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2022-11-18 21:10:54,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 220. [2022-11-18 21:10:54,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 145 states have (on average 3.8137931034482757) internal successors, (553), 219 states have internal predecessors, (553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:54,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 553 transitions. [2022-11-18 21:10:54,922 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 553 transitions. Word has length 2 [2022-11-18 21:10:54,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:54,923 INFO L495 AbstractCegarLoop]: Abstraction has 220 states and 553 transitions. [2022-11-18 21:10:54,924 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:54,924 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 553 transitions. [2022-11-18 21:10:54,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2022-11-18 21:10:54,924 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:54,925 INFO L195 NwaCegarLoop]: trace histogram [1, 1] [2022-11-18 21:10:54,948 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:55,136 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:55,137 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:55,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:55,138 INFO L85 PathProgramCache]: Analyzing trace with hash 25398, now seen corresponding path program 1 times [2022-11-18 21:10:55,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:55,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [750910086] [2022-11-18 21:10:55,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:55,144 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:55,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:55,146 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:55,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-18 21:10:55,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:55,218 INFO L263 TraceCheckSpWp]: Trace formula consists of 46 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-18 21:10:55,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:55,304 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:10:55,305 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:10:55,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:10:55,333 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:10:55,333 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:55,333 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [750910086] [2022-11-18 21:10:55,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [750910086] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:10:55,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:10:55,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:10:55,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613513510] [2022-11-18 21:10:55,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:10:55,335 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:10:55,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:55,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:10:55,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:55,336 INFO L87 Difference]: Start difference. First operand 220 states and 553 transitions. Second operand has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:55,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:55,735 INFO L93 Difference]: Finished difference Result 438 states and 1104 transitions. [2022-11-18 21:10:55,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:10:55,736 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 2 [2022-11-18 21:10:55,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:55,740 INFO L225 Difference]: With dead ends: 438 [2022-11-18 21:10:55,740 INFO L226 Difference]: Without dead ends: 438 [2022-11-18 21:10:55,740 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:55,741 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 30 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 4 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:55,742 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [30 Valid, 4 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-18 21:10:55,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states. [2022-11-18 21:10:55,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 221. [2022-11-18 21:10:55,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 146 states have (on average 3.815068493150685) internal successors, (557), 220 states have internal predecessors, (557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:55,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 557 transitions. [2022-11-18 21:10:55,758 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 557 transitions. Word has length 2 [2022-11-18 21:10:55,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:55,759 INFO L495 AbstractCegarLoop]: Abstraction has 221 states and 557 transitions. [2022-11-18 21:10:55,759 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:55,759 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 557 transitions. [2022-11-18 21:10:55,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2022-11-18 21:10:55,760 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:55,760 INFO L195 NwaCegarLoop]: trace histogram [1, 1] [2022-11-18 21:10:55,781 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:55,971 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:55,971 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:55,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:55,972 INFO L85 PathProgramCache]: Analyzing trace with hash 25498, now seen corresponding path program 1 times [2022-11-18 21:10:55,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:55,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [227865881] [2022-11-18 21:10:55,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:55,973 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:55,973 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:55,974 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:55,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-18 21:10:56,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:56,045 INFO L263 TraceCheckSpWp]: Trace formula consists of 52 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:10:56,046 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:56,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:10:56,089 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:10:56,089 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:56,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [227865881] [2022-11-18 21:10:56,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [227865881] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:10:56,090 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:10:56,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:10:56,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023391927] [2022-11-18 21:10:56,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:10:56,091 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:10:56,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:56,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:10:56,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:56,094 INFO L87 Difference]: Start difference. First operand 221 states and 557 transitions. Second operand has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:56,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:56,366 INFO L93 Difference]: Finished difference Result 221 states and 554 transitions. [2022-11-18 21:10:56,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:10:56,367 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 2 [2022-11-18 21:10:56,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:56,371 INFO L225 Difference]: With dead ends: 221 [2022-11-18 21:10:56,371 INFO L226 Difference]: Without dead ends: 221 [2022-11-18 21:10:56,371 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:56,372 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 0 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 4 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:56,373 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 4 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 21:10:56,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2022-11-18 21:10:56,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 221. [2022-11-18 21:10:56,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 146 states have (on average 3.7945205479452055) internal successors, (554), 220 states have internal predecessors, (554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:56,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 554 transitions. [2022-11-18 21:10:56,384 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 554 transitions. Word has length 2 [2022-11-18 21:10:56,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:56,384 INFO L495 AbstractCegarLoop]: Abstraction has 221 states and 554 transitions. [2022-11-18 21:10:56,384 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.0) internal successors, (2), 2 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:56,384 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 554 transitions. [2022-11-18 21:10:56,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-11-18 21:10:56,385 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:56,385 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-11-18 21:10:56,400 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:56,597 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:56,598 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:56,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:56,598 INFO L85 PathProgramCache]: Analyzing trace with hash 790633, now seen corresponding path program 1 times [2022-11-18 21:10:56,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:56,599 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [626428391] [2022-11-18 21:10:56,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:56,599 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:56,600 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:56,601 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:56,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-18 21:10:56,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:56,678 INFO L263 TraceCheckSpWp]: Trace formula consists of 57 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-18 21:10:56,683 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:56,781 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:10:56,782 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:10:56,858 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:10:56,858 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:10:57,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:10:57,124 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:57,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [626428391] [2022-11-18 21:10:57,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [626428391] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:10:57,124 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:10:57,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2] total 4 [2022-11-18 21:10:57,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483432823] [2022-11-18 21:10:57,125 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:10:57,125 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-18 21:10:57,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:57,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-18 21:10:57,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2022-11-18 21:10:57,126 INFO L87 Difference]: Start difference. First operand 221 states and 554 transitions. Second operand has 6 states, 5 states have (on average 1.2) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:58,016 INFO L93 Difference]: Finished difference Result 441 states and 1113 transitions. [2022-11-18 21:10:58,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 21:10:58,018 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 1.2) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-11-18 21:10:58,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:58,021 INFO L225 Difference]: With dead ends: 441 [2022-11-18 21:10:58,022 INFO L226 Difference]: Without dead ends: 441 [2022-11-18 21:10:58,022 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2022-11-18 21:10:58,023 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 93 mSDsluCounter, 4 mSDsCounter, 0 mSdLazyCounter, 98 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 93 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 98 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:58,023 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [93 Valid, 6 Invalid, 110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 98 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-18 21:10:58,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2022-11-18 21:10:58,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 224. [2022-11-18 21:10:58,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 149 states have (on average 3.7986577181208054) internal successors, (566), 223 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 566 transitions. [2022-11-18 21:10:58,037 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 566 transitions. Word has length 3 [2022-11-18 21:10:58,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:58,038 INFO L495 AbstractCegarLoop]: Abstraction has 224 states and 566 transitions. [2022-11-18 21:10:58,038 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 1.2) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,038 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 566 transitions. [2022-11-18 21:10:58,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-11-18 21:10:58,038 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:58,038 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-11-18 21:10:58,055 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:58,250 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:58,250 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:58,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:58,251 INFO L85 PathProgramCache]: Analyzing trace with hash 790733, now seen corresponding path program 1 times [2022-11-18 21:10:58,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:58,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1591196618] [2022-11-18 21:10:58,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:58,252 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:58,252 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:58,253 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:58,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-18 21:10:58,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:58,335 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-18 21:10:58,337 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:58,383 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:10:58,433 INFO L321 Elim1Store]: treesize reduction 24, result has 44.2 percent of original size [2022-11-18 21:10:58,433 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 26 [2022-11-18 21:10:58,453 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 8 [2022-11-18 21:10:58,613 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:10:58,613 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:10:58,614 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:58,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1591196618] [2022-11-18 21:10:58,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1591196618] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:10:58,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:10:58,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:10:58,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552955847] [2022-11-18 21:10:58,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:10:58,614 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:10:58,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:58,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:10:58,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:58,615 INFO L87 Difference]: Start difference. First operand 224 states and 566 transitions. Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:58,781 INFO L93 Difference]: Finished difference Result 223 states and 562 transitions. [2022-11-18 21:10:58,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:10:58,782 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-11-18 21:10:58,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:58,784 INFO L225 Difference]: With dead ends: 223 [2022-11-18 21:10:58,784 INFO L226 Difference]: Without dead ends: 223 [2022-11-18 21:10:58,784 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:58,785 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 0 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 4 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 29 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:58,785 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 4 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 29 Unchecked, 0.2s Time] [2022-11-18 21:10:58,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2022-11-18 21:10:58,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2022-11-18 21:10:58,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 223 states, 149 states have (on average 3.771812080536913) internal successors, (562), 222 states have internal predecessors, (562), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 562 transitions. [2022-11-18 21:10:58,809 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 562 transitions. Word has length 3 [2022-11-18 21:10:58,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:58,810 INFO L495 AbstractCegarLoop]: Abstraction has 223 states and 562 transitions. [2022-11-18 21:10:58,810 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:58,810 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 562 transitions. [2022-11-18 21:10:58,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-11-18 21:10:58,811 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:58,811 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-11-18 21:10:58,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:59,022 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:59,023 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:59,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:59,023 INFO L85 PathProgramCache]: Analyzing trace with hash 790734, now seen corresponding path program 1 times [2022-11-18 21:10:59,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:59,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [116832938] [2022-11-18 21:10:59,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:59,024 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:59,024 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:59,025 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:59,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-18 21:10:59,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:59,107 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-18 21:10:59,109 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:59,150 INFO L321 Elim1Store]: treesize reduction 50, result has 23.1 percent of original size [2022-11-18 21:10:59,150 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 3 case distinctions, treesize of input 22 treesize of output 29 [2022-11-18 21:10:59,210 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:10:59,210 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:10:59,210 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:10:59,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [116832938] [2022-11-18 21:10:59,210 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [116832938] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:10:59,210 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:10:59,211 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:10:59,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529634282] [2022-11-18 21:10:59,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:10:59,211 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:10:59,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:10:59,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:10:59,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:59,212 INFO L87 Difference]: Start difference. First operand 223 states and 562 transitions. Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:59,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:10:59,390 INFO L93 Difference]: Finished difference Result 222 states and 558 transitions. [2022-11-18 21:10:59,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:10:59,391 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-11-18 21:10:59,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:10:59,393 INFO L225 Difference]: With dead ends: 222 [2022-11-18 21:10:59,394 INFO L226 Difference]: Without dead ends: 222 [2022-11-18 21:10:59,394 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:10:59,395 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 0 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 4 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 28 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:10:59,395 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 4 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 28 Unchecked, 0.2s Time] [2022-11-18 21:10:59,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2022-11-18 21:10:59,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 222. [2022-11-18 21:10:59,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 222 states, 149 states have (on average 3.7449664429530203) internal successors, (558), 221 states have internal predecessors, (558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:59,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 558 transitions. [2022-11-18 21:10:59,406 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 558 transitions. Word has length 3 [2022-11-18 21:10:59,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:10:59,407 INFO L495 AbstractCegarLoop]: Abstraction has 222 states and 558 transitions. [2022-11-18 21:10:59,407 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:10:59,407 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 558 transitions. [2022-11-18 21:10:59,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-18 21:10:59,408 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:10:59,408 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-18 21:10:59,428 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-18 21:10:59,622 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:59,622 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr5REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:10:59,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:10:59,623 INFO L85 PathProgramCache]: Analyzing trace with hash 759910916, now seen corresponding path program 1 times [2022-11-18 21:10:59,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:10:59,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1473339342] [2022-11-18 21:10:59,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:10:59,624 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:10:59,624 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:10:59,625 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:10:59,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-18 21:10:59,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:10:59,734 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 21:10:59,735 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:10:59,825 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:10:59,825 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:00,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:00,123 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:00,430 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:00,430 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:00,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1473339342] [2022-11-18 21:11:00,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1473339342] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:00,431 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:00,431 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 6 [2022-11-18 21:11:00,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132520348] [2022-11-18 21:11:00,431 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:00,431 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 21:11:00,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:00,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:11:00,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:00,432 INFO L87 Difference]: Start difference. First operand 222 states and 558 transitions. Second operand has 8 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:00,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:00,578 INFO L93 Difference]: Finished difference Result 228 states and 578 transitions. [2022-11-18 21:11:00,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:11:00,579 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-18 21:11:00,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:00,581 INFO L225 Difference]: With dead ends: 228 [2022-11-18 21:11:00,581 INFO L226 Difference]: Without dead ends: 228 [2022-11-18 21:11:00,582 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:00,583 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 10 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 30 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:00,586 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 12 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 20 Invalid, 0 Unknown, 30 Unchecked, 0.1s Time] [2022-11-18 21:11:00,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2022-11-18 21:11:00,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 225. [2022-11-18 21:11:00,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 152 states have (on average 3.736842105263158) internal successors, (568), 224 states have internal predecessors, (568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:00,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 568 transitions. [2022-11-18 21:11:00,598 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 568 transitions. Word has length 5 [2022-11-18 21:11:00,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:00,598 INFO L495 AbstractCegarLoop]: Abstraction has 225 states and 568 transitions. [2022-11-18 21:11:00,598 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:00,598 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 568 transitions. [2022-11-18 21:11:00,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-18 21:11:00,599 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:00,599 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-18 21:11:00,624 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (8)] Ended with exit code 0 [2022-11-18 21:11:00,820 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:00,821 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr4REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:00,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:00,821 INFO L85 PathProgramCache]: Analyzing trace with hash 759910918, now seen corresponding path program 1 times [2022-11-18 21:11:00,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:00,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [533383192] [2022-11-18 21:11:00,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:00,822 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:00,822 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:00,823 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:00,843 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-18 21:11:00,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:00,944 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-18 21:11:00,946 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:00,992 INFO L321 Elim1Store]: treesize reduction 50, result has 23.1 percent of original size [2022-11-18 21:11:00,992 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 22 [2022-11-18 21:11:01,025 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:01,026 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:01,026 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:01,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [533383192] [2022-11-18 21:11:01,026 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [533383192] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:01,026 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:01,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:11:01,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345711800] [2022-11-18 21:11:01,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:01,027 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:11:01,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:01,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:11:01,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:01,027 INFO L87 Difference]: Start difference. First operand 225 states and 568 transitions. Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:01,238 INFO L93 Difference]: Finished difference Result 212 states and 540 transitions. [2022-11-18 21:11:01,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:11:01,239 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-18 21:11:01,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:01,241 INFO L225 Difference]: With dead ends: 212 [2022-11-18 21:11:01,241 INFO L226 Difference]: Without dead ends: 212 [2022-11-18 21:11:01,242 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:01,242 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 25 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:01,243 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [25 Valid, 2 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 21:11:01,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2022-11-18 21:11:01,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2022-11-18 21:11:01,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 148 states have (on average 3.6486486486486487) internal successors, (540), 211 states have internal predecessors, (540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 540 transitions. [2022-11-18 21:11:01,254 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 540 transitions. Word has length 5 [2022-11-18 21:11:01,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:01,255 INFO L495 AbstractCegarLoop]: Abstraction has 212 states and 540 transitions. [2022-11-18 21:11:01,255 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,255 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 540 transitions. [2022-11-18 21:11:01,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2022-11-18 21:11:01,256 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:01,256 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2022-11-18 21:11:01,277 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:01,471 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:01,472 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:01,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:01,472 INFO L85 PathProgramCache]: Analyzing trace with hash 2082395431, now seen corresponding path program 1 times [2022-11-18 21:11:01,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:01,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1144105471] [2022-11-18 21:11:01,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:01,473 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:01,473 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:01,475 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:01,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (10)] Waiting until timeout for monitored process [2022-11-18 21:11:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:01,564 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:11:01,565 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:01,622 INFO L321 Elim1Store]: treesize reduction 39, result has 40.0 percent of original size [2022-11-18 21:11:01,623 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 12 treesize of output 33 [2022-11-18 21:11:01,658 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:01,658 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:01,658 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:01,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1144105471] [2022-11-18 21:11:01,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1144105471] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:01,658 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:01,659 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 21:11:01,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531966939] [2022-11-18 21:11:01,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:01,659 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 21:11:01,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:01,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 21:11:01,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 21:11:01,660 INFO L87 Difference]: Start difference. First operand 212 states and 540 transitions. Second operand has 4 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:01,913 INFO L93 Difference]: Finished difference Result 139 states and 345 transitions. [2022-11-18 21:11:01,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 21:11:01,914 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 6 [2022-11-18 21:11:01,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:01,915 INFO L225 Difference]: With dead ends: 139 [2022-11-18 21:11:01,915 INFO L226 Difference]: Without dead ends: 139 [2022-11-18 21:11:01,916 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:11:01,916 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 44 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 44 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:01,917 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [44 Valid, 2 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 21:11:01,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-11-18 21:11:01,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2022-11-18 21:11:01,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 108 states have (on average 3.1944444444444446) internal successors, (345), 138 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 345 transitions. [2022-11-18 21:11:01,925 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 345 transitions. Word has length 6 [2022-11-18 21:11:01,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:01,925 INFO L495 AbstractCegarLoop]: Abstraction has 139 states and 345 transitions. [2022-11-18 21:11:01,925 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:01,926 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 345 transitions. [2022-11-18 21:11:01,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2022-11-18 21:11:01,926 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:01,926 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2022-11-18 21:11:01,947 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (10)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:02,127 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:02,127 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:02,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:02,128 INFO L85 PathProgramCache]: Analyzing trace with hash 2082395433, now seen corresponding path program 1 times [2022-11-18 21:11:02,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:02,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [141995167] [2022-11-18 21:11:02,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:02,128 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:02,128 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:02,130 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:02,163 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-18 21:11:02,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:02,234 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-18 21:11:02,235 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:02,339 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:02,339 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:02,532 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2022-11-18 21:11:02,666 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:02,666 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:02,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [141995167] [2022-11-18 21:11:02,666 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [141995167] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:02,666 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:02,666 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 6 [2022-11-18 21:11:02,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451166506] [2022-11-18 21:11:02,667 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:02,667 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 21:11:02,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:02,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:11:02,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:02,668 INFO L87 Difference]: Start difference. First operand 139 states and 345 transitions. Second operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:03,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:03,648 INFO L93 Difference]: Finished difference Result 313 states and 776 transitions. [2022-11-18 21:11:03,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:11:03,649 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 6 [2022-11-18 21:11:03,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:03,651 INFO L225 Difference]: With dead ends: 313 [2022-11-18 21:11:03,651 INFO L226 Difference]: Without dead ends: 313 [2022-11-18 21:11:03,651 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2022-11-18 21:11:03,652 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 182 mSDsluCounter, 6 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 182 SdHoareTripleChecker+Valid, 8 SdHoareTripleChecker+Invalid, 119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:03,652 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [182 Valid, 8 Invalid, 119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 116 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-11-18 21:11:03,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2022-11-18 21:11:03,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 166. [2022-11-18 21:11:03,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166 states, 135 states have (on average 3.2814814814814817) internal successors, (443), 165 states have internal predecessors, (443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:03,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 443 transitions. [2022-11-18 21:11:03,659 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 443 transitions. Word has length 6 [2022-11-18 21:11:03,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:03,659 INFO L495 AbstractCegarLoop]: Abstraction has 166 states and 443 transitions. [2022-11-18 21:11:03,660 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:03,660 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 443 transitions. [2022-11-18 21:11:03,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2022-11-18 21:11:03,660 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:03,660 INFO L195 NwaCegarLoop]: trace histogram [4, 1, 1] [2022-11-18 21:11:03,675 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:03,860 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:03,861 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:03,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:03,861 INFO L85 PathProgramCache]: Analyzing trace with hash 2082183158, now seen corresponding path program 2 times [2022-11-18 21:11:03,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:03,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1813460210] [2022-11-18 21:11:03,862 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:11:03,862 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:03,862 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:03,863 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:03,867 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-18 21:11:03,950 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:11:03,950 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:11:03,953 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-18 21:11:03,955 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:04,030 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:04,031 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:04,203 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:04,203 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:04,920 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:04,920 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:04,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1813460210] [2022-11-18 21:11:04,920 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1813460210] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:04,920 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:04,921 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 10 [2022-11-18 21:11:04,921 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679788228] [2022-11-18 21:11:04,921 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:04,921 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-11-18 21:11:04,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:04,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-11-18 21:11:04,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2022-11-18 21:11:04,922 INFO L87 Difference]: Start difference. First operand 166 states and 443 transitions. Second operand has 12 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:09,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:09,777 INFO L93 Difference]: Finished difference Result 1413 states and 3847 transitions. [2022-11-18 21:11:09,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:11:09,779 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 6 [2022-11-18 21:11:09,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:09,788 INFO L225 Difference]: With dead ends: 1413 [2022-11-18 21:11:09,788 INFO L226 Difference]: Without dead ends: 1413 [2022-11-18 21:11:09,789 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2022-11-18 21:11:09,790 INFO L413 NwaCegarLoop]: 8 mSDtfsCounter, 460 mSDsluCounter, 40 mSDsCounter, 0 mSdLazyCounter, 549 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 460 SdHoareTripleChecker+Valid, 48 SdHoareTripleChecker+Invalid, 559 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 549 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:09,790 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [460 Valid, 48 Invalid, 559 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 549 Invalid, 0 Unknown, 0 Unchecked, 3.3s Time] [2022-11-18 21:11:09,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1413 states. [2022-11-18 21:11:09,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1413 to 172. [2022-11-18 21:11:09,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 141 states have (on average 3.226950354609929) internal successors, (455), 171 states have internal predecessors, (455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:09,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 455 transitions. [2022-11-18 21:11:09,811 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 455 transitions. Word has length 6 [2022-11-18 21:11:09,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:09,811 INFO L495 AbstractCegarLoop]: Abstraction has 172 states and 455 transitions. [2022-11-18 21:11:09,812 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:09,812 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 455 transitions. [2022-11-18 21:11:09,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:09,812 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:09,812 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:09,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:10,025 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:10,026 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr6REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:10,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:10,026 INFO L85 PathProgramCache]: Analyzing trace with hash 129968283, now seen corresponding path program 1 times [2022-11-18 21:11:10,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:10,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1177333279] [2022-11-18 21:11:10,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:10,027 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:10,028 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:10,029 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:10,034 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-18 21:11:10,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:10,132 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-18 21:11:10,133 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:10,156 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:10,156 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:10,157 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:10,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1177333279] [2022-11-18 21:11:10,157 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1177333279] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:10,157 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:10,157 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 21:11:10,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757129771] [2022-11-18 21:11:10,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:10,158 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:11:10,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:10,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:11:10,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:10,159 INFO L87 Difference]: Start difference. First operand 172 states and 455 transitions. Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:10,329 INFO L93 Difference]: Finished difference Result 142 states and 359 transitions. [2022-11-18 21:11:10,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:11:10,330 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:10,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:10,331 INFO L225 Difference]: With dead ends: 142 [2022-11-18 21:11:10,331 INFO L226 Difference]: Without dead ends: 142 [2022-11-18 21:11:10,331 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:10,332 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 20 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 24 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:10,332 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 2 Invalid, 24 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 21:11:10,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2022-11-18 21:11:10,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2022-11-18 21:11:10,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 119 states have (on average 3.0168067226890756) internal successors, (359), 141 states have internal predecessors, (359), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 359 transitions. [2022-11-18 21:11:10,339 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 359 transitions. Word has length 7 [2022-11-18 21:11:10,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:10,339 INFO L495 AbstractCegarLoop]: Abstraction has 142 states and 359 transitions. [2022-11-18 21:11:10,339 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,339 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 359 transitions. [2022-11-18 21:11:10,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:10,340 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:10,340 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:10,359 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:10,552 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:10,552 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr7REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:10,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:10,553 INFO L85 PathProgramCache]: Analyzing trace with hash 129968281, now seen corresponding path program 1 times [2022-11-18 21:11:10,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:10,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [879644513] [2022-11-18 21:11:10,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:10,553 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:10,553 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:10,555 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:10,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-18 21:11:10,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:10,653 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-18 21:11:10,653 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:10,704 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:10,704 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:10,705 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:10,705 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [879644513] [2022-11-18 21:11:10,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [879644513] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:10,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:10,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 21:11:10,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965563143] [2022-11-18 21:11:10,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:10,706 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 21:11:10,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:10,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 21:11:10,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-18 21:11:10,706 INFO L87 Difference]: Start difference. First operand 142 states and 359 transitions. Second operand has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:10,860 INFO L93 Difference]: Finished difference Result 112 states and 263 transitions. [2022-11-18 21:11:10,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:11:10,861 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:10,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:10,861 INFO L225 Difference]: With dead ends: 112 [2022-11-18 21:11:10,862 INFO L226 Difference]: Without dead ends: 112 [2022-11-18 21:11:10,862 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-18 21:11:10,862 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 41 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:10,863 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 2 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 22 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 21:11:10,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2022-11-18 21:11:10,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2022-11-18 21:11:10,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 97 states have (on average 2.711340206185567) internal successors, (263), 111 states have internal predecessors, (263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 263 transitions. [2022-11-18 21:11:10,876 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 263 transitions. Word has length 7 [2022-11-18 21:11:10,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:10,876 INFO L495 AbstractCegarLoop]: Abstraction has 112 states and 263 transitions. [2022-11-18 21:11:10,876 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:10,876 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 263 transitions. [2022-11-18 21:11:10,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:10,878 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:10,878 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:10,895 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:11,087 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:11,087 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:11,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:11,087 INFO L85 PathProgramCache]: Analyzing trace with hash 129749692, now seen corresponding path program 1 times [2022-11-18 21:11:11,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:11,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [766891308] [2022-11-18 21:11:11,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:11,088 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:11,088 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:11,089 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:11,090 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-18 21:11:11,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:11,185 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-18 21:11:11,187 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:11,272 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:11,273 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:11,482 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:11,482 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:12,462 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:12,463 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:12,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [766891308] [2022-11-18 21:11:12,463 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [766891308] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:12,463 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:12,463 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 6 [2022-11-18 21:11:12,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808853194] [2022-11-18 21:11:12,463 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:12,463 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 21:11:12,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:12,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:11:12,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:12,464 INFO L87 Difference]: Start difference. First operand 112 states and 263 transitions. Second operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:13,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:13,139 INFO L93 Difference]: Finished difference Result 201 states and 508 transitions. [2022-11-18 21:11:13,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:11:13,140 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:13,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:13,141 INFO L225 Difference]: With dead ends: 201 [2022-11-18 21:11:13,141 INFO L226 Difference]: Without dead ends: 201 [2022-11-18 21:11:13,142 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:11:13,142 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 77 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 77 SdHoareTripleChecker+Valid, 14 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 96 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:13,144 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [77 Valid, 14 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 56 Invalid, 0 Unknown, 96 Unchecked, 0.3s Time] [2022-11-18 21:11:13,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2022-11-18 21:11:13,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 159. [2022-11-18 21:11:13,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159 states, 144 states have (on average 2.888888888888889) internal successors, (416), 158 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:13,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 416 transitions. [2022-11-18 21:11:13,150 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 416 transitions. Word has length 7 [2022-11-18 21:11:13,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:13,150 INFO L495 AbstractCegarLoop]: Abstraction has 159 states and 416 transitions. [2022-11-18 21:11:13,151 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:13,151 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 416 transitions. [2022-11-18 21:11:13,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:13,151 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:13,151 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:13,169 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:13,363 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:13,363 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr5REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:13,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:13,363 INFO L85 PathProgramCache]: Analyzing trace with hash 129749645, now seen corresponding path program 1 times [2022-11-18 21:11:13,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:13,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1222859148] [2022-11-18 21:11:13,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:13,364 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:13,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:13,365 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:13,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-18 21:11:13,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:13,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 21:11:13,483 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:13,558 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:13,559 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:13,813 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:13,813 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:14,103 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:14,104 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:14,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1222859148] [2022-11-18 21:11:14,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1222859148] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:14,104 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:14,104 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 6 [2022-11-18 21:11:14,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091794153] [2022-11-18 21:11:14,104 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:14,105 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 21:11:14,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:14,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:11:14,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:14,105 INFO L87 Difference]: Start difference. First operand 159 states and 416 transitions. Second operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:14,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:14,486 INFO L93 Difference]: Finished difference Result 158 states and 412 transitions. [2022-11-18 21:11:14,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:11:14,487 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:14,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:14,488 INFO L225 Difference]: With dead ends: 158 [2022-11-18 21:11:14,489 INFO L226 Difference]: Without dead ends: 158 [2022-11-18 21:11:14,489 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2022-11-18 21:11:14,489 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 20 mSDsluCounter, 10 mSDsCounter, 0 mSdLazyCounter, 45 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 13 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 45 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 33 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:14,490 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 13 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 45 Invalid, 0 Unknown, 33 Unchecked, 0.3s Time] [2022-11-18 21:11:14,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2022-11-18 21:11:14,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 157. [2022-11-18 21:11:14,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 142 states have (on average 2.880281690140845) internal successors, (409), 156 states have internal predecessors, (409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:14,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 409 transitions. [2022-11-18 21:11:14,496 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 409 transitions. Word has length 7 [2022-11-18 21:11:14,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:14,496 INFO L495 AbstractCegarLoop]: Abstraction has 157 states and 409 transitions. [2022-11-18 21:11:14,497 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:14,497 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 409 transitions. [2022-11-18 21:11:14,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:14,497 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:14,497 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:14,513 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (16)] Ended with exit code 0 [2022-11-18 21:11:14,709 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:14,709 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr5REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:14,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:14,710 INFO L85 PathProgramCache]: Analyzing trace with hash 129747940, now seen corresponding path program 1 times [2022-11-18 21:11:14,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:14,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [598695799] [2022-11-18 21:11:14,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:14,710 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:14,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:14,711 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:14,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (17)] Waiting until timeout for monitored process [2022-11-18 21:11:14,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:14,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 21:11:14,806 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:14,889 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:14,890 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:15,180 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:15,180 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:15,465 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:15,465 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:15,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [598695799] [2022-11-18 21:11:15,465 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [598695799] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:15,466 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:15,466 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 6 [2022-11-18 21:11:15,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1607729527] [2022-11-18 21:11:15,466 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:15,466 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-18 21:11:15,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:15,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-18 21:11:15,467 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-18 21:11:15,467 INFO L87 Difference]: Start difference. First operand 157 states and 409 transitions. Second operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:15,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:15,852 INFO L93 Difference]: Finished difference Result 160 states and 414 transitions. [2022-11-18 21:11:15,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:11:15,853 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:15,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:15,854 INFO L225 Difference]: With dead ends: 160 [2022-11-18 21:11:15,854 INFO L226 Difference]: Without dead ends: 160 [2022-11-18 21:11:15,855 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2022-11-18 21:11:15,855 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 20 mSDsluCounter, 10 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 13 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 33 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:15,856 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 13 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 44 Invalid, 0 Unknown, 33 Unchecked, 0.3s Time] [2022-11-18 21:11:15,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2022-11-18 21:11:15,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 160. [2022-11-18 21:11:15,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 145 states have (on average 2.8551724137931034) internal successors, (414), 159 states have internal predecessors, (414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:15,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 414 transitions. [2022-11-18 21:11:15,861 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 414 transitions. Word has length 7 [2022-11-18 21:11:15,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:15,862 INFO L495 AbstractCegarLoop]: Abstraction has 160 states and 414 transitions. [2022-11-18 21:11:15,862 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:15,862 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 414 transitions. [2022-11-18 21:11:15,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-18 21:11:15,863 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:15,863 INFO L195 NwaCegarLoop]: trace histogram [3, 1, 1, 1, 1] [2022-11-18 21:11:15,879 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (17)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:16,074 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:16,075 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr5REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:16,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:16,075 INFO L85 PathProgramCache]: Analyzing trace with hash 123178916, now seen corresponding path program 2 times [2022-11-18 21:11:16,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:16,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1795157019] [2022-11-18 21:11:16,076 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:11:16,076 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:16,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:16,077 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:16,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (18)] Waiting until timeout for monitored process [2022-11-18 21:11:16,164 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-11-18 21:11:16,164 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:11:16,167 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:11:16,169 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:16,184 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:11:16,185 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:11:16,209 INFO L321 Elim1Store]: treesize reduction 11, result has 45.0 percent of original size [2022-11-18 21:11:16,209 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 12 treesize of output 20 [2022-11-18 21:11:16,216 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2022-11-18 21:11:16,258 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-18 21:11:16,258 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:16,258 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:16,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1795157019] [2022-11-18 21:11:16,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1795157019] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:16,258 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:16,258 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-11-18 21:11:16,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790484050] [2022-11-18 21:11:16,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:16,259 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-11-18 21:11:16,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:16,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-18 21:11:16,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:16,260 INFO L87 Difference]: Start difference. First operand 160 states and 414 transitions. Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:16,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:16,399 INFO L93 Difference]: Finished difference Result 147 states and 385 transitions. [2022-11-18 21:11:16,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-18 21:11:16,400 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-11-18 21:11:16,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:16,400 INFO L225 Difference]: With dead ends: 147 [2022-11-18 21:11:16,400 INFO L226 Difference]: Without dead ends: 147 [2022-11-18 21:11:16,400 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-18 21:11:16,401 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 18 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 21 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:16,401 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 2 Invalid, 21 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-18 21:11:16,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2022-11-18 21:11:16,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 144. [2022-11-18 21:11:16,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144 states, 135 states have (on average 2.814814814814815) internal successors, (380), 143 states have internal predecessors, (380), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:16,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 380 transitions. [2022-11-18 21:11:16,406 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 380 transitions. Word has length 7 [2022-11-18 21:11:16,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:16,407 INFO L495 AbstractCegarLoop]: Abstraction has 144 states and 380 transitions. [2022-11-18 21:11:16,407 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:16,407 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 380 transitions. [2022-11-18 21:11:16,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-18 21:11:16,412 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:16,413 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:16,431 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (18)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:16,621 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:16,621 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting thread2Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:16,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:16,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1680239751, now seen corresponding path program 1 times [2022-11-18 21:11:16,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:16,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [786989648] [2022-11-18 21:11:16,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:16,622 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:16,622 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:16,623 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:16,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-18 21:11:16,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:16,728 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-18 21:11:16,729 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:16,866 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:16,866 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:17,081 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 31 [2022-11-18 21:11:17,304 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:17,304 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:17,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [786989648] [2022-11-18 21:11:17,305 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [786989648] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:17,305 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:17,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 8 [2022-11-18 21:11:17,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511907657] [2022-11-18 21:11:17,307 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:17,307 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:11:17,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:17,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:11:17,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:11:17,308 INFO L87 Difference]: Start difference. First operand 144 states and 380 transitions. Second operand has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:18,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:18,760 INFO L93 Difference]: Finished difference Result 215 states and 626 transitions. [2022-11-18 21:11:18,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 21:11:18,761 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-18 21:11:18,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:18,762 INFO L225 Difference]: With dead ends: 215 [2022-11-18 21:11:18,762 INFO L226 Difference]: Without dead ends: 215 [2022-11-18 21:11:18,763 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=82, Invalid=224, Unknown=0, NotChecked=0, Total=306 [2022-11-18 21:11:18,763 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 132 mSDsluCounter, 16 mSDsCounter, 0 mSdLazyCounter, 192 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 132 SdHoareTripleChecker+Valid, 20 SdHoareTripleChecker+Invalid, 199 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 192 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:18,763 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [132 Valid, 20 Invalid, 199 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 192 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-11-18 21:11:18,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2022-11-18 21:11:18,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 162. [2022-11-18 21:11:18,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 153 states have (on average 3.045751633986928) internal successors, (466), 161 states have internal predecessors, (466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:18,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 466 transitions. [2022-11-18 21:11:18,769 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 466 transitions. Word has length 9 [2022-11-18 21:11:18,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:18,769 INFO L495 AbstractCegarLoop]: Abstraction has 162 states and 466 transitions. [2022-11-18 21:11:18,769 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:18,769 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 466 transitions. [2022-11-18 21:11:18,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-18 21:11:18,770 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:18,770 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:18,787 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:18,982 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:18,982 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting thread2Err3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:18,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:18,983 INFO L85 PathProgramCache]: Analyzing trace with hash -1680239738, now seen corresponding path program 1 times [2022-11-18 21:11:18,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:18,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1778514966] [2022-11-18 21:11:18,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:18,983 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:18,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:18,984 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:18,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (20)] Waiting until timeout for monitored process [2022-11-18 21:11:19,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:19,112 INFO L263 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-18 21:11:19,114 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:19,209 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:19,210 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:19,445 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:19,446 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:20,959 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:20,959 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:20,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1778514966] [2022-11-18 21:11:20,960 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1778514966] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:20,960 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:20,960 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 8 [2022-11-18 21:11:20,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971510243] [2022-11-18 21:11:20,960 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:20,960 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:11:20,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:20,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:11:20,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:11:20,961 INFO L87 Difference]: Start difference. First operand 162 states and 466 transitions. Second operand has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:23,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:23,666 INFO L93 Difference]: Finished difference Result 177 states and 511 transitions. [2022-11-18 21:11:23,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 21:11:23,667 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-18 21:11:23,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:23,668 INFO L225 Difference]: With dead ends: 177 [2022-11-18 21:11:23,669 INFO L226 Difference]: Without dead ends: 177 [2022-11-18 21:11:23,669 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2022-11-18 21:11:23,670 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 11 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11 SdHoareTripleChecker+Valid, 26 SdHoareTripleChecker+Invalid, 101 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:23,670 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [11 Valid, 26 Invalid, 101 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 51 Invalid, 0 Unknown, 50 Unchecked, 0.2s Time] [2022-11-18 21:11:23,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2022-11-18 21:11:23,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 171. [2022-11-18 21:11:23,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 162 states have (on average 3.0308641975308643) internal successors, (491), 170 states have internal predecessors, (491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:23,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 491 transitions. [2022-11-18 21:11:23,676 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 491 transitions. Word has length 9 [2022-11-18 21:11:23,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:23,677 INFO L495 AbstractCegarLoop]: Abstraction has 171 states and 491 transitions. [2022-11-18 21:11:23,677 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:23,677 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 491 transitions. [2022-11-18 21:11:23,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-18 21:11:23,678 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:23,678 INFO L195 NwaCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:23,691 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (20)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:23,890 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:23,890 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:23,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:23,891 INFO L85 PathProgramCache]: Analyzing trace with hash -1884346276, now seen corresponding path program 2 times [2022-11-18 21:11:23,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:23,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1042864948] [2022-11-18 21:11:23,891 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:11:23,891 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:23,892 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:23,892 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:23,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (21)] Waiting until timeout for monitored process [2022-11-18 21:11:23,998 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-11-18 21:11:23,998 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:11:24,001 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-18 21:11:24,003 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:24,095 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:24,095 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:24,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-18 21:11:24,237 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:24,237 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:24,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1042864948] [2022-11-18 21:11:24,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1042864948] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:24,237 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:24,237 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-18 21:11:24,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [441772453] [2022-11-18 21:11:24,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:24,238 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-18 21:11:24,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:24,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-18 21:11:24,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-18 21:11:24,239 INFO L87 Difference]: Start difference. First operand 171 states and 491 transitions. Second operand has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:24,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:24,456 INFO L93 Difference]: Finished difference Result 125 states and 338 transitions. [2022-11-18 21:11:24,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-18 21:11:24,457 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-18 21:11:24,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:24,458 INFO L225 Difference]: With dead ends: 125 [2022-11-18 21:11:24,458 INFO L226 Difference]: Without dead ends: 125 [2022-11-18 21:11:24,458 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:11:24,459 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 27 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:24,459 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 2 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-18 21:11:24,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2022-11-18 21:11:24,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 46. [2022-11-18 21:11:24,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 44 states have (on average 2.159090909090909) internal successors, (95), 45 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:24,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 95 transitions. [2022-11-18 21:11:24,462 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 95 transitions. Word has length 9 [2022-11-18 21:11:24,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:24,462 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 95 transitions. [2022-11-18 21:11:24,462 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:24,462 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 95 transitions. [2022-11-18 21:11:24,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-11-18 21:11:24,463 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:24,463 INFO L195 NwaCegarLoop]: trace histogram [10, 1, 1] [2022-11-18 21:11:24,479 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (21)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:24,664 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:24,664 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:24,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:24,664 INFO L85 PathProgramCache]: Analyzing trace with hash 271037206, now seen corresponding path program 3 times [2022-11-18 21:11:24,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:24,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [628152300] [2022-11-18 21:11:24,665 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:11:24,665 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:24,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:24,666 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:24,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (22)] Waiting until timeout for monitored process [2022-11-18 21:11:24,860 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-18 21:11:24,860 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:11:24,868 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-18 21:11:24,870 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:24,946 INFO L321 Elim1Store]: treesize reduction 37, result has 37.3 percent of original size [2022-11-18 21:11:24,946 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 14 treesize of output 29 [2022-11-18 21:11:25,497 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:25,498 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:11:28,980 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:11:28,980 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:28,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [628152300] [2022-11-18 21:11:28,980 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [628152300] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:11:28,980 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:11:28,980 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 22 [2022-11-18 21:11:28,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156467997] [2022-11-18 21:11:28,981 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:11:28,981 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2022-11-18 21:11:28,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:28,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-18 21:11:28,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2022-11-18 21:11:28,982 INFO L87 Difference]: Start difference. First operand 46 states and 95 transitions. Second operand has 24 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:50,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:50,536 INFO L93 Difference]: Finished difference Result 718 states and 1559 transitions. [2022-11-18 21:11:50,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-18 21:11:50,543 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-11-18 21:11:50,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:50,545 INFO L225 Difference]: With dead ends: 718 [2022-11-18 21:11:50,545 INFO L226 Difference]: Without dead ends: 718 [2022-11-18 21:11:50,546 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 17.6s TimeCoverageRelationStatistics Valid=406, Invalid=716, Unknown=0, NotChecked=0, Total=1122 [2022-11-18 21:11:50,547 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 1710 mSDsluCounter, 220 mSDsCounter, 0 mSdLazyCounter, 1717 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 6.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1710 SdHoareTripleChecker+Valid, 240 SdHoareTripleChecker+Invalid, 1739 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 1717 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:50,547 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1710 Valid, 240 Invalid, 1739 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [22 Valid, 1717 Invalid, 0 Unknown, 0 Unchecked, 7.2s Time] [2022-11-18 21:11:50,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states. [2022-11-18 21:11:50,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 58. [2022-11-18 21:11:50,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 56 states have (on average 2.125) internal successors, (119), 57 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:50,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 119 transitions. [2022-11-18 21:11:50,555 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 119 transitions. Word has length 12 [2022-11-18 21:11:50,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:50,555 INFO L495 AbstractCegarLoop]: Abstraction has 58 states and 119 transitions. [2022-11-18 21:11:50,555 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:50,555 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 119 transitions. [2022-11-18 21:11:50,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-18 21:11:50,556 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:50,556 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:50,575 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (22)] Forceful destruction successful, exit code 0 [2022-11-18 21:11:50,769 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:50,769 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:50,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:50,769 INFO L85 PathProgramCache]: Analyzing trace with hash 713463347, now seen corresponding path program 1 times [2022-11-18 21:11:50,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:50,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1875185630] [2022-11-18 21:11:50,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:11:50,770 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:50,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:50,772 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:50,776 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (23)] Waiting until timeout for monitored process [2022-11-18 21:11:50,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:11:50,910 INFO L263 TraceCheckSpWp]: Trace formula consists of 109 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:11:50,911 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:51,026 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 9 [2022-11-18 21:11:58,330 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:11:58,331 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:11:58,331 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:11:58,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1875185630] [2022-11-18 21:11:58,331 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1875185630] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:11:58,331 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:11:58,331 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 21:11:58,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382848688] [2022-11-18 21:11:58,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:11:58,332 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 21:11:58,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:11:58,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 21:11:58,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:11:58,333 INFO L87 Difference]: Start difference. First operand 58 states and 119 transitions. Second operand has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:58,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:11:58,512 INFO L93 Difference]: Finished difference Result 92 states and 190 transitions. [2022-11-18 21:11:58,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 21:11:58,513 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-18 21:11:58,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:11:58,513 INFO L225 Difference]: With dead ends: 92 [2022-11-18 21:11:58,514 INFO L226 Difference]: Without dead ends: 87 [2022-11-18 21:11:58,514 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2022-11-18 21:11:58,517 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 27 mSDsluCounter, 4 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 7 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 45 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:11:58,517 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 7 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 45 Unchecked, 0.2s Time] [2022-11-18 21:11:58,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2022-11-18 21:11:58,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 64. [2022-11-18 21:11:58,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 62 states have (on average 2.129032258064516) internal successors, (132), 63 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:58,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 132 transitions. [2022-11-18 21:11:58,520 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 132 transitions. Word has length 15 [2022-11-18 21:11:58,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:11:58,521 INFO L495 AbstractCegarLoop]: Abstraction has 64 states and 132 transitions. [2022-11-18 21:11:58,521 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:11:58,521 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 132 transitions. [2022-11-18 21:11:58,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-18 21:11:58,522 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:11:58,522 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:11:58,532 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (23)] Ended with exit code 0 [2022-11-18 21:11:58,722 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:58,722 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:11:58,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:11:58,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1828076129, now seen corresponding path program 2 times [2022-11-18 21:11:58,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:11:58,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [171448000] [2022-11-18 21:11:58,723 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:11:58,723 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:11:58,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:11:58,724 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:11:58,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (24)] Waiting until timeout for monitored process [2022-11-18 21:11:58,817 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-11-18 21:11:58,817 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:11:58,821 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:11:58,822 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:11:58,930 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 9 [2022-11-18 21:12:03,033 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:03,033 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:12:03,033 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:03,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [171448000] [2022-11-18 21:12:03,034 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [171448000] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:12:03,034 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:12:03,034 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 21:12:03,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380572151] [2022-11-18 21:12:03,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:12:03,035 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 21:12:03,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:03,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 21:12:03,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:12:03,035 INFO L87 Difference]: Start difference. First operand 64 states and 132 transitions. Second operand has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:03,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:03,236 INFO L93 Difference]: Finished difference Result 92 states and 188 transitions. [2022-11-18 21:12:03,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 21:12:03,237 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-18 21:12:03,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:03,237 INFO L225 Difference]: With dead ends: 92 [2022-11-18 21:12:03,238 INFO L226 Difference]: Without dead ends: 87 [2022-11-18 21:12:03,238 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:12:03,238 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 15 mSDsluCounter, 4 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 7 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 35 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:03,239 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 7 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 35 Unchecked, 0.2s Time] [2022-11-18 21:12:03,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2022-11-18 21:12:03,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 70. [2022-11-18 21:12:03,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 68 states have (on average 2.264705882352941) internal successors, (154), 69 states have internal predecessors, (154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:03,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 154 transitions. [2022-11-18 21:12:03,242 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 154 transitions. Word has length 15 [2022-11-18 21:12:03,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:03,243 INFO L495 AbstractCegarLoop]: Abstraction has 70 states and 154 transitions. [2022-11-18 21:12:03,243 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:03,243 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 154 transitions. [2022-11-18 21:12:03,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-11-18 21:12:03,243 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:03,244 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:03,259 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (24)] Forceful destruction successful, exit code 0 [2022-11-18 21:12:03,455 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:03,455 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:03,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:03,456 INFO L85 PathProgramCache]: Analyzing trace with hash 416674547, now seen corresponding path program 3 times [2022-11-18 21:12:03,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:03,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2111149048] [2022-11-18 21:12:03,456 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:12:03,456 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:03,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:03,457 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:03,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (25)] Waiting until timeout for monitored process [2022-11-18 21:12:03,560 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2022-11-18 21:12:03,560 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:03,564 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:12:03,565 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:03,687 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 21:12:03,687 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 114 treesize of output 92 [2022-11-18 21:12:03,693 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 90 [2022-11-18 21:12:03,699 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 88 [2022-11-18 21:12:03,734 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:03,734 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-18 21:12:03,734 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:03,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2111149048] [2022-11-18 21:12:03,735 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2111149048] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-18 21:12:03,735 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-18 21:12:03,735 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-18 21:12:03,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406953253] [2022-11-18 21:12:03,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:12:03,736 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-18 21:12:03,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:03,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-18 21:12:03,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-18 21:12:03,737 INFO L87 Difference]: Start difference. First operand 70 states and 154 transitions. Second operand has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:04,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:04,021 INFO L93 Difference]: Finished difference Result 85 states and 178 transitions. [2022-11-18 21:12:04,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-18 21:12:04,022 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-11-18 21:12:04,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:04,022 INFO L225 Difference]: With dead ends: 85 [2022-11-18 21:12:04,023 INFO L226 Difference]: Without dead ends: 80 [2022-11-18 21:12:04,023 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2022-11-18 21:12:04,023 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 18 mSDsluCounter, 6 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 10 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:04,024 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 10 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-18 21:12:04,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2022-11-18 21:12:04,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2022-11-18 21:12:04,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 78 states have (on average 2.1794871794871793) internal successors, (170), 79 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:04,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 170 transitions. [2022-11-18 21:12:04,027 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 170 transitions. Word has length 15 [2022-11-18 21:12:04,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:04,028 INFO L495 AbstractCegarLoop]: Abstraction has 80 states and 170 transitions. [2022-11-18 21:12:04,028 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:04,028 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 170 transitions. [2022-11-18 21:12:04,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:04,029 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:04,029 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:04,041 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (25)] Ended with exit code 0 [2022-11-18 21:12:04,241 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:04,241 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:04,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:04,241 INFO L85 PathProgramCache]: Analyzing trace with hash -1946875860, now seen corresponding path program 1 times [2022-11-18 21:12:04,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:04,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [498152292] [2022-11-18 21:12:04,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:12:04,242 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:04,242 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:04,243 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:04,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (26)] Waiting until timeout for monitored process [2022-11-18 21:12:04,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:12:04,382 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-18 21:12:04,384 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:04,485 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-11-18 21:12:04,516 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-11-18 21:12:04,605 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 21:12:04,605 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 63 treesize of output 19 [2022-11-18 21:12:04,668 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:04,668 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:07,123 INFO L321 Elim1Store]: treesize reduction 168, result has 22.6 percent of original size [2022-11-18 21:12:07,124 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 221 treesize of output 199 [2022-11-18 21:12:07,136 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 139 [2022-11-18 21:12:07,150 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 139 treesize of output 137 [2022-11-18 21:12:09,258 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:09,258 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:09,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [498152292] [2022-11-18 21:12:09,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [498152292] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:09,258 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:09,258 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 8 [2022-11-18 21:12:09,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411500094] [2022-11-18 21:12:09,259 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:09,259 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:12:09,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:09,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:12:09,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=59, Unknown=1, NotChecked=0, Total=90 [2022-11-18 21:12:09,260 INFO L87 Difference]: Start difference. First operand 80 states and 170 transitions. Second operand has 10 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:11,482 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:12:11,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:11,547 INFO L93 Difference]: Finished difference Result 92 states and 184 transitions. [2022-11-18 21:12:11,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-18 21:12:11,549 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:11,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:11,549 INFO L225 Difference]: With dead ends: 92 [2022-11-18 21:12:11,549 INFO L226 Difference]: Without dead ends: 83 [2022-11-18 21:12:11,550 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=30, Invalid=59, Unknown=1, NotChecked=0, Total=90 [2022-11-18 21:12:11,550 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 20 mSDsluCounter, 11 mSDsCounter, 0 mSdLazyCounter, 80 mSolverCounterSat, 0 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 15 SdHoareTripleChecker+Invalid, 103 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 80 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:11,550 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 15 Invalid, 103 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 80 Invalid, 1 Unknown, 22 Unchecked, 2.3s Time] [2022-11-18 21:12:11,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2022-11-18 21:12:11,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2022-11-18 21:12:11,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 80 states have (on average 2.1625) internal successors, (173), 81 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:11,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 173 transitions. [2022-11-18 21:12:11,554 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 173 transitions. Word has length 16 [2022-11-18 21:12:11,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:11,554 INFO L495 AbstractCegarLoop]: Abstraction has 82 states and 173 transitions. [2022-11-18 21:12:11,555 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:11,555 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 173 transitions. [2022-11-18 21:12:11,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:11,555 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:11,555 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:11,572 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (26)] Forceful destruction successful, exit code 0 [2022-11-18 21:12:11,767 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:11,768 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:11,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:11,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1731032122, now seen corresponding path program 2 times [2022-11-18 21:12:11,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:11,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [544219213] [2022-11-18 21:12:11,769 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:12:11,769 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:11,769 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:11,770 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:11,771 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-18 21:12:11,915 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:12:11,915 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:11,920 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 21:12:11,922 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:12,129 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 19 [2022-11-18 21:12:12,233 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:12,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:14,377 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:12:14,387 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:12:15,024 INFO L321 Elim1Store]: treesize reduction 168, result has 22.6 percent of original size [2022-11-18 21:12:15,024 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 169 treesize of output 113 [2022-11-18 21:12:18,405 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:18,406 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:18,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [544219213] [2022-11-18 21:12:18,406 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [544219213] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:18,406 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:18,406 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:12:18,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746492545] [2022-11-18 21:12:18,407 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:18,407 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:12:18,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:18,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:12:18,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=123, Unknown=1, NotChecked=0, Total=182 [2022-11-18 21:12:18,410 INFO L87 Difference]: Start difference. First operand 82 states and 173 transitions. Second operand has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:21,576 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:12:23,580 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:12:25,584 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:12:28,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:28,325 INFO L93 Difference]: Finished difference Result 140 states and 304 transitions. [2022-11-18 21:12:28,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:12:28,327 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:28,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:28,328 INFO L225 Difference]: With dead ends: 140 [2022-11-18 21:12:28,328 INFO L226 Difference]: Without dead ends: 130 [2022-11-18 21:12:28,328 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=82, Invalid=188, Unknown=2, NotChecked=0, Total=272 [2022-11-18 21:12:28,329 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 91 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 177 mSolverCounterSat, 8 mSolverCounterUnsat, 3 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 6.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 91 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 315 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 177 IncrementalHoareTripleChecker+Invalid, 3 IncrementalHoareTripleChecker+Unknown, 127 IncrementalHoareTripleChecker+Unchecked, 7.0s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:28,329 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [91 Valid, 12 Invalid, 315 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 177 Invalid, 3 Unknown, 127 Unchecked, 7.0s Time] [2022-11-18 21:12:28,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2022-11-18 21:12:28,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 88. [2022-11-18 21:12:28,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 86 states have (on average 2.3255813953488373) internal successors, (200), 87 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:28,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 200 transitions. [2022-11-18 21:12:28,334 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 200 transitions. Word has length 16 [2022-11-18 21:12:28,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:28,334 INFO L495 AbstractCegarLoop]: Abstraction has 88 states and 200 transitions. [2022-11-18 21:12:28,334 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:28,335 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 200 transitions. [2022-11-18 21:12:28,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:28,335 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:28,335 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:28,359 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-18 21:12:28,548 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:28,548 INFO L420 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:28,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:28,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1844683259, now seen corresponding path program 1 times [2022-11-18 21:12:28,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:28,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1412577815] [2022-11-18 21:12:28,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:12:28,549 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:28,549 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:28,550 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:28,552 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (28)] Waiting until timeout for monitored process [2022-11-18 21:12:28,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:12:28,680 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:12:28,681 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:28,792 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:28,792 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:29,002 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:29,002 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:29,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1412577815] [2022-11-18 21:12:29,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1412577815] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:29,003 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:29,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:12:29,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506241197] [2022-11-18 21:12:29,003 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:29,003 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:12:29,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:29,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:12:29,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:12:29,004 INFO L87 Difference]: Start difference. First operand 88 states and 200 transitions. Second operand has 10 states, 10 states have (on average 2.3) internal successors, (23), 10 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:29,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:29,609 INFO L93 Difference]: Finished difference Result 112 states and 257 transitions. [2022-11-18 21:12:29,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 21:12:29,611 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.3) internal successors, (23), 10 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:29,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:29,611 INFO L225 Difference]: With dead ends: 112 [2022-11-18 21:12:29,611 INFO L226 Difference]: Without dead ends: 112 [2022-11-18 21:12:29,612 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2022-11-18 21:12:29,612 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 37 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 146 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 11 SdHoareTripleChecker+Invalid, 185 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 146 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 36 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:29,613 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [37 Valid, 11 Invalid, 185 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 146 Invalid, 0 Unknown, 36 Unchecked, 0.5s Time] [2022-11-18 21:12:29,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2022-11-18 21:12:29,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 100. [2022-11-18 21:12:29,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 98 states have (on average 2.2551020408163267) internal successors, (221), 99 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:29,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 221 transitions. [2022-11-18 21:12:29,616 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 221 transitions. Word has length 16 [2022-11-18 21:12:29,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:29,617 INFO L495 AbstractCegarLoop]: Abstraction has 100 states and 221 transitions. [2022-11-18 21:12:29,617 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.3) internal successors, (23), 10 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:29,617 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 221 transitions. [2022-11-18 21:12:29,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:29,618 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:29,618 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:29,630 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (28)] Ended with exit code 0 [2022-11-18 21:12:29,830 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:29,830 INFO L420 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:29,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:29,831 INFO L85 PathProgramCache]: Analyzing trace with hash -2126388887, now seen corresponding path program 2 times [2022-11-18 21:12:29,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:29,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1123920232] [2022-11-18 21:12:29,831 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:12:29,831 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:29,832 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:29,833 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:29,867 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (29)] Waiting until timeout for monitored process [2022-11-18 21:12:30,007 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:12:30,007 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:30,012 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:12:30,013 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:30,091 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:30,091 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:30,329 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:30,330 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:30,330 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1123920232] [2022-11-18 21:12:30,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1123920232] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:30,330 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:30,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:12:30,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725831938] [2022-11-18 21:12:30,330 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:30,331 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:12:30,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:30,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:12:30,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:12:30,331 INFO L87 Difference]: Start difference. First operand 100 states and 221 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:30,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:30,836 INFO L93 Difference]: Finished difference Result 130 states and 309 transitions. [2022-11-18 21:12:30,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 21:12:30,837 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:30,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:30,838 INFO L225 Difference]: With dead ends: 130 [2022-11-18 21:12:30,838 INFO L226 Difference]: Without dead ends: 130 [2022-11-18 21:12:30,839 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2022-11-18 21:12:30,839 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 49 mSDsluCounter, 6 mSDsCounter, 0 mSdLazyCounter, 144 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 49 SdHoareTripleChecker+Valid, 9 SdHoareTripleChecker+Invalid, 233 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 144 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 88 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:30,839 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [49 Valid, 9 Invalid, 233 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 144 Invalid, 0 Unknown, 88 Unchecked, 0.4s Time] [2022-11-18 21:12:30,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2022-11-18 21:12:30,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 104. [2022-11-18 21:12:30,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 102 states have (on average 2.343137254901961) internal successors, (239), 103 states have internal predecessors, (239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:30,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 239 transitions. [2022-11-18 21:12:30,843 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 239 transitions. Word has length 16 [2022-11-18 21:12:30,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:30,843 INFO L495 AbstractCegarLoop]: Abstraction has 104 states and 239 transitions. [2022-11-18 21:12:30,844 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:30,844 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 239 transitions. [2022-11-18 21:12:30,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:30,844 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:30,845 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:30,856 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (29)] Ended with exit code 0 [2022-11-18 21:12:31,055 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:31,055 INFO L420 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:31,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:31,055 INFO L85 PathProgramCache]: Analyzing trace with hash -2098769019, now seen corresponding path program 3 times [2022-11-18 21:12:31,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:31,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1876440531] [2022-11-18 21:12:31,056 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:12:31,056 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:31,056 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:31,057 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:31,061 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (30)] Waiting until timeout for monitored process [2022-11-18 21:12:31,196 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 21:12:31,196 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:31,202 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:12:31,203 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:31,300 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:31,300 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:31,346 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 58 [2022-11-18 21:12:31,354 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 56 [2022-11-18 21:12:31,421 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:31,421 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:31,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1876440531] [2022-11-18 21:12:31,421 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1876440531] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:31,421 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:31,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:12:31,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747038907] [2022-11-18 21:12:31,422 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:31,422 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:12:31,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:31,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:12:31,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:12:31,423 INFO L87 Difference]: Start difference. First operand 104 states and 239 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:32,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:32,156 INFO L93 Difference]: Finished difference Result 188 states and 445 transitions. [2022-11-18 21:12:32,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:12:32,157 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:32,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:32,159 INFO L225 Difference]: With dead ends: 188 [2022-11-18 21:12:32,159 INFO L226 Difference]: Without dead ends: 188 [2022-11-18 21:12:32,159 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2022-11-18 21:12:32,160 INFO L413 NwaCegarLoop]: 6 mSDtfsCounter, 66 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 243 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 66 SdHoareTripleChecker+Valid, 23 SdHoareTripleChecker+Invalid, 289 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 243 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 44 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:32,160 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [66 Valid, 23 Invalid, 289 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 243 Invalid, 0 Unknown, 44 Unchecked, 0.7s Time] [2022-11-18 21:12:32,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2022-11-18 21:12:32,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 110. [2022-11-18 21:12:32,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 108 states have (on average 2.3703703703703702) internal successors, (256), 109 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:32,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 256 transitions. [2022-11-18 21:12:32,165 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 256 transitions. Word has length 16 [2022-11-18 21:12:32,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:32,165 INFO L495 AbstractCegarLoop]: Abstraction has 110 states and 256 transitions. [2022-11-18 21:12:32,165 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:32,165 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 256 transitions. [2022-11-18 21:12:32,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:32,166 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:32,166 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:32,176 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (30)] Forceful destruction successful, exit code 0 [2022-11-18 21:12:32,371 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:32,371 INFO L420 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:32,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:32,371 INFO L85 PathProgramCache]: Analyzing trace with hash -345341199, now seen corresponding path program 4 times [2022-11-18 21:12:32,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:32,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [482382091] [2022-11-18 21:12:32,372 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 21:12:32,372 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:32,372 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:32,373 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:32,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (31)] Waiting until timeout for monitored process [2022-11-18 21:12:32,534 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 21:12:32,534 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:32,539 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:12:32,540 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:32,644 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:32,644 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:32,681 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 58 [2022-11-18 21:12:32,686 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 56 [2022-11-18 21:12:32,843 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:12:32,843 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:12:32,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [482382091] [2022-11-18 21:12:32,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [482382091] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:12:32,844 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:12:32,844 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:12:32,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965383134] [2022-11-18 21:12:32,844 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:12:32,844 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:12:32,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:12:32,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:12:32,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:12:32,845 INFO L87 Difference]: Start difference. First operand 110 states and 256 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:33,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:12:33,406 INFO L93 Difference]: Finished difference Result 172 states and 405 transitions. [2022-11-18 21:12:33,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 21:12:33,407 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:12:33,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:12:33,408 INFO L225 Difference]: With dead ends: 172 [2022-11-18 21:12:33,408 INFO L226 Difference]: Without dead ends: 172 [2022-11-18 21:12:33,408 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2022-11-18 21:12:33,409 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 48 mSDsluCounter, 9 mSDsCounter, 0 mSdLazyCounter, 191 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 48 SdHoareTripleChecker+Valid, 13 SdHoareTripleChecker+Invalid, 351 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 191 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 160 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-18 21:12:33,409 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [48 Valid, 13 Invalid, 351 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 191 Invalid, 0 Unknown, 160 Unchecked, 0.5s Time] [2022-11-18 21:12:33,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2022-11-18 21:12:33,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 110. [2022-11-18 21:12:33,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 108 states have (on average 2.3703703703703702) internal successors, (256), 109 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:33,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 256 transitions. [2022-11-18 21:12:33,413 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 256 transitions. Word has length 16 [2022-11-18 21:12:33,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:12:33,413 INFO L495 AbstractCegarLoop]: Abstraction has 110 states and 256 transitions. [2022-11-18 21:12:33,414 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 10 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:12:33,414 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 256 transitions. [2022-11-18 21:12:33,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:12:33,414 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:12:33,415 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:12:33,431 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (31)] Forceful destruction successful, exit code 0 [2022-11-18 21:12:33,627 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:33,627 INFO L420 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:12:33,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:12:33,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1899409477, now seen corresponding path program 5 times [2022-11-18 21:12:33,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:12:33,628 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [325175160] [2022-11-18 21:12:33,628 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 21:12:33,628 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:12:33,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:12:33,629 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:12:33,630 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (32)] Waiting until timeout for monitored process [2022-11-18 21:12:33,786 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:12:33,786 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:12:33,791 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-18 21:12:33,793 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:12:34,610 INFO L321 Elim1Store]: treesize reduction 456, result has 5.2 percent of original size [2022-11-18 21:12:34,611 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 12 select indices, 12 select index equivalence classes, 6 disjoint index pairs (out of 66 index pairs), introduced 20 new quantified variables, introduced 66 case distinctions, treesize of input 1681 treesize of output 303 [2022-11-18 21:12:34,632 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:12:34,639 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:12:34,730 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:12:34,730 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:12:34,822 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:12:34,828 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:12:37,023 INFO L321 Elim1Store]: treesize reduction 498, result has 21.3 percent of original size [2022-11-18 21:12:37,025 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 12 select indices, 12 select index equivalence classes, 0 disjoint index pairs (out of 66 index pairs), introduced 20 new quantified variables, introduced 66 case distinctions, treesize of input 2006 treesize of output 338 [2022-11-18 21:13:05,581 WARN L859 $PredicateComparison]: unable to prove that (or (not (bvsge c_~x2~0 (_ bv0 32))) (let ((.cse4 (bvmul c_~x2~0 (_ bv4 32)))) (let ((.cse154 (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse321 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse321 c_~size~0)) (not (bvsge .cse321 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse321) .cse4)))))) (and (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse3 (bvmul (_ bv4 32) .cse0))) (or (not (bvslt .cse0 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse2 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse1 (bvmul .cse2 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse1) (bvadd c_~f~0.offset (_ bv4 32) .cse1))) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse2 c_~size~0)) (= .cse3 .cse1) (not (bvsge .cse2 (_ bv0 32))) (= .cse4 .cse1))))) (not (bvsge .cse0 (_ bv0 32))) (= .cse3 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse5 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse5 c_~size~0)) (not (bvsge .cse5 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse5) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse6 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse9 (bvmul (_ bv4 32) .cse6))) (or (not (bvslt .cse6 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse8 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse7 (bvmul (_ bv4 32) .cse8))) (or (not (bvule (bvadd c_~f~0.offset .cse7) (bvadd c_~f~0.offset (_ bv4 32) .cse7))) (not (bvslt .cse8 c_~size~0)) (= .cse9 .cse7))))) (not (bvsge .cse6 (_ bv0 32))) (= .cse9 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse13 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse10 (concat (concat .cse13 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse10 c_~size~0)) (not (bvsge .cse10 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse10) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse12 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse11 (bvmul .cse12 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse11) (bvadd c_~f~0.offset (_ bv4 32) .cse11))) (not (bvslt .cse12 c_~size~0)) (not (bvsge .cse12 (_ bv0 32))) (= .cse4 .cse11) (= c_~x1~0 (concat (concat .cse13 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse14 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse15 (bvmul (_ bv4 32) .cse14))) (or (not (bvslt .cse14 c_~size~0)) (not (bvsge .cse14 (_ bv0 32))) (= .cse15 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse17 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse16 (bvmul .cse17 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse16) (bvadd c_~f~0.offset (_ bv4 32) .cse16))) (not (bvslt .cse17 c_~size~0)) (= .cse15 .cse16) (not (bvsge .cse17 (_ bv0 32))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse18 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse21 (bvmul (_ bv4 32) .cse18))) (or (not (bvslt .cse18 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse20 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse19 (bvmul (_ bv4 32) .cse20))) (or (not (bvule (bvadd c_~f~0.offset .cse19) (bvadd c_~f~0.offset (_ bv4 32) .cse19))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse20 c_~size~0)) (= .cse21 .cse19) (= .cse19 .cse4))))) (not (bvsge .cse18 (_ bv0 32))) (= .cse21 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse24 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse22 (concat (concat .cse24 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse22 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse23 (concat (concat .cse24 v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse4 (bvmul (_ bv4 32) .cse23)) (= c_~x1~0 .cse23)))) (not (bvsge .cse22 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse22) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse25 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse25 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse25 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse25) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse27 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse26 (concat (concat .cse27 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse26 c_~size~0)) (not (bvsge .cse26 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse26) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse27 v_arrayElimCell_81) v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse31 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse28 (concat (concat .cse31 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse28 c_~size~0)) (not (bvsge .cse28 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse28) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse29 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse30 (bvmul (_ bv4 32) .cse29))) (or (not (bvslt .cse29 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse30) (bvadd c_~f~0.offset (_ bv4 32) .cse30))) (not (bvsge .cse29 (_ bv0 32))) (= .cse4 .cse30) (= c_~x1~0 (concat (concat .cse31 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse33 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse32 (concat .cse33 v_arrayElimCell_78))) (or (not (bvslt .cse32 c_~size~0)) (not (bvsge .cse32 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse32) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (= c_~x1~0 (concat .cse33 v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse34 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse34 c_~size~0)) (not (bvsge .cse34 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse35 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse35 c_~x1~0) (= .cse4 (bvmul .cse35 (_ bv4 32)))))) (= (bvmul (_ bv4 32) .cse34) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse40 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse36 (concat (concat .cse40 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse39 (bvmul (_ bv4 32) .cse36))) (or (not (bvslt .cse36 c_~size~0)) (not (bvsge .cse36 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse38 (concat (concat .cse40 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse37 (bvmul (_ bv4 32) .cse38))) (or (not (bvule (bvadd c_~f~0.offset .cse37) (bvadd c_~f~0.offset (_ bv4 32) .cse37))) (= .cse4 .cse37) (not (bvslt .cse38 c_~size~0)) (= .cse39 .cse37))))) (= .cse39 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse45 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse41 (concat (concat .cse45 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse43 (bvmul (_ bv4 32) .cse41))) (or (not (bvslt .cse41 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse42 (concat (concat .cse45 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse44 (bvmul (_ bv4 32) .cse42))) (or (not (bvslt .cse42 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse43 .cse44) (= .cse4 .cse44) (not (bvule (bvadd c_~f~0.offset .cse44) (bvadd c_~f~0.offset (_ bv4 32) .cse44))))))) (not (bvsge .cse41 (_ bv0 32))) (= .cse43 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse50 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse46 (concat (concat .cse50 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse47 (bvmul (_ bv4 32) .cse46))) (or (not (bvslt .cse46 c_~size~0)) (not (bvsge .cse46 (_ bv0 32))) (= .cse47 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse48 (concat (concat .cse50 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse49 (bvmul (_ bv4 32) .cse48))) (or (not (bvslt .cse48 c_~size~0)) (= .cse47 .cse49) (= .cse4 .cse49) (not (bvule (bvadd c_~f~0.offset .cse49) (bvadd c_~f~0.offset (_ bv4 32) .cse49)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse56 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse51 (concat (concat .cse56 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse53 (bvmul (_ bv4 32) .cse51))) (or (not (bvslt .cse51 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse55 (concat .cse56 v_arrayElimCell_81))) (let ((.cse52 (concat .cse55 v_arrayElimCell_70))) (let ((.cse54 (bvmul (_ bv4 32) .cse52))) (or (not (bvslt .cse52 c_~size~0)) (= .cse53 .cse54) (= .cse4 .cse54) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat .cse55 v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse54) (bvadd c_~f~0.offset (_ bv4 32) .cse54)))))))) (not (bvsge .cse51 (_ bv0 32))) (= .cse53 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse61 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse57 (concat (concat .cse61 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse59 (bvmul (_ bv4 32) .cse57))) (or (not (bvslt .cse57 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse58 (concat (concat .cse61 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse60 (bvmul (_ bv4 32) .cse58))) (or (not (bvslt .cse58 c_~size~0)) (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse59 .cse60) (= .cse4 .cse60) (not (bvule (bvadd c_~f~0.offset .cse60) (bvadd c_~f~0.offset (_ bv4 32) .cse60))))))) (not (bvsge .cse57 (_ bv0 32))) (= .cse59 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse66 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse62 (concat (concat .cse66 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse64 (bvmul (_ bv4 32) .cse62))) (or (not (bvslt .cse62 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse63 (concat (concat .cse66 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse65 (bvmul (_ bv4 32) .cse63))) (or (not (bvslt .cse63 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse64 .cse65) (= .cse4 .cse65) (not (bvule (bvadd c_~f~0.offset .cse65) (bvadd c_~f~0.offset (_ bv4 32) .cse65))))))) (not (bvsge .cse62 (_ bv0 32))) (= .cse64 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse67 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse68 (bvmul (_ bv4 32) .cse67))) (or (not (bvslt .cse67 c_~size~0)) (not (bvsge .cse67 (_ bv0 32))) (= .cse68 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse70 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse69 (bvmul (_ bv4 32) .cse70))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse69) (bvadd c_~f~0.offset (_ bv4 32) .cse69))) (not (bvslt .cse70 c_~size~0)) (= .cse68 .cse69) (= .cse69 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse71 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse74 (bvmul (_ bv4 32) .cse71))) (or (not (bvslt .cse71 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse72 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse73 (bvmul (_ bv4 32) .cse72))) (or (not (bvsge .cse72 (_ bv0 32))) (= .cse73 .cse4) (not (bvule (bvadd c_~f~0.offset .cse73) (bvadd c_~f~0.offset .cse73 (_ bv4 32)))) (not (bvslt .cse72 c_~size~0)) (= .cse74 .cse73))))) (not (bvsge .cse71 (_ bv0 32))) (= .cse74 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse75 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse78 (bvmul (_ bv4 32) .cse75))) (or (not (bvslt .cse75 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse76 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse77 (bvmul (_ bv4 32) .cse76))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse76 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse77) (bvadd c_~f~0.offset (_ bv4 32) .cse77))) (not (bvsge .cse76 (_ bv0 32))) (= .cse4 .cse77) (= .cse78 .cse77))))) (not (bvsge .cse75 (_ bv0 32))) (= .cse78 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse79 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse79 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse79 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse79) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse80 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse80 c_~size~0)) (not (bvsge .cse80 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse80) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse81 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse84 (bvmul (_ bv4 32) .cse81))) (or (not (bvslt .cse81 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse83 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse82 (bvmul .cse83 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse82) (bvadd c_~f~0.offset (_ bv4 32) .cse82))) (not (bvslt .cse83 c_~size~0)) (= .cse84 .cse82) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvsge .cse83 (_ bv0 32))) (= .cse4 .cse82))))) (not (bvsge .cse81 (_ bv0 32))) (= .cse84 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse85 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse85 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse86 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= (bvmul (_ bv4 32) .cse86) .cse4) (= c_~x1~0 .cse86)))) (not (bvsge .cse85 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse85) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse87 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse87 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse87 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse87) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse88 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse91 (bvmul (_ bv4 32) .cse88))) (or (not (bvslt .cse88 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse90 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse89 (bvmul (_ bv4 32) .cse90))) (or (not (bvule (bvadd c_~f~0.offset .cse89) (bvadd c_~f~0.offset (_ bv4 32) .cse89))) (not (bvslt .cse90 c_~size~0)) (= .cse91 .cse89) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse89 .cse4))))) (not (bvsge .cse88 (_ bv0 32))) (= .cse91 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse92 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse95 (bvmul (_ bv4 32) .cse92))) (or (not (bvslt .cse92 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse93 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse94 (bvmul (_ bv4 32) .cse93))) (or (not (bvsge .cse93 (_ bv0 32))) (not (bvule (bvadd c_~f~0.offset .cse94) (bvadd c_~f~0.offset .cse94 (_ bv4 32)))) (not (bvslt .cse93 c_~size~0)) (= .cse95 .cse94))))) (not (bvsge .cse92 (_ bv0 32))) (= .cse95 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse96 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse99 (bvmul (_ bv4 32) .cse96))) (or (not (bvslt .cse96 c_~size~0)) (not (bvsge .cse96 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse98 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse97 (bvmul (_ bv4 32) .cse98))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse97) (bvadd c_~f~0.offset (_ bv4 32) .cse97))) (not (bvslt .cse98 c_~size~0)) (= .cse99 .cse97) (= .cse97 .cse4))))) (= .cse99 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse104 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse100 (concat (concat .cse104 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse101 (bvmul (_ bv4 32) .cse100))) (or (not (bvslt .cse100 c_~size~0)) (not (bvsge .cse100 (_ bv0 32))) (= .cse101 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse102 (concat (concat .cse104 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse103 (bvmul (_ bv4 32) .cse102))) (or (not (bvslt .cse102 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse101 .cse103) (= .cse4 .cse103) (not (bvule (bvadd c_~f~0.offset .cse103) (bvadd c_~f~0.offset (_ bv4 32) .cse103)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse105 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse105 c_~size~0)) (not (bvsge .cse105 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse105) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse106 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse106 c_~x1~0) (= .cse4 (bvmul .cse106 (_ bv4 32))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse111 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse107 (concat (concat .cse111 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse110 (bvmul (_ bv4 32) .cse107))) (or (not (bvslt .cse107 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse109 (concat (concat .cse111 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse108 (bvmul (_ bv4 32) .cse109))) (or (not (bvule (bvadd c_~f~0.offset .cse108) (bvadd c_~f~0.offset (_ bv4 32) .cse108))) (not (bvslt .cse109 c_~size~0)) (= .cse110 .cse108))))) (not (bvsge .cse107 (_ bv0 32))) (= .cse110 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse112 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse112 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse113 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= c_~x1~0 .cse113) (= .cse4 (bvmul (_ bv4 32) .cse113))))) (not (bvsge .cse112 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse112) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse114 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse118 (bvmul (_ bv4 32) .cse114))) (or (not (bvslt .cse114 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse115 (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse117 (concat .cse115 v_arrayElimCell_70))) (let ((.cse116 (bvmul (_ bv4 32) .cse117))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse115 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse116) (bvadd c_~f~0.offset (_ bv4 32) .cse116))) (not (bvslt .cse117 c_~size~0)) (= .cse118 .cse116) (= .cse116 .cse4)))))) (not (bvsge .cse114 (_ bv0 32))) (= .cse118 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse123 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse119 (concat (concat .cse123 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse121 (bvmul (_ bv4 32) .cse119))) (or (not (bvslt .cse119 c_~size~0)) (not (bvsge .cse119 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse120 (concat (concat .cse123 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse122 (bvmul (_ bv4 32) .cse120))) (or (not (bvslt .cse120 c_~size~0)) (= .cse121 .cse122) (not (bvule (bvadd c_~f~0.offset .cse122) (bvadd c_~f~0.offset (_ bv4 32) .cse122))))))) (= .cse121 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse124 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse127 (bvmul (_ bv4 32) .cse124))) (or (not (bvslt .cse124 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse125 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse126 (bvmul (_ bv4 32) .cse125))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse125 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse126) (bvadd c_~f~0.offset (_ bv4 32) .cse126))) (not (bvsge .cse125 (_ bv0 32))) (= .cse4 .cse126) (= .cse127 .cse126))))) (not (bvsge .cse124 (_ bv0 32))) (= .cse127 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse128 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse131 (bvmul (_ bv4 32) .cse128))) (or (not (bvslt .cse128 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse130 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse129 (bvmul (_ bv4 32) .cse130))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse129) (bvadd c_~f~0.offset (_ bv4 32) .cse129))) (not (bvslt .cse130 c_~size~0)) (= .cse131 .cse129) (= .cse129 .cse4))))) (not (bvsge .cse128 (_ bv0 32))) (= .cse131 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse132 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse132 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse132 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse132) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse134 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse133 (concat (concat .cse134 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse133 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse134 v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse133 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse133) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse135 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse136 (bvmul (_ bv4 32) .cse135))) (or (not (bvslt .cse135 c_~size~0)) (not (bvsge .cse135 (_ bv0 32))) (= .cse136 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse137 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse138 (bvmul (_ bv4 32) .cse137))) (or (not (bvslt .cse137 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse138) (bvadd c_~f~0.offset (_ bv4 32) .cse138))) (not (bvsge .cse137 (_ bv0 32))) (= .cse4 .cse138) (= .cse136 .cse138))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse139 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse139 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse139 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse139) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse144 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse140 (concat (concat .cse144 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse142 (bvmul (_ bv4 32) .cse140))) (or (not (bvslt .cse140 c_~size~0)) (not (bvsge .cse140 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse141 (concat (concat .cse144 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse143 (bvmul (_ bv4 32) .cse141))) (or (not (bvslt .cse141 c_~size~0)) (= .cse142 .cse143) (= .cse4 .cse143) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse143) (bvadd c_~f~0.offset (_ bv4 32) .cse143))))))) (= .cse142 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse145 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse148 (bvmul (_ bv4 32) .cse145))) (or (not (bvslt .cse145 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse146 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse147 (bvmul (_ bv4 32) .cse146))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse146 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse147) (bvadd c_~f~0.offset (_ bv4 32) .cse147))) (not (bvsge .cse146 (_ bv0 32))) (= .cse4 .cse147) (= .cse148 .cse147))))) (not (bvsge .cse145 (_ bv0 32))) (= .cse148 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse149 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse153 (bvmul (_ bv4 32) .cse149))) (or (not (bvslt .cse149 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse151 (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse150 (concat .cse151 v_arrayElimCell_70))) (let ((.cse152 (bvmul (_ bv4 32) .cse150))) (or (not (bvslt .cse150 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse151 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse152) (bvadd c_~f~0.offset (_ bv4 32) .cse152))) (not (bvsge .cse150 (_ bv0 32))) (= .cse4 .cse152) (= .cse153 .cse152)))))) (not (bvsge .cse149 (_ bv0 32))) (= .cse153 .cse4))))) (or .cse154 (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse155 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse4 (bvmul (_ bv4 32) .cse155)) (= c_~x1~0 .cse155))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse156 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse159 (bvmul (_ bv4 32) .cse156))) (or (not (bvslt .cse156 c_~size~0)) (not (bvsge .cse156 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse158 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse157 (bvmul (_ bv4 32) .cse158))) (or (not (bvule (bvadd c_~f~0.offset .cse157) (bvadd c_~f~0.offset (_ bv4 32) .cse157))) (not (bvslt .cse158 c_~size~0)) (= .cse159 .cse157) (= .cse157 .cse4))))) (= .cse159 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse160 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse164 (bvmul (_ bv4 32) .cse160))) (or (not (bvslt .cse160 c_~size~0)) (not (bvsge .cse160 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse163 (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81))) (let ((.cse162 (concat .cse163 v_arrayElimCell_70))) (let ((.cse161 (bvmul .cse162 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse161) (bvadd c_~f~0.offset (_ bv4 32) .cse161))) (not (bvslt .cse162 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse163 v_arrayElimCell_77))) (= .cse164 .cse161) (not (bvsge .cse162 (_ bv0 32))) (= .cse4 .cse161)))))) (= .cse164 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse168 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse165 (concat (concat .cse168 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse169 (bvmul (_ bv4 32) .cse165))) (or (not (bvslt .cse165 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse167 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse166 (bvmul (_ bv4 32) .cse167))) (or (not (bvule (bvadd c_~f~0.offset .cse166) (bvadd c_~f~0.offset (_ bv4 32) .cse166))) (not (bvslt .cse167 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse168 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse169 .cse166) (= .cse166 .cse4))))) (not (bvsge .cse165 (_ bv0 32))) (= .cse169 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse170 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse171 (bvmul (_ bv4 32) .cse170))) (or (not (bvslt .cse170 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse173 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse172 (bvmul (_ bv4 32) .cse173))) (or (= .cse171 .cse172) (not (bvslt .cse173 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse172) (bvadd c_~f~0.offset (_ bv4 32) .cse172))) (not (bvsge .cse173 (_ bv0 32))))))) (not (bvsge .cse170 (_ bv0 32))) (= .cse171 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse174 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse177 (bvmul (_ bv4 32) .cse174))) (or (not (bvslt .cse174 c_~size~0)) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse176 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse175 (bvmul (_ bv4 32) .cse176))) (or (not (bvule (bvadd c_~f~0.offset .cse175) (bvadd c_~f~0.offset (_ bv4 32) .cse175))) (not (bvslt .cse176 c_~size~0)) (not (bvsge .cse176 (_ bv0 32))) (= .cse177 .cse175))))) (not (bvsge .cse174 (_ bv0 32))) (= .cse177 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse178 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse178 c_~size~0)) (= .cse178 c_~x1~0) (not (bvsge .cse178 (_ bv0 32)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse179 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse182 (bvmul (_ bv4 32) .cse179))) (or (not (bvslt .cse179 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse181 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse180 (bvmul .cse181 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse180) (bvadd c_~f~0.offset (_ bv4 32) .cse180))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse181 c_~size~0)) (= .cse182 .cse180) (not (bvsge .cse181 (_ bv0 32))) (= .cse4 .cse180))))) (not (bvsge .cse179 (_ bv0 32))) (= .cse182 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse183 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse186 (bvmul (_ bv4 32) .cse183))) (or (not (bvslt .cse183 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse185 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse184 (bvmul .cse185 (_ bv4 32)))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse184) (bvadd c_~f~0.offset (_ bv4 32) .cse184))) (not (bvslt .cse185 c_~size~0)) (= .cse186 .cse184) (not (bvsge .cse185 (_ bv0 32))) (= .cse4 .cse184))))) (not (bvsge .cse183 (_ bv0 32))) (= .cse186 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse187 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse190 (bvmul (_ bv4 32) .cse187))) (or (not (bvslt .cse187 c_~size~0)) (not (bvsge .cse187 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse189 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse188 (bvmul .cse189 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse188) (bvadd c_~f~0.offset (_ bv4 32) .cse188))) (not (bvslt .cse189 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse190 .cse188) (not (bvsge .cse189 (_ bv0 32))) (= .cse4 .cse188))))) (= .cse190 .cse4))))) (or (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) .cse154) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse191 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse194 (bvmul (_ bv4 32) .cse191))) (or (not (bvslt .cse191 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse192 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse193 (bvmul (_ bv4 32) .cse192))) (or (not (bvslt .cse192 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse193) (bvadd c_~f~0.offset (_ bv4 32) .cse193))) (not (bvsge .cse192 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse4 .cse193) (= .cse194 .cse193))))) (not (bvsge .cse191 (_ bv0 32))) (= .cse194 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse195 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse198 (bvmul (_ bv4 32) .cse195))) (or (not (bvslt .cse195 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse196 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse197 (bvmul (_ bv4 32) .cse196))) (or (not (bvslt .cse196 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse197) (bvadd c_~f~0.offset (_ bv4 32) .cse197))) (not (bvsge .cse196 (_ bv0 32))) (= .cse198 .cse197))))) (not (bvsge .cse195 (_ bv0 32))) (= .cse198 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse202 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse200 (bvmul (_ bv4 32) .cse202))) (or (forall ((v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse201 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse199 (bvmul (_ bv4 32) .cse201))) (or (not (bvule (bvadd c_~f~0.offset .cse199) (bvadd c_~f~0.offset (_ bv4 32) .cse199))) (= .cse200 .cse199) (not (bvslt .cse201 c_~size~0)))))) (not (bvslt .cse202 c_~size~0)) (not (bvsge .cse202 (_ bv0 32))) (= .cse200 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse203 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse203 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse203 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse203) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse208 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse204 (concat (concat .cse208 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse206 (bvmul (_ bv4 32) .cse204))) (or (not (bvslt .cse204 c_~size~0)) (not (bvsge .cse204 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse205 (concat (concat .cse208 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse207 (bvmul (_ bv4 32) .cse205))) (or (not (bvslt .cse205 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse206 .cse207) (= .cse4 .cse207) (not (bvule (bvadd c_~f~0.offset .cse207) (bvadd c_~f~0.offset (_ bv4 32) .cse207))))))) (= .cse206 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse209 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse212 (bvmul (_ bv4 32) .cse209))) (or (not (bvslt .cse209 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse211 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse210 (bvmul (_ bv4 32) .cse211))) (or (not (bvule (bvadd c_~f~0.offset .cse210) (bvadd c_~f~0.offset (_ bv4 32) .cse210))) (not (bvsge .cse211 (_ bv0 32))) (not (bvslt .cse211 c_~size~0)) (= .cse212 .cse210))))) (not (bvsge .cse209 (_ bv0 32))) (= .cse212 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse216 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse213 (concat (concat .cse216 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse213 c_~size~0)) (not (bvsge .cse213 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse213) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse215 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse214 (bvmul (_ bv4 32) .cse215))) (or (not (bvule (bvadd c_~f~0.offset .cse214) (bvadd c_~f~0.offset (_ bv4 32) .cse214))) (not (bvslt .cse215 c_~size~0)) (= c_~x1~0 (concat (concat .cse216 v_arrayElimCell_81) v_arrayElimCell_78)) (= .cse214 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse221 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse217 (concat .cse221 v_arrayElimCell_78))) (let ((.cse218 (bvmul (_ bv4 32) .cse217))) (or (not (bvslt .cse217 c_~size~0)) (not (bvsge .cse217 (_ bv0 32))) (= .cse218 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (let ((.cse220 (concat .cse221 v_arrayElimCell_70))) (let ((.cse219 (bvmul (_ bv4 32) .cse220))) (or (= .cse218 .cse219) (not (bvslt .cse220 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse219) (bvadd c_~f~0.offset (_ bv4 32) .cse219)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse222 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse225 (bvmul (_ bv4 32) .cse222))) (or (not (bvslt .cse222 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse223 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse224 (bvmul (_ bv4 32) .cse223))) (or (not (bvslt .cse223 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse224) (bvadd c_~f~0.offset (_ bv4 32) .cse224))) (not (bvsge .cse223 (_ bv0 32))) (= .cse4 .cse224) (= .cse225 .cse224) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)))))) (not (bvsge .cse222 (_ bv0 32))) (= .cse225 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse226 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse228 (bvmul (_ bv4 32) .cse226))) (or (not (bvslt .cse226 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse229 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse227 (bvmul (_ bv4 32) .cse229))) (or (not (bvule (bvadd c_~f~0.offset .cse227) (bvadd c_~f~0.offset (_ bv4 32) .cse227))) (= .cse228 .cse227) (not (bvslt .cse229 c_~size~0)))))) (not (bvsge .cse226 (_ bv0 32))) (= .cse228 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse233 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse232 (bvmul (_ bv4 32) .cse233))) (or (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse230 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse231 (bvmul (_ bv4 32) .cse230))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvslt .cse230 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse231) (bvadd c_~f~0.offset (_ bv4 32) .cse231))) (not (bvsge .cse230 (_ bv0 32))) (= .cse4 .cse231) (= .cse232 .cse231))))) (not (bvslt .cse233 c_~size~0)) (not (bvsge .cse233 (_ bv0 32))) (= .cse232 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse234 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse236 (bvmul (_ bv4 32) .cse234))) (or (not (bvslt .cse234 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse235 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse237 (bvmul (_ bv4 32) .cse235))) (or (not (bvslt .cse235 c_~size~0)) (= .cse236 .cse237) (not (bvule (bvadd c_~f~0.offset .cse237) (bvadd c_~f~0.offset (_ bv4 32) .cse237))) (not (bvsge .cse235 (_ bv0 32))))))) (not (bvsge .cse234 (_ bv0 32))) (= .cse236 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse238 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse239 (bvmul (_ bv4 32) .cse238))) (or (not (bvslt .cse238 c_~size~0)) (not (bvsge .cse238 (_ bv0 32))) (= .cse239 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse240 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse241 (bvmul (_ bv4 32) .cse240))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvslt .cse240 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse241) (bvadd c_~f~0.offset (_ bv4 32) .cse241))) (not (bvsge .cse240 (_ bv0 32))) (= .cse4 .cse241) (= .cse239 .cse241))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse242 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse244 (bvmul (_ bv4 32) .cse242))) (or (not (bvslt .cse242 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse243 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse245 (bvmul .cse243 (_ bv4 32)))) (or (not (bvslt .cse243 c_~size~0)) (= .cse244 .cse245) (= .cse4 .cse245) (not (bvule (bvadd c_~f~0.offset .cse245) (bvadd c_~f~0.offset (_ bv4 32) .cse245))))))) (not (bvsge .cse242 (_ bv0 32))) (= .cse244 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse246 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse246 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse246 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse246) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse251 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse247 (concat (concat .cse251 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse248 (bvmul (_ bv4 32) .cse247))) (or (not (bvslt .cse247 c_~size~0)) (not (bvsge .cse247 (_ bv0 32))) (= .cse248 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse250 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse249 (bvmul .cse250 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse249) (bvadd c_~f~0.offset (_ bv4 32) .cse249))) (not (bvslt .cse250 c_~size~0)) (= .cse248 .cse249) (not (bvsge .cse250 (_ bv0 32))) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse251 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse4 .cse249)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse252 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse255 (bvmul (_ bv4 32) .cse252))) (or (not (bvslt .cse252 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse253 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse254 (bvmul (_ bv4 32) .cse253))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse253 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse254) (bvadd c_~f~0.offset (_ bv4 32) .cse254))) (not (bvsge .cse253 (_ bv0 32))) (= .cse4 .cse254) (= .cse255 .cse254))))) (not (bvsge .cse252 (_ bv0 32))) (= .cse255 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse256 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse257 (bvmul (_ bv4 32) .cse256))) (or (not (bvslt .cse256 c_~size~0)) (not (bvsge .cse256 (_ bv0 32))) (= .cse257 .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse259 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse258 (bvmul (_ bv4 32) .cse259))) (or (not (bvule (bvadd c_~f~0.offset .cse258) (bvadd c_~f~0.offset (_ bv4 32) .cse258))) (not (bvsge .cse259 (_ bv0 32))) (not (bvslt .cse259 c_~size~0)) (= .cse257 .cse258) (= .cse4 .cse258))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse264 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse260 (concat (concat .cse264 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse260 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse263 (concat .cse264 v_arrayElimCell_81))) (let ((.cse261 (concat .cse263 v_arrayElimCell_70))) (let ((.cse262 (bvmul (_ bv4 32) .cse261))) (or (not (bvslt .cse261 c_~size~0)) (= .cse4 .cse262) (not (bvule (bvadd c_~f~0.offset .cse262) (bvadd c_~f~0.offset (_ bv4 32) .cse262))) (= c_~x1~0 (concat .cse263 v_arrayElimCell_78))))))) (not (bvsge .cse260 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse260) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse265 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse268 (bvmul (_ bv4 32) .cse265))) (or (not (bvslt .cse265 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse266 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse267 (bvmul (_ bv4 32) .cse266))) (or (not (bvslt .cse266 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse267) (bvadd c_~f~0.offset (_ bv4 32) .cse267))) (not (bvsge .cse266 (_ bv0 32))) (= .cse4 .cse267) (= .cse268 .cse267))))) (not (bvsge .cse265 (_ bv0 32))) (= .cse268 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse269 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse269 c_~size~0)) (not (bvsge .cse269 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse269) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse270 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse273 (bvmul (_ bv4 32) .cse270))) (or (not (bvslt .cse270 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse271 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse272 (bvmul (_ bv4 32) .cse271))) (or (not (bvslt .cse271 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse272) (bvadd c_~f~0.offset (_ bv4 32) .cse272))) (not (bvsge .cse271 (_ bv0 32))) (= .cse4 .cse272) (= .cse273 .cse272) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))))))) (not (bvsge .cse270 (_ bv0 32))) (= .cse273 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse274 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse276 (bvmul (_ bv4 32) .cse274))) (or (not (bvslt .cse274 c_~size~0)) (not (bvsge .cse274 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse275 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse277 (bvmul .cse275 (_ bv4 32)))) (or (not (bvslt .cse275 c_~size~0)) (= .cse276 .cse277) (not (bvule (bvadd c_~f~0.offset .cse277) (bvadd c_~f~0.offset (_ bv4 32) .cse277))))))) (= .cse276 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse278 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse281 (bvmul (_ bv4 32) .cse278))) (or (not (bvslt .cse278 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse280 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse279 (bvmul .cse280 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse279) (bvadd c_~f~0.offset (_ bv4 32) .cse279))) (not (bvslt .cse280 c_~size~0)) (= .cse281 .cse279) (not (bvsge .cse280 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse4 .cse279))))) (not (bvsge .cse278 (_ bv0 32))) (= .cse281 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse282 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse283 (bvmul (_ bv4 32) .cse282))) (or (not (bvslt .cse282 c_~size~0)) (not (bvsge .cse282 (_ bv0 32))) (= .cse283 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse285 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse284 (bvmul .cse285 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse284) (bvadd c_~f~0.offset (_ bv4 32) .cse284))) (not (bvslt .cse285 c_~size~0)) (= .cse283 .cse284) (not (bvsge .cse285 (_ bv0 32))) (= .cse4 .cse284))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse290 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse286 (concat (concat .cse290 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse287 (bvmul (_ bv4 32) .cse286))) (or (not (bvslt .cse286 c_~size~0)) (not (bvsge .cse286 (_ bv0 32))) (= .cse287 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse288 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse289 (bvmul (_ bv4 32) .cse288))) (or (not (bvslt .cse288 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse289) (bvadd c_~f~0.offset (_ bv4 32) .cse289))) (not (bvsge .cse288 (_ bv0 32))) (= .cse4 .cse289) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse290 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse287 .cse289)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse291 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse294 (bvmul (_ bv4 32) .cse291))) (or (not (bvslt .cse291 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse293 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse292 (bvmul (_ bv4 32) .cse293))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse292) (bvadd c_~f~0.offset (_ bv4 32) .cse292))) (not (bvslt .cse293 c_~size~0)) (= .cse294 .cse292) (= .cse292 .cse4))))) (not (bvsge .cse291 (_ bv0 32))) (= .cse294 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse295 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse296 (bvmul (_ bv4 32) .cse295))) (or (not (bvslt .cse295 c_~size~0)) (not (bvsge .cse295 (_ bv0 32))) (= .cse296 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse298 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse297 (bvmul (_ bv4 32) .cse298))) (or (not (bvule (bvadd c_~f~0.offset .cse297) (bvadd c_~f~0.offset (_ bv4 32) .cse297))) (not (bvslt .cse298 c_~size~0)) (= .cse296 .cse297) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse297 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse299 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse302 (bvmul (_ bv4 32) .cse299))) (or (not (bvslt .cse299 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse301 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse300 (bvmul .cse301 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse300) (bvadd c_~f~0.offset (_ bv4 32) .cse300))) (not (bvslt .cse301 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse302 .cse300) (not (bvsge .cse301 (_ bv0 32))) (= .cse4 .cse300))))) (not (bvsge .cse299 (_ bv0 32))) (= .cse302 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse303 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse306 (bvmul (_ bv4 32) .cse303))) (or (not (bvslt .cse303 c_~size~0)) (not (bvsge .cse303 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse305 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse304 (bvmul (_ bv4 32) .cse305))) (or (not (bvule (bvadd c_~f~0.offset .cse304) (bvadd c_~f~0.offset (_ bv4 32) .cse304))) (not (bvslt .cse305 c_~size~0)) (= .cse306 .cse304) (not (bvsge .cse305 (_ bv0 32))))))) (= .cse306 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse307 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse310 (bvmul (_ bv4 32) .cse307))) (or (not (bvslt .cse307 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse309 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse308 (bvmul (_ bv4 32) .cse309))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse308) (bvadd c_~f~0.offset (_ bv4 32) .cse308))) (not (bvslt .cse309 c_~size~0)) (= .cse310 .cse308) (= .cse308 .cse4))))) (not (bvsge .cse307 (_ bv0 32))) (= .cse310 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse311 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse311 c_~size~0)) (not (bvsge .cse311 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse311) .cse4) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse314 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse312 (concat (concat .cse314 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse312 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse313 (concat (concat .cse314 v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse313) (= .cse4 (bvmul (_ bv4 32) .cse313))))) (not (bvsge .cse312 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse312) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse315 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse318 (bvmul (_ bv4 32) .cse315))) (or (not (bvslt .cse315 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse316 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse317 (bvmul (_ bv4 32) .cse316))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse316 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse317) (bvadd c_~f~0.offset (_ bv4 32) .cse317))) (not (bvsge .cse316 (_ bv0 32))) (= .cse4 .cse317) (= .cse318 .cse317))))) (not (bvsge .cse315 (_ bv0 32))) (= .cse318 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse319 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse319 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse320 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse320) (= (bvmul (_ bv4 32) .cse320) .cse4)))) (not (bvsge .cse319 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse319) .cse4))))))) (not (bvslt c_~x2~0 c_~size~0))) is different from true [2022-11-18 21:14:15,045 WARN L233 SmtUtils]: Spent 12.61s on a formula simplification. DAG size of input: 613 DAG size of output: 26 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 21:14:15,211 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-11-18 21:14:15,211 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:15,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [325175160] [2022-11-18 21:14:15,212 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [325175160] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:15,212 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:15,212 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 10 [2022-11-18 21:14:15,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15507525] [2022-11-18 21:14:15,212 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:15,213 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-11-18 21:14:15,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:15,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-11-18 21:14:15,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=70, Unknown=5, NotChecked=18, Total=132 [2022-11-18 21:14:15,215 INFO L87 Difference]: Start difference. First operand 110 states and 256 transitions. Second operand has 12 states, 11 states have (on average 2.909090909090909) internal successors, (32), 11 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:17,476 WARN L859 $PredicateComparison]: unable to prove that (and (= |c_ULTIMATE.start_create_fresh_int_array_~arr~0#1.offset| (_ bv0 32)) (not (bvslt (_ bv1 32) c_~size~0)) (= c_~x2~0 (_ bv0 32)) (= |c_ULTIMATE.start_create_fresh_int_array_~i~2#1| (_ bv1 32)) (= c_~x1~0 (_ bv0 32)) (= c_~size~0 |c_ULTIMATE.start_create_fresh_int_array_~size#1|) (bvsgt c_~size~0 (_ bv0 32)) (or (not (bvsge c_~x2~0 (_ bv0 32))) (let ((.cse4 (bvmul c_~x2~0 (_ bv4 32)))) (let ((.cse154 (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse321 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse321 c_~size~0)) (not (bvsge .cse321 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse321) .cse4)))))) (and (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse3 (bvmul (_ bv4 32) .cse0))) (or (not (bvslt .cse0 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse2 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse1 (bvmul .cse2 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse1) (bvadd c_~f~0.offset (_ bv4 32) .cse1))) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse2 c_~size~0)) (= .cse3 .cse1) (not (bvsge .cse2 (_ bv0 32))) (= .cse4 .cse1))))) (not (bvsge .cse0 (_ bv0 32))) (= .cse3 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse5 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse5 c_~size~0)) (not (bvsge .cse5 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse5) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse6 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse9 (bvmul (_ bv4 32) .cse6))) (or (not (bvslt .cse6 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse8 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse7 (bvmul (_ bv4 32) .cse8))) (or (not (bvule (bvadd c_~f~0.offset .cse7) (bvadd c_~f~0.offset (_ bv4 32) .cse7))) (not (bvslt .cse8 c_~size~0)) (= .cse9 .cse7))))) (not (bvsge .cse6 (_ bv0 32))) (= .cse9 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse13 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse10 (concat (concat .cse13 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse10 c_~size~0)) (not (bvsge .cse10 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse10) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse12 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse11 (bvmul .cse12 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse11) (bvadd c_~f~0.offset (_ bv4 32) .cse11))) (not (bvslt .cse12 c_~size~0)) (not (bvsge .cse12 (_ bv0 32))) (= .cse4 .cse11) (= c_~x1~0 (concat (concat .cse13 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse14 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse15 (bvmul (_ bv4 32) .cse14))) (or (not (bvslt .cse14 c_~size~0)) (not (bvsge .cse14 (_ bv0 32))) (= .cse15 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse17 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse16 (bvmul .cse17 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse16) (bvadd c_~f~0.offset (_ bv4 32) .cse16))) (not (bvslt .cse17 c_~size~0)) (= .cse15 .cse16) (not (bvsge .cse17 (_ bv0 32))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse18 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse21 (bvmul (_ bv4 32) .cse18))) (or (not (bvslt .cse18 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse20 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse19 (bvmul (_ bv4 32) .cse20))) (or (not (bvule (bvadd c_~f~0.offset .cse19) (bvadd c_~f~0.offset (_ bv4 32) .cse19))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse20 c_~size~0)) (= .cse21 .cse19) (= .cse19 .cse4))))) (not (bvsge .cse18 (_ bv0 32))) (= .cse21 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse24 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse22 (concat (concat .cse24 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse22 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse23 (concat (concat .cse24 v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse4 (bvmul (_ bv4 32) .cse23)) (= c_~x1~0 .cse23)))) (not (bvsge .cse22 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse22) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse25 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse25 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse25 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse25) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse27 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse26 (concat (concat .cse27 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse26 c_~size~0)) (not (bvsge .cse26 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse26) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse27 v_arrayElimCell_81) v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse31 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse28 (concat (concat .cse31 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse28 c_~size~0)) (not (bvsge .cse28 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse28) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse29 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse30 (bvmul (_ bv4 32) .cse29))) (or (not (bvslt .cse29 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse30) (bvadd c_~f~0.offset (_ bv4 32) .cse30))) (not (bvsge .cse29 (_ bv0 32))) (= .cse4 .cse30) (= c_~x1~0 (concat (concat .cse31 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse33 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse32 (concat .cse33 v_arrayElimCell_78))) (or (not (bvslt .cse32 c_~size~0)) (not (bvsge .cse32 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse32) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (= c_~x1~0 (concat .cse33 v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse34 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse34 c_~size~0)) (not (bvsge .cse34 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse35 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse35 c_~x1~0) (= .cse4 (bvmul .cse35 (_ bv4 32)))))) (= (bvmul (_ bv4 32) .cse34) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse40 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse36 (concat (concat .cse40 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse39 (bvmul (_ bv4 32) .cse36))) (or (not (bvslt .cse36 c_~size~0)) (not (bvsge .cse36 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse38 (concat (concat .cse40 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse37 (bvmul (_ bv4 32) .cse38))) (or (not (bvule (bvadd c_~f~0.offset .cse37) (bvadd c_~f~0.offset (_ bv4 32) .cse37))) (= .cse4 .cse37) (not (bvslt .cse38 c_~size~0)) (= .cse39 .cse37))))) (= .cse39 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse45 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse41 (concat (concat .cse45 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse43 (bvmul (_ bv4 32) .cse41))) (or (not (bvslt .cse41 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse42 (concat (concat .cse45 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse44 (bvmul (_ bv4 32) .cse42))) (or (not (bvslt .cse42 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse43 .cse44) (= .cse4 .cse44) (not (bvule (bvadd c_~f~0.offset .cse44) (bvadd c_~f~0.offset (_ bv4 32) .cse44))))))) (not (bvsge .cse41 (_ bv0 32))) (= .cse43 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse50 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse46 (concat (concat .cse50 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse47 (bvmul (_ bv4 32) .cse46))) (or (not (bvslt .cse46 c_~size~0)) (not (bvsge .cse46 (_ bv0 32))) (= .cse47 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse48 (concat (concat .cse50 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse49 (bvmul (_ bv4 32) .cse48))) (or (not (bvslt .cse48 c_~size~0)) (= .cse47 .cse49) (= .cse4 .cse49) (not (bvule (bvadd c_~f~0.offset .cse49) (bvadd c_~f~0.offset (_ bv4 32) .cse49)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse56 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse51 (concat (concat .cse56 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse53 (bvmul (_ bv4 32) .cse51))) (or (not (bvslt .cse51 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse55 (concat .cse56 v_arrayElimCell_81))) (let ((.cse52 (concat .cse55 v_arrayElimCell_70))) (let ((.cse54 (bvmul (_ bv4 32) .cse52))) (or (not (bvslt .cse52 c_~size~0)) (= .cse53 .cse54) (= .cse4 .cse54) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat .cse55 v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse54) (bvadd c_~f~0.offset (_ bv4 32) .cse54)))))))) (not (bvsge .cse51 (_ bv0 32))) (= .cse53 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse61 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse57 (concat (concat .cse61 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse59 (bvmul (_ bv4 32) .cse57))) (or (not (bvslt .cse57 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse58 (concat (concat .cse61 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse60 (bvmul (_ bv4 32) .cse58))) (or (not (bvslt .cse58 c_~size~0)) (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse59 .cse60) (= .cse4 .cse60) (not (bvule (bvadd c_~f~0.offset .cse60) (bvadd c_~f~0.offset (_ bv4 32) .cse60))))))) (not (bvsge .cse57 (_ bv0 32))) (= .cse59 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse66 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse62 (concat (concat .cse66 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse64 (bvmul (_ bv4 32) .cse62))) (or (not (bvslt .cse62 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse63 (concat (concat .cse66 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse65 (bvmul (_ bv4 32) .cse63))) (or (not (bvslt .cse63 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse64 .cse65) (= .cse4 .cse65) (not (bvule (bvadd c_~f~0.offset .cse65) (bvadd c_~f~0.offset (_ bv4 32) .cse65))))))) (not (bvsge .cse62 (_ bv0 32))) (= .cse64 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse67 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse68 (bvmul (_ bv4 32) .cse67))) (or (not (bvslt .cse67 c_~size~0)) (not (bvsge .cse67 (_ bv0 32))) (= .cse68 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse70 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse69 (bvmul (_ bv4 32) .cse70))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse69) (bvadd c_~f~0.offset (_ bv4 32) .cse69))) (not (bvslt .cse70 c_~size~0)) (= .cse68 .cse69) (= .cse69 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse71 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse74 (bvmul (_ bv4 32) .cse71))) (or (not (bvslt .cse71 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse72 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse73 (bvmul (_ bv4 32) .cse72))) (or (not (bvsge .cse72 (_ bv0 32))) (= .cse73 .cse4) (not (bvule (bvadd c_~f~0.offset .cse73) (bvadd c_~f~0.offset .cse73 (_ bv4 32)))) (not (bvslt .cse72 c_~size~0)) (= .cse74 .cse73))))) (not (bvsge .cse71 (_ bv0 32))) (= .cse74 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse75 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse78 (bvmul (_ bv4 32) .cse75))) (or (not (bvslt .cse75 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse76 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse77 (bvmul (_ bv4 32) .cse76))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse76 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse77) (bvadd c_~f~0.offset (_ bv4 32) .cse77))) (not (bvsge .cse76 (_ bv0 32))) (= .cse4 .cse77) (= .cse78 .cse77))))) (not (bvsge .cse75 (_ bv0 32))) (= .cse78 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse79 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse79 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse79 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse79) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse80 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse80 c_~size~0)) (not (bvsge .cse80 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse80) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse81 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse84 (bvmul (_ bv4 32) .cse81))) (or (not (bvslt .cse81 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse83 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse82 (bvmul .cse83 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse82) (bvadd c_~f~0.offset (_ bv4 32) .cse82))) (not (bvslt .cse83 c_~size~0)) (= .cse84 .cse82) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvsge .cse83 (_ bv0 32))) (= .cse4 .cse82))))) (not (bvsge .cse81 (_ bv0 32))) (= .cse84 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse85 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse85 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse86 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= (bvmul (_ bv4 32) .cse86) .cse4) (= c_~x1~0 .cse86)))) (not (bvsge .cse85 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse85) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse87 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse87 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse87 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse87) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse88 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse91 (bvmul (_ bv4 32) .cse88))) (or (not (bvslt .cse88 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse90 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse89 (bvmul (_ bv4 32) .cse90))) (or (not (bvule (bvadd c_~f~0.offset .cse89) (bvadd c_~f~0.offset (_ bv4 32) .cse89))) (not (bvslt .cse90 c_~size~0)) (= .cse91 .cse89) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse89 .cse4))))) (not (bvsge .cse88 (_ bv0 32))) (= .cse91 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse92 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse95 (bvmul (_ bv4 32) .cse92))) (or (not (bvslt .cse92 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse93 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse94 (bvmul (_ bv4 32) .cse93))) (or (not (bvsge .cse93 (_ bv0 32))) (not (bvule (bvadd c_~f~0.offset .cse94) (bvadd c_~f~0.offset .cse94 (_ bv4 32)))) (not (bvslt .cse93 c_~size~0)) (= .cse95 .cse94))))) (not (bvsge .cse92 (_ bv0 32))) (= .cse95 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse96 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse99 (bvmul (_ bv4 32) .cse96))) (or (not (bvslt .cse96 c_~size~0)) (not (bvsge .cse96 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse98 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse97 (bvmul (_ bv4 32) .cse98))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse97) (bvadd c_~f~0.offset (_ bv4 32) .cse97))) (not (bvslt .cse98 c_~size~0)) (= .cse99 .cse97) (= .cse97 .cse4))))) (= .cse99 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse104 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse100 (concat (concat .cse104 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse101 (bvmul (_ bv4 32) .cse100))) (or (not (bvslt .cse100 c_~size~0)) (not (bvsge .cse100 (_ bv0 32))) (= .cse101 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse102 (concat (concat .cse104 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse103 (bvmul (_ bv4 32) .cse102))) (or (not (bvslt .cse102 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse101 .cse103) (= .cse4 .cse103) (not (bvule (bvadd c_~f~0.offset .cse103) (bvadd c_~f~0.offset (_ bv4 32) .cse103)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse105 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse105 c_~size~0)) (not (bvsge .cse105 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse105) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse106 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse106 c_~x1~0) (= .cse4 (bvmul .cse106 (_ bv4 32))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse111 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse107 (concat (concat .cse111 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse110 (bvmul (_ bv4 32) .cse107))) (or (not (bvslt .cse107 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse109 (concat (concat .cse111 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse108 (bvmul (_ bv4 32) .cse109))) (or (not (bvule (bvadd c_~f~0.offset .cse108) (bvadd c_~f~0.offset (_ bv4 32) .cse108))) (not (bvslt .cse109 c_~size~0)) (= .cse110 .cse108))))) (not (bvsge .cse107 (_ bv0 32))) (= .cse110 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse112 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse112 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse113 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= c_~x1~0 .cse113) (= .cse4 (bvmul (_ bv4 32) .cse113))))) (not (bvsge .cse112 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse112) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse114 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse118 (bvmul (_ bv4 32) .cse114))) (or (not (bvslt .cse114 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse115 (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse117 (concat .cse115 v_arrayElimCell_70))) (let ((.cse116 (bvmul (_ bv4 32) .cse117))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse115 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse116) (bvadd c_~f~0.offset (_ bv4 32) .cse116))) (not (bvslt .cse117 c_~size~0)) (= .cse118 .cse116) (= .cse116 .cse4)))))) (not (bvsge .cse114 (_ bv0 32))) (= .cse118 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse123 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse119 (concat (concat .cse123 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse121 (bvmul (_ bv4 32) .cse119))) (or (not (bvslt .cse119 c_~size~0)) (not (bvsge .cse119 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse120 (concat (concat .cse123 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse122 (bvmul (_ bv4 32) .cse120))) (or (not (bvslt .cse120 c_~size~0)) (= .cse121 .cse122) (not (bvule (bvadd c_~f~0.offset .cse122) (bvadd c_~f~0.offset (_ bv4 32) .cse122))))))) (= .cse121 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse124 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse127 (bvmul (_ bv4 32) .cse124))) (or (not (bvslt .cse124 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse125 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse126 (bvmul (_ bv4 32) .cse125))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse125 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse126) (bvadd c_~f~0.offset (_ bv4 32) .cse126))) (not (bvsge .cse125 (_ bv0 32))) (= .cse4 .cse126) (= .cse127 .cse126))))) (not (bvsge .cse124 (_ bv0 32))) (= .cse127 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse128 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse131 (bvmul (_ bv4 32) .cse128))) (or (not (bvslt .cse128 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse130 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse129 (bvmul (_ bv4 32) .cse130))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse129) (bvadd c_~f~0.offset (_ bv4 32) .cse129))) (not (bvslt .cse130 c_~size~0)) (= .cse131 .cse129) (= .cse129 .cse4))))) (not (bvsge .cse128 (_ bv0 32))) (= .cse131 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse132 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse132 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse132 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse132) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse134 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse133 (concat (concat .cse134 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse133 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse134 v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse133 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse133) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse135 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse136 (bvmul (_ bv4 32) .cse135))) (or (not (bvslt .cse135 c_~size~0)) (not (bvsge .cse135 (_ bv0 32))) (= .cse136 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse137 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse138 (bvmul (_ bv4 32) .cse137))) (or (not (bvslt .cse137 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse138) (bvadd c_~f~0.offset (_ bv4 32) .cse138))) (not (bvsge .cse137 (_ bv0 32))) (= .cse4 .cse138) (= .cse136 .cse138))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse139 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse139 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse139 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse139) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse144 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse140 (concat (concat .cse144 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse142 (bvmul (_ bv4 32) .cse140))) (or (not (bvslt .cse140 c_~size~0)) (not (bvsge .cse140 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse141 (concat (concat .cse144 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse143 (bvmul (_ bv4 32) .cse141))) (or (not (bvslt .cse141 c_~size~0)) (= .cse142 .cse143) (= .cse4 .cse143) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse143) (bvadd c_~f~0.offset (_ bv4 32) .cse143))))))) (= .cse142 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse145 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse148 (bvmul (_ bv4 32) .cse145))) (or (not (bvslt .cse145 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse146 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse147 (bvmul (_ bv4 32) .cse146))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse146 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse147) (bvadd c_~f~0.offset (_ bv4 32) .cse147))) (not (bvsge .cse146 (_ bv0 32))) (= .cse4 .cse147) (= .cse148 .cse147))))) (not (bvsge .cse145 (_ bv0 32))) (= .cse148 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse149 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse153 (bvmul (_ bv4 32) .cse149))) (or (not (bvslt .cse149 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse151 (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse150 (concat .cse151 v_arrayElimCell_70))) (let ((.cse152 (bvmul (_ bv4 32) .cse150))) (or (not (bvslt .cse150 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse151 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse152) (bvadd c_~f~0.offset (_ bv4 32) .cse152))) (not (bvsge .cse150 (_ bv0 32))) (= .cse4 .cse152) (= .cse153 .cse152)))))) (not (bvsge .cse149 (_ bv0 32))) (= .cse153 .cse4))))) (or .cse154 (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse155 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse4 (bvmul (_ bv4 32) .cse155)) (= c_~x1~0 .cse155))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse156 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse159 (bvmul (_ bv4 32) .cse156))) (or (not (bvslt .cse156 c_~size~0)) (not (bvsge .cse156 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse158 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse157 (bvmul (_ bv4 32) .cse158))) (or (not (bvule (bvadd c_~f~0.offset .cse157) (bvadd c_~f~0.offset (_ bv4 32) .cse157))) (not (bvslt .cse158 c_~size~0)) (= .cse159 .cse157) (= .cse157 .cse4))))) (= .cse159 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse160 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse164 (bvmul (_ bv4 32) .cse160))) (or (not (bvslt .cse160 c_~size~0)) (not (bvsge .cse160 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse163 (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81))) (let ((.cse162 (concat .cse163 v_arrayElimCell_70))) (let ((.cse161 (bvmul .cse162 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse161) (bvadd c_~f~0.offset (_ bv4 32) .cse161))) (not (bvslt .cse162 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse163 v_arrayElimCell_77))) (= .cse164 .cse161) (not (bvsge .cse162 (_ bv0 32))) (= .cse4 .cse161)))))) (= .cse164 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse168 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse165 (concat (concat .cse168 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse169 (bvmul (_ bv4 32) .cse165))) (or (not (bvslt .cse165 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse167 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse166 (bvmul (_ bv4 32) .cse167))) (or (not (bvule (bvadd c_~f~0.offset .cse166) (bvadd c_~f~0.offset (_ bv4 32) .cse166))) (not (bvslt .cse167 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse168 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse169 .cse166) (= .cse166 .cse4))))) (not (bvsge .cse165 (_ bv0 32))) (= .cse169 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse170 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse171 (bvmul (_ bv4 32) .cse170))) (or (not (bvslt .cse170 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse173 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse172 (bvmul (_ bv4 32) .cse173))) (or (= .cse171 .cse172) (not (bvslt .cse173 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse172) (bvadd c_~f~0.offset (_ bv4 32) .cse172))) (not (bvsge .cse173 (_ bv0 32))))))) (not (bvsge .cse170 (_ bv0 32))) (= .cse171 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse174 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse177 (bvmul (_ bv4 32) .cse174))) (or (not (bvslt .cse174 c_~size~0)) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse176 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse175 (bvmul (_ bv4 32) .cse176))) (or (not (bvule (bvadd c_~f~0.offset .cse175) (bvadd c_~f~0.offset (_ bv4 32) .cse175))) (not (bvslt .cse176 c_~size~0)) (not (bvsge .cse176 (_ bv0 32))) (= .cse177 .cse175))))) (not (bvsge .cse174 (_ bv0 32))) (= .cse177 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse178 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse178 c_~size~0)) (= .cse178 c_~x1~0) (not (bvsge .cse178 (_ bv0 32)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse179 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse182 (bvmul (_ bv4 32) .cse179))) (or (not (bvslt .cse179 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse181 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse180 (bvmul .cse181 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse180) (bvadd c_~f~0.offset (_ bv4 32) .cse180))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse181 c_~size~0)) (= .cse182 .cse180) (not (bvsge .cse181 (_ bv0 32))) (= .cse4 .cse180))))) (not (bvsge .cse179 (_ bv0 32))) (= .cse182 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse183 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse186 (bvmul (_ bv4 32) .cse183))) (or (not (bvslt .cse183 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse185 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse184 (bvmul .cse185 (_ bv4 32)))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse184) (bvadd c_~f~0.offset (_ bv4 32) .cse184))) (not (bvslt .cse185 c_~size~0)) (= .cse186 .cse184) (not (bvsge .cse185 (_ bv0 32))) (= .cse4 .cse184))))) (not (bvsge .cse183 (_ bv0 32))) (= .cse186 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse187 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse190 (bvmul (_ bv4 32) .cse187))) (or (not (bvslt .cse187 c_~size~0)) (not (bvsge .cse187 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse189 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse188 (bvmul .cse189 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse188) (bvadd c_~f~0.offset (_ bv4 32) .cse188))) (not (bvslt .cse189 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse190 .cse188) (not (bvsge .cse189 (_ bv0 32))) (= .cse4 .cse188))))) (= .cse190 .cse4))))) (or (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) .cse154) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse191 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse194 (bvmul (_ bv4 32) .cse191))) (or (not (bvslt .cse191 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse192 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse193 (bvmul (_ bv4 32) .cse192))) (or (not (bvslt .cse192 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse193) (bvadd c_~f~0.offset (_ bv4 32) .cse193))) (not (bvsge .cse192 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse4 .cse193) (= .cse194 .cse193))))) (not (bvsge .cse191 (_ bv0 32))) (= .cse194 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse195 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse198 (bvmul (_ bv4 32) .cse195))) (or (not (bvslt .cse195 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse196 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse197 (bvmul (_ bv4 32) .cse196))) (or (not (bvslt .cse196 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse197) (bvadd c_~f~0.offset (_ bv4 32) .cse197))) (not (bvsge .cse196 (_ bv0 32))) (= .cse198 .cse197))))) (not (bvsge .cse195 (_ bv0 32))) (= .cse198 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse202 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse200 (bvmul (_ bv4 32) .cse202))) (or (forall ((v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse201 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse199 (bvmul (_ bv4 32) .cse201))) (or (not (bvule (bvadd c_~f~0.offset .cse199) (bvadd c_~f~0.offset (_ bv4 32) .cse199))) (= .cse200 .cse199) (not (bvslt .cse201 c_~size~0)))))) (not (bvslt .cse202 c_~size~0)) (not (bvsge .cse202 (_ bv0 32))) (= .cse200 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse203 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse203 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse203 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse203) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse208 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse204 (concat (concat .cse208 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse206 (bvmul (_ bv4 32) .cse204))) (or (not (bvslt .cse204 c_~size~0)) (not (bvsge .cse204 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse205 (concat (concat .cse208 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse207 (bvmul (_ bv4 32) .cse205))) (or (not (bvslt .cse205 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse206 .cse207) (= .cse4 .cse207) (not (bvule (bvadd c_~f~0.offset .cse207) (bvadd c_~f~0.offset (_ bv4 32) .cse207))))))) (= .cse206 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse209 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse212 (bvmul (_ bv4 32) .cse209))) (or (not (bvslt .cse209 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse211 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse210 (bvmul (_ bv4 32) .cse211))) (or (not (bvule (bvadd c_~f~0.offset .cse210) (bvadd c_~f~0.offset (_ bv4 32) .cse210))) (not (bvsge .cse211 (_ bv0 32))) (not (bvslt .cse211 c_~size~0)) (= .cse212 .cse210))))) (not (bvsge .cse209 (_ bv0 32))) (= .cse212 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse216 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse213 (concat (concat .cse216 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse213 c_~size~0)) (not (bvsge .cse213 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse213) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse215 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse214 (bvmul (_ bv4 32) .cse215))) (or (not (bvule (bvadd c_~f~0.offset .cse214) (bvadd c_~f~0.offset (_ bv4 32) .cse214))) (not (bvslt .cse215 c_~size~0)) (= c_~x1~0 (concat (concat .cse216 v_arrayElimCell_81) v_arrayElimCell_78)) (= .cse214 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse221 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse217 (concat .cse221 v_arrayElimCell_78))) (let ((.cse218 (bvmul (_ bv4 32) .cse217))) (or (not (bvslt .cse217 c_~size~0)) (not (bvsge .cse217 (_ bv0 32))) (= .cse218 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (let ((.cse220 (concat .cse221 v_arrayElimCell_70))) (let ((.cse219 (bvmul (_ bv4 32) .cse220))) (or (= .cse218 .cse219) (not (bvslt .cse220 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse219) (bvadd c_~f~0.offset (_ bv4 32) .cse219)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse222 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse225 (bvmul (_ bv4 32) .cse222))) (or (not (bvslt .cse222 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse223 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse224 (bvmul (_ bv4 32) .cse223))) (or (not (bvslt .cse223 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse224) (bvadd c_~f~0.offset (_ bv4 32) .cse224))) (not (bvsge .cse223 (_ bv0 32))) (= .cse4 .cse224) (= .cse225 .cse224) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)))))) (not (bvsge .cse222 (_ bv0 32))) (= .cse225 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse226 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse228 (bvmul (_ bv4 32) .cse226))) (or (not (bvslt .cse226 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse229 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse227 (bvmul (_ bv4 32) .cse229))) (or (not (bvule (bvadd c_~f~0.offset .cse227) (bvadd c_~f~0.offset (_ bv4 32) .cse227))) (= .cse228 .cse227) (not (bvslt .cse229 c_~size~0)))))) (not (bvsge .cse226 (_ bv0 32))) (= .cse228 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse233 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse232 (bvmul (_ bv4 32) .cse233))) (or (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse230 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse231 (bvmul (_ bv4 32) .cse230))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvslt .cse230 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse231) (bvadd c_~f~0.offset (_ bv4 32) .cse231))) (not (bvsge .cse230 (_ bv0 32))) (= .cse4 .cse231) (= .cse232 .cse231))))) (not (bvslt .cse233 c_~size~0)) (not (bvsge .cse233 (_ bv0 32))) (= .cse232 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse234 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse236 (bvmul (_ bv4 32) .cse234))) (or (not (bvslt .cse234 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse235 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse237 (bvmul (_ bv4 32) .cse235))) (or (not (bvslt .cse235 c_~size~0)) (= .cse236 .cse237) (not (bvule (bvadd c_~f~0.offset .cse237) (bvadd c_~f~0.offset (_ bv4 32) .cse237))) (not (bvsge .cse235 (_ bv0 32))))))) (not (bvsge .cse234 (_ bv0 32))) (= .cse236 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse238 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse239 (bvmul (_ bv4 32) .cse238))) (or (not (bvslt .cse238 c_~size~0)) (not (bvsge .cse238 (_ bv0 32))) (= .cse239 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse240 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse241 (bvmul (_ bv4 32) .cse240))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvslt .cse240 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse241) (bvadd c_~f~0.offset (_ bv4 32) .cse241))) (not (bvsge .cse240 (_ bv0 32))) (= .cse4 .cse241) (= .cse239 .cse241))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse242 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse244 (bvmul (_ bv4 32) .cse242))) (or (not (bvslt .cse242 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse243 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse245 (bvmul .cse243 (_ bv4 32)))) (or (not (bvslt .cse243 c_~size~0)) (= .cse244 .cse245) (= .cse4 .cse245) (not (bvule (bvadd c_~f~0.offset .cse245) (bvadd c_~f~0.offset (_ bv4 32) .cse245))))))) (not (bvsge .cse242 (_ bv0 32))) (= .cse244 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse246 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse246 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse246 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse246) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse251 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse247 (concat (concat .cse251 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse248 (bvmul (_ bv4 32) .cse247))) (or (not (bvslt .cse247 c_~size~0)) (not (bvsge .cse247 (_ bv0 32))) (= .cse248 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse250 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse249 (bvmul .cse250 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse249) (bvadd c_~f~0.offset (_ bv4 32) .cse249))) (not (bvslt .cse250 c_~size~0)) (= .cse248 .cse249) (not (bvsge .cse250 (_ bv0 32))) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse251 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse4 .cse249)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse252 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse255 (bvmul (_ bv4 32) .cse252))) (or (not (bvslt .cse252 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse253 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse254 (bvmul (_ bv4 32) .cse253))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse253 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse254) (bvadd c_~f~0.offset (_ bv4 32) .cse254))) (not (bvsge .cse253 (_ bv0 32))) (= .cse4 .cse254) (= .cse255 .cse254))))) (not (bvsge .cse252 (_ bv0 32))) (= .cse255 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse256 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse257 (bvmul (_ bv4 32) .cse256))) (or (not (bvslt .cse256 c_~size~0)) (not (bvsge .cse256 (_ bv0 32))) (= .cse257 .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse259 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse258 (bvmul (_ bv4 32) .cse259))) (or (not (bvule (bvadd c_~f~0.offset .cse258) (bvadd c_~f~0.offset (_ bv4 32) .cse258))) (not (bvsge .cse259 (_ bv0 32))) (not (bvslt .cse259 c_~size~0)) (= .cse257 .cse258) (= .cse4 .cse258))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse264 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse260 (concat (concat .cse264 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse260 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse263 (concat .cse264 v_arrayElimCell_81))) (let ((.cse261 (concat .cse263 v_arrayElimCell_70))) (let ((.cse262 (bvmul (_ bv4 32) .cse261))) (or (not (bvslt .cse261 c_~size~0)) (= .cse4 .cse262) (not (bvule (bvadd c_~f~0.offset .cse262) (bvadd c_~f~0.offset (_ bv4 32) .cse262))) (= c_~x1~0 (concat .cse263 v_arrayElimCell_78))))))) (not (bvsge .cse260 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse260) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse265 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse268 (bvmul (_ bv4 32) .cse265))) (or (not (bvslt .cse265 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse266 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse267 (bvmul (_ bv4 32) .cse266))) (or (not (bvslt .cse266 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse267) (bvadd c_~f~0.offset (_ bv4 32) .cse267))) (not (bvsge .cse266 (_ bv0 32))) (= .cse4 .cse267) (= .cse268 .cse267))))) (not (bvsge .cse265 (_ bv0 32))) (= .cse268 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse269 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse269 c_~size~0)) (not (bvsge .cse269 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse269) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse270 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse273 (bvmul (_ bv4 32) .cse270))) (or (not (bvslt .cse270 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse271 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse272 (bvmul (_ bv4 32) .cse271))) (or (not (bvslt .cse271 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse272) (bvadd c_~f~0.offset (_ bv4 32) .cse272))) (not (bvsge .cse271 (_ bv0 32))) (= .cse4 .cse272) (= .cse273 .cse272) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))))))) (not (bvsge .cse270 (_ bv0 32))) (= .cse273 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse274 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse276 (bvmul (_ bv4 32) .cse274))) (or (not (bvslt .cse274 c_~size~0)) (not (bvsge .cse274 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse275 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse277 (bvmul .cse275 (_ bv4 32)))) (or (not (bvslt .cse275 c_~size~0)) (= .cse276 .cse277) (not (bvule (bvadd c_~f~0.offset .cse277) (bvadd c_~f~0.offset (_ bv4 32) .cse277))))))) (= .cse276 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse278 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse281 (bvmul (_ bv4 32) .cse278))) (or (not (bvslt .cse278 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse280 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse279 (bvmul .cse280 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse279) (bvadd c_~f~0.offset (_ bv4 32) .cse279))) (not (bvslt .cse280 c_~size~0)) (= .cse281 .cse279) (not (bvsge .cse280 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse4 .cse279))))) (not (bvsge .cse278 (_ bv0 32))) (= .cse281 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse282 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse283 (bvmul (_ bv4 32) .cse282))) (or (not (bvslt .cse282 c_~size~0)) (not (bvsge .cse282 (_ bv0 32))) (= .cse283 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse285 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse284 (bvmul .cse285 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse284) (bvadd c_~f~0.offset (_ bv4 32) .cse284))) (not (bvslt .cse285 c_~size~0)) (= .cse283 .cse284) (not (bvsge .cse285 (_ bv0 32))) (= .cse4 .cse284))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse290 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse286 (concat (concat .cse290 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse287 (bvmul (_ bv4 32) .cse286))) (or (not (bvslt .cse286 c_~size~0)) (not (bvsge .cse286 (_ bv0 32))) (= .cse287 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse288 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse289 (bvmul (_ bv4 32) .cse288))) (or (not (bvslt .cse288 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse289) (bvadd c_~f~0.offset (_ bv4 32) .cse289))) (not (bvsge .cse288 (_ bv0 32))) (= .cse4 .cse289) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse290 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse287 .cse289)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse291 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse294 (bvmul (_ bv4 32) .cse291))) (or (not (bvslt .cse291 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse293 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse292 (bvmul (_ bv4 32) .cse293))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse292) (bvadd c_~f~0.offset (_ bv4 32) .cse292))) (not (bvslt .cse293 c_~size~0)) (= .cse294 .cse292) (= .cse292 .cse4))))) (not (bvsge .cse291 (_ bv0 32))) (= .cse294 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse295 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse296 (bvmul (_ bv4 32) .cse295))) (or (not (bvslt .cse295 c_~size~0)) (not (bvsge .cse295 (_ bv0 32))) (= .cse296 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse298 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse297 (bvmul (_ bv4 32) .cse298))) (or (not (bvule (bvadd c_~f~0.offset .cse297) (bvadd c_~f~0.offset (_ bv4 32) .cse297))) (not (bvslt .cse298 c_~size~0)) (= .cse296 .cse297) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse297 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse299 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse302 (bvmul (_ bv4 32) .cse299))) (or (not (bvslt .cse299 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse301 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse300 (bvmul .cse301 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse300) (bvadd c_~f~0.offset (_ bv4 32) .cse300))) (not (bvslt .cse301 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse302 .cse300) (not (bvsge .cse301 (_ bv0 32))) (= .cse4 .cse300))))) (not (bvsge .cse299 (_ bv0 32))) (= .cse302 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse303 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse306 (bvmul (_ bv4 32) .cse303))) (or (not (bvslt .cse303 c_~size~0)) (not (bvsge .cse303 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse305 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse304 (bvmul (_ bv4 32) .cse305))) (or (not (bvule (bvadd c_~f~0.offset .cse304) (bvadd c_~f~0.offset (_ bv4 32) .cse304))) (not (bvslt .cse305 c_~size~0)) (= .cse306 .cse304) (not (bvsge .cse305 (_ bv0 32))))))) (= .cse306 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse307 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse310 (bvmul (_ bv4 32) .cse307))) (or (not (bvslt .cse307 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse309 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse308 (bvmul (_ bv4 32) .cse309))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse308) (bvadd c_~f~0.offset (_ bv4 32) .cse308))) (not (bvslt .cse309 c_~size~0)) (= .cse310 .cse308) (= .cse308 .cse4))))) (not (bvsge .cse307 (_ bv0 32))) (= .cse310 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse311 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse311 c_~size~0)) (not (bvsge .cse311 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse311) .cse4) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse314 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse312 (concat (concat .cse314 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse312 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse313 (concat (concat .cse314 v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse313) (= .cse4 (bvmul (_ bv4 32) .cse313))))) (not (bvsge .cse312 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse312) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse315 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse318 (bvmul (_ bv4 32) .cse315))) (or (not (bvslt .cse315 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse316 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse317 (bvmul (_ bv4 32) .cse316))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse316 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse317) (bvadd c_~f~0.offset (_ bv4 32) .cse317))) (not (bvsge .cse316 (_ bv0 32))) (= .cse4 .cse317) (= .cse318 .cse317))))) (not (bvsge .cse315 (_ bv0 32))) (= .cse318 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse319 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse319 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse320 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse320) (= (bvmul (_ bv4 32) .cse320) .cse4)))) (not (bvsge .cse319 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse319) .cse4))))))) (not (bvslt c_~x2~0 c_~size~0))) (bvule |c_ULTIMATE.start_create_fresh_int_array_~size#1| (_ bv1073741823 32)) (= c_~f~0.offset (_ bv0 32))) is different from true [2022-11-18 21:14:19,664 WARN L859 $PredicateComparison]: unable to prove that (and (not (bvslt (_ bv1 32) c_~size~0)) (= c_~x2~0 (_ bv0 32)) (= c_~x1~0 (_ bv0 32)) (bvsgt c_~size~0 (_ bv0 32)) (or (not (bvsge c_~x2~0 (_ bv0 32))) (let ((.cse4 (bvmul c_~x2~0 (_ bv4 32)))) (let ((.cse154 (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse321 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse321 c_~size~0)) (not (bvsge .cse321 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse321) .cse4)))))) (and (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse3 (bvmul (_ bv4 32) .cse0))) (or (not (bvslt .cse0 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse2 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse1 (bvmul .cse2 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse1) (bvadd c_~f~0.offset (_ bv4 32) .cse1))) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse2 c_~size~0)) (= .cse3 .cse1) (not (bvsge .cse2 (_ bv0 32))) (= .cse4 .cse1))))) (not (bvsge .cse0 (_ bv0 32))) (= .cse3 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse5 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse5 c_~size~0)) (not (bvsge .cse5 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse5) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse6 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse9 (bvmul (_ bv4 32) .cse6))) (or (not (bvslt .cse6 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse8 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse7 (bvmul (_ bv4 32) .cse8))) (or (not (bvule (bvadd c_~f~0.offset .cse7) (bvadd c_~f~0.offset (_ bv4 32) .cse7))) (not (bvslt .cse8 c_~size~0)) (= .cse9 .cse7))))) (not (bvsge .cse6 (_ bv0 32))) (= .cse9 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse13 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse10 (concat (concat .cse13 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse10 c_~size~0)) (not (bvsge .cse10 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse10) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse12 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse11 (bvmul .cse12 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse11) (bvadd c_~f~0.offset (_ bv4 32) .cse11))) (not (bvslt .cse12 c_~size~0)) (not (bvsge .cse12 (_ bv0 32))) (= .cse4 .cse11) (= c_~x1~0 (concat (concat .cse13 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse14 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse15 (bvmul (_ bv4 32) .cse14))) (or (not (bvslt .cse14 c_~size~0)) (not (bvsge .cse14 (_ bv0 32))) (= .cse15 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse17 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse16 (bvmul .cse17 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse16) (bvadd c_~f~0.offset (_ bv4 32) .cse16))) (not (bvslt .cse17 c_~size~0)) (= .cse15 .cse16) (not (bvsge .cse17 (_ bv0 32))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse18 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse21 (bvmul (_ bv4 32) .cse18))) (or (not (bvslt .cse18 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse20 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse19 (bvmul (_ bv4 32) .cse20))) (or (not (bvule (bvadd c_~f~0.offset .cse19) (bvadd c_~f~0.offset (_ bv4 32) .cse19))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse20 c_~size~0)) (= .cse21 .cse19) (= .cse19 .cse4))))) (not (bvsge .cse18 (_ bv0 32))) (= .cse21 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse24 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse22 (concat (concat .cse24 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse22 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse23 (concat (concat .cse24 v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse4 (bvmul (_ bv4 32) .cse23)) (= c_~x1~0 .cse23)))) (not (bvsge .cse22 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse22) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse25 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse25 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse25 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse25) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse27 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse26 (concat (concat .cse27 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse26 c_~size~0)) (not (bvsge .cse26 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse26) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse27 v_arrayElimCell_81) v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse31 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse28 (concat (concat .cse31 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse28 c_~size~0)) (not (bvsge .cse28 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse28) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse29 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse30 (bvmul (_ bv4 32) .cse29))) (or (not (bvslt .cse29 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse30) (bvadd c_~f~0.offset (_ bv4 32) .cse30))) (not (bvsge .cse29 (_ bv0 32))) (= .cse4 .cse30) (= c_~x1~0 (concat (concat .cse31 v_arrayElimCell_81) v_arrayElimCell_78)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse33 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse32 (concat .cse33 v_arrayElimCell_78))) (or (not (bvslt .cse32 c_~size~0)) (not (bvsge .cse32 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse32) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (= c_~x1~0 (concat .cse33 v_arrayElimCell_70))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse34 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse34 c_~size~0)) (not (bvsge .cse34 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse35 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse35 c_~x1~0) (= .cse4 (bvmul .cse35 (_ bv4 32)))))) (= (bvmul (_ bv4 32) .cse34) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse40 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse36 (concat (concat .cse40 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse39 (bvmul (_ bv4 32) .cse36))) (or (not (bvslt .cse36 c_~size~0)) (not (bvsge .cse36 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse38 (concat (concat .cse40 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse37 (bvmul (_ bv4 32) .cse38))) (or (not (bvule (bvadd c_~f~0.offset .cse37) (bvadd c_~f~0.offset (_ bv4 32) .cse37))) (= .cse4 .cse37) (not (bvslt .cse38 c_~size~0)) (= .cse39 .cse37))))) (= .cse39 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse45 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse41 (concat (concat .cse45 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse43 (bvmul (_ bv4 32) .cse41))) (or (not (bvslt .cse41 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse42 (concat (concat .cse45 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse44 (bvmul (_ bv4 32) .cse42))) (or (not (bvslt .cse42 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse43 .cse44) (= .cse4 .cse44) (not (bvule (bvadd c_~f~0.offset .cse44) (bvadd c_~f~0.offset (_ bv4 32) .cse44))))))) (not (bvsge .cse41 (_ bv0 32))) (= .cse43 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse50 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse46 (concat (concat .cse50 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse47 (bvmul (_ bv4 32) .cse46))) (or (not (bvslt .cse46 c_~size~0)) (not (bvsge .cse46 (_ bv0 32))) (= .cse47 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse48 (concat (concat .cse50 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse49 (bvmul (_ bv4 32) .cse48))) (or (not (bvslt .cse48 c_~size~0)) (= .cse47 .cse49) (= .cse4 .cse49) (not (bvule (bvadd c_~f~0.offset .cse49) (bvadd c_~f~0.offset (_ bv4 32) .cse49)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse56 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse51 (concat (concat .cse56 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse53 (bvmul (_ bv4 32) .cse51))) (or (not (bvslt .cse51 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse55 (concat .cse56 v_arrayElimCell_81))) (let ((.cse52 (concat .cse55 v_arrayElimCell_70))) (let ((.cse54 (bvmul (_ bv4 32) .cse52))) (or (not (bvslt .cse52 c_~size~0)) (= .cse53 .cse54) (= .cse4 .cse54) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat .cse55 v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse54) (bvadd c_~f~0.offset (_ bv4 32) .cse54)))))))) (not (bvsge .cse51 (_ bv0 32))) (= .cse53 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse61 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse57 (concat (concat .cse61 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse59 (bvmul (_ bv4 32) .cse57))) (or (not (bvslt .cse57 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse58 (concat (concat .cse61 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse60 (bvmul (_ bv4 32) .cse58))) (or (not (bvslt .cse58 c_~size~0)) (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse59 .cse60) (= .cse4 .cse60) (not (bvule (bvadd c_~f~0.offset .cse60) (bvadd c_~f~0.offset (_ bv4 32) .cse60))))))) (not (bvsge .cse57 (_ bv0 32))) (= .cse59 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse66 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse62 (concat (concat .cse66 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse64 (bvmul (_ bv4 32) .cse62))) (or (not (bvslt .cse62 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse63 (concat (concat .cse66 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse65 (bvmul (_ bv4 32) .cse63))) (or (not (bvslt .cse63 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse64 .cse65) (= .cse4 .cse65) (not (bvule (bvadd c_~f~0.offset .cse65) (bvadd c_~f~0.offset (_ bv4 32) .cse65))))))) (not (bvsge .cse62 (_ bv0 32))) (= .cse64 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse67 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse68 (bvmul (_ bv4 32) .cse67))) (or (not (bvslt .cse67 c_~size~0)) (not (bvsge .cse67 (_ bv0 32))) (= .cse68 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse70 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse69 (bvmul (_ bv4 32) .cse70))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse69) (bvadd c_~f~0.offset (_ bv4 32) .cse69))) (not (bvslt .cse70 c_~size~0)) (= .cse68 .cse69) (= .cse69 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse71 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse74 (bvmul (_ bv4 32) .cse71))) (or (not (bvslt .cse71 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse72 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse73 (bvmul (_ bv4 32) .cse72))) (or (not (bvsge .cse72 (_ bv0 32))) (= .cse73 .cse4) (not (bvule (bvadd c_~f~0.offset .cse73) (bvadd c_~f~0.offset .cse73 (_ bv4 32)))) (not (bvslt .cse72 c_~size~0)) (= .cse74 .cse73))))) (not (bvsge .cse71 (_ bv0 32))) (= .cse74 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse75 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse78 (bvmul (_ bv4 32) .cse75))) (or (not (bvslt .cse75 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse76 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse77 (bvmul (_ bv4 32) .cse76))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse76 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse77) (bvadd c_~f~0.offset (_ bv4 32) .cse77))) (not (bvsge .cse76 (_ bv0 32))) (= .cse4 .cse77) (= .cse78 .cse77))))) (not (bvsge .cse75 (_ bv0 32))) (= .cse78 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse79 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse79 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse79 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse79) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse80 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse80 c_~size~0)) (not (bvsge .cse80 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse80) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse81 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse84 (bvmul (_ bv4 32) .cse81))) (or (not (bvslt .cse81 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse83 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse82 (bvmul .cse83 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse82) (bvadd c_~f~0.offset (_ bv4 32) .cse82))) (not (bvslt .cse83 c_~size~0)) (= .cse84 .cse82) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvsge .cse83 (_ bv0 32))) (= .cse4 .cse82))))) (not (bvsge .cse81 (_ bv0 32))) (= .cse84 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse85 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse85 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse86 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= (bvmul (_ bv4 32) .cse86) .cse4) (= c_~x1~0 .cse86)))) (not (bvsge .cse85 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse85) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse87 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse87 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse87 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse87) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse88 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse91 (bvmul (_ bv4 32) .cse88))) (or (not (bvslt .cse88 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse90 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse89 (bvmul (_ bv4 32) .cse90))) (or (not (bvule (bvadd c_~f~0.offset .cse89) (bvadd c_~f~0.offset (_ bv4 32) .cse89))) (not (bvslt .cse90 c_~size~0)) (= .cse91 .cse89) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse89 .cse4))))) (not (bvsge .cse88 (_ bv0 32))) (= .cse91 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse92 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse95 (bvmul (_ bv4 32) .cse92))) (or (not (bvslt .cse92 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse93 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse94 (bvmul (_ bv4 32) .cse93))) (or (not (bvsge .cse93 (_ bv0 32))) (not (bvule (bvadd c_~f~0.offset .cse94) (bvadd c_~f~0.offset .cse94 (_ bv4 32)))) (not (bvslt .cse93 c_~size~0)) (= .cse95 .cse94))))) (not (bvsge .cse92 (_ bv0 32))) (= .cse95 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse96 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse99 (bvmul (_ bv4 32) .cse96))) (or (not (bvslt .cse96 c_~size~0)) (not (bvsge .cse96 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse98 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse97 (bvmul (_ bv4 32) .cse98))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse97) (bvadd c_~f~0.offset (_ bv4 32) .cse97))) (not (bvslt .cse98 c_~size~0)) (= .cse99 .cse97) (= .cse97 .cse4))))) (= .cse99 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse104 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse100 (concat (concat .cse104 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse101 (bvmul (_ bv4 32) .cse100))) (or (not (bvslt .cse100 c_~size~0)) (not (bvsge .cse100 (_ bv0 32))) (= .cse101 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse102 (concat (concat .cse104 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse103 (bvmul (_ bv4 32) .cse102))) (or (not (bvslt .cse102 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse101 .cse103) (= .cse4 .cse103) (not (bvule (bvadd c_~f~0.offset .cse103) (bvadd c_~f~0.offset (_ bv4 32) .cse103)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse105 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse105 c_~size~0)) (not (bvsge .cse105 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse105) .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse106 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= .cse106 c_~x1~0) (= .cse4 (bvmul .cse106 (_ bv4 32))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse111 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse107 (concat (concat .cse111 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse110 (bvmul (_ bv4 32) .cse107))) (or (not (bvslt .cse107 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse109 (concat (concat .cse111 v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse108 (bvmul (_ bv4 32) .cse109))) (or (not (bvule (bvadd c_~f~0.offset .cse108) (bvadd c_~f~0.offset (_ bv4 32) .cse108))) (not (bvslt .cse109 c_~size~0)) (= .cse110 .cse108))))) (not (bvsge .cse107 (_ bv0 32))) (= .cse110 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse112 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse112 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse113 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (or (= c_~x1~0 .cse113) (= .cse4 (bvmul (_ bv4 32) .cse113))))) (not (bvsge .cse112 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse112) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse114 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse118 (bvmul (_ bv4 32) .cse114))) (or (not (bvslt .cse114 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse115 (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse117 (concat .cse115 v_arrayElimCell_70))) (let ((.cse116 (bvmul (_ bv4 32) .cse117))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse115 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse116) (bvadd c_~f~0.offset (_ bv4 32) .cse116))) (not (bvslt .cse117 c_~size~0)) (= .cse118 .cse116) (= .cse116 .cse4)))))) (not (bvsge .cse114 (_ bv0 32))) (= .cse118 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse123 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse119 (concat (concat .cse123 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse121 (bvmul (_ bv4 32) .cse119))) (or (not (bvslt .cse119 c_~size~0)) (not (bvsge .cse119 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse120 (concat (concat .cse123 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse122 (bvmul (_ bv4 32) .cse120))) (or (not (bvslt .cse120 c_~size~0)) (= .cse121 .cse122) (not (bvule (bvadd c_~f~0.offset .cse122) (bvadd c_~f~0.offset (_ bv4 32) .cse122))))))) (= .cse121 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse124 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse127 (bvmul (_ bv4 32) .cse124))) (or (not (bvslt .cse124 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse125 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse126 (bvmul (_ bv4 32) .cse125))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse125 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse126) (bvadd c_~f~0.offset (_ bv4 32) .cse126))) (not (bvsge .cse125 (_ bv0 32))) (= .cse4 .cse126) (= .cse127 .cse126))))) (not (bvsge .cse124 (_ bv0 32))) (= .cse127 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse128 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse131 (bvmul (_ bv4 32) .cse128))) (or (not (bvslt .cse128 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse130 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse129 (bvmul (_ bv4 32) .cse130))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse129) (bvadd c_~f~0.offset (_ bv4 32) .cse129))) (not (bvslt .cse130 c_~size~0)) (= .cse131 .cse129) (= .cse129 .cse4))))) (not (bvsge .cse128 (_ bv0 32))) (= .cse131 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse132 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse132 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse132 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse132) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse134 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse133 (concat (concat .cse134 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse133 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8))) (= c_~x1~0 (concat (concat .cse134 v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse133 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse133) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse135 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse136 (bvmul (_ bv4 32) .cse135))) (or (not (bvslt .cse135 c_~size~0)) (not (bvsge .cse135 (_ bv0 32))) (= .cse136 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse137 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse138 (bvmul (_ bv4 32) .cse137))) (or (not (bvslt .cse137 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse138) (bvadd c_~f~0.offset (_ bv4 32) .cse138))) (not (bvsge .cse137 (_ bv0 32))) (= .cse4 .cse138) (= .cse136 .cse138))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse139 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse139 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70) c_~x1~0)) (not (bvsge .cse139 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse139) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse144 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse140 (concat (concat .cse144 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse142 (bvmul (_ bv4 32) .cse140))) (or (not (bvslt .cse140 c_~size~0)) (not (bvsge .cse140 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse141 (concat (concat .cse144 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse143 (bvmul (_ bv4 32) .cse141))) (or (not (bvslt .cse141 c_~size~0)) (= .cse142 .cse143) (= .cse4 .cse143) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse143) (bvadd c_~f~0.offset (_ bv4 32) .cse143))))))) (= .cse142 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse145 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse148 (bvmul (_ bv4 32) .cse145))) (or (not (bvslt .cse145 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse146 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse147 (bvmul (_ bv4 32) .cse146))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse146 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse147) (bvadd c_~f~0.offset (_ bv4 32) .cse147))) (not (bvsge .cse146 (_ bv0 32))) (= .cse4 .cse147) (= .cse148 .cse147))))) (not (bvsge .cse145 (_ bv0 32))) (= .cse148 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse149 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse153 (bvmul (_ bv4 32) .cse149))) (or (not (bvslt .cse149 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse151 (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81))) (let ((.cse150 (concat .cse151 v_arrayElimCell_70))) (let ((.cse152 (bvmul (_ bv4 32) .cse150))) (or (not (bvslt .cse150 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse151 v_arrayElimCell_77))) (not (bvule (bvadd c_~f~0.offset .cse152) (bvadd c_~f~0.offset (_ bv4 32) .cse152))) (not (bvsge .cse150 (_ bv0 32))) (= .cse4 .cse152) (= .cse153 .cse152)))))) (not (bvsge .cse149 (_ bv0 32))) (= .cse153 .cse4))))) (or .cse154 (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse155 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= .cse4 (bvmul (_ bv4 32) .cse155)) (= c_~x1~0 .cse155))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse156 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse159 (bvmul (_ bv4 32) .cse156))) (or (not (bvslt .cse156 c_~size~0)) (not (bvsge .cse156 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse158 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse157 (bvmul (_ bv4 32) .cse158))) (or (not (bvule (bvadd c_~f~0.offset .cse157) (bvadd c_~f~0.offset (_ bv4 32) .cse157))) (not (bvslt .cse158 c_~size~0)) (= .cse159 .cse157) (= .cse157 .cse4))))) (= .cse159 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse160 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse164 (bvmul (_ bv4 32) .cse160))) (or (not (bvslt .cse160 c_~size~0)) (not (bvsge .cse160 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse163 (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81))) (let ((.cse162 (concat .cse163 v_arrayElimCell_70))) (let ((.cse161 (bvmul .cse162 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse161) (bvadd c_~f~0.offset (_ bv4 32) .cse161))) (not (bvslt .cse162 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat .cse163 v_arrayElimCell_77))) (= .cse164 .cse161) (not (bvsge .cse162 (_ bv0 32))) (= .cse4 .cse161)))))) (= .cse164 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse168 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse165 (concat (concat .cse168 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse169 (bvmul (_ bv4 32) .cse165))) (or (not (bvslt .cse165 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse167 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse166 (bvmul (_ bv4 32) .cse167))) (or (not (bvule (bvadd c_~f~0.offset .cse166) (bvadd c_~f~0.offset (_ bv4 32) .cse166))) (not (bvslt .cse167 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse168 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse169 .cse166) (= .cse166 .cse4))))) (not (bvsge .cse165 (_ bv0 32))) (= .cse169 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse170 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse171 (bvmul (_ bv4 32) .cse170))) (or (not (bvslt .cse170 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse173 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse172 (bvmul (_ bv4 32) .cse173))) (or (= .cse171 .cse172) (not (bvslt .cse173 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse172) (bvadd c_~f~0.offset (_ bv4 32) .cse172))) (not (bvsge .cse173 (_ bv0 32))))))) (not (bvsge .cse170 (_ bv0 32))) (= .cse171 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse174 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse177 (bvmul (_ bv4 32) .cse174))) (or (not (bvslt .cse174 c_~size~0)) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse176 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse175 (bvmul (_ bv4 32) .cse176))) (or (not (bvule (bvadd c_~f~0.offset .cse175) (bvadd c_~f~0.offset (_ bv4 32) .cse175))) (not (bvslt .cse176 c_~size~0)) (not (bvsge .cse176 (_ bv0 32))) (= .cse177 .cse175))))) (not (bvsge .cse174 (_ bv0 32))) (= .cse177 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse178 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse178 c_~size~0)) (= .cse178 c_~x1~0) (not (bvsge .cse178 (_ bv0 32)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse179 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse182 (bvmul (_ bv4 32) .cse179))) (or (not (bvslt .cse179 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse181 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse180 (bvmul .cse181 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse180) (bvadd c_~f~0.offset (_ bv4 32) .cse180))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse181 c_~size~0)) (= .cse182 .cse180) (not (bvsge .cse181 (_ bv0 32))) (= .cse4 .cse180))))) (not (bvsge .cse179 (_ bv0 32))) (= .cse182 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse183 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse186 (bvmul (_ bv4 32) .cse183))) (or (not (bvslt .cse183 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse185 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse184 (bvmul .cse185 (_ bv4 32)))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse184) (bvadd c_~f~0.offset (_ bv4 32) .cse184))) (not (bvslt .cse185 c_~size~0)) (= .cse186 .cse184) (not (bvsge .cse185 (_ bv0 32))) (= .cse4 .cse184))))) (not (bvsge .cse183 (_ bv0 32))) (= .cse186 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse187 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse190 (bvmul (_ bv4 32) .cse187))) (or (not (bvslt .cse187 c_~size~0)) (not (bvsge .cse187 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse189 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse188 (bvmul .cse189 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse188) (bvadd c_~f~0.offset (_ bv4 32) .cse188))) (not (bvslt .cse189 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse190 .cse188) (not (bvsge .cse189 (_ bv0 32))) (= .cse4 .cse188))))) (= .cse190 .cse4))))) (or (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) .cse154) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse191 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse194 (bvmul (_ bv4 32) .cse191))) (or (not (bvslt .cse191 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse192 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse193 (bvmul (_ bv4 32) .cse192))) (or (not (bvslt .cse192 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse193) (bvadd c_~f~0.offset (_ bv4 32) .cse193))) (not (bvsge .cse192 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse4 .cse193) (= .cse194 .cse193))))) (not (bvsge .cse191 (_ bv0 32))) (= .cse194 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse195 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse198 (bvmul (_ bv4 32) .cse195))) (or (not (bvslt .cse195 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse196 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse197 (bvmul (_ bv4 32) .cse196))) (or (not (bvslt .cse196 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse197) (bvadd c_~f~0.offset (_ bv4 32) .cse197))) (not (bvsge .cse196 (_ bv0 32))) (= .cse198 .cse197))))) (not (bvsge .cse195 (_ bv0 32))) (= .cse198 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse202 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse200 (bvmul (_ bv4 32) .cse202))) (or (forall ((v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse201 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse199 (bvmul (_ bv4 32) .cse201))) (or (not (bvule (bvadd c_~f~0.offset .cse199) (bvadd c_~f~0.offset (_ bv4 32) .cse199))) (= .cse200 .cse199) (not (bvslt .cse201 c_~size~0)))))) (not (bvslt .cse202 c_~size~0)) (not (bvsge .cse202 (_ bv0 32))) (= .cse200 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse203 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse203 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvsge .cse203 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse203) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse208 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse204 (concat (concat .cse208 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse206 (bvmul (_ bv4 32) .cse204))) (or (not (bvslt .cse204 c_~size~0)) (not (bvsge .cse204 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse205 (concat (concat .cse208 v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse207 (bvmul (_ bv4 32) .cse205))) (or (not (bvslt .cse205 c_~size~0)) (forall ((v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77))) (= .cse206 .cse207) (= .cse4 .cse207) (not (bvule (bvadd c_~f~0.offset .cse207) (bvadd c_~f~0.offset (_ bv4 32) .cse207))))))) (= .cse206 .cse4)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse209 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse212 (bvmul (_ bv4 32) .cse209))) (or (not (bvslt .cse209 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse211 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse210 (bvmul (_ bv4 32) .cse211))) (or (not (bvule (bvadd c_~f~0.offset .cse210) (bvadd c_~f~0.offset (_ bv4 32) .cse210))) (not (bvsge .cse211 (_ bv0 32))) (not (bvslt .cse211 c_~size~0)) (= .cse212 .cse210))))) (not (bvsge .cse209 (_ bv0 32))) (= .cse212 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse216 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse213 (concat (concat .cse216 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse213 c_~size~0)) (not (bvsge .cse213 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse213) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse215 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse214 (bvmul (_ bv4 32) .cse215))) (or (not (bvule (bvadd c_~f~0.offset .cse214) (bvadd c_~f~0.offset (_ bv4 32) .cse214))) (not (bvslt .cse215 c_~size~0)) (= c_~x1~0 (concat (concat .cse216 v_arrayElimCell_81) v_arrayElimCell_78)) (= .cse214 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse221 (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79))) (let ((.cse217 (concat .cse221 v_arrayElimCell_78))) (let ((.cse218 (bvmul (_ bv4 32) .cse217))) (or (not (bvslt .cse217 c_~size~0)) (not (bvsge .cse217 (_ bv0 32))) (= .cse218 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8))) (let ((.cse220 (concat .cse221 v_arrayElimCell_70))) (let ((.cse219 (bvmul (_ bv4 32) .cse220))) (or (= .cse218 .cse219) (not (bvslt .cse220 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse219) (bvadd c_~f~0.offset (_ bv4 32) .cse219)))))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse222 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse225 (bvmul (_ bv4 32) .cse222))) (or (not (bvslt .cse222 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse223 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse224 (bvmul (_ bv4 32) .cse223))) (or (not (bvslt .cse223 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse224) (bvadd c_~f~0.offset (_ bv4 32) .cse224))) (not (bvsge .cse223 (_ bv0 32))) (= .cse4 .cse224) (= .cse225 .cse224) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)))))) (not (bvsge .cse222 (_ bv0 32))) (= .cse225 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse226 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse228 (bvmul (_ bv4 32) .cse226))) (or (not (bvslt .cse226 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse229 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse227 (bvmul (_ bv4 32) .cse229))) (or (not (bvule (bvadd c_~f~0.offset .cse227) (bvadd c_~f~0.offset (_ bv4 32) .cse227))) (= .cse228 .cse227) (not (bvslt .cse229 c_~size~0)))))) (not (bvsge .cse226 (_ bv0 32))) (= .cse228 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse233 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse232 (bvmul (_ bv4 32) .cse233))) (or (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse230 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse231 (bvmul (_ bv4 32) .cse230))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvslt .cse230 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse231) (bvadd c_~f~0.offset (_ bv4 32) .cse231))) (not (bvsge .cse230 (_ bv0 32))) (= .cse4 .cse231) (= .cse232 .cse231))))) (not (bvslt .cse233 c_~size~0)) (not (bvsge .cse233 (_ bv0 32))) (= .cse232 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse234 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse236 (bvmul (_ bv4 32) .cse234))) (or (not (bvslt .cse234 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse235 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse237 (bvmul (_ bv4 32) .cse235))) (or (not (bvslt .cse235 c_~size~0)) (= .cse236 .cse237) (not (bvule (bvadd c_~f~0.offset .cse237) (bvadd c_~f~0.offset (_ bv4 32) .cse237))) (not (bvsge .cse235 (_ bv0 32))))))) (not (bvsge .cse234 (_ bv0 32))) (= .cse236 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse238 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse239 (bvmul (_ bv4 32) .cse238))) (or (not (bvslt .cse238 c_~size~0)) (not (bvsge .cse238 (_ bv0 32))) (= .cse239 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse240 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse241 (bvmul (_ bv4 32) .cse240))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (not (bvslt .cse240 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse241) (bvadd c_~f~0.offset (_ bv4 32) .cse241))) (not (bvsge .cse240 (_ bv0 32))) (= .cse4 .cse241) (= .cse239 .cse241))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse242 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse244 (bvmul (_ bv4 32) .cse242))) (or (not (bvslt .cse242 c_~size~0)) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse243 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse245 (bvmul .cse243 (_ bv4 32)))) (or (not (bvslt .cse243 c_~size~0)) (= .cse244 .cse245) (= .cse4 .cse245) (not (bvule (bvadd c_~f~0.offset .cse245) (bvadd c_~f~0.offset (_ bv4 32) .cse245))))))) (not (bvsge .cse242 (_ bv0 32))) (= .cse244 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse246 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse246 c_~size~0)) (forall ((v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_78))) (not (bvsge .cse246 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse246) .cse4)))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse251 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse247 (concat (concat .cse251 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse248 (bvmul (_ bv4 32) .cse247))) (or (not (bvslt .cse247 c_~size~0)) (not (bvsge .cse247 (_ bv0 32))) (= .cse248 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse250 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse249 (bvmul .cse250 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse249) (bvadd c_~f~0.offset (_ bv4 32) .cse249))) (not (bvslt .cse250 c_~size~0)) (= .cse248 .cse249) (not (bvsge .cse250 (_ bv0 32))) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse251 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse4 .cse249)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse252 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse255 (bvmul (_ bv4 32) .cse252))) (or (not (bvslt .cse252 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse253 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse254 (bvmul (_ bv4 32) .cse253))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvslt .cse253 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse254) (bvadd c_~f~0.offset (_ bv4 32) .cse254))) (not (bvsge .cse253 (_ bv0 32))) (= .cse4 .cse254) (= .cse255 .cse254))))) (not (bvsge .cse252 (_ bv0 32))) (= .cse255 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse256 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse257 (bvmul (_ bv4 32) .cse256))) (or (not (bvslt .cse256 c_~size~0)) (not (bvsge .cse256 (_ bv0 32))) (= .cse257 .cse4) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse259 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse258 (bvmul (_ bv4 32) .cse259))) (or (not (bvule (bvadd c_~f~0.offset .cse258) (bvadd c_~f~0.offset (_ bv4 32) .cse258))) (not (bvsge .cse259 (_ bv0 32))) (not (bvslt .cse259 c_~size~0)) (= .cse257 .cse258) (= .cse4 .cse258))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse264 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse260 (concat (concat .cse264 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse260 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse263 (concat .cse264 v_arrayElimCell_81))) (let ((.cse261 (concat .cse263 v_arrayElimCell_70))) (let ((.cse262 (bvmul (_ bv4 32) .cse261))) (or (not (bvslt .cse261 c_~size~0)) (= .cse4 .cse262) (not (bvule (bvadd c_~f~0.offset .cse262) (bvadd c_~f~0.offset (_ bv4 32) .cse262))) (= c_~x1~0 (concat .cse263 v_arrayElimCell_78))))))) (not (bvsge .cse260 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse260) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse265 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse268 (bvmul (_ bv4 32) .cse265))) (or (not (bvslt .cse265 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse266 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse267 (bvmul (_ bv4 32) .cse266))) (or (not (bvslt .cse266 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse267) (bvadd c_~f~0.offset (_ bv4 32) .cse267))) (not (bvsge .cse266 (_ bv0 32))) (= .cse4 .cse267) (= .cse268 .cse267))))) (not (bvsge .cse265 (_ bv0 32))) (= .cse268 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse269 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse269 c_~size~0)) (not (bvsge .cse269 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse269) .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70)))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse270 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse273 (bvmul (_ bv4 32) .cse270))) (or (not (bvslt .cse270 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse271 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse272 (bvmul (_ bv4 32) .cse271))) (or (not (bvslt .cse271 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse272) (bvadd c_~f~0.offset (_ bv4 32) .cse272))) (not (bvsge .cse271 (_ bv0 32))) (= .cse4 .cse272) (= .cse273 .cse272) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))))))) (not (bvsge .cse270 (_ bv0 32))) (= .cse273 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse274 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse276 (bvmul (_ bv4 32) .cse274))) (or (not (bvslt .cse274 c_~size~0)) (not (bvsge .cse274 (_ bv0 32))) (forall ((v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse275 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_78))) (let ((.cse277 (bvmul .cse275 (_ bv4 32)))) (or (not (bvslt .cse275 c_~size~0)) (= .cse276 .cse277) (not (bvule (bvadd c_~f~0.offset .cse277) (bvadd c_~f~0.offset (_ bv4 32) .cse277))))))) (= .cse276 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse278 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse281 (bvmul (_ bv4 32) .cse278))) (or (not (bvslt .cse278 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse280 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse279 (bvmul .cse280 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse279) (bvadd c_~f~0.offset (_ bv4 32) .cse279))) (not (bvslt .cse280 c_~size~0)) (= .cse281 .cse279) (not (bvsge .cse280 (_ bv0 32))) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse4 .cse279))))) (not (bvsge .cse278 (_ bv0 32))) (= .cse281 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse282 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse283 (bvmul (_ bv4 32) .cse282))) (or (not (bvslt .cse282 c_~size~0)) (not (bvsge .cse282 (_ bv0 32))) (= .cse283 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse285 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse284 (bvmul .cse285 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse284) (bvadd c_~f~0.offset (_ bv4 32) .cse284))) (not (bvslt .cse285 c_~size~0)) (= .cse283 .cse284) (not (bvsge .cse285 (_ bv0 32))) (= .cse4 .cse284))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse290 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse286 (concat (concat .cse290 v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse287 (bvmul (_ bv4 32) .cse286))) (or (not (bvslt .cse286 c_~size~0)) (not (bvsge .cse286 (_ bv0 32))) (= .cse287 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse288 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse289 (bvmul (_ bv4 32) .cse288))) (or (not (bvslt .cse288 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse289) (bvadd c_~f~0.offset (_ bv4 32) .cse289))) (not (bvsge .cse288 (_ bv0 32))) (= .cse4 .cse289) (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= (concat (concat .cse290 v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (= .cse287 .cse289)))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse291 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse294 (bvmul (_ bv4 32) .cse291))) (or (not (bvslt .cse291 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse293 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse292 (bvmul (_ bv4 32) .cse293))) (or (forall ((v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (not (bvule (bvadd c_~f~0.offset .cse292) (bvadd c_~f~0.offset (_ bv4 32) .cse292))) (not (bvslt .cse293 c_~size~0)) (= .cse294 .cse292) (= .cse292 .cse4))))) (not (bvsge .cse291 (_ bv0 32))) (= .cse294 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse295 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse296 (bvmul (_ bv4 32) .cse295))) (or (not (bvslt .cse295 c_~size~0)) (not (bvsge .cse295 (_ bv0 32))) (= .cse296 .cse4) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse298 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse297 (bvmul (_ bv4 32) .cse298))) (or (not (bvule (bvadd c_~f~0.offset .cse297) (bvadd c_~f~0.offset (_ bv4 32) .cse297))) (not (bvslt .cse298 c_~size~0)) (= .cse296 .cse297) (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_78))) (= .cse297 .cse4))))))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse299 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse302 (bvmul (_ bv4 32) .cse299))) (or (not (bvslt .cse299 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse301 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse300 (bvmul .cse301 (_ bv4 32)))) (or (not (bvule (bvadd c_~f~0.offset .cse300) (bvadd c_~f~0.offset (_ bv4 32) .cse300))) (not (bvslt .cse301 c_~size~0)) (forall ((v_arrayElimCell_76 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_78) c_~x1~0)) (= .cse302 .cse300) (not (bvsge .cse301 (_ bv0 32))) (= .cse4 .cse300))))) (not (bvsge .cse299 (_ bv0 32))) (= .cse302 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse303 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse306 (bvmul (_ bv4 32) .cse303))) (or (not (bvslt .cse303 c_~size~0)) (not (bvsge .cse303 (_ bv0 32))) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse305 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_79) v_arrayElimCell_70))) (let ((.cse304 (bvmul (_ bv4 32) .cse305))) (or (not (bvule (bvadd c_~f~0.offset .cse304) (bvadd c_~f~0.offset (_ bv4 32) .cse304))) (not (bvslt .cse305 c_~size~0)) (= .cse306 .cse304) (not (bvsge .cse305 (_ bv0 32))))))) (= .cse306 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse307 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse310 (bvmul (_ bv4 32) .cse307))) (or (not (bvslt .cse307 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse309 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse308 (bvmul (_ bv4 32) .cse309))) (or (forall ((v_arrayElimCell_76 (_ BitVec 8)) (v_arrayElimCell_77 (_ BitVec 8)) (v_arrayElimCell_80 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_76 v_arrayElimCell_80) v_arrayElimCell_81) v_arrayElimCell_77) c_~x1~0)) (not (bvule (bvadd c_~f~0.offset .cse308) (bvadd c_~f~0.offset (_ bv4 32) .cse308))) (not (bvslt .cse309 c_~size~0)) (= .cse310 .cse308) (= .cse308 .cse4))))) (not (bvsge .cse307 (_ bv0 32))) (= .cse310 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse311 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse311 c_~size~0)) (not (bvsge .cse311 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse311) .cse4) (forall ((v_arrayElimCell_74 (_ BitVec 8))) (= (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78) c_~x1~0))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse314 (concat v_arrayElimCell_71 v_arrayElimCell_75))) (let ((.cse312 (concat (concat .cse314 v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse312 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8))) (let ((.cse313 (concat (concat .cse314 v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse313) (= .cse4 (bvmul (_ bv4 32) .cse313))))) (not (bvsge .cse312 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse312) .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse315 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (let ((.cse318 (bvmul (_ bv4 32) .cse315))) (or (not (bvslt .cse315 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8)) (v_arrayElimCell_74 (_ BitVec 8))) (let ((.cse316 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (let ((.cse317 (bvmul (_ bv4 32) .cse316))) (or (forall ((v_arrayElimCell_77 (_ BitVec 8))) (= c_~x1~0 (concat (concat (concat v_arrayElimCell_74 v_arrayElimCell_75) v_arrayElimCell_81) v_arrayElimCell_77))) (not (bvslt .cse316 c_~size~0)) (not (bvule (bvadd c_~f~0.offset .cse317) (bvadd c_~f~0.offset (_ bv4 32) .cse317))) (not (bvsge .cse316 (_ bv0 32))) (= .cse4 .cse317) (= .cse318 .cse317))))) (not (bvsge .cse315 (_ bv0 32))) (= .cse318 .cse4))))) (forall ((v_arrayElimCell_75 (_ BitVec 8)) (v_arrayElimCell_78 (_ BitVec 8)) (v_arrayElimCell_79 (_ BitVec 8)) (v_arrayElimCell_71 (_ BitVec 8))) (let ((.cse319 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_75) v_arrayElimCell_79) v_arrayElimCell_78))) (or (not (bvslt .cse319 c_~size~0)) (forall ((v_arrayElimCell_70 (_ BitVec 8)) (v_arrayElimCell_81 (_ BitVec 8)) (v_arrayElimCell_72 (_ BitVec 8))) (let ((.cse320 (concat (concat (concat v_arrayElimCell_71 v_arrayElimCell_72) v_arrayElimCell_81) v_arrayElimCell_70))) (or (= c_~x1~0 .cse320) (= (bvmul (_ bv4 32) .cse320) .cse4)))) (not (bvsge .cse319 (_ bv0 32))) (= (bvmul (_ bv4 32) .cse319) .cse4))))))) (not (bvslt c_~x2~0 c_~size~0))) (= c_~f~0.offset (_ bv0 32))) is different from true [2022-11-18 21:14:19,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:19,832 INFO L93 Difference]: Finished difference Result 165 states and 395 transitions. [2022-11-18 21:14:19,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 21:14:19,832 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 2.909090909090909) internal successors, (32), 11 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:19,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:19,833 INFO L225 Difference]: With dead ends: 165 [2022-11-18 21:14:19,833 INFO L226 Difference]: Without dead ends: 154 [2022-11-18 21:14:19,833 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 32.2s TimeCoverageRelationStatistics Valid=43, Invalid=72, Unknown=7, NotChecked=60, Total=182 [2022-11-18 21:14:19,834 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 40 mSDsluCounter, 14 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 17 SdHoareTripleChecker+Invalid, 141 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 94 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:19,834 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 17 Invalid, 141 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 44 Invalid, 0 Unknown, 94 Unchecked, 0.2s Time] [2022-11-18 21:14:19,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2022-11-18 21:14:19,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 133. [2022-11-18 21:14:19,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 131 states have (on average 2.49618320610687) internal successors, (327), 132 states have internal predecessors, (327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:19,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 327 transitions. [2022-11-18 21:14:19,838 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 327 transitions. Word has length 16 [2022-11-18 21:14:19,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:19,838 INFO L495 AbstractCegarLoop]: Abstraction has 133 states and 327 transitions. [2022-11-18 21:14:19,838 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 2.909090909090909) internal successors, (32), 11 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:19,838 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 327 transitions. [2022-11-18 21:14:19,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:19,839 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:19,839 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:19,852 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (32)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:20,042 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:20,043 INFO L420 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:20,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:20,043 INFO L85 PathProgramCache]: Analyzing trace with hash 477229730, now seen corresponding path program 3 times [2022-11-18 21:14:20,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:20,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [393944982] [2022-11-18 21:14:20,044 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:14:20,044 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:20,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:20,050 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:20,058 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (33)] Waiting until timeout for monitored process [2022-11-18 21:14:20,201 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 21:14:20,201 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:20,206 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-18 21:14:20,207 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:20,550 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 19 [2022-11-18 21:14:20,632 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:20,632 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:22,731 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:14:22,739 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:14:23,815 INFO L321 Elim1Store]: treesize reduction 168, result has 22.6 percent of original size [2022-11-18 21:14:23,816 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 169 treesize of output 113 [2022-11-18 21:14:26,998 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:26,998 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:26,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [393944982] [2022-11-18 21:14:26,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [393944982] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:26,999 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:26,999 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:14:26,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852156848] [2022-11-18 21:14:26,999 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:27,000 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:14:27,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:27,000 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:14:27,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=124, Unknown=1, NotChecked=0, Total=182 [2022-11-18 21:14:27,001 INFO L87 Difference]: Start difference. First operand 133 states and 327 transitions. Second operand has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:29,882 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:14:32,249 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, BitVec], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-11-18 21:14:37,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:37,499 INFO L93 Difference]: Finished difference Result 190 states and 437 transitions. [2022-11-18 21:14:37,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-18 21:14:37,501 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:37,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:37,502 INFO L225 Difference]: With dead ends: 190 [2022-11-18 21:14:37,502 INFO L226 Difference]: Without dead ends: 176 [2022-11-18 21:14:37,502 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 8.3s TimeCoverageRelationStatistics Valid=118, Invalid=259, Unknown=3, NotChecked=0, Total=380 [2022-11-18 21:14:37,503 INFO L413 NwaCegarLoop]: 5 mSDtfsCounter, 97 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 187 mSolverCounterSat, 8 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 97 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 284 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 187 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 87 IncrementalHoareTripleChecker+Unchecked, 5.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:37,503 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [97 Valid, 12 Invalid, 284 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 187 Invalid, 2 Unknown, 87 Unchecked, 5.3s Time] [2022-11-18 21:14:37,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2022-11-18 21:14:37,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 137. [2022-11-18 21:14:37,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 137 states, 135 states have (on average 2.5407407407407407) internal successors, (343), 136 states have internal predecessors, (343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:37,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 343 transitions. [2022-11-18 21:14:37,507 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 343 transitions. Word has length 16 [2022-11-18 21:14:37,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:37,508 INFO L495 AbstractCegarLoop]: Abstraction has 137 states and 343 transitions. [2022-11-18 21:14:37,508 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:37,508 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 343 transitions. [2022-11-18 21:14:37,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:37,509 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:37,509 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:37,526 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (33)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:37,722 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:37,722 INFO L420 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:37,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:37,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1048269031, now seen corresponding path program 6 times [2022-11-18 21:14:37,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:37,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1584539727] [2022-11-18 21:14:37,723 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 21:14:37,723 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:37,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:37,724 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:37,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (34)] Waiting until timeout for monitored process [2022-11-18 21:14:37,870 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 2 check-sat command(s) [2022-11-18 21:14:37,870 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:37,875 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:14:37,876 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:37,998 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:37,998 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:38,288 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:38,288 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:38,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1584539727] [2022-11-18 21:14:38,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1584539727] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:38,288 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:38,288 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2022-11-18 21:14:38,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702360352] [2022-11-18 21:14:38,289 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:38,289 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-18 21:14:38,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:38,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-18 21:14:38,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-18 21:14:38,290 INFO L87 Difference]: Start difference. First operand 137 states and 343 transitions. Second operand has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:39,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:39,427 INFO L93 Difference]: Finished difference Result 181 states and 436 transitions. [2022-11-18 21:14:39,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 21:14:39,428 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:39,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:39,429 INFO L225 Difference]: With dead ends: 181 [2022-11-18 21:14:39,429 INFO L226 Difference]: Without dead ends: 181 [2022-11-18 21:14:39,429 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 24 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=52, Invalid=104, Unknown=0, NotChecked=0, Total=156 [2022-11-18 21:14:39,430 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 41 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 155 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 177 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 155 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 19 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:39,430 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 6 Invalid, 177 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 155 Invalid, 0 Unknown, 19 Unchecked, 0.7s Time] [2022-11-18 21:14:39,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2022-11-18 21:14:39,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 137. [2022-11-18 21:14:39,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 137 states, 135 states have (on average 2.5407407407407407) internal successors, (343), 136 states have internal predecessors, (343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:39,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 343 transitions. [2022-11-18 21:14:39,439 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 343 transitions. Word has length 16 [2022-11-18 21:14:39,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:39,440 INFO L495 AbstractCegarLoop]: Abstraction has 137 states and 343 transitions. [2022-11-18 21:14:39,440 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:39,441 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 343 transitions. [2022-11-18 21:14:39,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:39,441 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:39,441 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:39,457 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (34)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:39,653 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:39,653 INFO L420 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:39,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:39,654 INFO L85 PathProgramCache]: Analyzing trace with hash 720241961, now seen corresponding path program 7 times [2022-11-18 21:14:39,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:39,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [800954360] [2022-11-18 21:14:39,654 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 21:14:39,654 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:39,655 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:39,657 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:39,695 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (35)] Waiting until timeout for monitored process [2022-11-18 21:14:39,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:14:39,829 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:14:39,830 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:39,977 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:39,977 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:40,027 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 58 [2022-11-18 21:14:40,034 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 56 [2022-11-18 21:14:40,432 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:40,432 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:40,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [800954360] [2022-11-18 21:14:40,432 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [800954360] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:40,432 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:40,432 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2022-11-18 21:14:40,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204429955] [2022-11-18 21:14:40,433 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:40,433 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-18 21:14:40,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:40,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-18 21:14:40,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2022-11-18 21:14:40,434 INFO L87 Difference]: Start difference. First operand 137 states and 343 transitions. Second operand has 9 states, 9 states have (on average 2.2222222222222223) internal successors, (20), 9 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:41,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:41,009 INFO L93 Difference]: Finished difference Result 211 states and 495 transitions. [2022-11-18 21:14:41,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-18 21:14:41,010 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 2.2222222222222223) internal successors, (20), 9 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:41,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:41,011 INFO L225 Difference]: With dead ends: 211 [2022-11-18 21:14:41,011 INFO L226 Difference]: Without dead ends: 211 [2022-11-18 21:14:41,011 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:14:41,012 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 56 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 144 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 243 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 144 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 98 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:41,012 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [56 Valid, 6 Invalid, 243 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 144 Invalid, 0 Unknown, 98 Unchecked, 0.5s Time] [2022-11-18 21:14:41,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2022-11-18 21:14:41,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 139. [2022-11-18 21:14:41,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 137 states have (on average 2.5693430656934306) internal successors, (352), 138 states have internal predecessors, (352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:41,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 352 transitions. [2022-11-18 21:14:41,016 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 352 transitions. Word has length 16 [2022-11-18 21:14:41,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:41,017 INFO L495 AbstractCegarLoop]: Abstraction has 139 states and 352 transitions. [2022-11-18 21:14:41,017 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 2.2222222222222223) internal successors, (20), 9 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:41,017 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 352 transitions. [2022-11-18 21:14:41,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:41,018 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:41,018 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:41,035 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (35)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:41,230 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:41,230 INFO L420 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:41,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:41,230 INFO L85 PathProgramCache]: Analyzing trace with hash -997042964, now seen corresponding path program 4 times [2022-11-18 21:14:41,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:41,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1773213872] [2022-11-18 21:14:41,231 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 21:14:41,231 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:41,232 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:41,232 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:41,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (36)] Waiting until timeout for monitored process [2022-11-18 21:14:41,374 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 21:14:41,374 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:41,379 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-18 21:14:41,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:41,639 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 21:14:41,640 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 148 treesize of output 104 [2022-11-18 21:14:41,649 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 92 [2022-11-18 21:14:41,658 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 90 [2022-11-18 21:14:41,786 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:41,786 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:43,873 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:14:43,881 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:14:44,642 INFO L321 Elim1Store]: treesize reduction 210, result has 3.2 percent of original size [2022-11-18 21:14:44,642 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 6 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 85 treesize of output 23 [2022-11-18 21:14:44,883 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:44,884 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:44,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1773213872] [2022-11-18 21:14:44,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1773213872] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-18 21:14:44,884 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-18 21:14:44,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 8 [2022-11-18 21:14:44,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534971258] [2022-11-18 21:14:44,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-18 21:14:44,884 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-18 21:14:44,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:44,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-18 21:14:44,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=62, Unknown=1, NotChecked=0, Total=90 [2022-11-18 21:14:44,885 INFO L87 Difference]: Start difference. First operand 139 states and 352 transitions. Second operand has 6 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:48,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:48,540 INFO L93 Difference]: Finished difference Result 186 states and 456 transitions. [2022-11-18 21:14:48,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-18 21:14:48,542 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:48,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:48,543 INFO L225 Difference]: With dead ends: 186 [2022-11-18 21:14:48,543 INFO L226 Difference]: Without dead ends: 181 [2022-11-18 21:14:48,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=37, Invalid=93, Unknown=2, NotChecked=0, Total=132 [2022-11-18 21:14:48,544 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 31 mSDsluCounter, 10 mSDsCounter, 0 mSdLazyCounter, 141 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 14 SdHoareTripleChecker+Invalid, 147 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 141 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:48,544 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [31 Valid, 14 Invalid, 147 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 141 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2022-11-18 21:14:48,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2022-11-18 21:14:48,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 142. [2022-11-18 21:14:48,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 140 states have (on average 2.585714285714286) internal successors, (362), 141 states have internal predecessors, (362), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:48,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 362 transitions. [2022-11-18 21:14:48,554 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 362 transitions. Word has length 16 [2022-11-18 21:14:48,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:48,554 INFO L495 AbstractCegarLoop]: Abstraction has 142 states and 362 transitions. [2022-11-18 21:14:48,554 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:48,555 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 362 transitions. [2022-11-18 21:14:48,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:48,555 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:48,555 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:48,568 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (36)] Ended with exit code 0 [2022-11-18 21:14:48,767 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:48,768 INFO L420 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:48,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:48,768 INFO L85 PathProgramCache]: Analyzing trace with hash -75016763, now seen corresponding path program 8 times [2022-11-18 21:14:48,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:48,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1203921762] [2022-11-18 21:14:48,769 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:14:48,769 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:48,769 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:48,769 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:48,771 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (37)] Waiting until timeout for monitored process [2022-11-18 21:14:48,919 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:14:48,919 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:48,925 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:14:48,926 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:49,054 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:49,054 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:49,247 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:49,247 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:49,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1203921762] [2022-11-18 21:14:49,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1203921762] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:49,248 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:49,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 9 [2022-11-18 21:14:49,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719589278] [2022-11-18 21:14:49,248 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:49,248 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-18 21:14:49,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:49,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-18 21:14:49,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2022-11-18 21:14:49,249 INFO L87 Difference]: Start difference. First operand 142 states and 362 transitions. Second operand has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:50,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:50,355 INFO L93 Difference]: Finished difference Result 193 states and 461 transitions. [2022-11-18 21:14:50,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 21:14:50,356 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:50,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:50,358 INFO L225 Difference]: With dead ends: 193 [2022-11-18 21:14:50,358 INFO L226 Difference]: Without dead ends: 193 [2022-11-18 21:14:50,359 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 28 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=133, Unknown=0, NotChecked=0, Total=210 [2022-11-18 21:14:50,359 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 52 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 202 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 52 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 206 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 202 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:50,359 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [52 Valid, 12 Invalid, 206 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 202 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-11-18 21:14:50,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2022-11-18 21:14:50,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 147. [2022-11-18 21:14:50,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 145 states have (on average 2.5517241379310347) internal successors, (370), 146 states have internal predecessors, (370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:50,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 370 transitions. [2022-11-18 21:14:50,365 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 370 transitions. Word has length 16 [2022-11-18 21:14:50,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:50,365 INFO L495 AbstractCegarLoop]: Abstraction has 147 states and 370 transitions. [2022-11-18 21:14:50,365 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 9 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:50,365 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 370 transitions. [2022-11-18 21:14:50,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:50,366 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:50,366 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:50,383 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (37)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:50,578 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:50,579 INFO L420 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:50,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:50,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1081453181, now seen corresponding path program 9 times [2022-11-18 21:14:50,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:50,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [714978279] [2022-11-18 21:14:50,580 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:14:50,580 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:50,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:50,581 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:50,582 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (38)] Waiting until timeout for monitored process [2022-11-18 21:14:50,735 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 21:14:50,735 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:50,741 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-18 21:14:50,742 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:50,853 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:50,854 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:51,062 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:51,063 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:51,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [714978279] [2022-11-18 21:14:51,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [714978279] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:51,063 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:51,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:14:51,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770041308] [2022-11-18 21:14:51,064 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:51,064 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:14:51,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:51,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:14:51,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:14:51,065 INFO L87 Difference]: Start difference. First operand 147 states and 370 transitions. Second operand has 10 states, 10 states have (on average 2.2) internal successors, (22), 10 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:51,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:14:51,722 INFO L93 Difference]: Finished difference Result 240 states and 609 transitions. [2022-11-18 21:14:51,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 21:14:51,723 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.2) internal successors, (22), 10 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:14:51,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:14:51,727 INFO L225 Difference]: With dead ends: 240 [2022-11-18 21:14:51,727 INFO L226 Difference]: Without dead ends: 234 [2022-11-18 21:14:51,728 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=52, Invalid=104, Unknown=0, NotChecked=0, Total=156 [2022-11-18 21:14:51,731 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 33 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 16 SdHoareTripleChecker+Invalid, 266 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 109 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-18 21:14:51,732 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [33 Valid, 16 Invalid, 266 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 157 Invalid, 0 Unknown, 109 Unchecked, 0.6s Time] [2022-11-18 21:14:51,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2022-11-18 21:14:51,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 148. [2022-11-18 21:14:51,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 146 states have (on average 2.5342465753424657) internal successors, (370), 147 states have internal predecessors, (370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:51,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 370 transitions. [2022-11-18 21:14:51,737 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 370 transitions. Word has length 16 [2022-11-18 21:14:51,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:14:51,738 INFO L495 AbstractCegarLoop]: Abstraction has 148 states and 370 transitions. [2022-11-18 21:14:51,738 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.2) internal successors, (22), 10 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:14:51,738 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 370 transitions. [2022-11-18 21:14:51,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-18 21:14:51,740 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:14:51,740 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:14:51,755 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (38)] Forceful destruction successful, exit code 0 [2022-11-18 21:14:51,952 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:51,953 INFO L420 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:14:51,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:14:51,953 INFO L85 PathProgramCache]: Analyzing trace with hash 1692422778, now seen corresponding path program 5 times [2022-11-18 21:14:51,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:14:51,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1454950525] [2022-11-18 21:14:51,953 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 21:14:51,953 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:14:51,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:14:51,954 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:14:51,968 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (39)] Waiting until timeout for monitored process [2022-11-18 21:14:52,182 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:14:52,182 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:14:52,190 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-18 21:14:52,192 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:14:52,207 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2022-11-18 21:14:52,418 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 34 [2022-11-18 21:14:52,619 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-18 21:14:52,620 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 129 treesize of output 97 [2022-11-18 21:14:52,629 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 85 [2022-11-18 21:14:52,635 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 83 [2022-11-18 21:14:52,740 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:52,740 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:14:54,824 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:14:54,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:14:58,155 INFO L321 Elim1Store]: treesize reduction 168, result has 22.6 percent of original size [2022-11-18 21:14:58,155 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 6 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 172 treesize of output 115 [2022-11-18 21:14:58,179 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 19 [2022-11-18 21:14:59,146 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:14:59,146 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:14:59,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1454950525] [2022-11-18 21:14:59,146 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1454950525] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:14:59,146 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:14:59,146 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:14:59,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64172609] [2022-11-18 21:14:59,146 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:14:59,147 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:14:59,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:14:59,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:14:59,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=141, Unknown=2, NotChecked=0, Total=182 [2022-11-18 21:14:59,148 INFO L87 Difference]: Start difference. First operand 148 states and 370 transitions. Second operand has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:00,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:00,320 INFO L93 Difference]: Finished difference Result 190 states and 460 transitions. [2022-11-18 21:15:00,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-18 21:15:00,321 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-18 21:15:00,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:00,323 INFO L225 Difference]: With dead ends: 190 [2022-11-18 21:15:00,323 INFO L226 Difference]: Without dead ends: 185 [2022-11-18 21:15:00,323 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=71, Invalid=233, Unknown=2, NotChecked=0, Total=306 [2022-11-18 21:15:00,323 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 82 mSDsluCounter, 16 mSDsCounter, 0 mSdLazyCounter, 130 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 82 SdHoareTripleChecker+Valid, 19 SdHoareTripleChecker+Invalid, 275 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 130 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 142 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:00,324 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [82 Valid, 19 Invalid, 275 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 130 Invalid, 0 Unknown, 142 Unchecked, 0.7s Time] [2022-11-18 21:15:00,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2022-11-18 21:15:00,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 150. [2022-11-18 21:15:00,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 148 states have (on average 2.527027027027027) internal successors, (374), 149 states have internal predecessors, (374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:00,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 374 transitions. [2022-11-18 21:15:00,328 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 374 transitions. Word has length 16 [2022-11-18 21:15:00,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:00,329 INFO L495 AbstractCegarLoop]: Abstraction has 150 states and 374 transitions. [2022-11-18 21:15:00,329 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.4615384615384617) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:00,329 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 374 transitions. [2022-11-18 21:15:00,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 21:15:00,330 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:00,330 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:00,342 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (39)] Forceful destruction successful, exit code 0 [2022-11-18 21:15:00,539 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:00,539 INFO L420 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:00,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:00,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1481954643, now seen corresponding path program 6 times [2022-11-18 21:15:00,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:00,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2054163706] [2022-11-18 21:15:00,540 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-18 21:15:00,540 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:00,540 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:00,541 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:00,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (40)] Waiting until timeout for monitored process [2022-11-18 21:15:00,728 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 2 check-sat command(s) [2022-11-18 21:15:00,729 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:15:00,737 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-18 21:15:00,739 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:01,081 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-11-18 21:15:01,095 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-11-18 21:15:01,399 INFO L321 Elim1Store]: treesize reduction 164, result has 7.3 percent of original size [2022-11-18 21:15:01,399 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 6 disjoint index pairs (out of 28 index pairs), introduced 12 new quantified variables, introduced 28 case distinctions, treesize of input 207 treesize of output 103 [2022-11-18 21:15:01,620 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:15:01,620 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:04,336 INFO L321 Elim1Store]: treesize reduction 522, result has 22.4 percent of original size [2022-11-18 21:15:04,337 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 12 select indices, 12 select index equivalence classes, 0 disjoint index pairs (out of 66 index pairs), introduced 16 new quantified variables, introduced 66 case distinctions, treesize of input 475 treesize of output 380 [2022-11-18 21:15:04,378 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 139 [2022-11-18 21:15:04,395 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 139 treesize of output 137 [2022-11-18 21:15:12,021 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:15:12,021 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:15:12,023 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2054163706] [2022-11-18 21:15:12,023 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2054163706] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:15:12,023 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:15:12,023 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:15:12,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082445225] [2022-11-18 21:15:12,024 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:15:12,024 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:15:12,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:15:12,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:15:12,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=137, Unknown=1, NotChecked=0, Total=182 [2022-11-18 21:15:12,025 INFO L87 Difference]: Start difference. First operand 150 states and 374 transitions. Second operand has 14 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 13 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:13,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:13,477 INFO L93 Difference]: Finished difference Result 312 states and 763 transitions. [2022-11-18 21:15:13,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:15:13,478 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 13 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 21:15:13,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:13,479 INFO L225 Difference]: With dead ends: 312 [2022-11-18 21:15:13,480 INFO L226 Difference]: Without dead ends: 177 [2022-11-18 21:15:13,480 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=89, Invalid=216, Unknown=1, NotChecked=0, Total=306 [2022-11-18 21:15:13,480 INFO L413 NwaCegarLoop]: 5 mSDtfsCounter, 95 mSDsluCounter, 35 mSDsCounter, 0 mSdLazyCounter, 180 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 95 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 368 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 169 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:13,481 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [95 Valid, 40 Invalid, 368 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 180 Invalid, 0 Unknown, 169 Unchecked, 1.1s Time] [2022-11-18 21:15:13,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2022-11-18 21:15:13,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 155. [2022-11-18 21:15:13,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155 states, 153 states have (on average 2.3856209150326797) internal successors, (365), 154 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:13,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 365 transitions. [2022-11-18 21:15:13,485 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 365 transitions. Word has length 17 [2022-11-18 21:15:13,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:13,486 INFO L495 AbstractCegarLoop]: Abstraction has 155 states and 365 transitions. [2022-11-18 21:15:13,486 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 13 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:13,486 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 365 transitions. [2022-11-18 21:15:13,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 21:15:13,487 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:13,487 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:13,503 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (40)] Forceful destruction successful, exit code 0 [2022-11-18 21:15:13,699 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:13,699 INFO L420 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:13,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:13,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1585990579, now seen corresponding path program 7 times [2022-11-18 21:15:13,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:13,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [314907628] [2022-11-18 21:15:13,700 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-18 21:15:13,700 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:13,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:13,701 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:13,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (41)] Waiting until timeout for monitored process [2022-11-18 21:15:13,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:15:13,872 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:15:13,874 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:14,023 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:14,023 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:14,262 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:15:14,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [314907628] [2022-11-18 21:15:14,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [314907628] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:15:14,263 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:15:14,263 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:15:14,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276459617] [2022-11-18 21:15:14,263 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:15:14,263 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:15:14,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:15:14,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:15:14,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:15:14,264 INFO L87 Difference]: Start difference. First operand 155 states and 365 transitions. Second operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:15,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:15,804 INFO L93 Difference]: Finished difference Result 281 states and 630 transitions. [2022-11-18 21:15:15,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-11-18 21:15:15,805 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 21:15:15,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:15,807 INFO L225 Difference]: With dead ends: 281 [2022-11-18 21:15:15,807 INFO L226 Difference]: Without dead ends: 269 [2022-11-18 21:15:15,807 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=87, Invalid=219, Unknown=0, NotChecked=0, Total=306 [2022-11-18 21:15:15,808 INFO L413 NwaCegarLoop]: 7 mSDtfsCounter, 105 mSDsluCounter, 14 mSDsCounter, 0 mSdLazyCounter, 308 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 105 SdHoareTripleChecker+Valid, 21 SdHoareTripleChecker+Invalid, 319 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 308 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:15,808 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [105 Valid, 21 Invalid, 319 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 308 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2022-11-18 21:15:15,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2022-11-18 21:15:15,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 179. [2022-11-18 21:15:15,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 177 states have (on average 2.5028248587570623) internal successors, (443), 178 states have internal predecessors, (443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:15,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 443 transitions. [2022-11-18 21:15:15,814 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 443 transitions. Word has length 17 [2022-11-18 21:15:15,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:15,814 INFO L495 AbstractCegarLoop]: Abstraction has 179 states and 443 transitions. [2022-11-18 21:15:15,814 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:15,815 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 443 transitions. [2022-11-18 21:15:15,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 21:15:15,815 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:15,816 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:15,832 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (41)] Forceful destruction successful, exit code 0 [2022-11-18 21:15:16,028 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:16,028 INFO L420 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:16,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:16,029 INFO L85 PathProgramCache]: Analyzing trace with hash -802651457, now seen corresponding path program 8 times [2022-11-18 21:15:16,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:16,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1497825128] [2022-11-18 21:15:16,029 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:15:16,029 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:16,029 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:16,030 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:16,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (42)] Waiting until timeout for monitored process [2022-11-18 21:15:16,194 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:15:16,194 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:15:16,200 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:15:16,201 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:16,391 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:16,391 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:16,699 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:16,700 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:15:16,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1497825128] [2022-11-18 21:15:16,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1497825128] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:15:16,700 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:15:16,700 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:15:16,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664340539] [2022-11-18 21:15:16,703 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:15:16,703 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:15:16,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:15:16,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:15:16,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:15:16,706 INFO L87 Difference]: Start difference. First operand 179 states and 443 transitions. Second operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:19,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:19,037 INFO L93 Difference]: Finished difference Result 313 states and 694 transitions. [2022-11-18 21:15:19,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-18 21:15:19,039 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 21:15:19,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:19,040 INFO L225 Difference]: With dead ends: 313 [2022-11-18 21:15:19,041 INFO L226 Difference]: Without dead ends: 311 [2022-11-18 21:15:19,041 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=92, Invalid=288, Unknown=0, NotChecked=0, Total=380 [2022-11-18 21:15:19,041 INFO L413 NwaCegarLoop]: 7 mSDtfsCounter, 90 mSDsluCounter, 11 mSDsCounter, 0 mSdLazyCounter, 369 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 90 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 386 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 369 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:19,041 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [90 Valid, 18 Invalid, 386 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 369 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2022-11-18 21:15:19,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311 states. [2022-11-18 21:15:19,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 181. [2022-11-18 21:15:19,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 181 states, 179 states have (on average 2.536312849162011) internal successors, (454), 180 states have internal predecessors, (454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:19,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 454 transitions. [2022-11-18 21:15:19,048 INFO L78 Accepts]: Start accepts. Automaton has 181 states and 454 transitions. Word has length 17 [2022-11-18 21:15:19,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:19,048 INFO L495 AbstractCegarLoop]: Abstraction has 181 states and 454 transitions. [2022-11-18 21:15:19,048 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:19,048 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 454 transitions. [2022-11-18 21:15:19,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-11-18 21:15:19,049 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:19,049 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:19,067 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (42)] Forceful destruction successful, exit code 0 [2022-11-18 21:15:19,249 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:19,250 INFO L420 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:19,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:19,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1663904571, now seen corresponding path program 9 times [2022-11-18 21:15:19,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:19,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1794691072] [2022-11-18 21:15:19,250 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:15:19,250 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:19,251 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:19,251 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:19,252 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (43)] Waiting until timeout for monitored process [2022-11-18 21:15:19,410 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 21:15:19,410 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:15:19,416 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:15:19,417 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:19,563 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:19,563 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:19,930 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:19,930 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:15:19,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1794691072] [2022-11-18 21:15:19,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1794691072] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:15:19,930 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:15:19,930 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 10 [2022-11-18 21:15:19,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147131202] [2022-11-18 21:15:19,930 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:15:19,931 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-18 21:15:19,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:15:19,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-18 21:15:19,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2022-11-18 21:15:19,931 INFO L87 Difference]: Start difference. First operand 181 states and 454 transitions. Second operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:21,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:21,364 INFO L93 Difference]: Finished difference Result 233 states and 542 transitions. [2022-11-18 21:15:21,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-18 21:15:21,365 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-11-18 21:15:21,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:21,367 INFO L225 Difference]: With dead ends: 233 [2022-11-18 21:15:21,367 INFO L226 Difference]: Without dead ends: 213 [2022-11-18 21:15:21,367 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2022-11-18 21:15:21,367 INFO L413 NwaCegarLoop]: 7 mSDtfsCounter, 60 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 314 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 60 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 327 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 314 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:21,368 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [60 Valid, 24 Invalid, 327 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 314 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2022-11-18 21:15:21,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2022-11-18 21:15:21,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 179. [2022-11-18 21:15:21,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 177 states have (on average 2.5084745762711864) internal successors, (444), 178 states have internal predecessors, (444), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:21,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 444 transitions. [2022-11-18 21:15:21,373 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 444 transitions. Word has length 17 [2022-11-18 21:15:21,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:21,373 INFO L495 AbstractCegarLoop]: Abstraction has 179 states and 444 transitions. [2022-11-18 21:15:21,374 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 10 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:21,374 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 444 transitions. [2022-11-18 21:15:21,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:15:21,374 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:21,375 INFO L195 NwaCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:21,388 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (43)] Ended with exit code 0 [2022-11-18 21:15:21,575 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:21,575 INFO L420 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:21,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:21,575 INFO L85 PathProgramCache]: Analyzing trace with hash 2107161134, now seen corresponding path program 10 times [2022-11-18 21:15:21,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:21,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [680994236] [2022-11-18 21:15:21,576 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 21:15:21,576 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:21,576 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:21,578 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:21,617 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (44)] Waiting until timeout for monitored process [2022-11-18 21:15:21,752 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 21:15:21,752 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:15:21,760 INFO L263 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-18 21:15:21,761 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:21,988 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:21,988 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:22,430 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:22,430 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:15:22,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [680994236] [2022-11-18 21:15:22,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [680994236] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:15:22,431 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:15:22,431 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2022-11-18 21:15:22,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199350619] [2022-11-18 21:15:22,431 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:15:22,431 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:15:22,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:15:22,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:15:22,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=131, Unknown=0, NotChecked=0, Total=182 [2022-11-18 21:15:22,432 INFO L87 Difference]: Start difference. First operand 179 states and 444 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 14 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:25,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:15:25,184 INFO L93 Difference]: Finished difference Result 525 states and 1161 transitions. [2022-11-18 21:15:25,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-18 21:15:25,185 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 14 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-11-18 21:15:25,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:15:25,187 INFO L225 Difference]: With dead ends: 525 [2022-11-18 21:15:25,187 INFO L226 Difference]: Without dead ends: 473 [2022-11-18 21:15:25,188 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=188, Invalid=514, Unknown=0, NotChecked=0, Total=702 [2022-11-18 21:15:25,188 INFO L413 NwaCegarLoop]: 6 mSDtfsCounter, 202 mSDsluCounter, 23 mSDsCounter, 0 mSdLazyCounter, 552 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 202 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 687 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 552 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 129 IncrementalHoareTripleChecker+Unchecked, 1.8s IncrementalHoareTripleChecker+Time [2022-11-18 21:15:25,188 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [202 Valid, 29 Invalid, 687 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 552 Invalid, 0 Unknown, 129 Unchecked, 1.8s Time] [2022-11-18 21:15:25,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 473 states. [2022-11-18 21:15:25,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 473 to 210. [2022-11-18 21:15:25,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 208 states have (on average 2.5865384615384617) internal successors, (538), 209 states have internal predecessors, (538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:25,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 538 transitions. [2022-11-18 21:15:25,197 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 538 transitions. Word has length 18 [2022-11-18 21:15:25,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:15:25,197 INFO L495 AbstractCegarLoop]: Abstraction has 210 states and 538 transitions. [2022-11-18 21:15:25,198 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 14 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:15:25,198 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 538 transitions. [2022-11-18 21:15:25,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:15:25,199 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:15:25,199 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:15:25,215 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (44)] Ended with exit code 0 [2022-11-18 21:15:25,411 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:25,411 INFO L420 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:15:25,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:15:25,411 INFO L85 PathProgramCache]: Analyzing trace with hash 592813905, now seen corresponding path program 1 times [2022-11-18 21:15:25,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:15:25,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [790495191] [2022-11-18 21:15:25,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-18 21:15:25,412 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:15:25,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:15:25,413 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:15:25,417 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (45)] Waiting until timeout for monitored process [2022-11-18 21:15:25,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-18 21:15:25,658 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 21:15:25,659 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:15:26,558 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:15:26,559 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:15:26,562 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:15:26,563 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:15:26,565 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:15:26,567 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:15:26,568 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:15:27,140 INFO L321 Elim1Store]: treesize reduction 824, result has 4.3 percent of original size [2022-11-18 21:15:27,140 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 6 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 1720 treesize of output 324 [2022-11-18 21:15:27,170 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:15:27,179 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:15:27,270 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:15:27,271 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:15:27,352 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:15:27,359 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:15:32,804 INFO L321 Elim1Store]: treesize reduction 972, result has 22.7 percent of original size [2022-11-18 21:15:32,805 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 0 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 2088 treesize of output 500 [2022-11-18 21:17:31,654 WARN L233 SmtUtils]: Spent 37.18s on a formula simplification. DAG size of input: 1533 DAG size of output: 37 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 21:17:32,459 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:17:32,459 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:17:32,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [790495191] [2022-11-18 21:17:32,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [790495191] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:17:32,459 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:17:32,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:17:32,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870422886] [2022-11-18 21:17:32,460 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:17:32,460 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:17:32,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:17:32,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:17:32,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=131, Unknown=5, NotChecked=0, Total=182 [2022-11-18 21:17:32,461 INFO L87 Difference]: Start difference. First operand 210 states and 538 transitions. Second operand has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:17:34,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:17:34,499 INFO L93 Difference]: Finished difference Result 287 states and 747 transitions. [2022-11-18 21:17:34,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 21:17:34,501 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-11-18 21:17:34,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:17:34,503 INFO L225 Difference]: With dead ends: 287 [2022-11-18 21:17:34,503 INFO L226 Difference]: Without dead ends: 282 [2022-11-18 21:17:34,503 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 55.8s TimeCoverageRelationStatistics Valid=74, Invalid=227, Unknown=5, NotChecked=0, Total=306 [2022-11-18 21:17:34,503 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 34 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 25 SdHoareTripleChecker+Invalid, 162 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 100 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-18 21:17:34,503 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [34 Valid, 25 Invalid, 162 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 61 Invalid, 0 Unknown, 100 Unchecked, 0.6s Time] [2022-11-18 21:17:34,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2022-11-18 21:17:34,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 261. [2022-11-18 21:17:34,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 261 states, 259 states have (on average 2.687258687258687) internal successors, (696), 260 states have internal predecessors, (696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:17:34,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 261 states to 261 states and 696 transitions. [2022-11-18 21:17:34,510 INFO L78 Accepts]: Start accepts. Automaton has 261 states and 696 transitions. Word has length 18 [2022-11-18 21:17:34,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:17:34,511 INFO L495 AbstractCegarLoop]: Abstraction has 261 states and 696 transitions. [2022-11-18 21:17:34,511 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:17:34,511 INFO L276 IsEmpty]: Start isEmpty. Operand 261 states and 696 transitions. [2022-11-18 21:17:34,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:17:34,513 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:17:34,513 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:17:34,531 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (45)] Forceful destruction successful, exit code 0 [2022-11-18 21:17:34,726 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 45 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:17:34,726 INFO L420 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:17:34,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:17:34,726 INFO L85 PathProgramCache]: Analyzing trace with hash 787647045, now seen corresponding path program 2 times [2022-11-18 21:17:34,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:17:34,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1925558380] [2022-11-18 21:17:34,727 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-18 21:17:34,727 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:17:34,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:17:34,728 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:17:34,729 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (46)] Waiting until timeout for monitored process [2022-11-18 21:17:34,937 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:17:34,937 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:17:34,945 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 21:17:34,946 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:17:36,098 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,103 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,107 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,109 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:17:36,113 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,117 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,118 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:17:36,122 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:17:36,124 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:17:36,125 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:17:36,750 INFO L321 Elim1Store]: treesize reduction 824, result has 4.3 percent of original size [2022-11-18 21:17:36,751 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 6 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 1720 treesize of output 324 [2022-11-18 21:17:36,779 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:17:36,789 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:17:36,909 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:17:36,910 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:17:37,020 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:17:37,029 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:17:43,585 INFO L321 Elim1Store]: treesize reduction 972, result has 22.7 percent of original size [2022-11-18 21:17:43,585 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 0 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 2088 treesize of output 500 [2022-11-18 21:19:42,711 WARN L233 SmtUtils]: Spent 27.19s on a formula simplification. DAG size of input: 1674 DAG size of output: 35 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 21:19:43,441 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:19:43,441 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:19:43,441 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1925558380] [2022-11-18 21:19:43,441 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1925558380] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:19:43,441 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:19:43,441 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:19:43,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233299468] [2022-11-18 21:19:43,442 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:19:43,442 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:19:43,442 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:19:43,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:19:43,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=131, Unknown=5, NotChecked=0, Total=182 [2022-11-18 21:19:43,442 INFO L87 Difference]: Start difference. First operand 261 states and 696 transitions. Second operand has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:19:44,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:19:44,550 INFO L93 Difference]: Finished difference Result 324 states and 861 transitions. [2022-11-18 21:19:44,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-18 21:19:44,552 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-11-18 21:19:44,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:19:44,553 INFO L225 Difference]: With dead ends: 324 [2022-11-18 21:19:44,553 INFO L226 Difference]: Without dead ends: 321 [2022-11-18 21:19:44,553 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 46.4s TimeCoverageRelationStatistics Valid=61, Invalid=174, Unknown=5, NotChecked=0, Total=240 [2022-11-18 21:19:44,553 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 7 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 41 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 27 SdHoareTripleChecker+Invalid, 136 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 41 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 95 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-18 21:19:44,553 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 27 Invalid, 136 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 41 Invalid, 0 Unknown, 95 Unchecked, 0.3s Time] [2022-11-18 21:19:44,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2022-11-18 21:19:44,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 296. [2022-11-18 21:19:44,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 296 states, 294 states have (on average 2.748299319727891) internal successors, (808), 295 states have internal predecessors, (808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:19:44,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 808 transitions. [2022-11-18 21:19:44,561 INFO L78 Accepts]: Start accepts. Automaton has 296 states and 808 transitions. Word has length 18 [2022-11-18 21:19:44,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:19:44,562 INFO L495 AbstractCegarLoop]: Abstraction has 296 states and 808 transitions. [2022-11-18 21:19:44,562 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:19:44,562 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 808 transitions. [2022-11-18 21:19:44,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:19:44,563 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:19:44,564 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:19:44,579 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (46)] Forceful destruction successful, exit code 0 [2022-11-18 21:19:44,776 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 46 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:19:44,777 INFO L420 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:19:44,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:19:44,777 INFO L85 PathProgramCache]: Analyzing trace with hash 793701345, now seen corresponding path program 3 times [2022-11-18 21:19:44,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:19:44,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1120755698] [2022-11-18 21:19:44,777 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-18 21:19:44,777 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:19:44,777 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:19:44,778 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:19:44,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (47)] Waiting until timeout for monitored process [2022-11-18 21:19:44,979 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-18 21:19:44,980 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:19:44,987 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 21:19:44,989 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:19:45,953 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:19:45,957 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,961 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,964 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,965 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:19:45,969 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,972 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,976 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:19:45,977 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:19:45,978 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:19:46,622 INFO L321 Elim1Store]: treesize reduction 824, result has 4.3 percent of original size [2022-11-18 21:19:46,622 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 6 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 1720 treesize of output 324 [2022-11-18 21:19:46,644 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:19:46,654 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:19:46,799 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:19:46,799 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:19:46,902 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:19:46,911 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:19:53,330 INFO L321 Elim1Store]: treesize reduction 972, result has 22.7 percent of original size [2022-11-18 21:19:53,330 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 0 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 2088 treesize of output 500 [2022-11-18 21:21:53,835 WARN L233 SmtUtils]: Spent 32.46s on a formula simplification. DAG size of input: 1437 DAG size of output: 37 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 21:21:54,641 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:21:54,641 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:21:54,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1120755698] [2022-11-18 21:21:54,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1120755698] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:21:54,641 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:21:54,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:21:54,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452334338] [2022-11-18 21:21:54,642 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:21:54,642 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:21:54,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:21:54,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:21:54,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=131, Unknown=5, NotChecked=0, Total=182 [2022-11-18 21:21:54,643 INFO L87 Difference]: Start difference. First operand 296 states and 808 transitions. Second operand has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:21:56,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:21:56,413 INFO L93 Difference]: Finished difference Result 337 states and 900 transitions. [2022-11-18 21:21:56,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-18 21:21:56,416 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-11-18 21:21:56,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:21:56,417 INFO L225 Difference]: With dead ends: 337 [2022-11-18 21:21:56,418 INFO L226 Difference]: Without dead ends: 325 [2022-11-18 21:21:56,418 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 52.6s TimeCoverageRelationStatistics Valid=88, Invalid=249, Unknown=5, NotChecked=0, Total=342 [2022-11-18 21:21:56,418 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 20 mSDsluCounter, 29 mSDsCounter, 0 mSdLazyCounter, 83 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 33 SdHoareTripleChecker+Invalid, 223 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 83 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 139 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-18 21:21:56,419 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 33 Invalid, 223 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 83 Invalid, 0 Unknown, 139 Unchecked, 0.6s Time] [2022-11-18 21:21:56,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2022-11-18 21:21:56,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 257. [2022-11-18 21:21:56,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 257 states, 255 states have (on average 2.6941176470588237) internal successors, (687), 256 states have internal predecessors, (687), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:21:56,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 687 transitions. [2022-11-18 21:21:56,426 INFO L78 Accepts]: Start accepts. Automaton has 257 states and 687 transitions. Word has length 18 [2022-11-18 21:21:56,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:21:56,426 INFO L495 AbstractCegarLoop]: Abstraction has 257 states and 687 transitions. [2022-11-18 21:21:56,427 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:21:56,427 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 687 transitions. [2022-11-18 21:21:56,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:21:56,428 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:21:56,428 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:21:56,443 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (47)] Forceful destruction successful, exit code 0 [2022-11-18 21:21:56,641 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 47 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:21:56,641 INFO L420 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:21:56,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:21:56,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1397126447, now seen corresponding path program 4 times [2022-11-18 21:21:56,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:21:56,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [48721769] [2022-11-18 21:21:56,642 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-18 21:21:56,642 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:21:56,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:21:56,643 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:21:56,644 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (48)] Waiting until timeout for monitored process [2022-11-18 21:21:56,838 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-18 21:21:56,839 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:21:56,847 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-18 21:21:56,848 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:21:57,830 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:21:57,835 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:21:57,839 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:21:57,840 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:21:57,841 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:21:57,845 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:21:57,850 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:21:57,852 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:21:57,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:21:58,541 INFO L321 Elim1Store]: treesize reduction 824, result has 4.3 percent of original size [2022-11-18 21:21:58,542 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 6 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 1720 treesize of output 324 [2022-11-18 21:21:58,564 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:21:58,574 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:21:58,763 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:21:58,763 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:21:58,869 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:21:58,877 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:22:05,671 WARN L233 SmtUtils]: Spent 5.19s on a formula simplification. DAG size of input: 471 DAG size of output: 135 (called from [L 318] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.arrays.Elim1Store.elim1) [2022-11-18 21:22:05,672 INFO L321 Elim1Store]: treesize reduction 972, result has 22.7 percent of original size [2022-11-18 21:22:05,672 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 0 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 2088 treesize of output 500 [2022-11-18 21:24:19,408 WARN L233 SmtUtils]: Spent 51.36s on a formula simplification. DAG size of input: 1680 DAG size of output: 36 (called from [L 361] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-18 21:24:20,178 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-18 21:24:20,178 INFO L136 FreeRefinementEngine]: Strategy WOLF found an infeasible trace [2022-11-18 21:24:20,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [48721769] [2022-11-18 21:24:20,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [48721769] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-18 21:24:20,178 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-18 21:24:20,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 12 [2022-11-18 21:24:20,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055865522] [2022-11-18 21:24:20,178 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-18 21:24:20,179 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-18 21:24:20,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WOLF [2022-11-18 21:24:20,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-18 21:24:20,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=132, Unknown=4, NotChecked=0, Total=182 [2022-11-18 21:24:20,179 INFO L87 Difference]: Start difference. First operand 257 states and 687 transitions. Second operand has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:24:21,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-18 21:24:21,664 INFO L93 Difference]: Finished difference Result 312 states and 836 transitions. [2022-11-18 21:24:21,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-18 21:24:21,665 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-11-18 21:24:21,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-18 21:24:21,667 INFO L225 Difference]: With dead ends: 312 [2022-11-18 21:24:21,667 INFO L226 Difference]: Without dead ends: 308 [2022-11-18 21:24:21,667 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 69.1s TimeCoverageRelationStatistics Valid=74, Invalid=228, Unknown=4, NotChecked=0, Total=306 [2022-11-18 21:24:21,667 INFO L413 NwaCegarLoop]: 3 mSDtfsCounter, 5 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 120 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 49 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-18 21:24:21,668 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 24 Invalid, 120 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 70 Invalid, 0 Unknown, 49 Unchecked, 0.5s Time] [2022-11-18 21:24:21,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states. [2022-11-18 21:24:21,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 288. [2022-11-18 21:24:21,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 286 states have (on average 2.762237762237762) internal successors, (790), 287 states have internal predecessors, (790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:24:21,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 790 transitions. [2022-11-18 21:24:21,675 INFO L78 Accepts]: Start accepts. Automaton has 288 states and 790 transitions. Word has length 18 [2022-11-18 21:24:21,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-18 21:24:21,675 INFO L495 AbstractCegarLoop]: Abstraction has 288 states and 790 transitions. [2022-11-18 21:24:21,675 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 2.769230769230769) internal successors, (36), 13 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-18 21:24:21,675 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 790 transitions. [2022-11-18 21:24:21,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-11-18 21:24:21,676 INFO L187 NwaCegarLoop]: Found error trace [2022-11-18 21:24:21,676 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-18 21:24:21,695 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (48)] Forceful destruction successful, exit code 0 [2022-11-18 21:24:21,876 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 48 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:24:21,876 INFO L420 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONMEMORY_LEAK === [thread1Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread1Err1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, thread2Err0REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 27 more)] === [2022-11-18 21:24:21,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-18 21:24:21,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1596226427, now seen corresponding path program 5 times [2022-11-18 21:24:21,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy WOLF [2022-11-18 21:24:21,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1938552196] [2022-11-18 21:24:21,877 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-18 21:24:21,877 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 [2022-11-18 21:24:21,877 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat [2022-11-18 21:24:21,878 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-18 21:24:21,880 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70e2bdb7-115f-452a-b1c8-67b3cb697900/bin/uautomizer-TMbwUNV5ro/mathsat -theory.fp.to_bv_overflow_mode=1 -theory.fp.minmax_zero_mode=4 -theory.bv.div_by_zero_mode=1 -unsat_core_generation=3 (49)] Waiting until timeout for monitored process [2022-11-18 21:24:22,155 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-18 21:24:22,155 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-18 21:24:22,164 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-18 21:24:22,165 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-18 21:24:23,545 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,549 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,550 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:24:23,553 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,557 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,560 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,564 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,567 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,568 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:24:23,572 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-18 21:24:23,573 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:24:23,574 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-18 21:24:24,201 INFO L321 Elim1Store]: treesize reduction 824, result has 4.3 percent of original size [2022-11-18 21:24:24,202 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 6 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 1720 treesize of output 324 [2022-11-18 21:24:24,226 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 160 treesize of output 158 [2022-11-18 21:24:24,237 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 158 treesize of output 156 [2022-11-18 21:24:24,369 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-18 21:24:24,369 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-18 21:24:24,468 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 174 [2022-11-18 21:24:24,476 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 174 treesize of output 172 [2022-11-18 21:24:31,150 INFO L321 Elim1Store]: treesize reduction 972, result has 22.7 percent of original size [2022-11-18 21:24:31,151 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 16 select indices, 16 select index equivalence classes, 0 disjoint index pairs (out of 120 index pairs), introduced 24 new quantified variables, introduced 120 case distinctions, treesize of input 2088 treesize of output 500