./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6b4ec56b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-6b4ec56 [2022-11-20 10:31:18,855 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-20 10:31:18,858 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-20 10:31:18,907 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-20 10:31:18,909 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-20 10:31:18,913 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-20 10:31:18,917 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-20 10:31:18,920 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-20 10:31:18,923 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-20 10:31:18,930 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-20 10:31:18,932 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-20 10:31:18,935 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-20 10:31:18,936 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-20 10:31:18,939 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-20 10:31:18,941 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-20 10:31:18,944 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-20 10:31:18,946 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-20 10:31:18,947 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-20 10:31:18,949 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-20 10:31:18,957 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-20 10:31:18,959 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-20 10:31:18,962 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-20 10:31:18,964 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-20 10:31:18,965 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-20 10:31:18,978 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-20 10:31:18,980 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-20 10:31:18,980 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-20 10:31:18,983 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-20 10:31:18,983 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-20 10:31:18,985 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-20 10:31:18,985 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-20 10:31:18,986 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-20 10:31:18,989 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-20 10:31:18,990 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-20 10:31:18,992 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-20 10:31:18,992 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-20 10:31:18,993 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-20 10:31:18,993 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-20 10:31:18,994 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-20 10:31:18,996 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-20 10:31:18,997 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-20 10:31:18,998 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-20 10:31:19,043 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-20 10:31:19,045 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-20 10:31:19,045 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-20 10:31:19,046 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-20 10:31:19,047 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-20 10:31:19,048 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-20 10:31:19,048 INFO L138 SettingsManager]: * Use SBE=true [2022-11-20 10:31:19,048 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-20 10:31:19,048 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-20 10:31:19,049 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-20 10:31:19,050 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-20 10:31:19,050 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-20 10:31:19,051 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-20 10:31:19,051 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-20 10:31:19,051 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-20 10:31:19,051 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-20 10:31:19,052 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-20 10:31:19,052 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-20 10:31:19,052 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-20 10:31:19,053 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-20 10:31:19,053 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-20 10:31:19,053 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-20 10:31:19,053 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-20 10:31:19,054 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-20 10:31:19,054 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-20 10:31:19,054 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-20 10:31:19,055 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-20 10:31:19,055 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-20 10:31:19,057 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-20 10:31:19,057 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2022-11-20 10:31:19,384 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-20 10:31:19,409 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-20 10:31:19,412 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-20 10:31:19,414 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-20 10:31:19,415 INFO L275 PluginConnector]: CDTParser initialized [2022-11-20 10:31:19,416 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/../../sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-20 10:31:22,781 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-20 10:31:23,090 INFO L351 CDTParser]: Found 1 translation units. [2022-11-20 10:31:23,091 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/sv-benchmarks/c/termination-15/array12_alloca.i [2022-11-20 10:31:23,108 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/data/d75c97a09/a4cc34e8df9b4815adeafaf95f639579/FLAG7e2f90083 [2022-11-20 10:31:23,138 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/data/d75c97a09/a4cc34e8df9b4815adeafaf95f639579 [2022-11-20 10:31:23,142 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-20 10:31:23,144 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-20 10:31:23,147 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-20 10:31:23,147 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-20 10:31:23,152 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-20 10:31:23,153 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,154 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@744e88ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23, skipping insertion in model container [2022-11-20 10:31:23,154 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,164 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-20 10:31:23,223 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-20 10:31:23,667 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-20 10:31:23,683 INFO L203 MainTranslator]: Completed pre-run [2022-11-20 10:31:23,758 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-20 10:31:23,805 INFO L208 MainTranslator]: Completed translation [2022-11-20 10:31:23,807 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23 WrapperNode [2022-11-20 10:31:23,807 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-20 10:31:23,809 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-20 10:31:23,809 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-20 10:31:23,809 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-20 10:31:23,818 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,834 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,859 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-20 10:31:23,859 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-20 10:31:23,860 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-20 10:31:23,861 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-20 10:31:23,861 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-20 10:31:23,872 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,873 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,875 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,875 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,881 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,885 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,887 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,888 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,890 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-20 10:31:23,891 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-20 10:31:23,891 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-20 10:31:23,891 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-20 10:31:23,892 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (1/1) ... [2022-11-20 10:31:23,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:23,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:23,937 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:23,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-20 10:31:23,995 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-20 10:31:23,995 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-20 10:31:23,995 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-20 10:31:23,996 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-20 10:31:23,997 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-20 10:31:23,997 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-20 10:31:24,150 INFO L235 CfgBuilder]: Building ICFG [2022-11-20 10:31:24,153 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-20 10:31:24,323 INFO L276 CfgBuilder]: Performing block encoding [2022-11-20 10:31:24,330 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-20 10:31:24,330 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-20 10:31:24,332 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:31:24 BoogieIcfgContainer [2022-11-20 10:31:24,332 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-20 10:31:24,333 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-20 10:31:24,334 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-20 10:31:24,338 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-20 10:31:24,339 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 10:31:24,339 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 10:31:23" (1/3) ... [2022-11-20 10:31:24,340 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77850a74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:31:24, skipping insertion in model container [2022-11-20 10:31:24,341 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 10:31:24,341 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:31:23" (2/3) ... [2022-11-20 10:31:24,341 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77850a74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:31:24, skipping insertion in model container [2022-11-20 10:31:24,341 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 10:31:24,341 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:31:24" (3/3) ... [2022-11-20 10:31:24,343 INFO L332 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2022-11-20 10:31:24,398 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-20 10:31:24,398 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-20 10:31:24,398 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-20 10:31:24,398 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-20 10:31:24,398 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-20 10:31:24,399 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-20 10:31:24,399 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-20 10:31:24,399 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-20 10:31:24,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:24,420 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-20 10:31:24,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:24,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:24,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-20 10:31:24,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-20 10:31:24,448 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-20 10:31:24,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:24,449 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-20 10:31:24,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:24,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:24,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-20 10:31:24,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-20 10:31:24,459 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-20 10:31:24,459 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-20 10:31:24,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:24,466 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-20 10:31:24,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:24,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159285522] [2022-11-20 10:31:24,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:24,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:24,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:24,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,679 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:24,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:24,684 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-20 10:31:24,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:24,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677820933] [2022-11-20 10:31:24,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:24,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:24,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,720 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:24,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,749 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:24,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:24,751 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-20 10:31:24,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:24,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335390463] [2022-11-20 10:31:24,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:24,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:24,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,817 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:24,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:24,857 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:25,368 INFO L210 LassoAnalysis]: Preferences: [2022-11-20 10:31:25,370 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-20 10:31:25,370 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-20 10:31:25,370 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-20 10:31:25,371 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-20 10:31:25,371 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:25,371 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-20 10:31:25,371 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-20 10:31:25,372 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2022-11-20 10:31:25,372 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-20 10:31:25,373 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-20 10:31:25,401 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,415 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,420 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,434 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,438 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,442 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,643 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,647 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,660 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,663 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,667 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:25,671 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:26,129 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-20 10:31:26,137 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-20 10:31:26,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,144 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,147 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,161 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-20 10:31:26,162 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,162 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:26,163 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,163 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,163 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,166 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:26,166 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:26,176 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,186 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,188 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,195 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-20 10:31:26,196 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,212 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,212 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,212 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,213 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,217 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:26,218 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:26,240 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,247 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2022-11-20 10:31:26,252 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,252 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,255 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,259 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,274 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-20 10:31:26,275 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,275 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:26,275 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,275 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,275 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,277 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:26,277 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:26,287 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,297 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,297 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,297 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,299 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,308 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,321 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-20 10:31:26,322 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,322 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:26,322 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,323 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,323 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,324 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:26,324 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:26,334 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,343 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,343 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,344 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,345 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-20 10:31:26,354 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,369 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,369 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:26,369 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,369 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,370 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,370 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:26,371 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:26,380 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,385 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,385 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,387 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,391 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-20 10:31:26,392 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,406 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,406 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:26,406 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,406 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,406 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,408 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:26,408 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:26,417 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,427 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,428 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,428 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,430 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,441 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,457 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-20 10:31:26,460 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,460 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,460 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,460 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,471 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:26,471 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:26,491 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,505 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,507 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,521 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,534 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-20 10:31:26,536 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,536 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,536 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,536 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,568 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:26,568 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:26,583 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:26,593 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,593 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,596 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-20 10:31:26,601 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:26,616 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:26,617 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:26,617 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:26,617 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:26,628 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:26,628 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:26,647 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-20 10:31:26,704 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-20 10:31:26,704 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-20 10:31:26,706 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:26,706 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:26,750 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:26,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-20 10:31:26,753 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-20 10:31:26,774 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-20 10:31:26,774 INFO L513 LassoAnalysis]: Proved termination. [2022-11-20 10:31:26,775 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1) = -4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 Supporting invariants [] [2022-11-20 10:31:26,779 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:26,801 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-20 10:31:26,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:26,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:26,859 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-20 10:31:26,861 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:26,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:26,914 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 10:31:26,915 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:26,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:27,021 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-20 10:31:27,024 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:27,110 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-20 10:31:27,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-20 10:31:27,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:27,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-20 10:31:27,131 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-20 10:31:27,132 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:27,132 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-20 10:31:27,133 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:27,133 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-20 10:31:27,134 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:27,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-20 10:31:27,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:27,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-20 10:31:27,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-20 10:31:27,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-20 10:31:27,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-20 10:31:27,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:27,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 10:31:27,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-20 10:31:27,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-20 10:31:27,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:27,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-20 10:31:27,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 10:31:27,193 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 10:31:27,194 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-20 10:31:27,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-20 10:31:27,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:27,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:27,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:27,198 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:27,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:27,198 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-20 10:31:27,199 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 118#L378-2 [2022-11-20 10:31:27,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:27,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-20 10:31:27,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:27,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019400320] [2022-11-20 10:31:27,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:27,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:27,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:27,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:27,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:27,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019400320] [2022-11-20 10:31:27,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019400320] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-20 10:31:27,327 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-20 10:31:27,328 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-20 10:31:27,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860274982] [2022-11-20 10:31:27,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-20 10:31:27,331 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:27,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:27,332 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-20 10:31:27,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:27,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778222210] [2022-11-20 10:31:27,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:27,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:27,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,340 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:27,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:27,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:27,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-20 10:31:27,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-20 10:31:27,424 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:27,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:27,469 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-20 10:31:27,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-20 10:31:27,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:27,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-20 10:31:27,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-20 10:31:27,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-20 10:31:27,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-20 10:31:27,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:27,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-20 10:31:27,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-20 10:31:27,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-20 10:31:27,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:27,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-20 10:31:27,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-20 10:31:27,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-20 10:31:27,476 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-20 10:31:27,476 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-20 10:31:27,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-20 10:31:27,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:27,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:27,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:27,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:27,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:27,479 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-20 10:31:27,479 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 151#L378-2 [2022-11-20 10:31:27,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:27,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-20 10:31:27,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:27,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606489273] [2022-11-20 10:31:27,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:27,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:27,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,497 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:27,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,510 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:27,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:27,511 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-20 10:31:27,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:27,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126963040] [2022-11-20 10:31:27,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:27,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:27,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,517 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:27,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:27,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:27,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:27,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-20 10:31:27,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:27,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902362342] [2022-11-20 10:31:27,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:27,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:27,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:28,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:28,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:28,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902362342] [2022-11-20 10:31:28,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902362342] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:28,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [44840843] [2022-11-20 10:31:28,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:28,075 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:28,075 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:28,079 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:28,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-20 10:31:28,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:28,163 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-20 10:31:28,166 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:28,239 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-20 10:31:28,327 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:31:28,363 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:28,363 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:28,370 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:28,454 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:31:28,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-20 10:31:28,479 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:28,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [44840843] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:28,480 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:28,480 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-20 10:31:28,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237635739] [2022-11-20 10:31:28,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:28,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:28,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-20 10:31:28,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2022-11-20 10:31:28,538 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:28,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:28,703 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2022-11-20 10:31:28,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2022-11-20 10:31:28,706 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:28,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2022-11-20 10:31:28,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-20 10:31:28,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-20 10:31:28,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2022-11-20 10:31:28,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:28,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2022-11-20 10:31:28,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2022-11-20 10:31:28,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2022-11-20 10:31:28,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:28,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2022-11-20 10:31:28,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-20 10:31:28,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 10:31:28,718 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-20 10:31:28,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-20 10:31:28,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2022-11-20 10:31:28,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:28,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:28,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:28,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:28,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:28,725 INFO L748 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 277#L367 assume !(main_~length~0#1 < 1); 271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 278#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 279#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 280#L370-4 main_~j~0#1 := 0; 284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 274#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 275#L378-2 [2022-11-20 10:31:28,725 INFO L750 eck$LassoCheckResult]: Loop: 275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 282#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 275#L378-2 [2022-11-20 10:31:28,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:28,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-20 10:31:28,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:28,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411741216] [2022-11-20 10:31:28,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:28,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:28,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:28,757 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:28,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:28,773 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:28,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:28,778 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-20 10:31:28,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:28,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457330712] [2022-11-20 10:31:28,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:28,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:28,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:28,786 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:28,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:28,792 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:28,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:28,793 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2022-11-20 10:31:28,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:28,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695786126] [2022-11-20 10:31:28,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:28,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:28,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:28,924 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:28,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:28,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695786126] [2022-11-20 10:31:28,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695786126] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:28,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1390213171] [2022-11-20 10:31:28,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:28,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:28,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:28,932 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:28,957 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-20 10:31:28,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:28,997 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-20 10:31:28,998 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:29,069 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:29,069 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:29,124 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:29,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1390213171] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:29,125 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:29,125 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-20 10:31:29,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653572383] [2022-11-20 10:31:29,128 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:29,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:29,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-20 10:31:29,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-20 10:31:29,185 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:29,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:29,316 INFO L93 Difference]: Finished difference Result 43 states and 57 transitions. [2022-11-20 10:31:29,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2022-11-20 10:31:29,317 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:29,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 39 states and 51 transitions. [2022-11-20 10:31:29,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-20 10:31:29,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-20 10:31:29,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-20 10:31:29,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:29,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-20 10:31:29,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-20 10:31:29,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-20 10:31:29,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:29,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2022-11-20 10:31:29,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-20 10:31:29,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 10:31:29,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-20 10:31:29,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-20 10:31:29,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2022-11-20 10:31:29,325 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:29,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:29,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:29,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:29,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:29,326 INFO L748 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 444#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 445#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 461#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 457#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 458#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 440#L370-4 main_~j~0#1 := 0; 441#L378-2 [2022-11-20 10:31:29,326 INFO L750 eck$LassoCheckResult]: Loop: 441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 451#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 441#L378-2 [2022-11-20 10:31:29,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:29,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-20 10:31:29,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:29,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632072849] [2022-11-20 10:31:29,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:29,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:29,373 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:29,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:29,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632072849] [2022-11-20 10:31:29,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1632072849] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:29,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1255548258] [2022-11-20 10:31:29,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:29,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:29,378 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:29,407 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-20 10:31:29,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:29,443 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 10:31:29,445 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:29,493 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:29,494 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-20 10:31:29,494 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1255548258] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-20 10:31:29,494 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-20 10:31:29,494 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-20 10:31:29,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976076273] [2022-11-20 10:31:29,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-20 10:31:29,495 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:29,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:29,496 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-20 10:31:29,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:29,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683546697] [2022-11-20 10:31:29,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:29,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,501 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:29,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:29,563 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:29,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-20 10:31:29,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-20 10:31:29,564 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:29,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:29,588 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2022-11-20 10:31:29,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2022-11-20 10:31:29,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:29,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2022-11-20 10:31:29,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-20 10:31:29,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-20 10:31:29,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2022-11-20 10:31:29,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:29,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 10:31:29,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2022-11-20 10:31:29,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-20 10:31:29,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:29,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-11-20 10:31:29,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 10:31:29,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-20 10:31:29,603 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 10:31:29,604 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-20 10:31:29,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2022-11-20 10:31:29,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:29,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:29,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:29,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:29,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:29,605 INFO L748 eck$LassoCheckResult]: Stem: 542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 551#L367 assume !(main_~length~0#1 < 1); 544#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 545#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 552#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 553#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 558#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 557#L370-4 main_~j~0#1 := 0; 550#L378-2 [2022-11-20 10:31:29,605 INFO L750 eck$LassoCheckResult]: Loop: 550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 556#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 550#L378-2 [2022-11-20 10:31:29,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:29,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2022-11-20 10:31:29,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:29,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091382385] [2022-11-20 10:31:29,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:29,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:29,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,643 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:29,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:29,646 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-20 10:31:29,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:29,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562598772] [2022-11-20 10:31:29,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:29,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:29,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:29,655 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:29,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:29,656 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2022-11-20 10:31:29,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:29,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642876953] [2022-11-20 10:31:29,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:29,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:29,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:30,074 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:30,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:30,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642876953] [2022-11-20 10:31:30,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642876953] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:30,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1471285189] [2022-11-20 10:31:30,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:30,076 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:30,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:30,083 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:30,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-20 10:31:30,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:30,143 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-20 10:31:30,145 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:30,163 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:30,231 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:30,235 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:30,264 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:30,265 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:30,316 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:31:30,327 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:30,327 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:30,535 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2022-11-20 10:31:30,541 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 62 [2022-11-20 10:31:30,588 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:30,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1471285189] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:30,588 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:30,588 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-20 10:31:30,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717087589] [2022-11-20 10:31:30,589 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:30,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:30,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-20 10:31:30,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-20 10:31:30,644 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:30,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:30,816 INFO L93 Difference]: Finished difference Result 39 states and 51 transitions. [2022-11-20 10:31:30,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 51 transitions. [2022-11-20 10:31:30,819 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:30,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 51 transitions. [2022-11-20 10:31:30,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 10:31:30,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 10:31:30,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-20 10:31:30,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:30,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-20 10:31:30,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-20 10:31:30,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-11-20 10:31:30,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.3703703703703705) internal successors, (37), 26 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:30,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-11-20 10:31:30,833 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-20 10:31:30,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 10:31:30,834 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-20 10:31:30,835 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-20 10:31:30,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 37 transitions. [2022-11-20 10:31:30,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:30,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:30,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:30,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:30,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:30,839 INFO L748 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 723#L367 assume !(main_~length~0#1 < 1); 716#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 717#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 724#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 726#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 739#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 721#L370-4 main_~j~0#1 := 0; 722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 720#L378-2 [2022-11-20 10:31:30,839 INFO L750 eck$LassoCheckResult]: Loop: 720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 733#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 720#L378-2 [2022-11-20 10:31:30,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:30,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-20 10:31:30,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:30,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155840295] [2022-11-20 10:31:30,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:30,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:30,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:30,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:30,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:30,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:30,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:30,876 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-20 10:31:30,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:30,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548230679] [2022-11-20 10:31:30,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:30,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:30,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:30,882 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:30,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:30,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:30,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:30,890 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2022-11-20 10:31:30,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:30,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523435935] [2022-11-20 10:31:30,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:30,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:30,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:31,149 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:31,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:31,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523435935] [2022-11-20 10:31:31,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523435935] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:31,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1085856940] [2022-11-20 10:31:31,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:31,150 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:31,150 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:31,155 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:31,167 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-20 10:31:31,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:31,231 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-20 10:31:31,233 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:31,263 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:31,421 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-20 10:31:31,421 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-20 10:31:31,436 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:31,437 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:31,530 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 10:31:31,534 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2022-11-20 10:31:31,562 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:31,562 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1085856940] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:31,563 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:31,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2022-11-20 10:31:31,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510567415] [2022-11-20 10:31:31,563 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:31,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:31,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-20 10:31:31,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2022-11-20 10:31:31,622 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. cyclomatic complexity: 13 Second operand has 16 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:31,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:31,767 INFO L93 Difference]: Finished difference Result 36 states and 48 transitions. [2022-11-20 10:31:31,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 48 transitions. [2022-11-20 10:31:31,768 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:31,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 48 transitions. [2022-11-20 10:31:31,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-20 10:31:31,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-20 10:31:31,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 48 transitions. [2022-11-20 10:31:31,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:31,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36 states and 48 transitions. [2022-11-20 10:31:31,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 48 transitions. [2022-11-20 10:31:31,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 32. [2022-11-20 10:31:31,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:31,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2022-11-20 10:31:31,772 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-20 10:31:31,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-20 10:31:31,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-20 10:31:31,774 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-20 10:31:31,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2022-11-20 10:31:31,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:31,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:31,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:31,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:31,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:31,775 INFO L748 eck$LassoCheckResult]: Stem: 898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 906#L367 assume !(main_~length~0#1 < 1); 900#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 901#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 907#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 909#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 915#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 916#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 905#L370-4 main_~j~0#1 := 0; 904#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 910#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 919#L378-2 [2022-11-20 10:31:31,776 INFO L750 eck$LassoCheckResult]: Loop: 919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 918#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 919#L378-2 [2022-11-20 10:31:31,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:31,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2022-11-20 10:31:31,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:31,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063638740] [2022-11-20 10:31:31,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:31,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:31,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:31,788 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:31,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:31,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:31,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:31,797 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-20 10:31:31,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:31,798 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329038052] [2022-11-20 10:31:31,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:31,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:31,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:31,801 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:31,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:31,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:31,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:31,805 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2022-11-20 10:31:31,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:31,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417715879] [2022-11-20 10:31:31,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:31,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:31,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:32,000 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:32,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:32,001 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417715879] [2022-11-20 10:31:32,001 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417715879] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:32,001 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [405667083] [2022-11-20 10:31:32,001 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:31:32,002 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:32,002 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:32,005 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:32,035 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-20 10:31:32,085 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:31:32,085 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:32,086 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-20 10:31:32,088 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:32,164 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 10:31:32,287 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:31:32,289 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:32,290 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:32,375 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:31:32,379 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:31:32,396 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:32,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [405667083] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:32,397 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:32,397 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-20 10:31:32,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130822916] [2022-11-20 10:31:32,397 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:32,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:32,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-20 10:31:32,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2022-11-20 10:31:32,455 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 14 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:32,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:32,717 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2022-11-20 10:31:32,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 62 transitions. [2022-11-20 10:31:32,718 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:32,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 62 transitions. [2022-11-20 10:31:32,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-20 10:31:32,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-20 10:31:32,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 62 transitions. [2022-11-20 10:31:32,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:32,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 62 transitions. [2022-11-20 10:31:32,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 62 transitions. [2022-11-20 10:31:32,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 38. [2022-11-20 10:31:32,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.368421052631579) internal successors, (52), 37 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:32,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 52 transitions. [2022-11-20 10:31:32,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-20 10:31:32,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 10:31:32,749 INFO L428 stractBuchiCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-20 10:31:32,749 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-20 10:31:32,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 52 transitions. [2022-11-20 10:31:32,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:32,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:32,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:32,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:32,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:32,750 INFO L748 eck$LassoCheckResult]: Stem: 1105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1113#L367 assume !(main_~length~0#1 < 1); 1107#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1108#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1114#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1116#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1133#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1134#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1130#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1127#L370-4 main_~j~0#1 := 0; 1125#L378-2 [2022-11-20 10:31:32,750 INFO L750 eck$LassoCheckResult]: Loop: 1125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1126#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1125#L378-2 [2022-11-20 10:31:32,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:32,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1518446116, now seen corresponding path program 2 times [2022-11-20 10:31:32,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:32,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635444638] [2022-11-20 10:31:32,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:32,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:32,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:32,764 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:32,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:32,774 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:32,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:32,775 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-20 10:31:32,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:32,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915358185] [2022-11-20 10:31:32,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:32,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:32,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:32,779 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:32,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:32,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:32,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:32,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164511, now seen corresponding path program 2 times [2022-11-20 10:31:32,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:32,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618325886] [2022-11-20 10:31:32,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:32,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:32,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:33,341 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:33,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:33,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618325886] [2022-11-20 10:31:33,341 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618325886] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:33,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [914321697] [2022-11-20 10:31:33,341 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:31:33,342 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:33,342 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:33,346 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:33,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-20 10:31:33,436 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:31:33,436 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:33,437 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 10:31:33,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:33,480 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:33,574 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:33,575 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:33,591 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:33,592 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:33,634 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:33,635 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:33,653 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:33,654 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:31:33,736 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:31:33,739 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:31:33,740 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 10 [2022-11-20 10:31:33,754 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:33,755 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:34,448 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 25 [2022-11-20 10:31:34,460 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 74 [2022-11-20 10:31:34,539 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 10:31:34,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [914321697] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:34,540 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:34,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2022-11-20 10:31:34,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601944350] [2022-11-20 10:31:34,543 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:34,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:34,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-20 10:31:34,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=558, Unknown=0, NotChecked=0, Total=702 [2022-11-20 10:31:34,606 INFO L87 Difference]: Start difference. First operand 38 states and 52 transitions. cyclomatic complexity: 18 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:34,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:34,813 INFO L93 Difference]: Finished difference Result 43 states and 56 transitions. [2022-11-20 10:31:34,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 56 transitions. [2022-11-20 10:31:34,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:34,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 56 transitions. [2022-11-20 10:31:34,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 10:31:34,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 10:31:34,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 56 transitions. [2022-11-20 10:31:34,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:34,815 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 56 transitions. [2022-11-20 10:31:34,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 56 transitions. [2022-11-20 10:31:34,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 24. [2022-11-20 10:31:34,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:34,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2022-11-20 10:31:34,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-20 10:31:34,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 10:31:34,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-20 10:31:34,821 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-20 10:31:34,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2022-11-20 10:31:34,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:34,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:34,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:34,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:34,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:34,822 INFO L748 eck$LassoCheckResult]: Stem: 1329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1335#L367 assume !(main_~length~0#1 < 1); 1327#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1328#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1336#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1338#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1341#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1342#L370-4 main_~j~0#1 := 0; 1347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1334#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1340#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1345#L378-2 [2022-11-20 10:31:34,822 INFO L750 eck$LassoCheckResult]: Loop: 1345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1344#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1345#L378-2 [2022-11-20 10:31:34,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:34,822 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2022-11-20 10:31:34,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:34,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090791486] [2022-11-20 10:31:34,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:34,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:34,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:34,835 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:34,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:34,855 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:34,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:34,857 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-20 10:31:34,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:34,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659919311] [2022-11-20 10:31:34,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:34,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:34,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:34,861 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:34,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:34,865 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:34,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:34,866 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2022-11-20 10:31:34,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:34,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619186157] [2022-11-20 10:31:34,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:34,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:34,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:34,976 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:34,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619186157] [2022-11-20 10:31:34,976 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619186157] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:34,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [153224175] [2022-11-20 10:31:34,976 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:31:34,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:34,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:34,983 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:34,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-20 10:31:35,071 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-20 10:31:35,071 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:35,072 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-20 10:31:35,073 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:35,153 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:35,153 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:35,219 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:35,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [153224175] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:35,220 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:35,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-20 10:31:35,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374003956] [2022-11-20 10:31:35,220 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:35,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:35,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-20 10:31:35,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-20 10:31:35,274 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:35,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:35,416 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2022-11-20 10:31:35,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2022-11-20 10:31:35,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:35,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2022-11-20 10:31:35,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-20 10:31:35,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-20 10:31:35,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-20 10:31:35,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:35,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-20 10:31:35,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-20 10:31:35,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-11-20 10:31:35,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:35,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2022-11-20 10:31:35,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-20 10:31:35,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-20 10:31:35,421 INFO L428 stractBuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-20 10:31:35,421 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-20 10:31:35,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2022-11-20 10:31:35,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:35,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:35,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:35,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:35,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:35,423 INFO L748 eck$LassoCheckResult]: Stem: 1521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1530#L367 assume !(main_~length~0#1 < 1); 1523#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1524#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1531#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1534#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1533#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1541#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1540#L370-4 main_~j~0#1 := 0; 1529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1539#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1538#L378-2 [2022-11-20 10:31:35,423 INFO L750 eck$LassoCheckResult]: Loop: 1538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1537#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1538#L378-2 [2022-11-20 10:31:35,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:35,423 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 2 times [2022-11-20 10:31:35,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:35,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986351252] [2022-11-20 10:31:35,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:35,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:35,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:35,441 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:35,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:35,452 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:35,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:35,453 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-20 10:31:35,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:35,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117765832] [2022-11-20 10:31:35,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:35,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:35,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:35,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:35,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:35,465 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:35,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:35,467 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 2 times [2022-11-20 10:31:35,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:35,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514652927] [2022-11-20 10:31:35,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:35,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:35,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:35,764 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:35,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:35,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514652927] [2022-11-20 10:31:35,765 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514652927] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:35,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1157018651] [2022-11-20 10:31:35,765 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:31:35,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:35,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:35,771 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:35,776 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-20 10:31:35,844 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:31:35,845 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:35,846 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 10:31:35,848 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:35,922 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:36,011 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:36,013 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:36,025 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:36,026 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:36,123 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:31:36,129 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:36,129 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:36,274 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:31:36,277 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:31:36,298 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:36,298 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1157018651] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:36,298 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:36,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-20 10:31:36,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085470086] [2022-11-20 10:31:36,299 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:36,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:36,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-20 10:31:36,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-20 10:31:36,348 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:36,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:36,570 INFO L93 Difference]: Finished difference Result 30 states and 37 transitions. [2022-11-20 10:31:36,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2022-11-20 10:31:36,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:36,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 37 transitions. [2022-11-20 10:31:36,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 10:31:36,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 10:31:36,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2022-11-20 10:31:36,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:36,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 37 transitions. [2022-11-20 10:31:36,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2022-11-20 10:31:36,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 22. [2022-11-20 10:31:36,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:36,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2022-11-20 10:31:36,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-20 10:31:36,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-20 10:31:36,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-20 10:31:36,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-20 10:31:36,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2022-11-20 10:31:36,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:36,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:36,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:36,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:36,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:36,576 INFO L748 eck$LassoCheckResult]: Stem: 1727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1736#L367 assume !(main_~length~0#1 < 1); 1729#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1730#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1737#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1744#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1745#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1739#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1742#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1732#L370-4 main_~j~0#1 := 0; 1733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1734#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1741#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1748#L378-2 [2022-11-20 10:31:36,576 INFO L750 eck$LassoCheckResult]: Loop: 1748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1747#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1748#L378-2 [2022-11-20 10:31:36,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:36,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 4 times [2022-11-20 10:31:36,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:36,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077025154] [2022-11-20 10:31:36,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:36,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:36,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:36,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:36,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:36,619 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:36,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:36,620 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-20 10:31:36,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:36,620 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881590999] [2022-11-20 10:31:36,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:36,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:36,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:36,624 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:36,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:36,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:36,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:36,627 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2022-11-20 10:31:36,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:36,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952353679] [2022-11-20 10:31:36,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:36,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:36,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:36,854 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:36,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:36,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952353679] [2022-11-20 10:31:36,854 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952353679] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:36,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2082905053] [2022-11-20 10:31:36,855 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:31:36,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:36,855 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:36,861 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:36,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-20 10:31:36,937 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:31:36,938 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:36,939 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-20 10:31:36,940 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:36,966 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:37,083 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:31:37,086 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:37,086 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:37,171 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:31:37,174 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:31:37,200 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:37,201 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2082905053] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:37,201 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:37,201 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-20 10:31:37,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971700222] [2022-11-20 10:31:37,201 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:37,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:37,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-20 10:31:37,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-20 10:31:37,249 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:37,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:37,402 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2022-11-20 10:31:37,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 42 transitions. [2022-11-20 10:31:37,403 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:37,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 42 transitions. [2022-11-20 10:31:37,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 10:31:37,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 10:31:37,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2022-11-20 10:31:37,404 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:37,404 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 42 transitions. [2022-11-20 10:31:37,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2022-11-20 10:31:37,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 28. [2022-11-20 10:31:37,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:37,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2022-11-20 10:31:37,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-20 10:31:37,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 10:31:37,409 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-20 10:31:37,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-20 10:31:37,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2022-11-20 10:31:37,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:37,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:37,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:37,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:37,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:37,411 INFO L748 eck$LassoCheckResult]: Stem: 1933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1941#L367 assume !(main_~length~0#1 < 1); 1935#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1936#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1942#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1952#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1944#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 1946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1949#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1950#L370-4 main_~j~0#1 := 0; 1958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1938#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1939#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1945#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1956#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1955#L378-2 [2022-11-20 10:31:37,411 INFO L750 eck$LassoCheckResult]: Loop: 1955#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1954#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1955#L378-2 [2022-11-20 10:31:37,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:37,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 5 times [2022-11-20 10:31:37,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:37,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510677813] [2022-11-20 10:31:37,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:37,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:37,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:37,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:37,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:37,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:37,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:37,443 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-20 10:31:37,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:37,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068338165] [2022-11-20 10:31:37,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:37,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:37,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:37,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:37,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:37,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:37,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:37,453 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2022-11-20 10:31:37,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:37,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043996615] [2022-11-20 10:31:37,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:37,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:37,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:37,580 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:37,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:37,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043996615] [2022-11-20 10:31:37,581 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043996615] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:37,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1654984193] [2022-11-20 10:31:37,581 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:31:37,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:37,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:37,587 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:37,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-20 10:31:37,671 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-20 10:31:37,671 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:37,673 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-20 10:31:37,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:37,790 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:37,790 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:37,885 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:37,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1654984193] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:37,886 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:37,886 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-20 10:31:37,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085768590] [2022-11-20 10:31:37,886 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:37,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:37,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-20 10:31:37,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-20 10:31:37,935 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 9 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:38,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:38,073 INFO L93 Difference]: Finished difference Result 35 states and 42 transitions. [2022-11-20 10:31:38,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 42 transitions. [2022-11-20 10:31:38,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:38,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 27 states and 34 transitions. [2022-11-20 10:31:38,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:31:38,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:31:38,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2022-11-20 10:31:38,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:38,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 34 transitions. [2022-11-20 10:31:38,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2022-11-20 10:31:38,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2022-11-20 10:31:38,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.24) internal successors, (31), 24 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:38,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 31 transitions. [2022-11-20 10:31:38,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-20 10:31:38,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-20 10:31:38,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-20 10:31:38,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-20 10:31:38,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 31 transitions. [2022-11-20 10:31:38,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:38,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:38,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:38,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:38,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:38,080 INFO L748 eck$LassoCheckResult]: Stem: 2166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2175#L367 assume !(main_~length~0#1 < 1); 2168#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2169#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2176#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2178#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2187#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2183#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2182#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2171#L370-4 main_~j~0#1 := 0; 2172#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2173#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2180#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2190#L378-2 [2022-11-20 10:31:38,080 INFO L750 eck$LassoCheckResult]: Loop: 2190#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2189#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2190#L378-2 [2022-11-20 10:31:38,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:38,081 INFO L85 PathProgramCache]: Analyzing trace with hash 666851296, now seen corresponding path program 6 times [2022-11-20 10:31:38,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:38,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469310434] [2022-11-20 10:31:38,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:38,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:38,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:38,100 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:38,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:38,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:38,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:38,134 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-20 10:31:38,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:38,134 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354525851] [2022-11-20 10:31:38,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:38,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:38,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:38,138 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:38,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:38,141 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:38,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:38,142 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 6 times [2022-11-20 10:31:38,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:38,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728624833] [2022-11-20 10:31:38,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:38,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:38,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:38,528 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:38,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:38,529 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728624833] [2022-11-20 10:31:38,529 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728624833] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:38,529 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1941852429] [2022-11-20 10:31:38,529 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:31:38,530 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:38,530 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:38,535 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:38,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-20 10:31:38,639 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-20 10:31:38,640 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:38,641 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-20 10:31:38,647 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:38,752 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:38,870 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:38,871 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:39,033 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:31:39,035 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:39,036 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:39,205 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:31:39,210 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:31:39,248 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:39,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1941852429] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:39,249 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:39,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2022-11-20 10:31:39,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567789164] [2022-11-20 10:31:39,249 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:39,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:39,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-20 10:31:39,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2022-11-20 10:31:39,303 INFO L87 Difference]: Start difference. First operand 25 states and 31 transitions. cyclomatic complexity: 8 Second operand has 27 states, 26 states have (on average 2.0) internal successors, (52), 27 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:39,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:39,664 INFO L93 Difference]: Finished difference Result 27 states and 33 transitions. [2022-11-20 10:31:39,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 33 transitions. [2022-11-20 10:31:39,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:39,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 33 transitions. [2022-11-20 10:31:39,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-20 10:31:39,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-20 10:31:39,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 33 transitions. [2022-11-20 10:31:39,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:39,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 10:31:39,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 33 transitions. [2022-11-20 10:31:39,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-11-20 10:31:39,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:39,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2022-11-20 10:31:39,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 10:31:39,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-20 10:31:39,670 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 10:31:39,670 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-20 10:31:39,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2022-11-20 10:31:39,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:39,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:39,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:39,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:39,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:39,672 INFO L748 eck$LassoCheckResult]: Stem: 2406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2413#L367 assume !(main_~length~0#1 < 1); 2404#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2405#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2414#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2415#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2416#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2425#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2421#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2422#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2420#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2409#L370-4 main_~j~0#1 := 0; 2410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2411#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2418#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2429#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2428#L378-2 [2022-11-20 10:31:39,672 INFO L750 eck$LassoCheckResult]: Loop: 2428#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2427#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2428#L378-2 [2022-11-20 10:31:39,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:39,672 INFO L85 PathProgramCache]: Analyzing trace with hash 893969701, now seen corresponding path program 7 times [2022-11-20 10:31:39,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:39,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796617155] [2022-11-20 10:31:39,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:39,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:39,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:39,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:39,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:39,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:39,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:39,701 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-20 10:31:39,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:39,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894094292] [2022-11-20 10:31:39,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:39,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:39,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:39,704 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:39,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:39,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:39,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:39,708 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 7 times [2022-11-20 10:31:39,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:39,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920904587] [2022-11-20 10:31:39,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:39,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:39,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:40,052 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:40,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:40,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920904587] [2022-11-20 10:31:40,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920904587] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:40,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1543035085] [2022-11-20 10:31:40,052 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:31:40,053 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:40,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:40,058 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:40,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-20 10:31:40,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:40,150 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-20 10:31:40,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:40,193 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:40,397 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:31:40,401 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:40,402 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:40,518 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:31:40,522 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:31:40,569 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:40,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1543035085] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:40,569 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:40,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 19 [2022-11-20 10:31:40,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599321624] [2022-11-20 10:31:40,570 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:40,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:40,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-20 10:31:40,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2022-11-20 10:31:40,628 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 8 Second operand has 20 states, 19 states have (on average 2.1578947368421053) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:40,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:40,899 INFO L93 Difference]: Finished difference Result 43 states and 53 transitions. [2022-11-20 10:31:40,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 53 transitions. [2022-11-20 10:31:40,900 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:40,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 53 transitions. [2022-11-20 10:31:40,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2022-11-20 10:31:40,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2022-11-20 10:31:40,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 53 transitions. [2022-11-20 10:31:40,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:40,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 53 transitions. [2022-11-20 10:31:40,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 53 transitions. [2022-11-20 10:31:40,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 34. [2022-11-20 10:31:40,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:40,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-20 10:31:40,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-20 10:31:40,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-20 10:31:40,906 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-20 10:31:40,906 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-20 10:31:40,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-20 10:31:40,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:40,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:40,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:40,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:40,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:40,909 INFO L748 eck$LassoCheckResult]: Stem: 2657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2665#L367 assume !(main_~length~0#1 < 1); 2659#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2660#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2666#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2668#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2679#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2676#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2672#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2673#L370-4 main_~j~0#1 := 0; 2687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2685#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2684#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2683#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2682#L378-2 [2022-11-20 10:31:40,909 INFO L750 eck$LassoCheckResult]: Loop: 2682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2681#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2682#L378-2 [2022-11-20 10:31:40,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:40,909 INFO L85 PathProgramCache]: Analyzing trace with hash 111424810, now seen corresponding path program 8 times [2022-11-20 10:31:40,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:40,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344824439] [2022-11-20 10:31:40,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:40,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:40,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:40,924 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:40,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:40,942 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:40,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:40,942 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-20 10:31:40,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:40,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421488172] [2022-11-20 10:31:40,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:40,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:40,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:40,946 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:40,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:40,949 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:40,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:40,950 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 8 times [2022-11-20 10:31:40,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:40,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665422405] [2022-11-20 10:31:40,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:40,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:40,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:41,164 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:41,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:41,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665422405] [2022-11-20 10:31:41,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665422405] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:41,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1491641973] [2022-11-20 10:31:41,165 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:31:41,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:41,165 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:41,170 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:41,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-20 10:31:41,258 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:31:41,258 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:41,259 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-20 10:31:41,260 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:41,403 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:41,403 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:41,520 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:41,520 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1491641973] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:41,520 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:41,520 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-20 10:31:41,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024646003] [2022-11-20 10:31:41,521 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:41,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:41,600 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-20 10:31:41,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-20 10:31:41,600 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 12 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:41,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:41,755 INFO L93 Difference]: Finished difference Result 49 states and 59 transitions. [2022-11-20 10:31:41,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 59 transitions. [2022-11-20 10:31:41,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:41,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 39 states and 49 transitions. [2022-11-20 10:31:41,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 10:31:41,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 10:31:41,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2022-11-20 10:31:41,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:41,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-20 10:31:41,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2022-11-20 10:31:41,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 36. [2022-11-20 10:31:41,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.25) internal successors, (45), 35 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:41,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 45 transitions. [2022-11-20 10:31:41,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-20 10:31:41,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-20 10:31:41,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-20 10:31:41,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-20 10:31:41,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 45 transitions. [2022-11-20 10:31:41,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:41,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:41,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:41,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:41,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:41,771 INFO L748 eck$LassoCheckResult]: Stem: 2945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2953#L367 assume !(main_~length~0#1 < 1); 2947#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2948#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2954#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2970#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2956#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2969#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2966#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 2965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2963#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2964#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2960#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2952#L370-4 main_~j~0#1 := 0; 2951#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2958#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2975#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2973#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2972#L378-2 [2022-11-20 10:31:41,771 INFO L750 eck$LassoCheckResult]: Loop: 2972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2971#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2972#L378-2 [2022-11-20 10:31:41,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:41,772 INFO L85 PathProgramCache]: Analyzing trace with hash -188031059, now seen corresponding path program 3 times [2022-11-20 10:31:41,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:41,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975977371] [2022-11-20 10:31:41,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:41,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:41,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:41,791 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:41,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:41,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:41,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:41,807 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-20 10:31:41,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:41,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659907411] [2022-11-20 10:31:41,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:41,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:41,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:41,811 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:41,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:41,813 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:41,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:41,814 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 3 times [2022-11-20 10:31:41,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:41,815 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340120949] [2022-11-20 10:31:41,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:41,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:41,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:42,240 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:42,240 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:42,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340120949] [2022-11-20 10:31:42,240 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340120949] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:42,240 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [957869345] [2022-11-20 10:31:42,240 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:31:42,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:42,241 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:42,245 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:42,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-20 10:31:42,376 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-20 10:31:42,377 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:42,378 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 10:31:42,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:42,454 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:42,587 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:31:42,587 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-20 10:31:42,662 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:31:42,662 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-20 10:31:43,309 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-20 10:31:43,310 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-20 10:31:43,335 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:43,335 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:44,051 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:31:44,055 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:31:44,132 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 39 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-20 10:31:44,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [957869345] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:44,132 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:44,133 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 14] total 37 [2022-11-20 10:31:44,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883993402] [2022-11-20 10:31:44,133 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:44,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:44,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 10:31:44,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1216, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 10:31:44,189 INFO L87 Difference]: Start difference. First operand 36 states and 45 transitions. cyclomatic complexity: 12 Second operand has 38 states, 37 states have (on average 1.864864864864865) internal successors, (69), 38 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:45,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:45,938 INFO L93 Difference]: Finished difference Result 73 states and 87 transitions. [2022-11-20 10:31:45,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 87 transitions. [2022-11-20 10:31:45,939 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-20 10:31:45,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 87 transitions. [2022-11-20 10:31:45,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-20 10:31:45,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-20 10:31:45,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 87 transitions. [2022-11-20 10:31:45,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:31:45,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 87 transitions. [2022-11-20 10:31:45,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 87 transitions. [2022-11-20 10:31:45,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 43. [2022-11-20 10:31:45,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:45,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-20 10:31:45,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 10:31:45,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-20 10:31:45,952 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 10:31:45,952 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-20 10:31:45,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-20 10:31:45,953 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:45,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:45,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:45,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:45,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:45,954 INFO L748 eck$LassoCheckResult]: Stem: 3321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3327#L367 assume !(main_~length~0#1 < 1); 3319#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3320#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3337#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3343#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3340#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3330#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3331#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3335#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3324#L370-4 main_~j~0#1 := 0; 3325#L378-2 [2022-11-20 10:31:45,954 INFO L750 eck$LassoCheckResult]: Loop: 3325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3326#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3325#L378-2 [2022-11-20 10:31:45,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:45,954 INFO L85 PathProgramCache]: Analyzing trace with hash 438748702, now seen corresponding path program 3 times [2022-11-20 10:31:45,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:45,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76231371] [2022-11-20 10:31:45,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:45,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:45,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:45,968 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:45,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:45,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:45,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:45,980 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-20 10:31:45,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:45,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447320455] [2022-11-20 10:31:45,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:45,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:45,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:45,984 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:45,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:45,987 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:45,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:45,987 INFO L85 PathProgramCache]: Analyzing trace with hash 730708963, now seen corresponding path program 4 times [2022-11-20 10:31:45,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:45,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23333122] [2022-11-20 10:31:45,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:45,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:46,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:46,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:46,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:46,013 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:47,799 INFO L210 LassoAnalysis]: Preferences: [2022-11-20 10:31:47,800 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-20 10:31:47,800 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-20 10:31:47,800 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-20 10:31:47,800 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-20 10:31:47,800 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:47,800 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-20 10:31:47,800 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-20 10:31:47,800 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration18_Lasso [2022-11-20 10:31:47,800 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-20 10:31:47,800 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-20 10:31:47,803 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:47,807 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:47,810 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:47,813 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:47,815 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:47,817 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,198 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,200 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,203 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,205 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,208 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,211 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 10:31:48,580 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-20 10:31:48,580 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-20 10:31:48,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,589 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,592 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-20 10:31:48,606 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,607 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,607 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,607 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,613 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,613 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,631 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,642 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,643 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,643 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,644 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,661 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-20 10:31:48,675 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,676 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:48,676 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,676 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,676 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,677 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:48,677 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:48,686 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,696 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,697 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,697 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,698 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,709 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,721 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,721 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,721 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,721 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,723 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,723 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,727 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-20 10:31:48,733 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,743 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,744 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,748 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,760 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,760 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:48,760 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,760 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,760 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,761 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:48,761 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:48,763 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-20 10:31:48,774 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,784 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,784 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,785 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,789 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,802 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,802 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 10:31:48,802 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,802 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,802 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,803 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 10:31:48,803 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 10:31:48,805 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-20 10:31:48,819 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,828 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,829 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,830 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,833 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,845 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,846 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,846 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,846 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-20 10:31:48,848 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,849 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,869 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,878 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,880 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,883 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,896 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,896 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,896 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,896 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-20 10:31:48,905 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,905 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,916 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,921 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,921 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,922 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,923 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,927 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,940 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,940 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,940 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,940 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,943 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,943 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,948 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-11-20 10:31:48,955 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:48,964 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:48,965 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:48,965 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:48,966 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:48,972 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:48,984 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:48,984 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:48,984 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:48,984 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:48,986 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:48,987 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:48,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-11-20 10:31:49,003 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:49,012 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:49,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:49,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:49,014 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:49,017 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:49,023 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-11-20 10:31:49,029 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:49,030 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:49,030 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:49,030 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:49,031 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:49,031 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:49,042 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 10:31:49,048 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:49,048 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:49,048 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:49,049 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:49,053 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 10:31:49,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-11-20 10:31:49,065 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 10:31:49,065 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 10:31:49,065 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 10:31:49,066 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 10:31:49,073 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 10:31:49,073 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 10:31:49,089 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-20 10:31:49,123 INFO L443 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2022-11-20 10:31:49,123 INFO L444 ModelExtractionUtils]: 2 out of 25 variables were initially zero. Simplification set additionally 19 variables to zero. [2022-11-20 10:31:49,123 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 10:31:49,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:49,131 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 10:31:49,132 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-20 10:31:49,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-11-20 10:31:49,162 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-20 10:31:49,162 INFO L513 LassoAnalysis]: Proved termination. [2022-11-20 10:31:49,163 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1, v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2) = -1*ULTIMATE.start_main_~arr~0#1.offset - 4*ULTIMATE.start_main_~j~0#1 + 2*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 Supporting invariants [] [2022-11-20 10:31:49,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:49,196 INFO L156 tatePredicateManager]: 7 out of 8 supporting invariants were superfluous and have been removed [2022-11-20 10:31:49,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:49,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:49,248 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 10:31:49,249 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:49,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:49,349 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-20 10:31:49,350 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:49,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:49,379 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-20 10:31:49,380 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:49,420 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 53 states and 68 transitions. Complement of second has 6 states. [2022-11-20 10:31:49,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-20 10:31:49,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:49,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2022-11-20 10:31:49,421 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 2 letters. [2022-11-20 10:31:49,421 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:49,422 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 24 letters. Loop has 2 letters. [2022-11-20 10:31:49,422 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:49,422 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 4 letters. [2022-11-20 10:31:49,422 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 10:31:49,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 68 transitions. [2022-11-20 10:31:49,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:49,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 44 states and 56 transitions. [2022-11-20 10:31:49,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-20 10:31:49,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:31:49,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2022-11-20 10:31:49,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:31:49,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 56 transitions. [2022-11-20 10:31:49,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2022-11-20 10:31:49,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2022-11-20 10:31:49,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:49,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-20 10:31:49,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 10:31:49,429 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 10:31:49,429 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-20 10:31:49,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-20 10:31:49,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:49,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:49,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:49,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:49,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:49,432 INFO L748 eck$LassoCheckResult]: Stem: 3546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3557#L367 assume !(main_~length~0#1 < 1); 3548#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3549#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3558#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3559#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3560#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3586#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3583#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3579#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3574#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3573#L370-4 main_~j~0#1 := 0; 3572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3553#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3562#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3569#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3568#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3551#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-20 10:31:49,432 INFO L750 eck$LassoCheckResult]: Loop: 3552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3565#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-20 10:31:49,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:49,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 9 times [2022-11-20 10:31:49,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:49,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122709217] [2022-11-20 10:31:49,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:49,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:49,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:49,540 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2022-11-20 10:31:49,796 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:49,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:49,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122709217] [2022-11-20 10:31:49,797 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122709217] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:49,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2147217064] [2022-11-20 10:31:49,797 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:31:49,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:49,797 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:49,799 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:49,801 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-20 10:31:49,905 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-20 10:31:49,906 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:49,907 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-20 10:31:49,908 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:50,010 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:50,461 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:31:50,462 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:31:50,465 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:50,466 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:51,044 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:31:51,049 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:31:51,153 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:51,153 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2147217064] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:51,153 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:51,153 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2022-11-20 10:31:51,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564964544] [2022-11-20 10:31:51,155 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:51,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:51,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:51,156 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-20 10:31:51,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:51,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111233011] [2022-11-20 10:31:51,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:51,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:51,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:51,160 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:51,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:51,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:51,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:51,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-20 10:31:51,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=1288, Unknown=0, NotChecked=0, Total=1482 [2022-11-20 10:31:51,214 INFO L87 Difference]: Start difference. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 39 states, 38 states have (on average 1.9210526315789473) internal successors, (73), 39 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:52,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:52,121 INFO L93 Difference]: Finished difference Result 60 states and 74 transitions. [2022-11-20 10:31:52,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 74 transitions. [2022-11-20 10:31:52,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:52,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 47 states and 59 transitions. [2022-11-20 10:31:52,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:31:52,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:31:52,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-20 10:31:52,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:31:52,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 10:31:52,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-20 10:31:52,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-11-20 10:31:52,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.2666666666666666) internal successors, (57), 44 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:52,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 57 transitions. [2022-11-20 10:31:52,126 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-20 10:31:52,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-20 10:31:52,135 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-20 10:31:52,135 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-20 10:31:52,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 57 transitions. [2022-11-20 10:31:52,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:52,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:52,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:52,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:52,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:52,137 INFO L748 eck$LassoCheckResult]: Stem: 3925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3936#L367 assume !(main_~length~0#1 < 1); 3927#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3928#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3929#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3969#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3939#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3967#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3965#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3964#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3963#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3961#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3942#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3958#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 3956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3952#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3934#L370-4 main_~j~0#1 := 0; 3935#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3932#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3933#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3948#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3946#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3930#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-20 10:31:52,137 INFO L750 eck$LassoCheckResult]: Loop: 3931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3944#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-20 10:31:52,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:52,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1236423398, now seen corresponding path program 4 times [2022-11-20 10:31:52,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:52,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947790734] [2022-11-20 10:31:52,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:52,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:52,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:52,632 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:52,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:52,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947790734] [2022-11-20 10:31:52,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947790734] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:52,633 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [725240295] [2022-11-20 10:31:52,633 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:31:52,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:52,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:52,634 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:52,663 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-20 10:31:52,742 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:31:52,743 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:52,744 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-20 10:31:52,746 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:52,779 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:52,866 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 10:31:52,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:52,887 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 10:31:52,888 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:52,938 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 10:31:52,939 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:53,112 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:31:53,116 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:53,116 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:53,396 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:31:53,402 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:31:53,449 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 10:31:53,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [725240295] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:53,449 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:53,449 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-20 10:31:53,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416987043] [2022-11-20 10:31:53,450 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:53,451 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:53,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:53,451 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-20 10:31:53,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:53,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065280727] [2022-11-20 10:31:53,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:53,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:53,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:53,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:53,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:53,458 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:53,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:53,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-20 10:31:53,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=478, Unknown=0, NotChecked=0, Total=552 [2022-11-20 10:31:53,512 INFO L87 Difference]: Start difference. First operand 45 states and 57 transitions. cyclomatic complexity: 17 Second operand has 24 states, 23 states have (on average 2.217391304347826) internal successors, (51), 24 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:53,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:53,920 INFO L93 Difference]: Finished difference Result 54 states and 66 transitions. [2022-11-20 10:31:53,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 66 transitions. [2022-11-20 10:31:53,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:53,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 65 transitions. [2022-11-20 10:31:53,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:31:53,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:31:53,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 65 transitions. [2022-11-20 10:31:53,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:31:53,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 65 transitions. [2022-11-20 10:31:53,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 65 transitions. [2022-11-20 10:31:53,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 40. [2022-11-20 10:31:53,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.25) internal successors, (50), 39 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:53,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2022-11-20 10:31:53,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-20 10:31:53,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-20 10:31:53,932 INFO L428 stractBuchiCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-20 10:31:53,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-20 10:31:53,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 50 transitions. [2022-11-20 10:31:53,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:53,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:53,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:53,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:53,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:53,937 INFO L748 eck$LassoCheckResult]: Stem: 4253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4264#L367 assume !(main_~length~0#1 < 1); 4255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4270#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4291#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4289#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4288#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4285#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4283#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4282#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4279#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4275#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4262#L370-4 main_~j~0#1 := 0; 4263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4268#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4260#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4258#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-20 10:31:53,937 INFO L750 eck$LassoCheckResult]: Loop: 4259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4274#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-20 10:31:53,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:53,938 INFO L85 PathProgramCache]: Analyzing trace with hash -1503052245, now seen corresponding path program 5 times [2022-11-20 10:31:53,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:53,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703616872] [2022-11-20 10:31:53,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:53,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:53,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:54,386 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:54,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:54,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703616872] [2022-11-20 10:31:54,387 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703616872] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:54,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [751151559] [2022-11-20 10:31:54,387 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:31:54,387 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:54,387 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:54,399 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:54,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-20 10:31:54,528 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-20 10:31:54,528 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:54,530 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-20 10:31:54,532 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:54,714 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:54,793 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:31:54,793 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:31:55,150 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:31:55,152 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:31:55,153 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 10:31:55,209 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:55,210 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:55,860 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 26 [2022-11-20 10:31:55,865 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 86 [2022-11-20 10:31:55,954 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:55,954 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [751151559] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:55,954 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:55,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 16] total 40 [2022-11-20 10:31:55,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142141897] [2022-11-20 10:31:55,955 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:55,955 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:55,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:55,955 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-20 10:31:55,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:55,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420358369] [2022-11-20 10:31:55,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:55,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:55,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:55,959 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:55,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:55,962 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:56,005 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:56,006 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 10:31:56,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=1492, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 10:31:56,007 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. cyclomatic complexity: 14 Second operand has 41 states, 40 states have (on average 2.075) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:56,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:56,905 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2022-11-20 10:31:56,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 77 transitions. [2022-11-20 10:31:56,906 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:56,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 76 transitions. [2022-11-20 10:31:56,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-20 10:31:56,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-20 10:31:56,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 76 transitions. [2022-11-20 10:31:56,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:31:56,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 76 transitions. [2022-11-20 10:31:56,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 76 transitions. [2022-11-20 10:31:56,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 47. [2022-11-20 10:31:56,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2553191489361701) internal successors, (59), 46 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:56,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 59 transitions. [2022-11-20 10:31:56,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 10:31:56,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-20 10:31:56,919 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 10:31:56,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-20 10:31:56,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 59 transitions. [2022-11-20 10:31:56,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:56,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:56,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:56,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:56,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:56,923 INFO L748 eck$LassoCheckResult]: Stem: 4622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4633#L367 assume !(main_~length~0#1 < 1); 4624#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4625#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4634#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4640#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4636#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4656#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4650#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4648#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 4668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4667#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4666#L370-4 main_~j~0#1 := 0; 4637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4629#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4659#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4627#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-20 10:31:56,923 INFO L750 eck$LassoCheckResult]: Loop: 4628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4660#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-20 10:31:56,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:56,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 10 times [2022-11-20 10:31:56,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:56,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030908274] [2022-11-20 10:31:56,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:56,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:56,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:57,399 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:57,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:57,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030908274] [2022-11-20 10:31:57,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030908274] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:57,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1027459583] [2022-11-20 10:31:57,400 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:31:57,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:57,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:57,406 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:57,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-20 10:31:57,501 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:31:57,501 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:57,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-20 10:31:57,504 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:57,555 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:57,652 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:31:57,652 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:31:57,817 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:31:57,820 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:57,820 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:31:58,023 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:31:58,026 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:31:58,078 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:58,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1027459583] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:31:58,078 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:31:58,078 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-11-20 10:31:58,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117015259] [2022-11-20 10:31:58,079 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:31:58,079 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:31:58,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:58,079 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-20 10:31:58,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:58,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007400554] [2022-11-20 10:31:58,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:58,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:58,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:58,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:31:58,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:31:58,086 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:31:58,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:31:58,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-20 10:31:58,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2022-11-20 10:31:58,133 INFO L87 Difference]: Start difference. First operand 47 states and 59 transitions. cyclomatic complexity: 17 Second operand has 26 states, 25 states have (on average 2.12) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:58,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:31:58,496 INFO L93 Difference]: Finished difference Result 84 states and 102 transitions. [2022-11-20 10:31:58,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 102 transitions. [2022-11-20 10:31:58,496 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:31:58,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 101 transitions. [2022-11-20 10:31:58,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-20 10:31:58,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-20 10:31:58,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 101 transitions. [2022-11-20 10:31:58,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:31:58,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 101 transitions. [2022-11-20 10:31:58,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 101 transitions. [2022-11-20 10:31:58,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 50. [2022-11-20 10:31:58,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.28) internal successors, (64), 49 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:31:58,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 64 transitions. [2022-11-20 10:31:58,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-20 10:31:58,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-20 10:31:58,501 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-20 10:31:58,502 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-20 10:31:58,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 64 transitions. [2022-11-20 10:31:58,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:31:58,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:31:58,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:31:58,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:31:58,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:31:58,503 INFO L748 eck$LassoCheckResult]: Stem: 4988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4999#L367 assume !(main_~length~0#1 < 1); 4990#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4991#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5000#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5035#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5032#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5029#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5002#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5004#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4993#L370-4 main_~j~0#1 := 0; 4994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4997#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4998#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5006#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5016#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5015#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5014#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5013#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5012#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5010#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4995#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-20 10:31:58,504 INFO L750 eck$LassoCheckResult]: Loop: 4996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5011#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-20 10:31:58,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:31:58,504 INFO L85 PathProgramCache]: Analyzing trace with hash -1324192720, now seen corresponding path program 6 times [2022-11-20 10:31:58,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:31:58,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898756146] [2022-11-20 10:31:58,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:31:58,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:31:58,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:31:58,917 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:58,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:31:58,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898756146] [2022-11-20 10:31:58,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898756146] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:31:58,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1314119699] [2022-11-20 10:31:58,918 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:31:58,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:31:58,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:31:58,921 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:31:58,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-20 10:31:59,104 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-20 10:31:59,104 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:31:59,106 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-20 10:31:59,108 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:31:59,252 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:31:59,888 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:31:59,888 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:31:59,892 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:31:59,892 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:00,697 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:32:00,701 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:32:00,845 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:00,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1314119699] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:00,846 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:00,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 43 [2022-11-20 10:32:00,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028305583] [2022-11-20 10:32:00,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:00,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:00,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:00,847 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-20 10:32:00,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:00,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824118234] [2022-11-20 10:32:00,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:00,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:00,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:00,850 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:00,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:00,854 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:00,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:00,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-20 10:32:00,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=1654, Unknown=0, NotChecked=0, Total=1892 [2022-11-20 10:32:00,905 INFO L87 Difference]: Start difference. First operand 50 states and 64 transitions. cyclomatic complexity: 19 Second operand has 44 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 44 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:02,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:02,022 INFO L93 Difference]: Finished difference Result 72 states and 89 transitions. [2022-11-20 10:32:02,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 89 transitions. [2022-11-20 10:32:02,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:02,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 57 states and 71 transitions. [2022-11-20 10:32:02,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:02,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:02,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 71 transitions. [2022-11-20 10:32:02,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:02,024 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 71 transitions. [2022-11-20 10:32:02,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 71 transitions. [2022-11-20 10:32:02,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 55. [2022-11-20 10:32:02,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.2545454545454546) internal successors, (69), 54 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:02,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 69 transitions. [2022-11-20 10:32:02,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 69 transitions. [2022-11-20 10:32:02,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-11-20 10:32:02,035 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 69 transitions. [2022-11-20 10:32:02,035 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-20 10:32:02,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 69 transitions. [2022-11-20 10:32:02,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:02,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:02,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:02,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:02,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:02,037 INFO L748 eck$LassoCheckResult]: Stem: 5426#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5437#L367 assume !(main_~length~0#1 < 1); 5428#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5429#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5430#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5438#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5480#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5440#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5479#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5478#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5477#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5476#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5475#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5474#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5471#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5469#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5465#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5463#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5462#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5461#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5456#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5431#L370-4 main_~j~0#1 := 0; 5432#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5435#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5436#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5454#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5452#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5450#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5449#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5433#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5434#L378-2 [2022-11-20 10:32:02,037 INFO L750 eck$LassoCheckResult]: Loop: 5434#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5448#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5434#L378-2 [2022-11-20 10:32:02,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:02,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1722738829, now seen corresponding path program 11 times [2022-11-20 10:32:02,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:02,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643133466] [2022-11-20 10:32:02,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:02,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:02,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:02,575 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:02,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:02,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643133466] [2022-11-20 10:32:02,575 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643133466] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:02,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [903847487] [2022-11-20 10:32:02,576 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:32:02,576 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:02,576 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:02,579 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:02,597 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-20 10:32:02,732 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-20 10:32:02,732 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:02,734 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-20 10:32:02,737 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:02,926 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:03,041 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:32:03,043 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:32:03,110 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:32:03,111 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:32:03,472 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:32:03,474 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:32:03,475 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 10:32:03,479 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 1 proven. 89 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:03,479 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:03,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:32:03,832 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:32:03,891 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 1 proven. 88 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 10:32:03,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [903847487] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:03,892 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:03,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 18] total 38 [2022-11-20 10:32:03,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773679345] [2022-11-20 10:32:03,892 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:03,893 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:03,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:03,893 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-20 10:32:03,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:03,894 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199432897] [2022-11-20 10:32:03,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:03,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:03,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:03,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:03,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:03,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:03,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:03,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-20 10:32:03,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=158, Invalid=1324, Unknown=0, NotChecked=0, Total=1482 [2022-11-20 10:32:03,955 INFO L87 Difference]: Start difference. First operand 55 states and 69 transitions. cyclomatic complexity: 19 Second operand has 39 states, 38 states have (on average 2.1315789473684212) internal successors, (81), 39 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:04,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:04,511 INFO L93 Difference]: Finished difference Result 66 states and 80 transitions. [2022-11-20 10:32:04,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 80 transitions. [2022-11-20 10:32:04,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:04,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 65 states and 79 transitions. [2022-11-20 10:32:04,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:04,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:04,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 79 transitions. [2022-11-20 10:32:04,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:04,513 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65 states and 79 transitions. [2022-11-20 10:32:04,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 79 transitions. [2022-11-20 10:32:04,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 48. [2022-11-20 10:32:04,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.25) internal successors, (60), 47 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:04,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 60 transitions. [2022-11-20 10:32:04,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 48 states and 60 transitions. [2022-11-20 10:32:04,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-20 10:32:04,516 INFO L428 stractBuchiCegarLoop]: Abstraction has 48 states and 60 transitions. [2022-11-20 10:32:04,517 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-20 10:32:04,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 60 transitions. [2022-11-20 10:32:04,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:04,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:04,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:04,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:04,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:04,521 INFO L748 eck$LassoCheckResult]: Stem: 5825#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5836#L367 assume !(main_~length~0#1 < 1); 5827#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5828#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5837#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5872#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5869#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5867#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5866#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5865#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5864#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5863#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5860#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5859#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5857#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5852#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5851#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 5849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5843#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5830#L370-4 main_~j~0#1 := 0; 5831#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5834#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5835#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5841#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5871#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5856#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5853#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5850#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5848#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5846#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5832#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5833#L378-2 [2022-11-20 10:32:04,521 INFO L750 eck$LassoCheckResult]: Loop: 5833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5847#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5833#L378-2 [2022-11-20 10:32:04,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:04,522 INFO L85 PathProgramCache]: Analyzing trace with hash -519513416, now seen corresponding path program 7 times [2022-11-20 10:32:04,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:04,522 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013334906] [2022-11-20 10:32:04,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:04,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:04,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:05,035 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:05,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:05,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013334906] [2022-11-20 10:32:05,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013334906] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:05,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1550916906] [2022-11-20 10:32:05,036 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:32:05,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:05,036 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:05,040 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:05,042 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-20 10:32:05,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:05,157 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-20 10:32:05,159 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:05,404 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:05,490 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:32:05,807 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:32:05,832 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:05,832 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:06,261 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-20 10:32:06,264 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 62 [2022-11-20 10:32:06,337 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:06,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1550916906] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:06,337 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:06,337 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 17] total 43 [2022-11-20 10:32:06,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133898504] [2022-11-20 10:32:06,338 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:06,338 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:06,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:06,339 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-20 10:32:06,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:06,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298236854] [2022-11-20 10:32:06,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:06,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:06,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:06,342 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:06,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:06,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:06,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:06,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-20 10:32:06,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1739, Unknown=0, NotChecked=0, Total=1892 [2022-11-20 10:32:06,404 INFO L87 Difference]: Start difference. First operand 48 states and 60 transitions. cyclomatic complexity: 16 Second operand has 44 states, 43 states have (on average 2.2093023255813953) internal successors, (95), 44 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:07,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:07,480 INFO L93 Difference]: Finished difference Result 77 states and 94 transitions. [2022-11-20 10:32:07,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 94 transitions. [2022-11-20 10:32:07,487 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:32:07,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 76 states and 93 transitions. [2022-11-20 10:32:07,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-20 10:32:07,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-20 10:32:07,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 93 transitions. [2022-11-20 10:32:07,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:07,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76 states and 93 transitions. [2022-11-20 10:32:07,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 93 transitions. [2022-11-20 10:32:07,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 60. [2022-11-20 10:32:07,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.25) internal successors, (75), 59 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:07,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2022-11-20 10:32:07,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2022-11-20 10:32:07,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-20 10:32:07,495 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 75 transitions. [2022-11-20 10:32:07,496 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-20 10:32:07,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 75 transitions. [2022-11-20 10:32:07,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:07,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:07,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:07,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:07,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:07,498 INFO L748 eck$LassoCheckResult]: Stem: 6253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6264#L367 assume !(main_~length~0#1 < 1); 6255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6265#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6266#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6267#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6271#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6272#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6296#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6294#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6293#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6292#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6291#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6290#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6287#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6284#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6279#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6274#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6310#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6309#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6308#L370-4 main_~j~0#1 := 0; 6269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6262#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6306#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6305#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6304#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6302#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6301#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6299#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6260#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6261#L378-2 [2022-11-20 10:32:07,499 INFO L750 eck$LassoCheckResult]: Loop: 6261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6300#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6261#L378-2 [2022-11-20 10:32:07,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:07,499 INFO L85 PathProgramCache]: Analyzing trace with hash 2086510138, now seen corresponding path program 8 times [2022-11-20 10:32:07,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:07,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930258666] [2022-11-20 10:32:07,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:07,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:07,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:07,990 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:07,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:07,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930258666] [2022-11-20 10:32:07,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930258666] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:07,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1577485638] [2022-11-20 10:32:07,991 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:32:07,991 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:07,991 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:07,992 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:07,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-20 10:32:08,142 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:32:08,143 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:08,144 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-20 10:32:08,155 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:08,386 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:08,524 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:32:08,524 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:32:08,825 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:32:08,828 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:08,828 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:09,056 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:32:09,059 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:32:09,131 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:09,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1577485638] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:09,131 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:09,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 18] total 38 [2022-11-20 10:32:09,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1817946139] [2022-11-20 10:32:09,132 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:09,132 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:09,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:09,133 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-20 10:32:09,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:09,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935516107] [2022-11-20 10:32:09,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:09,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:09,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:09,136 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:09,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:09,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:09,188 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:09,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-20 10:32:09,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=1339, Unknown=0, NotChecked=0, Total=1482 [2022-11-20 10:32:09,191 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. cyclomatic complexity: 19 Second operand has 39 states, 38 states have (on average 2.1578947368421053) internal successors, (82), 39 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:09,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:09,875 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2022-11-20 10:32:09,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 87 transitions. [2022-11-20 10:32:09,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:09,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 71 states and 86 transitions. [2022-11-20 10:32:09,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:09,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:09,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 86 transitions. [2022-11-20 10:32:09,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:09,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71 states and 86 transitions. [2022-11-20 10:32:09,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 86 transitions. [2022-11-20 10:32:09,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2022-11-20 10:32:09,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.24) internal successors, (62), 49 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:09,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 62 transitions. [2022-11-20 10:32:09,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-20 10:32:09,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-20 10:32:09,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 62 transitions. [2022-11-20 10:32:09,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-20 10:32:09,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 62 transitions. [2022-11-20 10:32:09,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:09,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:09,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:09,880 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:09,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:09,880 INFO L748 eck$LassoCheckResult]: Stem: 6677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6688#L367 assume !(main_~length~0#1 < 1); 6679#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6680#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6681#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6689#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6723#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6722#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6720#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6719#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6718#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6717#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6716#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6715#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6714#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6712#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6711#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6709#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6704#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6703#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 6701#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6698#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6686#L370-4 main_~j~0#1 := 0; 6687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6684#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6692#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6726#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6725#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6702#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6696#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6695#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6682#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6683#L378-2 [2022-11-20 10:32:09,880 INFO L750 eck$LassoCheckResult]: Loop: 6683#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6697#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6683#L378-2 [2022-11-20 10:32:09,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:09,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1036183171, now seen corresponding path program 9 times [2022-11-20 10:32:09,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:09,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810611168] [2022-11-20 10:32:09,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:09,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:09,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:10,341 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:10,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:10,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810611168] [2022-11-20 10:32:10,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810611168] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:10,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [491742902] [2022-11-20 10:32:10,342 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:32:10,342 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:10,342 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:10,350 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:10,367 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-20 10:32:10,552 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-20 10:32:10,552 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:10,554 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 10:32:10,556 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:10,763 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:11,547 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:32:11,547 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:32:11,551 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 36 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:11,551 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:12,409 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:32:12,413 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:32:12,596 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 30 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:12,596 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [491742902] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:12,596 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:12,596 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 20] total 48 [2022-11-20 10:32:12,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620971356] [2022-11-20 10:32:12,597 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:12,597 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:12,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:12,597 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-20 10:32:12,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:12,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147863017] [2022-11-20 10:32:12,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:12,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:12,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:12,601 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:12,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:12,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:12,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:12,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-20 10:32:12,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=287, Invalid=2065, Unknown=0, NotChecked=0, Total=2352 [2022-11-20 10:32:12,656 INFO L87 Difference]: Start difference. First operand 50 states and 62 transitions. cyclomatic complexity: 16 Second operand has 49 states, 48 states have (on average 2.0208333333333335) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:14,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:14,031 INFO L93 Difference]: Finished difference Result 75 states and 91 transitions. [2022-11-20 10:32:14,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 91 transitions. [2022-11-20 10:32:14,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:14,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 58 states and 72 transitions. [2022-11-20 10:32:14,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-20 10:32:14,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-20 10:32:14,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 72 transitions. [2022-11-20 10:32:14,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:14,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-20 10:32:14,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 72 transitions. [2022-11-20 10:32:14,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2022-11-20 10:32:14,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.25) internal successors, (70), 55 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:14,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 70 transitions. [2022-11-20 10:32:14,036 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56 states and 70 transitions. [2022-11-20 10:32:14,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-11-20 10:32:14,038 INFO L428 stractBuchiCegarLoop]: Abstraction has 56 states and 70 transitions. [2022-11-20 10:32:14,038 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-20 10:32:14,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 70 transitions. [2022-11-20 10:32:14,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:14,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:14,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:14,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:14,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:14,040 INFO L748 eck$LassoCheckResult]: Stem: 7168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7179#L367 assume !(main_~length~0#1 < 1); 7170#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7171#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7172#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7180#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7183#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7182#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7213#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7212#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7206#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7203#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7201#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7197#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7195#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7189#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7186#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7173#L370-4 main_~j~0#1 := 0; 7174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7184#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7185#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7177#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7223#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7222#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7221#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7219#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7217#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7216#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7175#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7176#L378-2 [2022-11-20 10:32:14,040 INFO L750 eck$LassoCheckResult]: Loop: 7176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7215#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7176#L378-2 [2022-11-20 10:32:14,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:14,040 INFO L85 PathProgramCache]: Analyzing trace with hash -1188134923, now seen corresponding path program 10 times [2022-11-20 10:32:14,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:14,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581995056] [2022-11-20 10:32:14,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:14,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:14,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:14,672 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:14,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:14,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581995056] [2022-11-20 10:32:14,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581995056] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:14,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [246577826] [2022-11-20 10:32:14,673 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:32:14,673 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:14,673 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:14,679 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:14,707 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-20 10:32:14,811 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:32:14,811 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:14,813 INFO L263 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-20 10:32:14,815 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:14,889 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:15,001 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:32:15,001 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:32:15,509 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-20 10:32:15,509 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-20 10:32:15,540 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:15,540 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:19,785 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-20 10:32:19,796 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 138 [2022-11-20 10:32:19,906 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:19,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [246577826] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:19,906 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:19,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 40 [2022-11-20 10:32:19,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107831976] [2022-11-20 10:32:19,907 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:19,907 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:19,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:19,908 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-20 10:32:19,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:19,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011700773] [2022-11-20 10:32:19,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:19,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:19,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:19,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:19,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:19,915 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:19,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:19,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 10:32:19,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=1500, Unknown=2, NotChecked=0, Total=1640 [2022-11-20 10:32:19,967 INFO L87 Difference]: Start difference. First operand 56 states and 70 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.15) internal successors, (86), 41 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:21,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:21,011 INFO L93 Difference]: Finished difference Result 81 states and 99 transitions. [2022-11-20 10:32:21,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 99 transitions. [2022-11-20 10:32:21,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:21,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 98 transitions. [2022-11-20 10:32:21,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:21,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:21,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 98 transitions. [2022-11-20 10:32:21,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:21,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-20 10:32:21,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 98 transitions. [2022-11-20 10:32:21,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 68. [2022-11-20 10:32:21,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.25) internal successors, (85), 67 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:21,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 85 transitions. [2022-11-20 10:32:21,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-20 10:32:21,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-20 10:32:21,016 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-20 10:32:21,017 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-20 10:32:21,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 85 transitions. [2022-11-20 10:32:21,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:21,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:21,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:21,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:21,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:21,019 INFO L748 eck$LassoCheckResult]: Stem: 7632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7643#L367 assume !(main_~length~0#1 < 1); 7634#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7635#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7636#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7644#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7647#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7645#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7646#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7690#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7688#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7687#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7686#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7685#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7684#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7682#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7681#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7676#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7674#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7670#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7665#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7662#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7651#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 7658#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7696#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7695#L370-4 main_~j~0#1 := 0; 7648#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7641#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7642#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7693#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7692#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7691#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7667#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7664#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7661#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7653#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7652#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7639#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7640#L378-2 [2022-11-20 10:32:21,019 INFO L750 eck$LassoCheckResult]: Loop: 7640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7654#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7640#L378-2 [2022-11-20 10:32:21,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:21,019 INFO L85 PathProgramCache]: Analyzing trace with hash -765433097, now seen corresponding path program 11 times [2022-11-20 10:32:21,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:21,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110136082] [2022-11-20 10:32:21,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:21,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:21,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:21,589 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:21,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:21,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110136082] [2022-11-20 10:32:21,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110136082] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:21,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [129462779] [2022-11-20 10:32:21,589 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:32:21,589 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:21,589 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:21,593 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:21,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-20 10:32:21,809 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2022-11-20 10:32:21,809 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:21,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 41 conjunts are in the unsatisfiable core [2022-11-20 10:32:21,813 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:22,051 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:22,178 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:32:22,179 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:32:22,683 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:32:22,686 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:32:22,686 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 10:32:22,691 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:22,691 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:22,991 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:32:22,997 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:32:23,073 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:23,074 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [129462779] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:23,074 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:23,074 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 44 [2022-11-20 10:32:23,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17710345] [2022-11-20 10:32:23,074 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:23,075 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:23,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:23,075 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-20 10:32:23,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:23,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222845766] [2022-11-20 10:32:23,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:23,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:23,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:23,078 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:23,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:23,086 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:23,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:23,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-11-20 10:32:23,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=1811, Unknown=0, NotChecked=0, Total=1980 [2022-11-20 10:32:23,160 INFO L87 Difference]: Start difference. First operand 68 states and 85 transitions. cyclomatic complexity: 21 Second operand has 45 states, 44 states have (on average 2.090909090909091) internal successors, (92), 45 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:24,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:24,113 INFO L93 Difference]: Finished difference Result 82 states and 99 transitions. [2022-11-20 10:32:24,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 99 transitions. [2022-11-20 10:32:24,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:24,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 81 states and 98 transitions. [2022-11-20 10:32:24,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:24,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:24,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 98 transitions. [2022-11-20 10:32:24,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:24,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81 states and 98 transitions. [2022-11-20 10:32:24,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 98 transitions. [2022-11-20 10:32:24,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 58. [2022-11-20 10:32:24,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2413793103448276) internal successors, (72), 57 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:24,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 72 transitions. [2022-11-20 10:32:24,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-20 10:32:24,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-20 10:32:24,119 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 72 transitions. [2022-11-20 10:32:24,119 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-20 10:32:24,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 72 transitions. [2022-11-20 10:32:24,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:24,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:24,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:24,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:24,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:24,121 INFO L748 eck$LassoCheckResult]: Stem: 8112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8123#L367 assume !(main_~length~0#1 < 1); 8114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8116#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8124#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8164#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8163#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8162#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8161#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8160#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8159#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8158#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8157#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8156#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8155#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8154#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8152#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8151#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8149#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8147#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8145#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8140#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8142#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8139#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8137#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8134#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8121#L370-4 main_~j~0#1 := 0; 8122#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8127#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8128#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8119#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8120#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8168#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8167#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8165#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8144#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8143#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8141#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8138#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8136#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8132#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8131#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8117#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8118#L378-2 [2022-11-20 10:32:24,121 INFO L750 eck$LassoCheckResult]: Loop: 8118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8133#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8118#L378-2 [2022-11-20 10:32:24,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:24,122 INFO L85 PathProgramCache]: Analyzing trace with hash 663643002, now seen corresponding path program 12 times [2022-11-20 10:32:24,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:24,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986329278] [2022-11-20 10:32:24,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:24,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:24,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:24,771 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:24,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:24,771 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986329278] [2022-11-20 10:32:24,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986329278] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:24,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1230852379] [2022-11-20 10:32:24,772 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:32:24,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:24,772 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:24,779 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:24,798 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-20 10:32:25,115 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-20 10:32:25,115 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:25,117 INFO L263 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-20 10:32:25,120 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:25,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:26,160 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:32:26,160 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:32:26,164 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 49 proven. 99 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:26,164 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:27,204 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:32:27,209 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:32:27,428 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 42 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:27,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1230852379] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:27,429 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:27,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 53 [2022-11-20 10:32:27,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213602758] [2022-11-20 10:32:27,429 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:27,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:27,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:27,430 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-20 10:32:27,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:27,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657132951] [2022-11-20 10:32:27,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:27,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:27,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:27,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:27,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:27,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:27,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:27,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-20 10:32:27,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2521, Unknown=0, NotChecked=0, Total=2862 [2022-11-20 10:32:27,491 INFO L87 Difference]: Start difference. First operand 58 states and 72 transitions. cyclomatic complexity: 18 Second operand has 54 states, 53 states have (on average 2.056603773584906) internal successors, (109), 54 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:29,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:29,087 INFO L93 Difference]: Finished difference Result 85 states and 103 transitions. [2022-11-20 10:32:29,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 103 transitions. [2022-11-20 10:32:29,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:29,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 66 states and 82 transitions. [2022-11-20 10:32:29,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-20 10:32:29,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-20 10:32:29,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 82 transitions. [2022-11-20 10:32:29,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:29,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-20 10:32:29,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 82 transitions. [2022-11-20 10:32:29,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 64. [2022-11-20 10:32:29,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.25) internal successors, (80), 63 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:29,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 80 transitions. [2022-11-20 10:32:29,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 80 transitions. [2022-11-20 10:32:29,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-20 10:32:29,092 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 80 transitions. [2022-11-20 10:32:29,092 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-20 10:32:29,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 80 transitions. [2022-11-20 10:32:29,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:29,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:29,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:29,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:29,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:29,093 INFO L748 eck$LassoCheckResult]: Stem: 8666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8667#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8677#L367 assume !(main_~length~0#1 < 1); 8668#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8669#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8670#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8678#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8679#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8680#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8717#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8716#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8715#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8714#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8713#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8712#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8711#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8710#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8709#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8708#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8706#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8704#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8702#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8700#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8698#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8696#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8692#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8683#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8688#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 8687#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8685#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8671#L370-4 main_~j~0#1 := 0; 8672#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8675#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8676#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8682#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8728#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8726#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8724#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8723#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8722#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8721#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8719#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8673#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8674#L378-2 [2022-11-20 10:32:29,094 INFO L750 eck$LassoCheckResult]: Loop: 8674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8720#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8674#L378-2 [2022-11-20 10:32:29,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:29,094 INFO L85 PathProgramCache]: Analyzing trace with hash -1169012734, now seen corresponding path program 13 times [2022-11-20 10:32:29,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:29,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941621545] [2022-11-20 10:32:29,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:29,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:29,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:29,729 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:29,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:29,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941621545] [2022-11-20 10:32:29,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941621545] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:29,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1906257614] [2022-11-20 10:32:29,730 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:32:29,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:29,730 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:29,734 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:29,755 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-20 10:32:29,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:29,875 INFO L263 TraceCheckSpWp]: Trace formula consists of 279 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-20 10:32:29,878 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:30,203 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:30,298 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:32:30,779 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:32:30,810 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:30,810 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:31,344 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-20 10:32:31,346 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 62 [2022-11-20 10:32:31,435 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:31,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1906257614] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:31,435 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:31,435 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 21] total 53 [2022-11-20 10:32:31,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191632650] [2022-11-20 10:32:31,436 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:31,436 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:31,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:31,436 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-20 10:32:31,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:31,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030856323] [2022-11-20 10:32:31,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:31,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:31,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:31,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:31,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:31,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:31,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:31,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-20 10:32:31,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=2675, Unknown=0, NotChecked=0, Total=2862 [2022-11-20 10:32:31,486 INFO L87 Difference]: Start difference. First operand 64 states and 80 transitions. cyclomatic complexity: 20 Second operand has 54 states, 53 states have (on average 2.2452830188679247) internal successors, (119), 54 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:33,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:33,370 INFO L93 Difference]: Finished difference Result 126 states and 152 transitions. [2022-11-20 10:32:33,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 152 transitions. [2022-11-20 10:32:33,371 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-20 10:32:33,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 124 states and 150 transitions. [2022-11-20 10:32:33,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2022-11-20 10:32:33,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-11-20 10:32:33,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124 states and 150 transitions. [2022-11-20 10:32:33,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:33,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124 states and 150 transitions. [2022-11-20 10:32:33,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states and 150 transitions. [2022-11-20 10:32:33,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 82. [2022-11-20 10:32:33,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2682926829268293) internal successors, (104), 81 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:33,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 104 transitions. [2022-11-20 10:32:33,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-20 10:32:33,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-20 10:32:33,380 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 104 transitions. [2022-11-20 10:32:33,380 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-20 10:32:33,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 104 transitions. [2022-11-20 10:32:33,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:33,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:33,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:33,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:33,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:33,382 INFO L748 eck$LassoCheckResult]: Stem: 9252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9263#L367 assume !(main_~length~0#1 < 1); 9254#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9255#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9256#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9264#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9269#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9310#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9309#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9308#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9307#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9306#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9305#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9304#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9303#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9301#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9298#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9296#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9294#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9290#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9283#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9280#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9328#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9329#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9327#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9326#L370-4 main_~j~0#1 := 0; 9267#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9324#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9323#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9322#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9321#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9320#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9319#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9318#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9317#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9316#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9315#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9314#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9313#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9257#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9258#L378-2 [2022-11-20 10:32:33,382 INFO L750 eck$LassoCheckResult]: Loop: 9258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9312#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9258#L378-2 [2022-11-20 10:32:33,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:33,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1320516228, now seen corresponding path program 14 times [2022-11-20 10:32:33,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:33,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676130316] [2022-11-20 10:32:33,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:33,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:33,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:34,078 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:34,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:34,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1676130316] [2022-11-20 10:32:34,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1676130316] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:34,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [225697194] [2022-11-20 10:32:34,078 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:32:34,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:34,079 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:34,082 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:34,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-20 10:32:34,228 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:32:34,228 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:34,230 INFO L263 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-20 10:32:34,232 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:34,550 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:34,686 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:32:34,687 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:32:35,162 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:32:35,165 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:35,165 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:35,395 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:32:35,400 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:32:35,471 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:35,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [225697194] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:35,472 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:35,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 46 [2022-11-20 10:32:35,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426337678] [2022-11-20 10:32:35,472 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:35,472 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:35,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:35,473 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-20 10:32:35,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:35,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530197452] [2022-11-20 10:32:35,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:35,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:35,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:35,476 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:35,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:35,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:35,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:35,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-20 10:32:35,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1991, Unknown=0, NotChecked=0, Total=2162 [2022-11-20 10:32:35,529 INFO L87 Difference]: Start difference. First operand 82 states and 104 transitions. cyclomatic complexity: 26 Second operand has 47 states, 46 states have (on average 2.217391304347826) internal successors, (102), 47 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:36,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:36,429 INFO L93 Difference]: Finished difference Result 98 states and 120 transitions. [2022-11-20 10:32:36,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 120 transitions. [2022-11-20 10:32:36,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:36,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 97 states and 119 transitions. [2022-11-20 10:32:36,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:36,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:36,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 119 transitions. [2022-11-20 10:32:36,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:36,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 119 transitions. [2022-11-20 10:32:36,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 119 transitions. [2022-11-20 10:32:36,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 66. [2022-11-20 10:32:36,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.2424242424242424) internal successors, (82), 65 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:36,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 82 transitions. [2022-11-20 10:32:36,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-20 10:32:36,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 10:32:36,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 66 states and 82 transitions. [2022-11-20 10:32:36,438 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-20 10:32:36,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 82 transitions. [2022-11-20 10:32:36,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:36,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:36,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:36,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:36,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:36,440 INFO L748 eck$LassoCheckResult]: Stem: 9796#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9807#L367 assume !(main_~length~0#1 < 1); 9798#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9799#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9800#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9808#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9811#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9860#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9859#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9855#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9854#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9853#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9852#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9851#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9849#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9845#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9843#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9840#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9836#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9834#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9809#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9810#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 9830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9814#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9801#L370-4 main_~j~0#1 := 0; 9802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9805#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9806#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9812#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9829#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9828#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9827#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9826#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9825#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9824#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9823#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9822#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9821#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9820#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9819#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9817#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9803#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9804#L378-2 [2022-11-20 10:32:36,440 INFO L750 eck$LassoCheckResult]: Loop: 9804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9816#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9804#L378-2 [2022-11-20 10:32:36,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:36,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1860197447, now seen corresponding path program 15 times [2022-11-20 10:32:36,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:36,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336293697] [2022-11-20 10:32:36,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:36,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:36,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:37,088 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:37,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:37,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336293697] [2022-11-20 10:32:37,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336293697] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:37,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1818093812] [2022-11-20 10:32:37,089 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:32:37,089 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:37,089 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:37,093 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:37,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-20 10:32:37,393 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-20 10:32:37,394 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:37,396 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-20 10:32:37,398 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:37,653 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:38,528 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:32:38,528 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:32:38,531 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:38,531 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:39,715 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:32:39,719 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:32:39,979 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:39,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1818093812] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:39,979 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:39,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2022-11-20 10:32:39,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031833160] [2022-11-20 10:32:39,979 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:39,980 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:39,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:39,980 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-20 10:32:39,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:39,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177964687] [2022-11-20 10:32:39,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:39,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:39,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:39,987 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:39,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:39,992 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:40,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:40,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-20 10:32:40,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3022, Unknown=0, NotChecked=0, Total=3422 [2022-11-20 10:32:40,043 INFO L87 Difference]: Start difference. First operand 66 states and 82 transitions. cyclomatic complexity: 20 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:42,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:42,639 INFO L93 Difference]: Finished difference Result 184 states and 219 transitions. [2022-11-20 10:32:42,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 219 transitions. [2022-11-20 10:32:42,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:42,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 160 states and 194 transitions. [2022-11-20 10:32:42,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:42,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:42,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 160 states and 194 transitions. [2022-11-20 10:32:42,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:42,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 160 states and 194 transitions. [2022-11-20 10:32:42,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states and 194 transitions. [2022-11-20 10:32:42,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 105. [2022-11-20 10:32:42,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.2666666666666666) internal successors, (133), 104 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:42,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 133 transitions. [2022-11-20 10:32:42,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 105 states and 133 transitions. [2022-11-20 10:32:42,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2022-11-20 10:32:42,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 105 states and 133 transitions. [2022-11-20 10:32:42,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-20 10:32:42,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 133 transitions. [2022-11-20 10:32:42,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:42,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:42,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:42,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:42,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:42,647 INFO L748 eck$LassoCheckResult]: Stem: 10516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10527#L367 assume !(main_~length~0#1 < 1); 10518#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10519#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10520#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10528#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10534#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10529#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10530#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10619#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10616#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10600#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10568#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10564#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10563#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10562#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10559#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10560#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10555#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10548#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10547#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 10549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10538#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10539#L370-4 main_~j~0#1 := 0; 10531#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10523#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10524#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10614#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10613#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10612#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10611#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10610#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10609#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10607#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10605#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10597#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10596#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10536#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10521#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10522#L378-2 [2022-11-20 10:32:42,647 INFO L750 eck$LassoCheckResult]: Loop: 10522#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10537#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10522#L378-2 [2022-11-20 10:32:42,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:42,648 INFO L85 PathProgramCache]: Analyzing trace with hash -68075255, now seen corresponding path program 16 times [2022-11-20 10:32:42,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:42,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875952488] [2022-11-20 10:32:42,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:42,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:42,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:43,340 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:43,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:43,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875952488] [2022-11-20 10:32:43,341 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875952488] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:43,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1417778474] [2022-11-20 10:32:43,341 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:32:43,341 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:43,341 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:43,345 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:43,356 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-20 10:32:43,502 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:32:43,502 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:43,504 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-20 10:32:43,506 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:43,603 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:44,106 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:32:44,109 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:44,109 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:44,282 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:32:44,292 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:32:44,374 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:44,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1417778474] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:44,374 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:44,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22] total 34 [2022-11-20 10:32:44,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841115275] [2022-11-20 10:32:44,375 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:44,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:44,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:44,375 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-20 10:32:44,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:44,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945887060] [2022-11-20 10:32:44,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:44,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:44,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:44,378 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:44,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:44,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:44,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:44,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-20 10:32:44,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=1088, Unknown=0, NotChecked=0, Total=1190 [2022-11-20 10:32:44,424 INFO L87 Difference]: Start difference. First operand 105 states and 133 transitions. cyclomatic complexity: 32 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:45,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:45,201 INFO L93 Difference]: Finished difference Result 160 states and 196 transitions. [2022-11-20 10:32:45,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 160 states and 196 transitions. [2022-11-20 10:32:45,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:32:45,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 160 states to 159 states and 195 transitions. [2022-11-20 10:32:45,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 10:32:45,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 10:32:45,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 159 states and 195 transitions. [2022-11-20 10:32:45,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:45,204 INFO L218 hiAutomatonCegarLoop]: Abstraction has 159 states and 195 transitions. [2022-11-20 10:32:45,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states and 195 transitions. [2022-11-20 10:32:45,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 118. [2022-11-20 10:32:45,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.2796610169491525) internal successors, (151), 117 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:45,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 151 transitions. [2022-11-20 10:32:45,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-20 10:32:45,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-20 10:32:45,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 118 states and 151 transitions. [2022-11-20 10:32:45,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-20 10:32:45,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 151 transitions. [2022-11-20 10:32:45,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:45,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:45,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:45,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:45,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:45,212 INFO L748 eck$LassoCheckResult]: Stem: 11127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11138#L367 assume !(main_~length~0#1 < 1); 11129#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11130#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11131#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11139#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11236#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11142#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11143#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11141#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11243#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11242#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11241#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11240#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11239#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11238#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11229#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11223#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11220#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11214#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11211#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11205#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11166#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11148#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11146#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11132#L370-4 main_~j~0#1 := 0; 11133#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11169#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11136#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11137#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11163#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11161#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11160#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11159#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11157#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11156#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11155#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11154#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11153#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11150#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11149#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11134#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11135#L378-2 [2022-11-20 10:32:45,212 INFO L750 eck$LassoCheckResult]: Loop: 11135#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11151#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11135#L378-2 [2022-11-20 10:32:45,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:45,212 INFO L85 PathProgramCache]: Analyzing trace with hash -995807346, now seen corresponding path program 17 times [2022-11-20 10:32:45,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:45,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147597350] [2022-11-20 10:32:45,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:45,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:45,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:45,623 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:45,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:45,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147597350] [2022-11-20 10:32:45,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147597350] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:45,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1300467991] [2022-11-20 10:32:45,624 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:32:45,624 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:45,624 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:45,633 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:45,655 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-20 10:32:46,039 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-20 10:32:46,040 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:46,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 309 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-20 10:32:46,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:46,388 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:46,388 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:46,634 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 81 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:46,634 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1300467991] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:46,634 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:46,634 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-20 10:32:46,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703494509] [2022-11-20 10:32:46,634 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:46,635 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:46,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:46,635 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-20 10:32:46,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:46,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54161780] [2022-11-20 10:32:46,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:46,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:46,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:46,638 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:46,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:46,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:46,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:46,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-20 10:32:46,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-20 10:32:46,695 INFO L87 Difference]: Start difference. First operand 118 states and 151 transitions. cyclomatic complexity: 38 Second operand has 35 states, 35 states have (on average 2.2857142857142856) internal successors, (80), 35 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:47,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:47,023 INFO L93 Difference]: Finished difference Result 144 states and 178 transitions. [2022-11-20 10:32:47,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144 states and 178 transitions. [2022-11-20 10:32:47,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:47,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144 states to 124 states and 158 transitions. [2022-11-20 10:32:47,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:32:47,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:32:47,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124 states and 158 transitions. [2022-11-20 10:32:47,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:47,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124 states and 158 transitions. [2022-11-20 10:32:47,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states and 158 transitions. [2022-11-20 10:32:47,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 82. [2022-11-20 10:32:47,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:47,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-20 10:32:47,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 10:32:47,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 10:32:47,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 10:32:47,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-20 10:32:47,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-20 10:32:47,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:47,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:47,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:47,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:47,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:47,031 INFO L748 eck$LassoCheckResult]: Stem: 11767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11778#L367 assume !(main_~length~0#1 < 1); 11769#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11770#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11779#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11780#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11781#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11848#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11847#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11846#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11844#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11843#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11842#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11838#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11832#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11826#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11820#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11815#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 11816#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11811#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11806#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11802#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11784#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11772#L370-4 main_~j~0#1 := 0; 11773#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11783#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11800#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11798#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11797#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11796#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11795#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11794#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11792#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11791#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11790#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11787#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11786#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11774#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11775#L378-2 [2022-11-20 10:32:47,031 INFO L750 eck$LassoCheckResult]: Loop: 11775#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11788#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11775#L378-2 [2022-11-20 10:32:47,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:47,032 INFO L85 PathProgramCache]: Analyzing trace with hash 307442051, now seen corresponding path program 18 times [2022-11-20 10:32:47,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:47,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671988990] [2022-11-20 10:32:47,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:47,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:47,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:47,811 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:47,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:47,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671988990] [2022-11-20 10:32:47,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671988990] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:47,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87191527] [2022-11-20 10:32:47,812 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:32:47,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:47,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:47,813 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:47,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-20 10:32:48,691 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-20 10:32:48,691 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:32:48,694 INFO L263 TraceCheckSpWp]: Trace formula consists of 312 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-20 10:32:48,697 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:32:48,958 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:32:49,127 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:32:49,127 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-20 10:32:49,230 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:32:49,230 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-20 10:32:51,952 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-20 10:32:51,952 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-20 10:32:51,989 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 64 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:51,990 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:32:53,501 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:32:53,505 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:32:53,752 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 56 proven. 159 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-20 10:32:53,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87191527] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:32:53,753 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:32:53,753 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 27, 24] total 62 [2022-11-20 10:32:53,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937803907] [2022-11-20 10:32:53,753 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:32:53,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:32:53,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:53,754 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-20 10:32:53,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:53,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662597276] [2022-11-20 10:32:53,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:53,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:53,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:53,758 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:32:53,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:32:53,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:32:53,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:32:53,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2022-11-20 10:32:53,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=440, Invalid=3465, Unknown=1, NotChecked=0, Total=3906 [2022-11-20 10:32:53,807 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 63 states, 62 states have (on average 2.0806451612903225) internal successors, (129), 63 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:59,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:32:59,102 INFO L93 Difference]: Finished difference Result 176 states and 204 transitions. [2022-11-20 10:32:59,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 204 transitions. [2022-11-20 10:32:59,104 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 10:32:59,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 133 states and 159 transitions. [2022-11-20 10:32:59,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 10:32:59,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 10:32:59,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133 states and 159 transitions. [2022-11-20 10:32:59,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:32:59,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133 states and 159 transitions. [2022-11-20 10:32:59,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states and 159 transitions. [2022-11-20 10:32:59,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 68. [2022-11-20 10:32:59,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.25) internal successors, (85), 67 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:32:59,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 85 transitions. [2022-11-20 10:32:59,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-20 10:32:59,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2022-11-20 10:32:59,109 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 85 transitions. [2022-11-20 10:32:59,109 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-20 10:32:59,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 85 transitions. [2022-11-20 10:32:59,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:32:59,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:32:59,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:32:59,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:32:59,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:32:59,111 INFO L748 eck$LassoCheckResult]: Stem: 12563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12574#L367 assume !(main_~length~0#1 < 1); 12565#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12566#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12575#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12580#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12576#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12577#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12628#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12627#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12625#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12622#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12619#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12614#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12613#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12612#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12611#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12610#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12609#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 12585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12583#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12572#L370-4 main_~j~0#1 := 0; 12573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12570#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12601#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12600#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12598#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12597#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12596#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12594#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12593#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12592#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12591#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12590#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12589#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12568#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12569#L378-2 [2022-11-20 10:32:59,111 INFO L750 eck$LassoCheckResult]: Loop: 12569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12586#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12569#L378-2 [2022-11-20 10:32:59,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:32:59,112 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 12 times [2022-11-20 10:32:59,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:32:59,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624645033] [2022-11-20 10:32:59,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:32:59,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:32:59,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:32:59,931 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:32:59,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:32:59,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624645033] [2022-11-20 10:32:59,931 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624645033] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:32:59,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1210242132] [2022-11-20 10:32:59,931 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:32:59,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:32:59,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:32:59,939 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:32:59,955 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-20 10:33:00,626 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2022-11-20 10:33:00,626 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:00,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-20 10:33:00,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:00,933 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:33:01,954 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 10:33:01,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 10:33:01,957 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:01,957 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:03,241 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:33:03,245 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:33:03,540 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:03,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1210242132] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:03,540 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:03,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-20 10:33:03,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82947986] [2022-11-20 10:33:03,541 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:03,541 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:03,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:03,541 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-20 10:33:03,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:03,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660219252] [2022-11-20 10:33:03,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:03,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:03,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:03,544 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:03,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:03,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:03,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:03,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-20 10:33:03,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=3568, Unknown=0, NotChecked=0, Total=4032 [2022-11-20 10:33:03,598 INFO L87 Difference]: Start difference. First operand 68 states and 85 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:05,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:05,668 INFO L93 Difference]: Finished difference Result 105 states and 128 transitions. [2022-11-20 10:33:05,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 128 transitions. [2022-11-20 10:33:05,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:05,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 82 states and 103 transitions. [2022-11-20 10:33:05,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:33:05,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:33:05,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 103 transitions. [2022-11-20 10:33:05,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:05,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 10:33:05,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 103 transitions. [2022-11-20 10:33:05,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2022-11-20 10:33:05,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:05,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-20 10:33:05,672 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 10:33:05,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-20 10:33:05,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 10:33:05,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-20 10:33:05,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-20 10:33:05,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:05,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:05,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:05,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:05,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:33:05,681 INFO L748 eck$LassoCheckResult]: Stem: 13233#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13234#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13244#L367 assume !(main_~length~0#1 < 1); 13235#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13236#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13237#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13245#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13250#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13246#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13247#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13314#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13313#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13312#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13309#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13307#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13305#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13304#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13303#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13300#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13301#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13299#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13295#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13290#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13285#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13282#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13279#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13274#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13272#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13266#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13242#L370-4 main_~j~0#1 := 0; 13243#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13268#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13249#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13240#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13265#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13264#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13263#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13262#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13261#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13260#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13259#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13257#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13255#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13252#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13251#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13238#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13239#L378-2 [2022-11-20 10:33:05,682 INFO L750 eck$LassoCheckResult]: Loop: 13239#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13253#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13239#L378-2 [2022-11-20 10:33:05,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:05,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1364903176, now seen corresponding path program 19 times [2022-11-20 10:33:05,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:05,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198977442] [2022-11-20 10:33:05,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:05,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:05,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:06,394 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:06,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:06,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198977442] [2022-11-20 10:33:06,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198977442] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:06,395 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [501281257] [2022-11-20 10:33:06,395 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:33:06,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:06,395 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:06,398 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:06,399 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-20 10:33:06,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:06,560 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-20 10:33:06,563 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:06,652 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:33:07,136 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:33:07,138 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:07,138 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:07,303 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:33:07,308 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:33:07,398 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:07,398 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [501281257] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:07,398 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:07,398 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24] total 37 [2022-11-20 10:33:07,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683424037] [2022-11-20 10:33:07,399 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:07,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:07,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:07,399 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-20 10:33:07,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:07,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853685237] [2022-11-20 10:33:07,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:07,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:07,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:07,409 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:07,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:07,412 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:07,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:07,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 10:33:07,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1295, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 10:33:07,458 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:08,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:08,384 INFO L93 Difference]: Finished difference Result 151 states and 187 transitions. [2022-11-20 10:33:08,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 187 transitions. [2022-11-20 10:33:08,385 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 22 [2022-11-20 10:33:08,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 150 states and 186 transitions. [2022-11-20 10:33:08,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2022-11-20 10:33:08,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2022-11-20 10:33:08,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150 states and 186 transitions. [2022-11-20 10:33:08,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:08,387 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150 states and 186 transitions. [2022-11-20 10:33:08,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states and 186 transitions. [2022-11-20 10:33:08,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 129. [2022-11-20 10:33:08,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.2635658914728682) internal successors, (163), 128 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:08,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 163 transitions. [2022-11-20 10:33:08,390 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 163 transitions. [2022-11-20 10:33:08,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-20 10:33:08,394 INFO L428 stractBuchiCegarLoop]: Abstraction has 129 states and 163 transitions. [2022-11-20 10:33:08,395 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-20 10:33:08,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 163 transitions. [2022-11-20 10:33:08,396 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 20 [2022-11-20 10:33:08,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:08,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:08,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 9, 9, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:08,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 10:33:08,397 INFO L748 eck$LassoCheckResult]: Stem: 13845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13856#L367 assume !(main_~length~0#1 < 1); 13847#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13848#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13849#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13857#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13902#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13900#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13899#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13896#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13895#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13893#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13892#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13891#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13889#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13890#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13907#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13862#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13863#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13858#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13859#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13883#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13905#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13939#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13938#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13875#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13936#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 13935#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13933#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13932#L370-4 main_~j~0#1 := 0; 13931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13930#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13929#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13928#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13927#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13926#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13925#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13924#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13922#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13920#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13918#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13917#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13916#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13911#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13957#L378-2 [2022-11-20 10:33:08,397 INFO L750 eck$LassoCheckResult]: Loop: 13957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13959#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13956#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13957#L378-2 [2022-11-20 10:33:08,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:08,398 INFO L85 PathProgramCache]: Analyzing trace with hash 568849027, now seen corresponding path program 20 times [2022-11-20 10:33:08,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:08,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536436444] [2022-11-20 10:33:08,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:08,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:08,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:09,350 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 0 proven. 248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:09,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:09,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536436444] [2022-11-20 10:33:09,351 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536436444] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:09,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1991637286] [2022-11-20 10:33:09,351 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:33:09,351 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:09,351 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:09,359 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:09,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-20 10:33:09,541 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:33:09,541 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:09,544 INFO L263 TraceCheckSpWp]: Trace formula consists of 302 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-20 10:33:09,547 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:10,031 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:33:10,211 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:33:10,211 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:33:10,222 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:33:10,222 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:33:10,300 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:33:10,350 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:33:10,905 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:33:10,907 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:10,907 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:11,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:33:11,260 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:33:11,346 INFO L134 CoverageAnalysis]: Checked inductivity of 248 backedges. 1 proven. 246 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 10:33:11,346 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1991637286] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:11,346 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:11,346 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 25] total 52 [2022-11-20 10:33:11,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84780757] [2022-11-20 10:33:11,346 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:11,347 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:11,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:11,347 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 1 times [2022-11-20 10:33:11,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:11,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967521979] [2022-11-20 10:33:11,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:11,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:11,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:11,352 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:11,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:11,355 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:11,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:11,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-20 10:33:11,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=2554, Unknown=0, NotChecked=0, Total=2756 [2022-11-20 10:33:11,439 INFO L87 Difference]: Start difference. First operand 129 states and 163 transitions. cyclomatic complexity: 41 Second operand has 53 states, 52 states have (on average 2.3076923076923075) internal successors, (120), 53 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:12,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:12,683 INFO L93 Difference]: Finished difference Result 128 states and 152 transitions. [2022-11-20 10:33:12,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 152 transitions. [2022-11-20 10:33:12,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:12,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 126 states and 150 transitions. [2022-11-20 10:33:12,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-20 10:33:12,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-20 10:33:12,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 150 transitions. [2022-11-20 10:33:12,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:12,685 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126 states and 150 transitions. [2022-11-20 10:33:12,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 150 transitions. [2022-11-20 10:33:12,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 87. [2022-11-20 10:33:12,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.2528735632183907) internal successors, (109), 86 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:12,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 109 transitions. [2022-11-20 10:33:12,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 109 transitions. [2022-11-20 10:33:12,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-20 10:33:12,697 INFO L428 stractBuchiCegarLoop]: Abstraction has 87 states and 109 transitions. [2022-11-20 10:33:12,697 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-20 10:33:12,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 109 transitions. [2022-11-20 10:33:12,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:12,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:12,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:12,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:12,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:33:12,699 INFO L748 eck$LassoCheckResult]: Stem: 14522#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14533#L367 assume !(main_~length~0#1 < 1); 14524#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14525#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14526#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14534#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14600#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14597#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14594#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14593#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14592#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14591#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14587#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14537#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14606#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14605#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14604#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 14550#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14548#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14527#L370-4 main_~j~0#1 := 0; 14528#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14564#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14540#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14531#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14560#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14559#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14558#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14557#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14556#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14555#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14554#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14553#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14552#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14551#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14549#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14547#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14546#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14543#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14529#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14530#L378-2 [2022-11-20 10:33:12,699 INFO L750 eck$LassoCheckResult]: Loop: 14530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14544#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 14530#L378-2 [2022-11-20 10:33:12,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:12,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1706930125, now seen corresponding path program 21 times [2022-11-20 10:33:12,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:12,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888237587] [2022-11-20 10:33:12,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:12,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:12,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:13,198 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:13,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:13,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888237587] [2022-11-20 10:33:13,199 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888237587] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:13,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1755438866] [2022-11-20 10:33:13,199 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:33:13,199 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:13,199 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:13,205 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:13,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-20 10:33:13,895 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-20 10:33:13,895 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:13,897 INFO L263 TraceCheckSpWp]: Trace formula consists of 302 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-20 10:33:13,898 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:14,293 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:14,293 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:14,592 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:14,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1755438866] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:14,592 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:14,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-20 10:33:14,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488737773] [2022-11-20 10:33:14,595 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:14,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:14,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:14,596 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-20 10:33:14,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:14,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801152319] [2022-11-20 10:33:14,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:14,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:14,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:14,601 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:14,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:14,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:14,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:14,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 10:33:14,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 10:33:14,652 INFO L87 Difference]: Start difference. First operand 87 states and 109 transitions. cyclomatic complexity: 27 Second operand has 38 states, 38 states have (on average 2.3157894736842106) internal successors, (88), 38 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:14,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:14,980 INFO L93 Difference]: Finished difference Result 115 states and 138 transitions. [2022-11-20 10:33:14,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 138 transitions. [2022-11-20 10:33:14,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:14,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 93 states and 116 transitions. [2022-11-20 10:33:14,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 10:33:14,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 10:33:14,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 116 transitions. [2022-11-20 10:33:14,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:14,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 116 transitions. [2022-11-20 10:33:14,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 116 transitions. [2022-11-20 10:33:14,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 75. [2022-11-20 10:33:14,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.24) internal successors, (93), 74 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:14,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 93 transitions. [2022-11-20 10:33:14,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 93 transitions. [2022-11-20 10:33:14,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-20 10:33:14,999 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 93 transitions. [2022-11-20 10:33:14,999 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-20 10:33:14,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 93 transitions. [2022-11-20 10:33:15,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:15,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:15,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:15,001 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:15,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:33:15,002 INFO L748 eck$LassoCheckResult]: Stem: 15137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15148#L367 assume !(main_~length~0#1 < 1); 15139#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15140#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15141#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15149#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15154#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15150#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15151#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15209#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15207#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15206#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15205#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15204#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15203#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15202#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15201#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15200#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15199#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15198#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15197#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15194#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15191#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15190#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15189#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15186#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15187#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15188#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15173#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15176#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15175#L370-4 main_~j~0#1 := 0; 15152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15144#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15145#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15171#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15170#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15169#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15168#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15167#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15166#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15165#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15164#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15163#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15162#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15161#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15160#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15159#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15158#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15156#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15155#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15142#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15143#L378-2 [2022-11-20 10:33:15,002 INFO L750 eck$LassoCheckResult]: Loop: 15143#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15157#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15143#L378-2 [2022-11-20 10:33:15,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:15,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1414945998, now seen corresponding path program 22 times [2022-11-20 10:33:15,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:15,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151387382] [2022-11-20 10:33:15,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:15,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:15,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:15,894 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:15,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:15,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151387382] [2022-11-20 10:33:15,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151387382] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:15,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1349719651] [2022-11-20 10:33:15,894 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:33:15,894 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:15,894 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:15,897 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:15,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-20 10:33:16,061 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:33:16,062 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:16,064 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-20 10:33:16,066 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:16,146 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:33:16,260 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:33:16,261 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:33:16,282 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:33:16,283 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:33:16,700 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:33:16,703 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:16,703 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:17,001 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:33:17,004 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:33:17,110 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:17,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1349719651] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:17,110 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:17,110 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-11-20 10:33:17,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040081767] [2022-11-20 10:33:17,111 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:17,111 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:17,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:17,111 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-20 10:33:17,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:17,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304547234] [2022-11-20 10:33:17,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:17,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:17,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:17,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:17,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:17,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:17,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:17,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 10:33:17,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=1525, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 10:33:17,171 INFO L87 Difference]: Start difference. First operand 75 states and 93 transitions. cyclomatic complexity: 23 Second operand has 41 states, 40 states have (on average 2.225) internal successors, (89), 41 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:18,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:18,491 INFO L93 Difference]: Finished difference Result 158 states and 185 transitions. [2022-11-20 10:33:18,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158 states and 185 transitions. [2022-11-20 10:33:18,495 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-20 10:33:18,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158 states to 157 states and 184 transitions. [2022-11-20 10:33:18,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-11-20 10:33:18,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-11-20 10:33:18,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157 states and 184 transitions. [2022-11-20 10:33:18,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:18,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 157 states and 184 transitions. [2022-11-20 10:33:18,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states and 184 transitions. [2022-11-20 10:33:18,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 81. [2022-11-20 10:33:18,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.271604938271605) internal successors, (103), 80 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:18,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 103 transitions. [2022-11-20 10:33:18,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81 states and 103 transitions. [2022-11-20 10:33:18,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2022-11-20 10:33:18,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 81 states and 103 transitions. [2022-11-20 10:33:18,503 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-20 10:33:18,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 103 transitions. [2022-11-20 10:33:18,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 10:33:18,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:18,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:18,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:18,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:33:18,507 INFO L748 eck$LassoCheckResult]: Stem: 15792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15803#L367 assume !(main_~length~0#1 < 1); 15794#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15795#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15796#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15804#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15807#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15846#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15845#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15844#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15842#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15841#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15840#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15839#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15838#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15837#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15836#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15835#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15834#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15833#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15832#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15831#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15830#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15829#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15827#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15825#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15824#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15823#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15822#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15820#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15870#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15816#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 15813#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15811#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15797#L370-4 main_~j~0#1 := 0; 15798#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15864#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15801#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15802#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15863#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15862#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15861#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15860#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15859#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15858#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15857#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15856#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15855#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15854#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15853#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15851#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15850#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15848#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15847#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15799#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15800#L378-2 [2022-11-20 10:33:18,508 INFO L750 eck$LassoCheckResult]: Loop: 15800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15849#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15800#L378-2 [2022-11-20 10:33:18,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:18,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1229278031, now seen corresponding path program 23 times [2022-11-20 10:33:18,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:18,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186781284] [2022-11-20 10:33:18,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:18,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:18,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:19,399 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:19,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:19,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186781284] [2022-11-20 10:33:19,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186781284] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:19,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [365683612] [2022-11-20 10:33:19,400 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:33:19,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:19,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:19,405 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:19,427 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-20 10:33:19,816 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-20 10:33:19,816 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:19,820 INFO L263 TraceCheckSpWp]: Trace formula consists of 316 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-20 10:33:19,823 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:20,335 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 10:33:21,193 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:33:21,195 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:33:21,196 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 10:33:21,204 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:21,204 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:33:21,513 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:33:21,515 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:33:21,667 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:21,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [365683612] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:33:21,668 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:33:21,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 27] total 56 [2022-11-20 10:33:21,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81554518] [2022-11-20 10:33:21,668 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:33:21,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:33:21,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:21,669 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-20 10:33:21,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:21,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889653199] [2022-11-20 10:33:21,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:21,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:21,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:21,673 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:33:21,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:33:21,677 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:33:21,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:33:21,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2022-11-20 10:33:21,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=2980, Unknown=0, NotChecked=0, Total=3192 [2022-11-20 10:33:21,738 INFO L87 Difference]: Start difference. First operand 81 states and 103 transitions. cyclomatic complexity: 27 Second operand has 57 states, 56 states have (on average 2.25) internal successors, (126), 57 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:23,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:33:23,528 INFO L93 Difference]: Finished difference Result 162 states and 201 transitions. [2022-11-20 10:33:23,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162 states and 201 transitions. [2022-11-20 10:33:23,529 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 25 [2022-11-20 10:33:23,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162 states to 161 states and 200 transitions. [2022-11-20 10:33:23,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2022-11-20 10:33:23,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2022-11-20 10:33:23,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161 states and 200 transitions. [2022-11-20 10:33:23,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:33:23,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 161 states and 200 transitions. [2022-11-20 10:33:23,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states and 200 transitions. [2022-11-20 10:33:23,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 136. [2022-11-20 10:33:23,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.2720588235294117) internal successors, (173), 135 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:33:23,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 173 transitions. [2022-11-20 10:33:23,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 173 transitions. [2022-11-20 10:33:23,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-20 10:33:23,535 INFO L428 stractBuchiCegarLoop]: Abstraction has 136 states and 173 transitions. [2022-11-20 10:33:23,535 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-20 10:33:23,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 173 transitions. [2022-11-20 10:33:23,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:33:23,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:33:23,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:33:23,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:33:23,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 10:33:23,537 INFO L748 eck$LassoCheckResult]: Stem: 16469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16480#L367 assume !(main_~length~0#1 < 1); 16471#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16472#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16473#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16481#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16485#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16486#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16523#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16521#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16520#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16517#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16514#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16511#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16508#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16507#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16505#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16504#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16502#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16497#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16559#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16556#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16554#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 16553#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16551#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 16550#L370-4 main_~j~0#1 := 0; 16549#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16548#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16547#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16546#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16545#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16544#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16543#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16542#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16536#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16535#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16534#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16533#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16532#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16525#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16526#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16586#L378-2 [2022-11-20 10:33:23,537 INFO L750 eck$LassoCheckResult]: Loop: 16586#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16588#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16585#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16586#L378-2 [2022-11-20 10:33:23,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:33:23,538 INFO L85 PathProgramCache]: Analyzing trace with hash -719241402, now seen corresponding path program 24 times [2022-11-20 10:33:23,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:33:23,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745058883] [2022-11-20 10:33:23,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:33:23,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:33:23,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:33:24,435 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:24,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:33:24,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745058883] [2022-11-20 10:33:24,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745058883] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:33:24,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1733114165] [2022-11-20 10:33:24,435 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:33:24,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:33:24,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:33:24,439 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:33:24,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-20 10:33:25,503 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2022-11-20 10:33:25,503 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:33:25,506 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-20 10:33:25,509 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:33:25,962 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:33:26,073 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:33:26,087 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:33:26,223 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:33:26,224 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:33:26,227 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:33:26,227 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 36 [2022-11-20 10:33:26,981 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:33:26,981 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-20 10:33:27,023 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:33:27,023 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:00,327 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 31 [2022-11-20 10:35:00,340 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 249 treesize of output 241 [2022-11-20 10:35:01,052 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 1 proven. 299 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:01,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1733114165] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:01,053 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:01,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 28, 27] total 78 [2022-11-20 10:35:01,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498135044] [2022-11-20 10:35:01,053 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:01,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:01,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:01,054 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-20 10:35:01,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:01,055 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826569994] [2022-11-20 10:35:01,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:01,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:01,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:01,058 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:01,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:01,062 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:01,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:01,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2022-11-20 10:35:01,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=372, Invalid=5778, Unknown=12, NotChecked=0, Total=6162 [2022-11-20 10:35:01,178 INFO L87 Difference]: Start difference. First operand 136 states and 173 transitions. cyclomatic complexity: 44 Second operand has 79 states, 78 states have (on average 2.3205128205128207) internal successors, (181), 79 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:04,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:04,466 INFO L93 Difference]: Finished difference Result 273 states and 324 transitions. [2022-11-20 10:35:04,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 273 states and 324 transitions. [2022-11-20 10:35:04,467 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26 [2022-11-20 10:35:04,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 273 states to 270 states and 321 transitions. [2022-11-20 10:35:04,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2022-11-20 10:35:04,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2022-11-20 10:35:04,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 321 transitions. [2022-11-20 10:35:04,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:04,470 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 321 transitions. [2022-11-20 10:35:04,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 321 transitions. [2022-11-20 10:35:04,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 142. [2022-11-20 10:35:04,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 142 states have (on average 1.2887323943661972) internal successors, (183), 141 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:04,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 183 transitions. [2022-11-20 10:35:04,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142 states and 183 transitions. [2022-11-20 10:35:04,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-20 10:35:04,475 INFO L428 stractBuchiCegarLoop]: Abstraction has 142 states and 183 transitions. [2022-11-20 10:35:04,475 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-20 10:35:04,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142 states and 183 transitions. [2022-11-20 10:35:04,476 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:04,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:04,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:04,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 10, 10, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:04,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:35:04,477 INFO L748 eck$LassoCheckResult]: Stem: 17369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 17370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 17380#L367 assume !(main_~length~0#1 < 1); 17371#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 17372#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 17373#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17381#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17384#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17386#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17425#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17422#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17420#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17419#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17418#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17417#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17416#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17415#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17414#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17413#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17412#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17411#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17410#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17409#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17407#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17405#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17404#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17399#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 17401#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17382#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17383#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17459#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17457#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17454#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17456#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17477#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17476#L370-4 main_~j~0#1 := 0; 17475#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17474#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17473#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17472#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17470#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17468#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17467#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17466#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17465#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17464#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17463#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17462#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17461#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17429#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17432#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17430#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17431#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17433#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17377#L378-2 [2022-11-20 10:35:04,477 INFO L750 eck$LassoCheckResult]: Loop: 17377#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17426#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 17377#L378-2 [2022-11-20 10:35:04,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:04,478 INFO L85 PathProgramCache]: Analyzing trace with hash -562595642, now seen corresponding path program 25 times [2022-11-20 10:35:04,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:04,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555478720] [2022-11-20 10:35:04,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:04,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:04,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:05,544 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:05,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:05,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555478720] [2022-11-20 10:35:05,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555478720] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:05,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [426302094] [2022-11-20 10:35:05,544 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:35:05,545 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:05,545 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:05,549 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:05,550 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-20 10:35:05,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:05,760 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-20 10:35:05,763 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:06,264 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:35:06,462 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:35:06,478 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:35:06,570 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:35:06,571 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:35:06,587 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:35:07,431 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:35:07,433 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:07,433 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:08,082 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-20 10:35:08,088 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 61 [2022-11-20 10:35:08,219 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:08,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [426302094] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:08,220 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:08,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 28] total 58 [2022-11-20 10:35:08,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363987611] [2022-11-20 10:35:08,220 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:08,220 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:08,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:08,223 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-20 10:35:08,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:08,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261017819] [2022-11-20 10:35:08,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:08,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:08,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:08,227 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:08,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:08,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:08,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:08,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-20 10:35:08,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=3190, Unknown=0, NotChecked=0, Total=3422 [2022-11-20 10:35:08,295 INFO L87 Difference]: Start difference. First operand 142 states and 183 transitions. cyclomatic complexity: 50 Second operand has 59 states, 58 states have (on average 2.2586206896551726) internal successors, (131), 59 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:10,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:10,975 INFO L93 Difference]: Finished difference Result 493 states and 572 transitions. [2022-11-20 10:35:10,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 493 states and 572 transitions. [2022-11-20 10:35:10,977 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 30 [2022-11-20 10:35:10,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 493 states to 487 states and 566 transitions. [2022-11-20 10:35:10,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78 [2022-11-20 10:35:10,979 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78 [2022-11-20 10:35:10,979 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 566 transitions. [2022-11-20 10:35:10,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:10,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 566 transitions. [2022-11-20 10:35:10,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 566 transitions. [2022-11-20 10:35:10,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 163. [2022-11-20 10:35:10,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.3374233128834356) internal successors, (218), 162 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:10,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 218 transitions. [2022-11-20 10:35:10,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163 states and 218 transitions. [2022-11-20 10:35:10,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-11-20 10:35:10,986 INFO L428 stractBuchiCegarLoop]: Abstraction has 163 states and 218 transitions. [2022-11-20 10:35:10,986 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-20 10:35:10,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 218 transitions. [2022-11-20 10:35:10,986 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:10,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:10,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:10,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:10,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:35:10,988 INFO L748 eck$LassoCheckResult]: Stem: 18515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18526#L367 assume !(main_~length~0#1 < 1); 18517#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18518#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18527#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18613#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18608#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18604#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18603#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18602#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18601#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18600#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18598#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18597#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18596#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18595#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18594#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18593#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18592#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18591#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18590#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18589#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18588#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18586#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18587#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18653#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18654#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 18533#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18534#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18568#L370-4 main_~j~0#1 := 0; 18650#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18649#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18522#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18523#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18628#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18627#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18626#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18625#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18624#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18621#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18620#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18619#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18618#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18617#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18616#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18615#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18539#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18540#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18541#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18543#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18521#L378-2 [2022-11-20 10:35:10,988 INFO L750 eck$LassoCheckResult]: Loop: 18521#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18536#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18521#L378-2 [2022-11-20 10:35:10,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:10,988 INFO L85 PathProgramCache]: Analyzing trace with hash 220184660, now seen corresponding path program 26 times [2022-11-20 10:35:10,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:10,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076063938] [2022-11-20 10:35:10,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:10,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:11,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:11,535 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:11,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:11,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076063938] [2022-11-20 10:35:11,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076063938] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:11,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1979179687] [2022-11-20 10:35:11,536 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 10:35:11,536 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:11,536 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:11,542 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:11,559 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-20 10:35:11,748 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 10:35:11,748 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:35:11,750 INFO L263 TraceCheckSpWp]: Trace formula consists of 327 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-20 10:35:11,752 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:12,270 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:12,270 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:12,704 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:12,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1979179687] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:12,704 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:12,704 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 41 [2022-11-20 10:35:12,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512282398] [2022-11-20 10:35:12,705 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:12,705 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:12,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:12,705 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-20 10:35:12,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:12,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628612056] [2022-11-20 10:35:12,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:12,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:12,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:12,730 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:12,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:12,732 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:12,781 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:12,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 10:35:12,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=1258, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 10:35:12,782 INFO L87 Difference]: Start difference. First operand 163 states and 218 transitions. cyclomatic complexity: 64 Second operand has 41 states, 41 states have (on average 2.317073170731707) internal successors, (95), 41 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:13,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:13,258 INFO L93 Difference]: Finished difference Result 193 states and 249 transitions. [2022-11-20 10:35:13,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 249 transitions. [2022-11-20 10:35:13,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:13,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 169 states and 223 transitions. [2022-11-20 10:35:13,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-20 10:35:13,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-20 10:35:13,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 169 states and 223 transitions. [2022-11-20 10:35:13,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:13,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 169 states and 223 transitions. [2022-11-20 10:35:13,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states and 223 transitions. [2022-11-20 10:35:13,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 165. [2022-11-20 10:35:13,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 165 states, 165 states have (on average 1.3212121212121213) internal successors, (218), 164 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:13,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 218 transitions. [2022-11-20 10:35:13,264 INFO L240 hiAutomatonCegarLoop]: Abstraction has 165 states and 218 transitions. [2022-11-20 10:35:13,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-20 10:35:13,265 INFO L428 stractBuchiCegarLoop]: Abstraction has 165 states and 218 transitions. [2022-11-20 10:35:13,265 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-20 10:35:13,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 165 states and 218 transitions. [2022-11-20 10:35:13,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:13,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:13,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:13,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:13,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:35:13,267 INFO L748 eck$LassoCheckResult]: Stem: 19319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19330#L367 assume !(main_~length~0#1 < 1); 19321#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19322#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19331#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19460#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19459#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19458#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19457#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19455#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19454#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19453#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19452#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19451#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19450#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19449#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19448#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19447#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19446#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19445#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19444#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19443#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19442#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19441#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19440#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19437#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19436#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19435#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19434#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19432#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19431#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19338#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19339#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19335#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 19337#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19333#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19344#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19328#L370-4 main_~j~0#1 := 0; 19329#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19334#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19386#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19384#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19382#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19380#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19378#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19376#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19374#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19372#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19370#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19368#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19364#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19360#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19349#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19355#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19350#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19351#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19352#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19325#L378-2 [2022-11-20 10:35:13,268 INFO L750 eck$LassoCheckResult]: Loop: 19325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19464#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19325#L378-2 [2022-11-20 10:35:13,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:13,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1622914383, now seen corresponding path program 27 times [2022-11-20 10:35:13,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:13,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433619789] [2022-11-20 10:35:13,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:13,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:13,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:14,250 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:14,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:14,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433619789] [2022-11-20 10:35:14,250 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433619789] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:14,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [737313833] [2022-11-20 10:35:14,251 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 10:35:14,251 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:14,251 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:14,254 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:14,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-20 10:35:15,155 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2022-11-20 10:35:15,155 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:35:15,159 INFO L263 TraceCheckSpWp]: Trace formula consists of 338 conjuncts, 37 conjunts are in the unsatisfiable core [2022-11-20 10:35:15,161 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:15,613 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:35:15,829 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:35:15,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-20 10:35:15,971 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 10:35:15,971 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-20 10:35:19,950 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-20 10:35:19,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-20 10:35:19,997 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 100 proven. 220 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:19,997 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:26,710 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:35:26,715 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2022-11-20 10:35:27,176 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 90 proven. 228 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-20 10:35:27,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [737313833] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:27,176 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:27,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 31, 28] total 72 [2022-11-20 10:35:27,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691804227] [2022-11-20 10:35:27,177 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:27,177 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:27,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:27,177 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-20 10:35:27,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:27,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430128977] [2022-11-20 10:35:27,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:27,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:27,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:27,181 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:27,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:27,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:27,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:27,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2022-11-20 10:35:27,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=4672, Unknown=2, NotChecked=0, Total=5256 [2022-11-20 10:35:27,241 INFO L87 Difference]: Start difference. First operand 165 states and 218 transitions. cyclomatic complexity: 62 Second operand has 73 states, 72 states have (on average 2.125) internal successors, (153), 73 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:36,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:36,869 INFO L93 Difference]: Finished difference Result 444 states and 553 transitions. [2022-11-20 10:35:36,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 444 states and 553 transitions. [2022-11-20 10:35:36,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:36,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 444 states to 395 states and 496 transitions. [2022-11-20 10:35:36,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2022-11-20 10:35:36,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2022-11-20 10:35:36,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 395 states and 496 transitions. [2022-11-20 10:35:36,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:36,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 395 states and 496 transitions. [2022-11-20 10:35:36,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states and 496 transitions. [2022-11-20 10:35:36,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 241. [2022-11-20 10:35:36,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 241 states, 241 states have (on average 1.2987551867219918) internal successors, (313), 240 states have internal predecessors, (313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:36,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 313 transitions. [2022-11-20 10:35:36,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 241 states and 313 transitions. [2022-11-20 10:35:36,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2022-11-20 10:35:36,884 INFO L428 stractBuchiCegarLoop]: Abstraction has 241 states and 313 transitions. [2022-11-20 10:35:36,884 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-20 10:35:36,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 241 states and 313 transitions. [2022-11-20 10:35:36,885 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:36,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:36,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:36,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:36,886 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:35:36,886 INFO L748 eck$LassoCheckResult]: Stem: 20501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20512#L367 assume !(main_~length~0#1 < 1); 20503#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20504#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20505#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20513#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20584#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20615#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20616#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20614#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20577#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20612#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20573#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20610#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20609#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20569#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20608#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20607#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20565#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20604#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20603#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20557#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20601#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20600#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20599#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20597#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20594#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20596#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20533#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 20535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20514#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20515#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20694#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20689#L370-4 main_~j~0#1 := 0; 20516#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20517#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20675#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20674#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20672#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20670#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20669#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20668#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20667#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20666#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20665#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20664#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20662#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20621#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20624#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20622#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20623#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20625#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20507#L378-2 [2022-11-20 10:35:36,886 INFO L750 eck$LassoCheckResult]: Loop: 20507#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20618#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20507#L378-2 [2022-11-20 10:35:36,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:36,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1062214605, now seen corresponding path program 28 times [2022-11-20 10:35:36,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:36,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506495213] [2022-11-20 10:35:36,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:36,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:36,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:37,974 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:37,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:37,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506495213] [2022-11-20 10:35:37,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506495213] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:37,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [871742738] [2022-11-20 10:35:37,975 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 10:35:37,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:37,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:37,979 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:37,980 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-20 10:35:38,166 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 10:35:38,167 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:35:38,169 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 55 conjunts are in the unsatisfiable core [2022-11-20 10:35:38,172 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:38,287 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:35:38,427 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:35:38,428 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:35:38,451 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 10:35:38,452 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 10:35:39,035 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 10:35:39,037 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:39,038 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:39,403 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 10:35:39,406 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 10:35:39,540 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:39,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [871742738] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:39,541 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:39,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2022-11-20 10:35:39,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855856700] [2022-11-20 10:35:39,541 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:39,541 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:39,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:39,542 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-20 10:35:39,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:39,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741415297] [2022-11-20 10:35:39,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:39,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:39,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:39,544 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:39,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:39,546 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:39,600 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:39,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-11-20 10:35:39,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1769, Unknown=0, NotChecked=0, Total=1892 [2022-11-20 10:35:39,601 INFO L87 Difference]: Start difference. First operand 241 states and 313 transitions. cyclomatic complexity: 82 Second operand has 44 states, 43 states have (on average 2.2325581395348837) internal successors, (96), 44 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:41,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:41,348 INFO L93 Difference]: Finished difference Result 332 states and 414 transitions. [2022-11-20 10:35:41,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 332 states and 414 transitions. [2022-11-20 10:35:41,349 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26 [2022-11-20 10:35:41,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 332 states to 331 states and 413 transitions. [2022-11-20 10:35:41,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2022-11-20 10:35:41,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2022-11-20 10:35:41,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 331 states and 413 transitions. [2022-11-20 10:35:41,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:41,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 331 states and 413 transitions. [2022-11-20 10:35:41,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states and 413 transitions. [2022-11-20 10:35:41,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 249. [2022-11-20 10:35:41,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 249 states have (on average 1.3092369477911647) internal successors, (326), 248 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:41,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 326 transitions. [2022-11-20 10:35:41,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 249 states and 326 transitions. [2022-11-20 10:35:41,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-11-20 10:35:41,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 249 states and 326 transitions. [2022-11-20 10:35:41,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-20 10:35:41,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 326 transitions. [2022-11-20 10:35:41,360 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 10:35:41,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:41,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:41,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:41,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:35:41,362 INFO L748 eck$LassoCheckResult]: Stem: 21531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21542#L367 assume !(main_~length~0#1 < 1); 21533#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21534#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21535#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21543#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21623#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21617#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21611#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21608#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21607#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21605#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21602#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21601#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21599#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21596#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21593#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21590#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21589#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21588#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21581#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21579#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21577#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21573#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21574#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21633#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21568#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21548#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21740#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 21558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21550#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21551#L370-4 main_~j~0#1 := 0; 21546#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21538#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21539#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21547#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21708#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21707#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21705#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21703#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21702#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21701#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21700#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21699#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21697#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21696#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21695#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21694#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21652#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21656#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21654#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21655#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21657#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21537#L378-2 [2022-11-20 10:35:41,362 INFO L750 eck$LassoCheckResult]: Loop: 21537#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21653#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21537#L378-2 [2022-11-20 10:35:41,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:41,362 INFO L85 PathProgramCache]: Analyzing trace with hash 1669916558, now seen corresponding path program 29 times [2022-11-20 10:35:41,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:41,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694282968] [2022-11-20 10:35:41,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:41,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:41,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:42,425 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:42,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:42,425 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694282968] [2022-11-20 10:35:42,425 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694282968] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:42,425 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [917640669] [2022-11-20 10:35:42,425 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 10:35:42,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:42,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:42,460 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:42,461 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-20 10:35:42,880 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-11-20 10:35:42,880 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:35:42,883 INFO L263 TraceCheckSpWp]: Trace formula consists of 357 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-20 10:35:42,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:43,459 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 10:35:44,520 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 10:35:44,522 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:35:44,522 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 10:35:44,525 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:44,525 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:35:44,877 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 10:35:44,880 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 10:35:44,996 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:44,997 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [917640669] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:35:44,997 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:35:44,997 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 29] total 60 [2022-11-20 10:35:44,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104197294] [2022-11-20 10:35:44,997 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:35:44,997 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:35:44,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:44,998 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-20 10:35:44,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:44,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061557463] [2022-11-20 10:35:44,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:44,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:45,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:45,001 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:35:45,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:35:45,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:35:45,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:35:45,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-11-20 10:35:45,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=227, Invalid=3433, Unknown=0, NotChecked=0, Total=3660 [2022-11-20 10:35:45,115 INFO L87 Difference]: Start difference. First operand 249 states and 326 transitions. cyclomatic complexity: 87 Second operand has 61 states, 60 states have (on average 2.2666666666666666) internal successors, (136), 61 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:47,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:35:47,320 INFO L93 Difference]: Finished difference Result 366 states and 467 transitions. [2022-11-20 10:35:47,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 467 transitions. [2022-11-20 10:35:47,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 48 [2022-11-20 10:35:47,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 365 states and 466 transitions. [2022-11-20 10:35:47,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2022-11-20 10:35:47,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2022-11-20 10:35:47,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 365 states and 466 transitions. [2022-11-20 10:35:47,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 10:35:47,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 365 states and 466 transitions. [2022-11-20 10:35:47,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365 states and 466 transitions. [2022-11-20 10:35:47,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365 to 337. [2022-11-20 10:35:47,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 337 states, 337 states have (on average 1.2937685459940653) internal successors, (436), 336 states have internal predecessors, (436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:35:47,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 436 transitions. [2022-11-20 10:35:47,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 337 states and 436 transitions. [2022-11-20 10:35:47,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-20 10:35:47,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 337 states and 436 transitions. [2022-11-20 10:35:47,344 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-20 10:35:47,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states and 436 transitions. [2022-11-20 10:35:47,345 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-20 10:35:47,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:35:47,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:35:47,346 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 11, 10, 9, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:35:47,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 10:35:47,347 INFO L748 eck$LassoCheckResult]: Stem: 22614#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22625#L367 assume !(main_~length~0#1 < 1); 22616#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22617#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22618#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22626#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22707#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22701#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22697#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22696#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22695#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22691#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22690#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22689#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22685#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22684#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22683#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22679#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22678#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22677#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22673#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22672#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22671#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22666#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22663#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22658#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22659#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22719#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22650#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22631#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22836#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22830#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22828#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 22826#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22824#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22770#L370-4 main_~j~0#1 := 0; 22820#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22818#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22816#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22814#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22812#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22810#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22808#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22806#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22804#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22802#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22800#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22798#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22796#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22794#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22793#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22786#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22787#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22779#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22780#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22740#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22741#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22792#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22909#L378-2 [2022-11-20 10:35:47,348 INFO L750 eck$LassoCheckResult]: Loop: 22909#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22917#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22908#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22909#L378-2 [2022-11-20 10:35:47,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:35:47,348 INFO L85 PathProgramCache]: Analyzing trace with hash -2004200815, now seen corresponding path program 30 times [2022-11-20 10:35:47,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:35:47,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255633965] [2022-11-20 10:35:47,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:35:47,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:35:47,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:35:48,320 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 0 proven. 357 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:48,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:35:48,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255633965] [2022-11-20 10:35:48,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255633965] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:35:48,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [598469698] [2022-11-20 10:35:48,320 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 10:35:48,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:35:48,321 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:35:48,323 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:35:48,325 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-20 10:35:49,397 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2022-11-20 10:35:49,397 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 10:35:49,402 INFO L263 TraceCheckSpWp]: Trace formula consists of 368 conjuncts, 52 conjunts are in the unsatisfiable core [2022-11-20 10:35:49,406 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:35:49,796 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:35:49,898 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:35:49,906 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:35:50,034 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:35:50,034 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 42 [2022-11-20 10:35:50,049 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 10:35:50,049 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 42 [2022-11-20 10:35:50,204 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 57 [2022-11-20 10:35:56,919 INFO L321 Elim1Store]: treesize reduction 14, result has 74.5 percent of original size [2022-11-20 10:35:56,919 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 59 treesize of output 56 [2022-11-20 10:35:57,006 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 100 proven. 257 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:35:57,007 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:36:00,018 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2022-11-20 10:36:00,022 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 22 [2022-11-20 10:36:00,472 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 90 proven. 254 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-20 10:36:00,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [598469698] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 10:36:00,472 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 10:36:00,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 33, 27] total 76 [2022-11-20 10:36:00,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003304696] [2022-11-20 10:36:00,473 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 10:36:00,473 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 10:36:00,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:36:00,473 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2022-11-20 10:36:00,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:36:00,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571828689] [2022-11-20 10:36:00,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:36:00,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:36:00,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:36:00,477 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 10:36:00,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 10:36:00,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 10:36:00,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 10:36:00,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2022-11-20 10:36:00,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=574, Invalid=5276, Unknown=2, NotChecked=0, Total=5852 [2022-11-20 10:36:00,583 INFO L87 Difference]: Start difference. First operand 337 states and 436 transitions. cyclomatic complexity: 112 Second operand has 77 states, 76 states have (on average 2.1842105263157894) internal successors, (166), 77 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:38:00,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 10:38:00,119 INFO L93 Difference]: Finished difference Result 711 states and 859 transitions. [2022-11-20 10:38:00,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 711 states and 859 transitions. [2022-11-20 10:38:00,121 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-20 10:38:00,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 711 states to 387 states and 473 transitions. [2022-11-20 10:38:00,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83 [2022-11-20 10:38:00,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2022-11-20 10:38:00,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387 states and 473 transitions. [2022-11-20 10:38:00,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 10:38:00,127 INFO L218 hiAutomatonCegarLoop]: Abstraction has 387 states and 473 transitions. [2022-11-20 10:38:00,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387 states and 473 transitions. [2022-11-20 10:38:00,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387 to 193. [2022-11-20 10:38:00,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 193 states have (on average 1.2487046632124352) internal successors, (241), 192 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 10:38:00,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 241 transitions. [2022-11-20 10:38:00,134 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193 states and 241 transitions. [2022-11-20 10:38:00,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 181 states. [2022-11-20 10:38:00,134 INFO L428 stractBuchiCegarLoop]: Abstraction has 193 states and 241 transitions. [2022-11-20 10:38:00,134 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-20 10:38:00,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 241 transitions. [2022-11-20 10:38:00,135 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 44 [2022-11-20 10:38:00,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 10:38:00,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 10:38:00,138 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 12, 10, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 10:38:00,138 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 10:38:00,139 INFO L748 eck$LassoCheckResult]: Stem: 24500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24509#L367 assume !(main_~length~0#1 < 1); 24502#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24503#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24510#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24569#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24568#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24513#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24514#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24511#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24512#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24567#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24566#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24565#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24564#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24563#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24562#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24560#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24559#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24558#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24557#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24556#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24554#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24553#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24552#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24551#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24550#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24549#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24542#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24541#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24538#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24536#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24534#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24548#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24546#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24531#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24543#L372 assume main_#t~mem209#1 < 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24527#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24540#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24539#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24537#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24517#L372 assume !(main_#t~mem209#1 < 0);havoc main_#t~mem209#1; 24518#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24516#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24505#L370-4 main_~j~0#1 := 0; 24506#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24515#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24590#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24589#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24588#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24587#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24586#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24585#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24584#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24583#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24581#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24580#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24579#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24578#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24577#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24576#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24574#L378 assume !(main_#t~mem210#1 < 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24570#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24508#L378-2 [2022-11-20 10:38:00,139 INFO L750 eck$LassoCheckResult]: Loop: 24508#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24571#L378 assume main_#t~mem210#1 < 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24508#L378-2 [2022-11-20 10:38:00,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 10:38:00,139 INFO L85 PathProgramCache]: Analyzing trace with hash 1909429774, now seen corresponding path program 31 times [2022-11-20 10:38:00,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 10:38:00,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423156021] [2022-11-20 10:38:00,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 10:38:00,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 10:38:00,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:38:01,698 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 18 proven. 402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:38:01,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 10:38:01,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423156021] [2022-11-20 10:38:01,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423156021] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 10:38:01,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [54143201] [2022-11-20 10:38:01,699 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 10:38:01,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 10:38:01,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 10:38:01,701 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 10:38:01,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1ca18b65-e7f2-40cb-8a60-dac99a72cbab/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-20 10:38:01,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 10:38:01,928 INFO L263 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 76 conjunts are in the unsatisfiable core [2022-11-20 10:38:01,933 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 10:38:02,500 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 10:38:02,708 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:38:02,721 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:38:02,802 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:38:02,813 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 10:38:02,902 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:38:02,905 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:38:02,919 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:38:02,920 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:38:03,000 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 10:38:03,004 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 10:38:03,096 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 10:38:03,978 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 10:38:03,981 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 10:38:03,981 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 10:38:05,786 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 53 [2022-11-20 10:38:05,799 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 70137 treesize of output 69625