./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array13_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6b4ec56b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array13_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash bcb4bc0abad87560c498c61782d3ccf631503b41762d0db8553a6c831cbdcaff --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-6b4ec56 [2022-11-20 11:49:02,811 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-20 11:49:02,813 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-20 11:49:02,853 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-20 11:49:02,854 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-20 11:49:02,858 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-20 11:49:02,860 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-20 11:49:02,863 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-20 11:49:02,865 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-20 11:49:02,871 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-20 11:49:02,873 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-20 11:49:02,875 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-20 11:49:02,876 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-20 11:49:02,878 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-20 11:49:02,880 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-20 11:49:02,882 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-20 11:49:02,883 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-20 11:49:02,884 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-20 11:49:02,886 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-20 11:49:02,892 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-20 11:49:02,894 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-20 11:49:02,896 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-20 11:49:02,897 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-20 11:49:02,898 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-20 11:49:02,908 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-20 11:49:02,909 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-20 11:49:02,909 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-20 11:49:02,911 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-20 11:49:02,911 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-20 11:49:02,912 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-20 11:49:02,912 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-20 11:49:02,914 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-20 11:49:02,915 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-20 11:49:02,917 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-20 11:49:02,919 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-20 11:49:02,919 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-20 11:49:02,920 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-20 11:49:02,920 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-20 11:49:02,929 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-20 11:49:02,931 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-20 11:49:02,932 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-20 11:49:02,932 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-11-20 11:49:02,991 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-20 11:49:02,991 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-20 11:49:02,992 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-20 11:49:02,992 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-20 11:49:02,993 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-20 11:49:02,994 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-20 11:49:02,994 INFO L138 SettingsManager]: * Use SBE=true [2022-11-20 11:49:02,994 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-20 11:49:02,994 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-20 11:49:02,995 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-20 11:49:02,996 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-20 11:49:02,996 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-20 11:49:02,996 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-20 11:49:02,997 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-20 11:49:02,997 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-20 11:49:02,997 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-20 11:49:02,997 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-20 11:49:02,997 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-20 11:49:02,998 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-20 11:49:02,998 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-20 11:49:02,998 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-20 11:49:02,998 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-20 11:49:02,998 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-20 11:49:02,999 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-20 11:49:02,999 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-20 11:49:02,999 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-20 11:49:02,999 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-20 11:49:03,000 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-20 11:49:03,001 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-20 11:49:03,001 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcb4bc0abad87560c498c61782d3ccf631503b41762d0db8553a6c831cbdcaff [2022-11-20 11:49:03,294 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-20 11:49:03,326 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-20 11:49:03,329 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-20 11:49:03,331 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-20 11:49:03,332 INFO L275 PluginConnector]: CDTParser initialized [2022-11-20 11:49:03,333 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/../../sv-benchmarks/c/termination-15/array13_alloca.i [2022-11-20 11:49:06,443 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-20 11:49:06,728 INFO L351 CDTParser]: Found 1 translation units. [2022-11-20 11:49:06,729 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/sv-benchmarks/c/termination-15/array13_alloca.i [2022-11-20 11:49:06,746 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/data/faf9a52f8/10eff98a30c94de2b361825ea7b7238d/FLAG9ec4f9d2c [2022-11-20 11:49:06,765 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/data/faf9a52f8/10eff98a30c94de2b361825ea7b7238d [2022-11-20 11:49:06,768 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-20 11:49:06,769 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-20 11:49:06,774 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-20 11:49:06,774 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-20 11:49:06,778 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-20 11:49:06,779 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 11:49:06" (1/1) ... [2022-11-20 11:49:06,780 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2bf4a3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:06, skipping insertion in model container [2022-11-20 11:49:06,780 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 11:49:06" (1/1) ... [2022-11-20 11:49:06,787 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-20 11:49:06,813 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-20 11:49:07,130 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-20 11:49:07,144 INFO L203 MainTranslator]: Completed pre-run [2022-11-20 11:49:07,193 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-20 11:49:07,232 INFO L208 MainTranslator]: Completed translation [2022-11-20 11:49:07,233 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07 WrapperNode [2022-11-20 11:49:07,233 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-20 11:49:07,235 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-20 11:49:07,235 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-20 11:49:07,235 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-20 11:49:07,243 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,255 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,274 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2022-11-20 11:49:07,275 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-20 11:49:07,275 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-20 11:49:07,275 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-20 11:49:07,276 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-20 11:49:07,284 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,285 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,286 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,287 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,291 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,295 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,295 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,296 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,298 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-20 11:49:07,299 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-20 11:49:07,299 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-20 11:49:07,299 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-20 11:49:07,300 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (1/1) ... [2022-11-20 11:49:07,306 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:07,318 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:07,330 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:07,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-20 11:49:07,367 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-11-20 11:49:07,367 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-11-20 11:49:07,367 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-11-20 11:49:07,368 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-11-20 11:49:07,368 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-20 11:49:07,368 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-20 11:49:07,440 INFO L235 CfgBuilder]: Building ICFG [2022-11-20 11:49:07,443 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-20 11:49:07,557 INFO L276 CfgBuilder]: Performing block encoding [2022-11-20 11:49:07,563 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-20 11:49:07,563 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-11-20 11:49:07,565 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 11:49:07 BoogieIcfgContainer [2022-11-20 11:49:07,565 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-20 11:49:07,566 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-20 11:49:07,566 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-20 11:49:07,570 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-20 11:49:07,571 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 11:49:07,571 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 11:49:06" (1/3) ... [2022-11-20 11:49:07,572 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5a73235a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 11:49:07, skipping insertion in model container [2022-11-20 11:49:07,572 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 11:49:07,572 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 11:49:07" (2/3) ... [2022-11-20 11:49:07,572 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5a73235a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 11:49:07, skipping insertion in model container [2022-11-20 11:49:07,572 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-20 11:49:07,573 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 11:49:07" (3/3) ... [2022-11-20 11:49:07,574 INFO L332 chiAutomizerObserver]: Analyzing ICFG array13_alloca.i [2022-11-20 11:49:07,627 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-20 11:49:07,628 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-20 11:49:07,628 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-20 11:49:07,628 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-20 11:49:07,628 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-20 11:49:07,628 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-20 11:49:07,628 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-20 11:49:07,628 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-20 11:49:07,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:07,667 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-20 11:49:07,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:07,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:07,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-20 11:49:07,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-20 11:49:07,673 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-20 11:49:07,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:07,691 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-11-20 11:49:07,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:07,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:07,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-11-20 11:49:07,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-11-20 11:49:07,700 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10#L367true assume !(main_~length~0#1 < 1); 7#L367-2true call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4#L369true assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5#L370-3true [2022-11-20 11:49:07,701 INFO L750 eck$LassoCheckResult]: Loop: 5#L370-3true assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12#L372true assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15#L370-2true main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5#L370-3true [2022-11-20 11:49:07,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:07,707 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2022-11-20 11:49:07,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:07,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362643612] [2022-11-20 11:49:07,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:07,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:07,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:07,942 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:07,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:08,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:08,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:08,055 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2022-11-20 11:49:08,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:08,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41567209] [2022-11-20 11:49:08,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:08,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:08,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:08,072 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:08,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:08,082 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:08,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:08,084 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2022-11-20 11:49:08,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:08,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012064352] [2022-11-20 11:49:08,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:08,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:08,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:08,131 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:08,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:08,150 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:08,482 INFO L210 LassoAnalysis]: Preferences: [2022-11-20 11:49:08,482 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-20 11:49:08,482 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-20 11:49:08,482 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-20 11:49:08,483 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-20 11:49:08,483 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:08,483 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-20 11:49:08,483 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-20 11:49:08,484 INFO L133 ssoRankerPreferences]: Filename of dumped script: array13_alloca.i_Iteration1_Lasso [2022-11-20 11:49:08,484 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-20 11:49:08,484 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-20 11:49:08,506 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,523 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,529 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,535 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,539 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,543 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,758 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,762 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,767 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,770 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,773 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:08,780 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:09,088 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-20 11:49:09,092 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-20 11:49:09,094 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,094 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,097 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-11-20 11:49:09,110 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,126 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,126 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:09,126 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,127 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,127 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,129 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:09,129 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:09,143 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,152 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,152 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,152 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,153 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-11-20 11:49:09,157 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,168 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,168 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,168 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,168 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,171 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:09,172 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:09,183 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,191 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,192 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,192 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,193 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-11-20 11:49:09,201 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,214 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,214 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:09,214 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,214 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,214 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,215 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:09,215 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:09,225 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,235 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,237 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,243 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-11-20 11:49:09,243 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,256 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,256 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:09,256 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,257 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,257 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,258 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:09,258 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:09,270 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,279 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,280 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,280 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,281 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,292 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,304 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,304 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:09,304 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,304 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,305 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,306 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:09,306 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:09,309 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-11-20 11:49:09,318 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,323 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,324 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-11-20 11:49:09,330 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,339 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,340 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:09,340 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,340 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,340 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,341 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:09,341 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:09,346 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,358 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-11-20 11:49:09,359 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,359 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,360 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-11-20 11:49:09,363 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,374 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,374 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,374 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,374 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,377 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:09,377 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:09,406 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,411 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,415 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,427 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,427 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-11-20 11:49:09,437 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,437 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,438 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,438 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,442 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:09,442 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:09,456 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:09,470 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,472 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,481 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:09,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-11-20 11:49:09,493 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:09,494 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:09,494 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:09,494 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:09,503 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:09,503 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:09,520 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-20 11:49:09,568 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-11-20 11:49:09,568 INFO L444 ModelExtractionUtils]: 7 out of 22 variables were initially zero. Simplification set additionally 11 variables to zero. [2022-11-20 11:49:09,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:09,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:09,602 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:09,604 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-20 11:49:09,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-11-20 11:49:09,623 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-20 11:49:09,623 INFO L513 LassoAnalysis]: Proved termination. [2022-11-20 11:49:09,624 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~arr~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~arr~0#1.offset Supporting invariants [] [2022-11-20 11:49:09,630 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,646 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2022-11-20 11:49:09,687 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:09,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:09,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:09,729 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 2 conjunts are in the unsatisfiable core [2022-11-20 11:49:09,730 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:09,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:09,758 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 11:49:09,760 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:09,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:09,849 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-11-20 11:49:09,851 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:09,909 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2022-11-20 11:49:09,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-11-20 11:49:09,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:09,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-11-20 11:49:09,921 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2022-11-20 11:49:09,922 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:09,922 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2022-11-20 11:49:09,923 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:09,924 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2022-11-20 11:49:09,925 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:09,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2022-11-20 11:49:09,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:09,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2022-11-20 11:49:09,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-11-20 11:49:09,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-20 11:49:09,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2022-11-20 11:49:09,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:09,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 11:49:09,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2022-11-20 11:49:09,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-11-20 11:49:09,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:09,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2022-11-20 11:49:09,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 11:49:09,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2022-11-20 11:49:09,970 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-20 11:49:09,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2022-11-20 11:49:09,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:09,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:09,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:09,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:09,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:09,974 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 120#L367 assume !(main_~length~0#1 < 1); 114#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 115#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 116#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 117#L370-4 main_~j~0#1 := 0; 118#L378-2 [2022-11-20 11:49:09,974 INFO L750 eck$LassoCheckResult]: Loop: 118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 119#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 118#L378-2 [2022-11-20 11:49:09,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:09,982 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2022-11-20 11:49:09,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:09,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151128004] [2022-11-20 11:49:09,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:09,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:10,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:10,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:10,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:10,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151128004] [2022-11-20 11:49:10,096 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151128004] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-20 11:49:10,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-20 11:49:10,096 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-20 11:49:10,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708379427] [2022-11-20 11:49:10,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-20 11:49:10,099 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:10,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:10,099 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2022-11-20 11:49:10,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:10,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367946365] [2022-11-20 11:49:10,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:10,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:10,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,105 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:10,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,110 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:10,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:10,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-20 11:49:10,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-11-20 11:49:10,163 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:10,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:10,189 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2022-11-20 11:49:10,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2022-11-20 11:49:10,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:10,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2022-11-20 11:49:10,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-11-20 11:49:10,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-11-20 11:49:10,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2022-11-20 11:49:10,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:10,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 19 transitions. [2022-11-20 11:49:10,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2022-11-20 11:49:10,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2022-11-20 11:49:10,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:10,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2022-11-20 11:49:10,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-20 11:49:10,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-20 11:49:10,194 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2022-11-20 11:49:10,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-20 11:49:10,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2022-11-20 11:49:10,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:10,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:10,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:10,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:10,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:10,196 INFO L748 eck$LassoCheckResult]: Stem: 145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 153#L367 assume !(main_~length~0#1 < 1); 147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 154#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 155#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 150#L370-4 main_~j~0#1 := 0; 151#L378-2 [2022-11-20 11:49:10,197 INFO L750 eck$LassoCheckResult]: Loop: 151#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 152#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 151#L378-2 [2022-11-20 11:49:10,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:10,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2022-11-20 11:49:10,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:10,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886580874] [2022-11-20 11:49:10,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:10,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:10,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,213 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:10,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:10,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:10,231 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2022-11-20 11:49:10,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:10,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574947645] [2022-11-20 11:49:10,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:10,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:10,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,242 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:10,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:10,246 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:10,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:10,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2022-11-20 11:49:10,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:10,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093272935] [2022-11-20 11:49:10,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:10,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:10,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:10,683 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:10,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:10,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093272935] [2022-11-20 11:49:10,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093272935] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:10,684 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [323379980] [2022-11-20 11:49:10,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:10,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:10,684 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:10,686 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:10,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-20 11:49:10,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:10,762 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-20 11:49:10,765 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:10,819 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-11-20 11:49:10,892 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:10,901 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:10,901 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:11,006 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2022-11-20 11:49:11,011 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2022-11-20 11:49:11,032 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,033 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [323379980] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:11,033 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:11,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6] total 14 [2022-11-20 11:49:11,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301541666] [2022-11-20 11:49:11,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:11,086 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:11,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-11-20 11:49:11,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=158, Unknown=0, NotChecked=0, Total=210 [2022-11-20 11:49:11,089 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 15 states, 14 states have (on average 1.7857142857142858) internal successors, (25), 15 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:11,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:11,240 INFO L93 Difference]: Finished difference Result 22 states and 30 transitions. [2022-11-20 11:49:11,241 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 30 transitions. [2022-11-20 11:49:11,245 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:11,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 30 transitions. [2022-11-20 11:49:11,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-20 11:49:11,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-20 11:49:11,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2022-11-20 11:49:11,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:11,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2022-11-20 11:49:11,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2022-11-20 11:49:11,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 19. [2022-11-20 11:49:11,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.368421052631579) internal successors, (26), 18 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:11,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 26 transitions. [2022-11-20 11:49:11,256 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-20 11:49:11,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 11:49:11,258 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 26 transitions. [2022-11-20 11:49:11,258 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-20 11:49:11,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 26 transitions. [2022-11-20 11:49:11,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:11,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:11,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:11,262 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:11,262 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:11,262 INFO L748 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 277#L367 assume !(main_~length~0#1 < 1); 271#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 272#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 273#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 278#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 283#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 279#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 280#L370-4 main_~j~0#1 := 0; 284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 274#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 275#L378-2 [2022-11-20 11:49:11,263 INFO L750 eck$LassoCheckResult]: Loop: 275#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 282#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 275#L378-2 [2022-11-20 11:49:11,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:11,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2022-11-20 11:49:11,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:11,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496095315] [2022-11-20 11:49:11,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:11,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,286 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:11,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,296 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:11,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:11,296 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2022-11-20 11:49:11,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:11,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263184765] [2022-11-20 11:49:11,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:11,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,312 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:11,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:11,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:11,316 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2022-11-20 11:49:11,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:11,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697043293] [2022-11-20 11:49:11,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:11,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:11,426 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:11,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697043293] [2022-11-20 11:49:11,430 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697043293] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:11,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [935304507] [2022-11-20 11:49:11,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,431 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:11,431 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:11,432 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:11,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-20 11:49:11,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:11,489 INFO L263 TraceCheckSpWp]: Trace formula consists of 69 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-20 11:49:11,490 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:11,545 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,546 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:11,590 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [935304507] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:11,591 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:11,591 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 11 [2022-11-20 11:49:11,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216425884] [2022-11-20 11:49:11,592 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:11,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:11,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-20 11:49:11,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-11-20 11:49:11,643 INFO L87 Difference]: Start difference. First operand 19 states and 26 transitions. cyclomatic complexity: 10 Second operand has 11 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:11,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:11,758 INFO L93 Difference]: Finished difference Result 43 states and 57 transitions. [2022-11-20 11:49:11,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 57 transitions. [2022-11-20 11:49:11,759 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:11,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 39 states and 51 transitions. [2022-11-20 11:49:11,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-20 11:49:11,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-20 11:49:11,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-20 11:49:11,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:11,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-20 11:49:11,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-20 11:49:11,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 34. [2022-11-20 11:49:11,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 33 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:11,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 45 transitions. [2022-11-20 11:49:11,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-20 11:49:11,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 11:49:11,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 45 transitions. [2022-11-20 11:49:11,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-20 11:49:11,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 45 transitions. [2022-11-20 11:49:11,767 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:11,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:11,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:11,768 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:11,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:11,768 INFO L748 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 444#L367 assume main_~length~0#1 < 1;main_~length~0#1 := 1; 445#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 461#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 457#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 455#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 456#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 458#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 452#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 453#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 440#L370-4 main_~j~0#1 := 0; 441#L378-2 [2022-11-20 11:49:11,769 INFO L750 eck$LassoCheckResult]: Loop: 441#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 451#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 441#L378-2 [2022-11-20 11:49:11,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:11,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1080825110, now seen corresponding path program 1 times [2022-11-20 11:49:11,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:11,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883505987] [2022-11-20 11:49:11,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:11,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:11,814 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:11,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883505987] [2022-11-20 11:49:11,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883505987] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:11,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1079430598] [2022-11-20 11:49:11,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:11,816 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:11,822 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:11,823 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-20 11:49:11,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:11,884 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 11:49:11,885 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:11,923 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:11,923 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-20 11:49:11,923 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1079430598] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-20 11:49:11,923 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-20 11:49:11,923 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2022-11-20 11:49:11,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199023363] [2022-11-20 11:49:11,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-20 11:49:11,924 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:11,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:11,924 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2022-11-20 11:49:11,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:11,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922233158] [2022-11-20 11:49:11,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:11,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:11,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,928 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:11,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:11,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:11,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:11,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-20 11:49:11,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2022-11-20 11:49:11,979 INFO L87 Difference]: Start difference. First operand 34 states and 45 transitions. cyclomatic complexity: 17 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:12,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:12,003 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2022-11-20 11:49:12,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2022-11-20 11:49:12,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:12,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 21 states and 27 transitions. [2022-11-20 11:49:12,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-20 11:49:12,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-11-20 11:49:12,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 27 transitions. [2022-11-20 11:49:12,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:12,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 11:49:12,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 27 transitions. [2022-11-20 11:49:12,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-11-20 11:49:12,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:12,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-11-20 11:49:12,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 11:49:12,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-20 11:49:12,008 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-11-20 11:49:12,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-20 11:49:12,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2022-11-20 11:49:12,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:12,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:12,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:12,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:12,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:12,009 INFO L748 eck$LassoCheckResult]: Stem: 542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 551#L367 assume !(main_~length~0#1 < 1); 544#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 545#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 546#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 552#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 555#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 553#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 554#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 558#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 557#L370-4 main_~j~0#1 := 0; 550#L378-2 [2022-11-20 11:49:12,010 INFO L750 eck$LassoCheckResult]: Loop: 550#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 556#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 550#L378-2 [2022-11-20 11:49:12,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:12,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1781889688, now seen corresponding path program 1 times [2022-11-20 11:49:12,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:12,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278082207] [2022-11-20 11:49:12,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:12,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:12,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:12,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:12,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:12,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:12,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:12,054 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2022-11-20 11:49:12,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:12,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448752115] [2022-11-20 11:49:12,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:12,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:12,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:12,058 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:12,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:12,062 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:12,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:12,063 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959589, now seen corresponding path program 1 times [2022-11-20 11:49:12,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:12,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377422091] [2022-11-20 11:49:12,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:12,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:12,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:12,416 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:12,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:12,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [377422091] [2022-11-20 11:49:12,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [377422091] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:12,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [38591319] [2022-11-20 11:49:12,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:12,417 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:12,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:12,423 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:12,429 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-11-20 11:49:12,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:12,489 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-20 11:49:12,491 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:12,510 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:12,578 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:12,579 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:12,595 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:12,596 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:12,644 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:12,653 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:12,654 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:12,865 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:12,872 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 54 [2022-11-20 11:49:12,921 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:12,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [38591319] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:12,922 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:12,922 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-20 11:49:12,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006104427] [2022-11-20 11:49:12,922 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:12,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:12,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-20 11:49:12,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2022-11-20 11:49:12,985 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 19 states, 18 states have (on average 1.8333333333333333) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:13,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:13,121 INFO L93 Difference]: Finished difference Result 39 states and 51 transitions. [2022-11-20 11:49:13,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 51 transitions. [2022-11-20 11:49:13,122 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:13,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 51 transitions. [2022-11-20 11:49:13,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 11:49:13,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 11:49:13,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2022-11-20 11:49:13,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:13,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2022-11-20 11:49:13,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2022-11-20 11:49:13,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-11-20 11:49:13,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.3703703703703705) internal successors, (37), 26 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:13,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-11-20 11:49:13,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-20 11:49:13,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 11:49:13,129 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-11-20 11:49:13,130 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-20 11:49:13,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 37 transitions. [2022-11-20 11:49:13,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:13,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:13,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:13,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:13,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:13,132 INFO L748 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 723#L367 assume !(main_~length~0#1 < 1); 716#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 717#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 718#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 724#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 725#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 728#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 739#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 721#L370-4 main_~j~0#1 := 0; 722#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 719#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 720#L378-2 [2022-11-20 11:49:13,133 INFO L750 eck$LassoCheckResult]: Loop: 720#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 733#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 720#L378-2 [2022-11-20 11:49:13,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:13,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1295959587, now seen corresponding path program 1 times [2022-11-20 11:49:13,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:13,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248216573] [2022-11-20 11:49:13,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:13,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:13,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:13,155 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:13,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:13,176 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:13,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:13,177 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2022-11-20 11:49:13,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:13,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378936862] [2022-11-20 11:49:13,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:13,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:13,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:13,183 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:13,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:13,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:13,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:13,191 INFO L85 PathProgramCache]: Analyzing trace with hash 123354080, now seen corresponding path program 1 times [2022-11-20 11:49:13,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:13,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575841365] [2022-11-20 11:49:13,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:13,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:13,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:13,420 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:13,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:13,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575841365] [2022-11-20 11:49:13,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575841365] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:13,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [492804014] [2022-11-20 11:49:13,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:13,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:13,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:13,426 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:13,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-20 11:49:13,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:13,501 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-20 11:49:13,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:13,535 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:13,671 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-20 11:49:13,671 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-20 11:49:13,684 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:13,684 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:13,754 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:13,757 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:13,776 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:13,777 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [492804014] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:13,777 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:13,777 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 15 [2022-11-20 11:49:13,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084216135] [2022-11-20 11:49:13,777 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:13,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:13,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-20 11:49:13,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=190, Unknown=0, NotChecked=0, Total=240 [2022-11-20 11:49:13,853 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. cyclomatic complexity: 13 Second operand has 16 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:13,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:13,979 INFO L93 Difference]: Finished difference Result 36 states and 48 transitions. [2022-11-20 11:49:13,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 48 transitions. [2022-11-20 11:49:13,979 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:13,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 48 transitions. [2022-11-20 11:49:13,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-11-20 11:49:13,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-11-20 11:49:13,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 48 transitions. [2022-11-20 11:49:13,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:13,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36 states and 48 transitions. [2022-11-20 11:49:13,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 48 transitions. [2022-11-20 11:49:13,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 32. [2022-11-20 11:49:13,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.34375) internal successors, (43), 31 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:13,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 43 transitions. [2022-11-20 11:49:13,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-20 11:49:13,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-20 11:49:13,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 32 states and 43 transitions. [2022-11-20 11:49:13,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-20 11:49:13,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 43 transitions. [2022-11-20 11:49:13,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:13,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:13,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:13,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:13,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:13,987 INFO L748 eck$LassoCheckResult]: Stem: 898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 906#L367 assume !(main_~length~0#1 < 1); 900#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 901#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 902#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 907#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 911#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 909#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 915#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 916#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 905#L370-4 main_~j~0#1 := 0; 904#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 910#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 919#L378-2 [2022-11-20 11:49:13,987 INFO L750 eck$LassoCheckResult]: Loop: 919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 918#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 919#L378-2 [2022-11-20 11:49:13,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:13,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2022-11-20 11:49:13,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:13,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091811608] [2022-11-20 11:49:13,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:13,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:13,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:13,997 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:14,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:14,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:14,005 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2022-11-20 11:49:14,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:14,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240344996] [2022-11-20 11:49:14,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:14,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:14,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:14,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:14,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:14,011 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2022-11-20 11:49:14,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:14,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40123342] [2022-11-20 11:49:14,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:14,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:14,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:14,158 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:14,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:14,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40123342] [2022-11-20 11:49:14,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40123342] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:14,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1810776674] [2022-11-20 11:49:14,159 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:49:14,159 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:14,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:14,166 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:14,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-20 11:49:14,232 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:49:14,232 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:14,233 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-20 11:49:14,234 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:14,296 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 11:49:14,417 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:14,420 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:14,420 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:14,515 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:14,519 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:14,537 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:14,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1810776674] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:14,537 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:14,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 18 [2022-11-20 11:49:14,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584646279] [2022-11-20 11:49:14,538 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:14,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:14,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-20 11:49:14,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2022-11-20 11:49:14,591 INFO L87 Difference]: Start difference. First operand 32 states and 43 transitions. cyclomatic complexity: 14 Second operand has 19 states, 18 states have (on average 2.0) internal successors, (36), 19 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:14,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:14,799 INFO L93 Difference]: Finished difference Result 47 states and 62 transitions. [2022-11-20 11:49:14,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 62 transitions. [2022-11-20 11:49:14,799 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:14,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 62 transitions. [2022-11-20 11:49:14,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-11-20 11:49:14,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-11-20 11:49:14,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 62 transitions. [2022-11-20 11:49:14,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:14,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 62 transitions. [2022-11-20 11:49:14,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 62 transitions. [2022-11-20 11:49:14,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 38. [2022-11-20 11:49:14,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.368421052631579) internal successors, (52), 37 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:14,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 52 transitions. [2022-11-20 11:49:14,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-20 11:49:14,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 11:49:14,806 INFO L428 stractBuchiCegarLoop]: Abstraction has 38 states and 52 transitions. [2022-11-20 11:49:14,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-20 11:49:14,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 52 transitions. [2022-11-20 11:49:14,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:14,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:14,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:14,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:14,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:14,811 INFO L748 eck$LassoCheckResult]: Stem: 1105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1113#L367 assume !(main_~length~0#1 < 1); 1107#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1108#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1114#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1123#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1115#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1116#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1117#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1139#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1133#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1134#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1130#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1127#L370-4 main_~j~0#1 := 0; 1125#L378-2 [2022-11-20 11:49:14,811 INFO L750 eck$LassoCheckResult]: Loop: 1125#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1126#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1125#L378-2 [2022-11-20 11:49:14,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:14,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1518446116, now seen corresponding path program 2 times [2022-11-20 11:49:14,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:14,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733576721] [2022-11-20 11:49:14,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:14,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:14,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:14,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:14,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:14,843 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2022-11-20 11:49:14,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:14,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735873081] [2022-11-20 11:49:14,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:14,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:14,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,847 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:14,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:14,850 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:14,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:14,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1062164511, now seen corresponding path program 2 times [2022-11-20 11:49:14,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:14,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492778469] [2022-11-20 11:49:14,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:14,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:14,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:15,311 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:15,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:15,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492778469] [2022-11-20 11:49:15,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492778469] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:15,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1562866315] [2022-11-20 11:49:15,312 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:49:15,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:15,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:15,316 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:15,325 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-20 11:49:15,389 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:49:15,389 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:15,390 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 11:49:15,392 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:15,422 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:15,500 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:15,500 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:15,516 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:15,517 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:15,551 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:15,552 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:15,568 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:15,568 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:15,637 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:49:15,640 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:49:15,640 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 10 [2022-11-20 11:49:15,651 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:15,651 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:16,214 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2022-11-20 11:49:16,222 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 66 [2022-11-20 11:49:16,289 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 11:49:16,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1562866315] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:16,290 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:16,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 9] total 26 [2022-11-20 11:49:16,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031767769] [2022-11-20 11:49:16,290 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:16,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:16,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-20 11:49:16,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=558, Unknown=0, NotChecked=0, Total=702 [2022-11-20 11:49:16,357 INFO L87 Difference]: Start difference. First operand 38 states and 52 transitions. cyclomatic complexity: 18 Second operand has 27 states, 26 states have (on average 1.8076923076923077) internal successors, (47), 27 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:16,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:16,555 INFO L93 Difference]: Finished difference Result 43 states and 56 transitions. [2022-11-20 11:49:16,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 56 transitions. [2022-11-20 11:49:16,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:16,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 56 transitions. [2022-11-20 11:49:16,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 11:49:16,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 11:49:16,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 56 transitions. [2022-11-20 11:49:16,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:16,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 56 transitions. [2022-11-20 11:49:16,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 56 transitions. [2022-11-20 11:49:16,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 24. [2022-11-20 11:49:16,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2916666666666667) internal successors, (31), 23 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:16,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 31 transitions. [2022-11-20 11:49:16,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-20 11:49:16,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-20 11:49:16,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 31 transitions. [2022-11-20 11:49:16,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-20 11:49:16,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 31 transitions. [2022-11-20 11:49:16,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:16,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:16,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:16,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:16,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:16,562 INFO L748 eck$LassoCheckResult]: Stem: 1329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1335#L367 assume !(main_~length~0#1 < 1); 1327#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1328#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1331#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1336#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1337#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1338#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1341#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1342#L370-4 main_~j~0#1 := 0; 1347#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1334#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1333#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1340#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1345#L378-2 [2022-11-20 11:49:16,562 INFO L750 eck$LassoCheckResult]: Loop: 1345#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1344#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1345#L378-2 [2022-11-20 11:49:16,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:16,563 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2022-11-20 11:49:16,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:16,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683272437] [2022-11-20 11:49:16,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:16,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:16,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:16,573 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:16,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:16,582 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:16,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:16,583 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2022-11-20 11:49:16,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:16,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530404735] [2022-11-20 11:49:16,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:16,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:16,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:16,588 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:16,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:16,591 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:16,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:16,592 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2022-11-20 11:49:16,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:16,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311549015] [2022-11-20 11:49:16,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:16,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:16,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:16,714 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:16,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:16,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311549015] [2022-11-20 11:49:16,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311549015] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:16,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [839589057] [2022-11-20 11:49:16,715 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:49:16,715 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:16,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:16,719 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:16,751 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-20 11:49:16,796 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-20 11:49:16,796 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:16,797 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-20 11:49:16,798 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:16,874 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:16,875 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:16,933 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:16,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [839589057] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:16,933 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:16,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 14 [2022-11-20 11:49:16,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509029412] [2022-11-20 11:49:16,934 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:16,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:16,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-20 11:49:16,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-11-20 11:49:16,984 INFO L87 Difference]: Start difference. First operand 24 states and 31 transitions. cyclomatic complexity: 10 Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 14 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:17,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:17,091 INFO L93 Difference]: Finished difference Result 35 states and 43 transitions. [2022-11-20 11:49:17,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 43 transitions. [2022-11-20 11:49:17,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:17,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 37 transitions. [2022-11-20 11:49:17,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-11-20 11:49:17,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-11-20 11:49:17,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 37 transitions. [2022-11-20 11:49:17,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:17,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 37 transitions. [2022-11-20 11:49:17,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 37 transitions. [2022-11-20 11:49:17,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-11-20 11:49:17,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2692307692307692) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:17,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 33 transitions. [2022-11-20 11:49:17,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-20 11:49:17,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-20 11:49:17,098 INFO L428 stractBuchiCegarLoop]: Abstraction has 26 states and 33 transitions. [2022-11-20 11:49:17,098 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-20 11:49:17,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 33 transitions. [2022-11-20 11:49:17,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:17,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:17,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:17,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:17,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:17,100 INFO L748 eck$LassoCheckResult]: Stem: 1521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1530#L367 assume !(main_~length~0#1 < 1); 1523#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1524#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1531#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1546#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1545#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1534#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1535#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1532#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1533#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1543#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1541#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1540#L370-4 main_~j~0#1 := 0; 1529#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1539#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1538#L378-2 [2022-11-20 11:49:17,100 INFO L750 eck$LassoCheckResult]: Loop: 1538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1537#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1538#L378-2 [2022-11-20 11:49:17,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:17,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1742222883, now seen corresponding path program 2 times [2022-11-20 11:49:17,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:17,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209050846] [2022-11-20 11:49:17,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:17,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:17,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:17,110 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:17,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:17,119 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:17,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:17,120 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2022-11-20 11:49:17,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:17,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28050106] [2022-11-20 11:49:17,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:17,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:17,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:17,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:17,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:17,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:17,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:17,126 INFO L85 PathProgramCache]: Analyzing trace with hash -761053530, now seen corresponding path program 2 times [2022-11-20 11:49:17,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:17,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785847707] [2022-11-20 11:49:17,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:17,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:17,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:17,373 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:17,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:17,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785847707] [2022-11-20 11:49:17,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785847707] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:17,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1571123262] [2022-11-20 11:49:17,373 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:49:17,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:17,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:17,378 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:17,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-20 11:49:17,459 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:49:17,459 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:17,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 11:49:17,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:17,524 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:17,606 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:17,607 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:17,619 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:17,619 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:17,725 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:17,727 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:17,727 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:17,866 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:17,869 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:17,888 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:17,888 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1571123262] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:17,888 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:17,888 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 10] total 22 [2022-11-20 11:49:17,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917241325] [2022-11-20 11:49:17,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:17,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:17,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-11-20 11:49:17,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2022-11-20 11:49:17,936 INFO L87 Difference]: Start difference. First operand 26 states and 33 transitions. cyclomatic complexity: 10 Second operand has 23 states, 22 states have (on average 1.9090909090909092) internal successors, (42), 23 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:18,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:18,157 INFO L93 Difference]: Finished difference Result 30 states and 37 transitions. [2022-11-20 11:49:18,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2022-11-20 11:49:18,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:18,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 37 transitions. [2022-11-20 11:49:18,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 11:49:18,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 11:49:18,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 37 transitions. [2022-11-20 11:49:18,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:18,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 37 transitions. [2022-11-20 11:49:18,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 37 transitions. [2022-11-20 11:49:18,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 22. [2022-11-20 11:49:18,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:18,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2022-11-20 11:49:18,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-20 11:49:18,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-20 11:49:18,161 INFO L428 stractBuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2022-11-20 11:49:18,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-20 11:49:18,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2022-11-20 11:49:18,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:18,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:18,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:18,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:18,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:18,163 INFO L748 eck$LassoCheckResult]: Stem: 1727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1736#L367 assume !(main_~length~0#1 < 1); 1729#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1730#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1737#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1743#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1744#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1745#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1746#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1738#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1739#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1740#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1742#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1732#L370-4 main_~j~0#1 := 0; 1733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1734#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1741#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1748#L378-2 [2022-11-20 11:49:18,163 INFO L750 eck$LassoCheckResult]: Loop: 1748#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1747#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1748#L378-2 [2022-11-20 11:49:18,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 4 times [2022-11-20 11:49:18,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010207107] [2022-11-20 11:49:18,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,174 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:18,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,184 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:18,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,184 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2022-11-20 11:49:18,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388127824] [2022-11-20 11:49:18,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,187 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:18,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:18,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 4 times [2022-11-20 11:49:18,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828074447] [2022-11-20 11:49:18,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:18,389 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:18,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:18,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828074447] [2022-11-20 11:49:18,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828074447] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:18,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1631827663] [2022-11-20 11:49:18,390 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:49:18,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:18,390 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:18,397 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:18,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-20 11:49:18,469 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:49:18,470 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:18,471 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-20 11:49:18,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:18,497 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:18,609 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:18,612 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:18,612 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:18,694 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:18,697 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:18,722 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:18,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1631827663] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:18,722 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:18,723 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2022-11-20 11:49:18,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426674496] [2022-11-20 11:49:18,723 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:18,794 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:18,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-20 11:49:18,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2022-11-20 11:49:18,795 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 17 states, 16 states have (on average 2.125) internal successors, (34), 17 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:18,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:18,935 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2022-11-20 11:49:18,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 42 transitions. [2022-11-20 11:49:18,936 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:18,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 42 transitions. [2022-11-20 11:49:18,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-11-20 11:49:18,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-11-20 11:49:18,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2022-11-20 11:49:18,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:18,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 42 transitions. [2022-11-20 11:49:18,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2022-11-20 11:49:18,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 28. [2022-11-20 11:49:18,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:18,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2022-11-20 11:49:18,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-20 11:49:18,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-20 11:49:18,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2022-11-20 11:49:18,943 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-20 11:49:18,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2022-11-20 11:49:18,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:18,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:18,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:18,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:18,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:18,944 INFO L748 eck$LassoCheckResult]: Stem: 1933#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 1941#L367 assume !(main_~length~0#1 < 1); 1935#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 1936#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 1937#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1942#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1948#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1952#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1953#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 1944#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 1946#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 1949#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 1950#L370-4 main_~j~0#1 := 0; 1958#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1938#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1939#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1945#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1957#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1956#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 1955#L378-2 [2022-11-20 11:49:18,944 INFO L750 eck$LassoCheckResult]: Loop: 1955#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 1954#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 1955#L378-2 [2022-11-20 11:49:18,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 5 times [2022-11-20 11:49:18,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076318706] [2022-11-20 11:49:18,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:18,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:18,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,976 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2022-11-20 11:49:18,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052154546] [2022-11-20 11:49:18,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,981 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:18,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:18,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:18,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:18,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 5 times [2022-11-20 11:49:18,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:18,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363287841] [2022-11-20 11:49:18,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:18,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:18,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:19,135 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:19,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:19,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363287841] [2022-11-20 11:49:19,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363287841] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:19,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937412625] [2022-11-20 11:49:19,136 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:49:19,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:19,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:19,145 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:19,166 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-20 11:49:19,230 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-11-20 11:49:19,230 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:19,231 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-20 11:49:19,232 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:19,334 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:19,335 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:19,425 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:19,426 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937412625] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:19,426 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:19,426 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 17 [2022-11-20 11:49:19,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191362930] [2022-11-20 11:49:19,426 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:19,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:19,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-11-20 11:49:19,474 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2022-11-20 11:49:19,474 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 9 Second operand has 17 states, 17 states have (on average 2.235294117647059) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:19,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:19,615 INFO L93 Difference]: Finished difference Result 35 states and 42 transitions. [2022-11-20 11:49:19,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 42 transitions. [2022-11-20 11:49:19,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:19,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 27 states and 34 transitions. [2022-11-20 11:49:19,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:49:19,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:49:19,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2022-11-20 11:49:19,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:19,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 34 transitions. [2022-11-20 11:49:19,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2022-11-20 11:49:19,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2022-11-20 11:49:19,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.24) internal successors, (31), 24 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:19,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 31 transitions. [2022-11-20 11:49:19,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-20 11:49:19,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-20 11:49:19,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2022-11-20 11:49:19,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-20 11:49:19,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 31 transitions. [2022-11-20 11:49:19,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:19,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:19,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:19,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:19,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:19,620 INFO L748 eck$LassoCheckResult]: Stem: 2166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2175#L367 assume !(main_~length~0#1 < 1); 2168#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2169#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2170#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2176#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2177#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2178#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2187#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2186#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2185#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2183#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2184#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2182#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2171#L370-4 main_~j~0#1 := 0; 2172#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2173#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2174#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2180#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2190#L378-2 [2022-11-20 11:49:19,620 INFO L750 eck$LassoCheckResult]: Loop: 2190#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2189#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2190#L378-2 [2022-11-20 11:49:19,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:19,621 INFO L85 PathProgramCache]: Analyzing trace with hash 666851296, now seen corresponding path program 6 times [2022-11-20 11:49:19,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:19,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641639055] [2022-11-20 11:49:19,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:19,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:19,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:19,633 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:19,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:19,644 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:19,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:19,644 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2022-11-20 11:49:19,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:19,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499326867] [2022-11-20 11:49:19,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:19,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:19,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:19,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:19,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:19,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:19,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:19,651 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 6 times [2022-11-20 11:49:19,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:19,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281568643] [2022-11-20 11:49:19,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:19,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:19,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:20,006 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:20,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:20,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281568643] [2022-11-20 11:49:20,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281568643] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:20,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1960016377] [2022-11-20 11:49:20,007 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:49:20,007 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:20,007 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:20,011 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:20,039 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-20 11:49:20,102 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-11-20 11:49:20,102 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:20,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-20 11:49:20,108 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:20,200 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:20,302 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:20,303 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:20,452 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:20,454 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:20,454 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:20,612 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:20,618 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:20,654 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:20,654 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1960016377] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:20,654 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:20,655 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2022-11-20 11:49:20,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622871003] [2022-11-20 11:49:20,655 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:20,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:20,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-11-20 11:49:20,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2022-11-20 11:49:20,703 INFO L87 Difference]: Start difference. First operand 25 states and 31 transitions. cyclomatic complexity: 8 Second operand has 27 states, 26 states have (on average 2.0) internal successors, (52), 27 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:20,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:20,999 INFO L93 Difference]: Finished difference Result 27 states and 33 transitions. [2022-11-20 11:49:20,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 33 transitions. [2022-11-20 11:49:20,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:20,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 33 transitions. [2022-11-20 11:49:20,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-11-20 11:49:21,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-11-20 11:49:21,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 33 transitions. [2022-11-20 11:49:21,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:21,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 11:49:21,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 33 transitions. [2022-11-20 11:49:21,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-11-20 11:49:21,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:21,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2022-11-20 11:49:21,001 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 11:49:21,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-20 11:49:21,003 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2022-11-20 11:49:21,003 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-20 11:49:21,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2022-11-20 11:49:21,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:21,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:21,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:21,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:21,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:21,005 INFO L748 eck$LassoCheckResult]: Stem: 2406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2413#L367 assume !(main_~length~0#1 < 1); 2404#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2405#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2414#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2426#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2415#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2416#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2417#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2419#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2425#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2424#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2423#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2421#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2422#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2420#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2409#L370-4 main_~j~0#1 := 0; 2410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2411#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2418#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2430#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2429#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2428#L378-2 [2022-11-20 11:49:21,005 INFO L750 eck$LassoCheckResult]: Loop: 2428#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2427#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2428#L378-2 [2022-11-20 11:49:21,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:21,005 INFO L85 PathProgramCache]: Analyzing trace with hash 893969701, now seen corresponding path program 7 times [2022-11-20 11:49:21,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:21,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871463532] [2022-11-20 11:49:21,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:21,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:21,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:21,018 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:21,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:21,030 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:21,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:21,030 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2022-11-20 11:49:21,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:21,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530154512] [2022-11-20 11:49:21,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:21,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:21,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:21,038 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:21,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:21,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:21,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:21,042 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 7 times [2022-11-20 11:49:21,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:21,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026500058] [2022-11-20 11:49:21,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:21,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:21,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:21,339 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:21,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:21,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026500058] [2022-11-20 11:49:21,339 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026500058] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:21,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1282203275] [2022-11-20 11:49:21,339 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:49:21,340 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:21,340 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:21,346 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:21,366 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-20 11:49:21,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:21,433 INFO L263 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-20 11:49:21,435 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:21,467 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:21,625 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:21,628 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:21,628 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:21,723 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:21,726 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:21,761 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:21,761 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1282203275] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:21,761 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:21,762 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12] total 19 [2022-11-20 11:49:21,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844319095] [2022-11-20 11:49:21,762 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:21,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:21,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-20 11:49:21,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=323, Unknown=0, NotChecked=0, Total=380 [2022-11-20 11:49:21,809 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 8 Second operand has 20 states, 19 states have (on average 2.1578947368421053) internal successors, (41), 20 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:22,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:22,040 INFO L93 Difference]: Finished difference Result 43 states and 53 transitions. [2022-11-20 11:49:22,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 53 transitions. [2022-11-20 11:49:22,040 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:22,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 53 transitions. [2022-11-20 11:49:22,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2022-11-20 11:49:22,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2022-11-20 11:49:22,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 53 transitions. [2022-11-20 11:49:22,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:22,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 53 transitions. [2022-11-20 11:49:22,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 53 transitions. [2022-11-20 11:49:22,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 34. [2022-11-20 11:49:22,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.2647058823529411) internal successors, (43), 33 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:22,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 43 transitions. [2022-11-20 11:49:22,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-20 11:49:22,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-20 11:49:22,044 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 43 transitions. [2022-11-20 11:49:22,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-20 11:49:22,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 43 transitions. [2022-11-20 11:49:22,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:22,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:22,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:22,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:22,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:22,046 INFO L748 eck$LassoCheckResult]: Stem: 2657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2665#L367 assume !(main_~length~0#1 < 1); 2659#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2660#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2661#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2666#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2680#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2668#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2669#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2671#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2679#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2678#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2677#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2676#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2675#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2672#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2673#L370-4 main_~j~0#1 := 0; 2687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2664#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2670#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2686#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2685#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2684#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2683#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2682#L378-2 [2022-11-20 11:49:22,046 INFO L750 eck$LassoCheckResult]: Loop: 2682#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2681#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2682#L378-2 [2022-11-20 11:49:22,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,047 INFO L85 PathProgramCache]: Analyzing trace with hash 111424810, now seen corresponding path program 8 times [2022-11-20 11:49:22,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010254845] [2022-11-20 11:49:22,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:22,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,072 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:22,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,072 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2022-11-20 11:49:22,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046404049] [2022-11-20 11:49:22,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,075 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:22,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:22,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,078 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 8 times [2022-11-20 11:49:22,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77036135] [2022-11-20 11:49:22,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:22,235 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:22,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:22,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77036135] [2022-11-20 11:49:22,236 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77036135] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:22,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1993304749] [2022-11-20 11:49:22,236 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:49:22,236 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:22,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:22,242 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:22,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-11-20 11:49:22,325 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:49:22,325 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:22,326 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-20 11:49:22,327 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:22,456 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:22,456 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:22,556 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:22,557 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1993304749] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:22,557 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:22,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 20 [2022-11-20 11:49:22,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234545327] [2022-11-20 11:49:22,557 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:22,600 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:22,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-20 11:49:22,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2022-11-20 11:49:22,601 INFO L87 Difference]: Start difference. First operand 34 states and 43 transitions. cyclomatic complexity: 12 Second operand has 20 states, 20 states have (on average 2.3) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:22,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:22,796 INFO L93 Difference]: Finished difference Result 49 states and 59 transitions. [2022-11-20 11:49:22,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 59 transitions. [2022-11-20 11:49:22,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:22,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 39 states and 49 transitions. [2022-11-20 11:49:22,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 11:49:22,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 11:49:22,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2022-11-20 11:49:22,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:22,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 49 transitions. [2022-11-20 11:49:22,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2022-11-20 11:49:22,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 36. [2022-11-20 11:49:22,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.25) internal successors, (45), 35 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:22,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 45 transitions. [2022-11-20 11:49:22,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-20 11:49:22,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-20 11:49:22,805 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-20 11:49:22,805 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-20 11:49:22,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 45 transitions. [2022-11-20 11:49:22,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:22,806 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:22,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:22,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:22,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:22,808 INFO L748 eck$LassoCheckResult]: Stem: 2945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 2953#L367 assume !(main_~length~0#1 < 1); 2947#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 2948#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 2949#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2954#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2970#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2955#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2956#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2959#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2969#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2966#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 2965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2963#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2964#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 2962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 2960#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 2952#L370-4 main_~j~0#1 := 0; 2951#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2958#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2976#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2975#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2974#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2973#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 2972#L378-2 [2022-11-20 11:49:22,808 INFO L750 eck$LassoCheckResult]: Loop: 2972#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 2971#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 2972#L378-2 [2022-11-20 11:49:22,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,809 INFO L85 PathProgramCache]: Analyzing trace with hash -188031059, now seen corresponding path program 3 times [2022-11-20 11:49:22,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,809 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625811214] [2022-11-20 11:49:22,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:22,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:22,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,840 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2022-11-20 11:49:22,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429021831] [2022-11-20 11:49:22,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,844 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:22,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:22,846 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:22,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:22,847 INFO L85 PathProgramCache]: Analyzing trace with hash -309219920, now seen corresponding path program 3 times [2022-11-20 11:49:22,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:22,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228559072] [2022-11-20 11:49:22,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:22,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:22,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:23,248 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:23,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:23,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228559072] [2022-11-20 11:49:23,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228559072] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:23,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1065168335] [2022-11-20 11:49:23,249 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:49:23,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:23,249 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:23,257 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:23,261 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-20 11:49:23,371 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-20 11:49:23,371 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:23,373 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-20 11:49:23,375 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:23,451 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:23,568 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 11:49:23,570 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-20 11:49:23,645 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 11:49:23,645 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-20 11:49:24,257 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-20 11:49:24,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-20 11:49:24,274 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 9 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:24,275 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:25,028 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:49:25,032 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:49:25,102 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 6 proven. 39 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-20 11:49:25,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1065168335] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:25,103 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:25,103 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 14] total 37 [2022-11-20 11:49:25,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151490751] [2022-11-20 11:49:25,104 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:25,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:25,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 11:49:25,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1216, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 11:49:25,150 INFO L87 Difference]: Start difference. First operand 36 states and 45 transitions. cyclomatic complexity: 12 Second operand has 38 states, 37 states have (on average 1.864864864864865) internal successors, (69), 38 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:26,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:26,059 INFO L93 Difference]: Finished difference Result 73 states and 87 transitions. [2022-11-20 11:49:26,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 87 transitions. [2022-11-20 11:49:26,060 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6 [2022-11-20 11:49:26,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 87 transitions. [2022-11-20 11:49:26,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-11-20 11:49:26,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-11-20 11:49:26,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 87 transitions. [2022-11-20 11:49:26,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:49:26,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 87 transitions. [2022-11-20 11:49:26,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 87 transitions. [2022-11-20 11:49:26,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 43. [2022-11-20 11:49:26,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:26,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-20 11:49:26,064 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 11:49:26,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-20 11:49:26,067 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 11:49:26,067 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-20 11:49:26,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-20 11:49:26,067 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:26,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:26,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:26,070 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:26,070 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:26,070 INFO L748 eck$LassoCheckResult]: Stem: 3321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3327#L367 assume !(main_~length~0#1 < 1); 3319#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3320#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3328#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3334#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3343#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3340#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3330#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3331#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3335#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3324#L370-4 main_~j~0#1 := 0; 3325#L378-2 [2022-11-20 11:49:26,070 INFO L750 eck$LassoCheckResult]: Loop: 3325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3326#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3325#L378-2 [2022-11-20 11:49:26,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:26,071 INFO L85 PathProgramCache]: Analyzing trace with hash 438748702, now seen corresponding path program 3 times [2022-11-20 11:49:26,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:26,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916274810] [2022-11-20 11:49:26,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:26,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:26,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:26,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,091 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:26,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:26,092 INFO L85 PathProgramCache]: Analyzing trace with hash 2310, now seen corresponding path program 1 times [2022-11-20 11:49:26,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:26,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1646365550] [2022-11-20 11:49:26,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:26,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:26,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:26,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:26,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:26,098 INFO L85 PathProgramCache]: Analyzing trace with hash 730708963, now seen corresponding path program 4 times [2022-11-20 11:49:26,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:26,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799464956] [2022-11-20 11:49:26,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:26,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:26,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:26,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:26,118 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:27,876 INFO L210 LassoAnalysis]: Preferences: [2022-11-20 11:49:27,876 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-11-20 11:49:27,876 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-11-20 11:49:27,876 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-11-20 11:49:27,877 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-11-20 11:49:27,877 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:27,877 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-11-20 11:49:27,877 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-11-20 11:49:27,877 INFO L133 ssoRankerPreferences]: Filename of dumped script: array13_alloca.i_Iteration18_Lasso [2022-11-20 11:49:27,877 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-11-20 11:49:27,877 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-11-20 11:49:27,879 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:27,885 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:27,887 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:27,890 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:27,892 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:27,895 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,238 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,241 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,243 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,245 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,247 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,251 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-11-20 11:49:28,579 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-11-20 11:49:28,586 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-11-20 11:49:28,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,587 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,590 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-11-20 11:49:28,598 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,607 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,608 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,608 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,608 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,609 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,609 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,634 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,644 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,645 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,646 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,666 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,678 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,678 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:28,678 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,678 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,679 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,679 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:28,679 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:28,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-11-20 11:49:28,697 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,707 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,707 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,708 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-11-20 11:49:28,719 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,729 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,729 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,729 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,730 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,731 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,731 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,738 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,742 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,744 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,744 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,745 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,748 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-11-20 11:49:28,758 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,758 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:28,758 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,758 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,758 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,758 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:28,759 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:28,760 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,763 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,764 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,766 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-11-20 11:49:28,766 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,776 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,776 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-11-20 11:49:28,777 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,777 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,777 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,777 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-11-20 11:49:28,777 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-11-20 11:49:28,779 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,781 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,782 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,782 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,783 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,786 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-11-20 11:49:28,786 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,796 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,797 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,797 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,797 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,799 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,800 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,807 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,811 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,813 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,823 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,836 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,836 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,836 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,836 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,839 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-11-20 11:49:28,844 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,844 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,850 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,852 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,854 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-11-20 11:49:28,857 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,868 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,868 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,868 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,868 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,870 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,871 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,876 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,879 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,880 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,881 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-11-20 11:49:28,884 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,893 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,894 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,894 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,894 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,896 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,896 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,934 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,938 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,939 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,939 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,940 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,947 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:28,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-11-20 11:49:28,959 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:28,959 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:28,959 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:28,959 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:28,961 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:28,961 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:28,975 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:28,987 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:28,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:28,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:28,989 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:28,998 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:29,011 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:29,011 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:29,011 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:29,011 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:29,013 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:29,013 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:29,014 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-11-20 11:49:29,030 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-11-20 11:49:29,034 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:29,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:29,035 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:29,036 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:29,040 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-11-20 11:49:29,053 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-11-20 11:49:29,053 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-11-20 11:49:29,053 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-11-20 11:49:29,053 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-11-20 11:49:29,055 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-11-20 11:49:29,060 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-11-20 11:49:29,060 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-11-20 11:49:29,082 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-11-20 11:49:29,114 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-11-20 11:49:29,114 INFO L444 ModelExtractionUtils]: 8 out of 25 variables were initially zero. Simplification set additionally 13 variables to zero. [2022-11-20 11:49:29,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-20 11:49:29,114 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:29,118 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-20 11:49:29,121 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-11-20 11:49:29,126 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2022-11-20 11:49:29,142 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-11-20 11:49:29,142 INFO L513 LassoAnalysis]: Proved termination. [2022-11-20 11:49:29,142 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, ULTIMATE.start_main_~j~0#1, v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2) = -1*ULTIMATE.start_main_~arr~0#1.offset - 2*ULTIMATE.start_main_~j~0#1 + 1*v_rep(select #length ULTIMATE.start_main_#t~malloc206#1.base)_2 Supporting invariants [] [2022-11-20 11:49:29,152 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:29,175 INFO L156 tatePredicateManager]: 7 out of 8 supporting invariants were superfluous and have been removed [2022-11-20 11:49:29,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:29,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:29,235 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-20 11:49:29,235 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:29,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:29,310 INFO L263 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-20 11:49:29,311 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:29,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:29,336 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.2 stem predicates 2 loop predicates [2022-11-20 11:49:29,336 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:29,369 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 43 states and 55 transitions. cyclomatic complexity: 17. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 53 states and 68 transitions. Complement of second has 6 states. [2022-11-20 11:49:29,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 2 stem states 1 non-accepting loop states 1 accepting loop states [2022-11-20 11:49:29,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 4 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:29,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 13 transitions. [2022-11-20 11:49:29,370 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 2 letters. [2022-11-20 11:49:29,371 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:29,371 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 24 letters. Loop has 2 letters. [2022-11-20 11:49:29,371 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:29,371 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 13 transitions. Stem has 22 letters. Loop has 4 letters. [2022-11-20 11:49:29,371 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-11-20 11:49:29,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 68 transitions. [2022-11-20 11:49:29,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:29,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 44 states and 56 transitions. [2022-11-20 11:49:29,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-11-20 11:49:29,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:49:29,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2022-11-20 11:49:29,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:29,373 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 56 transitions. [2022-11-20 11:49:29,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2022-11-20 11:49:29,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2022-11-20 11:49:29,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2790697674418605) internal successors, (55), 42 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:29,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 55 transitions. [2022-11-20 11:49:29,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 11:49:29,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 43 states and 55 transitions. [2022-11-20 11:49:29,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-20 11:49:29,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 55 transitions. [2022-11-20 11:49:29,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:29,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:29,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:29,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:29,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:29,376 INFO L748 eck$LassoCheckResult]: Stem: 3546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3557#L367 assume !(main_~length~0#1 < 1); 3548#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3549#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3550#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3558#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3561#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3559#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3560#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3587#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3586#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3585#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3584#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3583#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3581#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3580#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3579#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3576#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3574#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3573#L370-4 main_~j~0#1 := 0; 3572#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3553#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3554#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3562#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3570#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3569#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3568#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3564#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3563#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3551#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-20 11:49:29,376 INFO L750 eck$LassoCheckResult]: Loop: 3552#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3565#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3552#L378-2 [2022-11-20 11:49:29,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:29,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 9 times [2022-11-20 11:49:29,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:29,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920262722] [2022-11-20 11:49:29,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:29,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:29,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:29,695 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:29,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:29,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920262722] [2022-11-20 11:49:29,696 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920262722] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:29,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87593957] [2022-11-20 11:49:29,696 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:49:29,696 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:29,696 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:29,698 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:29,726 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-11-20 11:49:29,847 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-11-20 11:49:29,848 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:29,849 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-20 11:49:29,851 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:29,952 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:30,460 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2022-11-20 11:49:30,463 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 11:49:30,464 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 11:49:30,468 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 16 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:30,468 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:31,009 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:49:31,013 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:49:31,113 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 12 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:31,113 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87593957] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:31,114 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:31,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2022-11-20 11:49:31,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850110279] [2022-11-20 11:49:31,114 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:31,114 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:31,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:31,115 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2022-11-20 11:49:31,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:31,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814460031] [2022-11-20 11:49:31,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:31,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:31,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:31,118 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:31,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:31,120 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:31,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:31,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-20 11:49:31,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=1288, Unknown=0, NotChecked=0, Total=1482 [2022-11-20 11:49:31,169 INFO L87 Difference]: Start difference. First operand 43 states and 55 transitions. cyclomatic complexity: 17 Second operand has 39 states, 38 states have (on average 1.9210526315789473) internal successors, (73), 39 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:31,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:31,964 INFO L93 Difference]: Finished difference Result 60 states and 74 transitions. [2022-11-20 11:49:31,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 74 transitions. [2022-11-20 11:49:31,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:31,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 47 states and 59 transitions. [2022-11-20 11:49:31,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:49:31,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:49:31,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 59 transitions. [2022-11-20 11:49:31,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:31,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 11:49:31,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 59 transitions. [2022-11-20 11:49:31,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-11-20 11:49:31,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.2666666666666666) internal successors, (57), 44 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:31,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 57 transitions. [2022-11-20 11:49:31,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-20 11:49:31,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-20 11:49:31,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 57 transitions. [2022-11-20 11:49:31,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-20 11:49:31,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 57 transitions. [2022-11-20 11:49:31,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:31,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:31,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:31,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:31,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:31,970 INFO L748 eck$LassoCheckResult]: Stem: 3925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 3936#L367 assume !(main_~length~0#1 < 1); 3927#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 3928#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 3929#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3937#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3969#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3938#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3939#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3941#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3967#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3966#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3965#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3964#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3963#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3962#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3961#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3942#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3943#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 3958#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 3956#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 3952#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 3934#L370-4 main_~j~0#1 := 0; 3935#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3932#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3933#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3948#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3946#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 3945#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3930#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-20 11:49:31,970 INFO L750 eck$LassoCheckResult]: Loop: 3931#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 3944#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 3931#L378-2 [2022-11-20 11:49:31,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:31,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1236423398, now seen corresponding path program 4 times [2022-11-20 11:49:31,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:31,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29772064] [2022-11-20 11:49:31,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:31,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:31,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:32,568 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:32,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:32,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29772064] [2022-11-20 11:49:32,568 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29772064] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:32,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1892611021] [2022-11-20 11:49:32,569 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:49:32,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:32,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:32,571 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:32,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-20 11:49:32,665 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:49:32,665 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:32,667 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-20 11:49:32,669 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:32,704 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:32,780 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:32,780 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:32,798 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:32,799 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:32,841 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:32,842 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:32,947 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:32,949 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:32,950 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:33,186 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:33,189 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:33,232 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 61 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 11:49:33,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1892611021] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:33,233 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:33,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 23 [2022-11-20 11:49:33,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539051216] [2022-11-20 11:49:33,233 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:33,234 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:33,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:33,234 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2022-11-20 11:49:33,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:33,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899902621] [2022-11-20 11:49:33,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:33,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:33,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:33,238 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:33,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:33,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:33,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:33,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-20 11:49:33,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=478, Unknown=0, NotChecked=0, Total=552 [2022-11-20 11:49:33,289 INFO L87 Difference]: Start difference. First operand 45 states and 57 transitions. cyclomatic complexity: 17 Second operand has 24 states, 23 states have (on average 2.217391304347826) internal successors, (51), 24 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:33,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:33,661 INFO L93 Difference]: Finished difference Result 54 states and 66 transitions. [2022-11-20 11:49:33,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 66 transitions. [2022-11-20 11:49:33,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:33,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 65 transitions. [2022-11-20 11:49:33,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:49:33,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:49:33,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 65 transitions. [2022-11-20 11:49:33,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:33,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 65 transitions. [2022-11-20 11:49:33,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 65 transitions. [2022-11-20 11:49:33,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 40. [2022-11-20 11:49:33,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.25) internal successors, (50), 39 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:33,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2022-11-20 11:49:33,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-20 11:49:33,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-20 11:49:33,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 40 states and 50 transitions. [2022-11-20 11:49:33,666 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-20 11:49:33,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 50 transitions. [2022-11-20 11:49:33,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:33,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:33,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:33,667 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:33,667 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:33,668 INFO L748 eck$LassoCheckResult]: Stem: 4253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4264#L367 assume !(main_~length~0#1 < 1); 4255#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4256#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4257#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4265#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4270#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4292#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4291#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4290#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4289#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4288#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4287#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4285#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4284#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4283#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4282#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4280#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4281#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4279#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4275#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4262#L370-4 main_~j~0#1 := 0; 4263#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4268#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4269#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4260#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4261#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4278#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4273#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4272#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4258#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-20 11:49:33,668 INFO L750 eck$LassoCheckResult]: Loop: 4259#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4274#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4259#L378-2 [2022-11-20 11:49:33,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:33,668 INFO L85 PathProgramCache]: Analyzing trace with hash -1503052245, now seen corresponding path program 5 times [2022-11-20 11:49:33,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:33,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086152629] [2022-11-20 11:49:33,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:33,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:33,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:34,146 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:34,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:34,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086152629] [2022-11-20 11:49:34,147 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086152629] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:34,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [272204241] [2022-11-20 11:49:34,147 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:49:34,148 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:34,148 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:34,152 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:34,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-20 11:49:34,299 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-11-20 11:49:34,300 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:34,302 INFO L263 TraceCheckSpWp]: Trace formula consists of 180 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-20 11:49:34,303 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:34,482 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:34,554 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:34,554 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:34,883 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:49:34,890 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:49:34,890 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:49:34,917 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:34,917 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:35,547 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-20 11:49:35,552 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 78 [2022-11-20 11:49:35,634 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:35,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [272204241] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:35,635 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:35,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 16] total 40 [2022-11-20 11:49:35,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703410816] [2022-11-20 11:49:35,635 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:35,636 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:35,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:35,636 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2022-11-20 11:49:35,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:35,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793495451] [2022-11-20 11:49:35,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:35,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:35,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:35,640 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:35,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:35,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:35,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:35,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 11:49:35,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=1492, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 11:49:35,692 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. cyclomatic complexity: 14 Second operand has 41 states, 40 states have (on average 2.075) internal successors, (83), 41 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:36,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:36,618 INFO L93 Difference]: Finished difference Result 62 states and 77 transitions. [2022-11-20 11:49:36,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 77 transitions. [2022-11-20 11:49:36,618 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:36,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 76 transitions. [2022-11-20 11:49:36,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-20 11:49:36,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-20 11:49:36,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 76 transitions. [2022-11-20 11:49:36,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:36,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 76 transitions. [2022-11-20 11:49:36,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 76 transitions. [2022-11-20 11:49:36,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 47. [2022-11-20 11:49:36,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2553191489361701) internal successors, (59), 46 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:36,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 59 transitions. [2022-11-20 11:49:36,622 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 11:49:36,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-20 11:49:36,627 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 59 transitions. [2022-11-20 11:49:36,627 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-20 11:49:36,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 59 transitions. [2022-11-20 11:49:36,628 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:36,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:36,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:36,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:36,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:36,628 INFO L748 eck$LassoCheckResult]: Stem: 4622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4633#L367 assume !(main_~length~0#1 < 1); 4624#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4625#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4626#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4634#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4640#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4636#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4657#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4656#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4655#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4654#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4653#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4652#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4651#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4650#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4649#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4647#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 4648#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 4668#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 4667#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4666#L370-4 main_~j~0#1 := 0; 4637#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4629#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4630#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4664#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4663#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4662#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4661#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4659#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4627#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-20 11:49:36,628 INFO L750 eck$LassoCheckResult]: Loop: 4628#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4660#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4628#L378-2 [2022-11-20 11:49:36,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:36,629 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 10 times [2022-11-20 11:49:36,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:36,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621098571] [2022-11-20 11:49:36,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:36,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:36,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:37,050 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:37,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:37,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621098571] [2022-11-20 11:49:37,051 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621098571] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:37,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1329573784] [2022-11-20 11:49:37,051 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:49:37,051 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:37,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:37,057 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:37,074 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-11-20 11:49:37,155 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:49:37,156 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:37,157 INFO L263 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-20 11:49:37,159 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:37,203 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:37,298 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:49:37,299 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:49:37,470 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:37,473 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:37,473 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:37,658 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:37,661 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:37,719 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:37,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1329573784] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:37,720 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:37,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-11-20 11:49:37,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326827032] [2022-11-20 11:49:37,720 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:37,720 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:37,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:37,721 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2022-11-20 11:49:37,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:37,721 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548451060] [2022-11-20 11:49:37,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:37,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:37,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:37,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:37,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:37,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:37,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:37,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-20 11:49:37,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=575, Unknown=0, NotChecked=0, Total=650 [2022-11-20 11:49:37,779 INFO L87 Difference]: Start difference. First operand 47 states and 59 transitions. cyclomatic complexity: 17 Second operand has 26 states, 25 states have (on average 2.12) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:38,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:38,119 INFO L93 Difference]: Finished difference Result 84 states and 102 transitions. [2022-11-20 11:49:38,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 102 transitions. [2022-11-20 11:49:38,120 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:49:38,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 101 transitions. [2022-11-20 11:49:38,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-20 11:49:38,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-20 11:49:38,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 101 transitions. [2022-11-20 11:49:38,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:38,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83 states and 101 transitions. [2022-11-20 11:49:38,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 101 transitions. [2022-11-20 11:49:38,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 50. [2022-11-20 11:49:38,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.28) internal successors, (64), 49 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:38,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 64 transitions. [2022-11-20 11:49:38,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-20 11:49:38,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-20 11:49:38,126 INFO L428 stractBuchiCegarLoop]: Abstraction has 50 states and 64 transitions. [2022-11-20 11:49:38,126 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-20 11:49:38,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 64 transitions. [2022-11-20 11:49:38,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:38,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:38,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:38,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:38,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:38,128 INFO L748 eck$LassoCheckResult]: Stem: 4988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 4999#L367 assume !(main_~length~0#1 < 1); 4990#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 4991#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 4992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5000#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5035#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5032#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5029#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5028#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5026#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5003#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5002#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5004#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 4993#L370-4 main_~j~0#1 := 0; 4994#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4997#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 4998#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5006#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5016#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5015#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5014#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5013#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5012#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5010#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5009#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 4995#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-20 11:49:38,128 INFO L750 eck$LassoCheckResult]: Loop: 4996#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5011#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 4996#L378-2 [2022-11-20 11:49:38,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:38,129 INFO L85 PathProgramCache]: Analyzing trace with hash -1324192720, now seen corresponding path program 6 times [2022-11-20 11:49:38,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:38,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096447031] [2022-11-20 11:49:38,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:38,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:38,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:38,555 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:38,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:38,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096447031] [2022-11-20 11:49:38,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096447031] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:38,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [389332629] [2022-11-20 11:49:38,556 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:49:38,556 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:38,556 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:38,562 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:38,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-11-20 11:49:38,715 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-20 11:49:38,715 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:38,717 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-20 11:49:38,718 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:38,938 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 11:49:39,281 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:39,284 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:39,284 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:39,415 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:39,418 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:39,480 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:39,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [389332629] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:39,480 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:39,480 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 16] total 34 [2022-11-20 11:49:39,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928512691] [2022-11-20 11:49:39,481 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:39,481 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:39,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:39,482 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2022-11-20 11:49:39,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:39,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496592467] [2022-11-20 11:49:39,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:39,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:39,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:39,485 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:39,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:39,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:39,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:39,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-20 11:49:39,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=1066, Unknown=0, NotChecked=0, Total=1190 [2022-11-20 11:49:39,538 INFO L87 Difference]: Start difference. First operand 50 states and 64 transitions. cyclomatic complexity: 19 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:40,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:40,186 INFO L93 Difference]: Finished difference Result 105 states and 133 transitions. [2022-11-20 11:49:40,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 133 transitions. [2022-11-20 11:49:40,187 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 14 [2022-11-20 11:49:40,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 132 transitions. [2022-11-20 11:49:40,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2022-11-20 11:49:40,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2022-11-20 11:49:40,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 132 transitions. [2022-11-20 11:49:40,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:40,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104 states and 132 transitions. [2022-11-20 11:49:40,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 132 transitions. [2022-11-20 11:49:40,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 89. [2022-11-20 11:49:40,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.2921348314606742) internal successors, (115), 88 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:40,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 115 transitions. [2022-11-20 11:49:40,191 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89 states and 115 transitions. [2022-11-20 11:49:40,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-11-20 11:49:40,198 INFO L428 stractBuchiCegarLoop]: Abstraction has 89 states and 115 transitions. [2022-11-20 11:49:40,198 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-20 11:49:40,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 115 transitions. [2022-11-20 11:49:40,199 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-20 11:49:40,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:40,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:40,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:40,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:40,200 INFO L748 eck$LassoCheckResult]: Stem: 5405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 5416#L367 assume !(main_~length~0#1 < 1); 5407#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 5408#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 5409#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5417#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5421#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5445#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5444#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5443#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5442#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5441#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5440#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5439#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5438#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5437#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5436#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5434#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5433#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5431#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5432#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 5468#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5467#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5464#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 5466#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 5476#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 5475#L370-4 main_~j~0#1 := 0; 5474#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5472#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5470#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5469#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5448#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5453#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5450#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 5451#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5452#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5411#L378-2 [2022-11-20 11:49:40,200 INFO L750 eck$LassoCheckResult]: Loop: 5411#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 5446#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 5411#L378-2 [2022-11-20 11:49:40,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:40,200 INFO L85 PathProgramCache]: Analyzing trace with hash -711621579, now seen corresponding path program 7 times [2022-11-20 11:49:40,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:40,200 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982228863] [2022-11-20 11:49:40,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:40,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:40,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:40,750 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:40,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:40,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982228863] [2022-11-20 11:49:40,750 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982228863] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:40,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [891779160] [2022-11-20 11:49:40,750 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:49:40,750 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:40,750 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:40,752 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:40,757 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-20 11:49:40,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:40,869 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-20 11:49:40,871 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:41,054 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:41,171 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:41,173 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:41,229 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:41,230 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:41,243 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:49:41,496 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:49:41,499 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:41,499 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:41,891 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-20 11:49:41,895 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 61 [2022-11-20 11:49:41,955 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:41,956 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [891779160] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:41,956 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:41,956 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18, 18] total 38 [2022-11-20 11:49:41,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13728512] [2022-11-20 11:49:41,957 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:41,957 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:41,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:41,958 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2022-11-20 11:49:41,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:41,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037842231] [2022-11-20 11:49:41,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:41,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:41,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:41,966 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:41,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:41,970 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:42,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:42,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-20 11:49:42,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=1320, Unknown=0, NotChecked=0, Total=1482 [2022-11-20 11:49:42,022 INFO L87 Difference]: Start difference. First operand 89 states and 115 transitions. cyclomatic complexity: 34 Second operand has 39 states, 38 states have (on average 2.1315789473684212) internal successors, (81), 39 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:43,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:43,163 INFO L93 Difference]: Finished difference Result 234 states and 286 transitions. [2022-11-20 11:49:43,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234 states and 286 transitions. [2022-11-20 11:49:43,165 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 18 [2022-11-20 11:49:43,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234 states to 231 states and 283 transitions. [2022-11-20 11:49:43,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61 [2022-11-20 11:49:43,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61 [2022-11-20 11:49:43,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231 states and 283 transitions. [2022-11-20 11:49:43,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:43,168 INFO L218 hiAutomatonCegarLoop]: Abstraction has 231 states and 283 transitions. [2022-11-20 11:49:43,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states and 283 transitions. [2022-11-20 11:49:43,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 103. [2022-11-20 11:49:43,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.3398058252427185) internal successors, (138), 102 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:43,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 138 transitions. [2022-11-20 11:49:43,173 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 138 transitions. [2022-11-20 11:49:43,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2022-11-20 11:49:43,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 138 transitions. [2022-11-20 11:49:43,174 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-11-20 11:49:43,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 138 transitions. [2022-11-20 11:49:43,175 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-20 11:49:43,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:43,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:43,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:43,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:43,176 INFO L748 eck$LassoCheckResult]: Stem: 6029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6040#L367 assume !(main_~length~0#1 < 1); 6031#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6032#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6041#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6101#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6100#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6099#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6098#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6097#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6096#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6095#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6094#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6093#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6092#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6090#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6087#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6088#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6104#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6048#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6073#L370-4 main_~j~0#1 := 0; 6118#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6117#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6038#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6109#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6108#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6107#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6106#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6052#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6057#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6055#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6058#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6037#L378-2 [2022-11-20 11:49:43,177 INFO L750 eck$LassoCheckResult]: Loop: 6037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6054#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6037#L378-2 [2022-11-20 11:49:43,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:43,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1238881035, now seen corresponding path program 8 times [2022-11-20 11:49:43,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:43,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794632861] [2022-11-20 11:49:43,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:43,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:43,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:43,414 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:43,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:43,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794632861] [2022-11-20 11:49:43,414 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794632861] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:43,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2413572] [2022-11-20 11:49:43,414 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:49:43,415 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:43,415 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:43,426 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:43,442 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-11-20 11:49:43,548 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:49:43,549 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:43,550 INFO L263 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-20 11:49:43,552 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:43,766 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:43,767 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:43,930 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:43,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2413572] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:43,931 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:43,931 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 26 [2022-11-20 11:49:43,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667719562] [2022-11-20 11:49:43,931 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:43,932 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:43,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:43,932 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2022-11-20 11:49:43,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:43,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013732818] [2022-11-20 11:49:43,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:43,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:43,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:43,936 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:43,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:43,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:43,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:43,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-20 11:49:43,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=493, Unknown=0, NotChecked=0, Total=650 [2022-11-20 11:49:43,996 INFO L87 Difference]: Start difference. First operand 103 states and 138 transitions. cyclomatic complexity: 43 Second operand has 26 states, 26 states have (on average 2.3076923076923075) internal successors, (60), 26 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:44,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:44,200 INFO L93 Difference]: Finished difference Result 129 states and 167 transitions. [2022-11-20 11:49:44,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 167 transitions. [2022-11-20 11:49:44,204 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-20 11:49:44,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 115 states and 151 transitions. [2022-11-20 11:49:44,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2022-11-20 11:49:44,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-11-20 11:49:44,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 151 transitions. [2022-11-20 11:49:44,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:44,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 151 transitions. [2022-11-20 11:49:44,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 151 transitions. [2022-11-20 11:49:44,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 107. [2022-11-20 11:49:44,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107 states, 107 states have (on average 1.3177570093457944) internal successors, (141), 106 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:44,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 141 transitions. [2022-11-20 11:49:44,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 107 states and 141 transitions. [2022-11-20 11:49:44,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-20 11:49:44,216 INFO L428 stractBuchiCegarLoop]: Abstraction has 107 states and 141 transitions. [2022-11-20 11:49:44,216 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-11-20 11:49:44,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states and 141 transitions. [2022-11-20 11:49:44,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-20 11:49:44,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:44,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:44,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:44,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:44,219 INFO L748 eck$LassoCheckResult]: Stem: 6534#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 6535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 6545#L367 assume !(main_~length~0#1 < 1); 6536#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 6537#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 6538#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6546#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6624#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6623#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6622#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6621#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6620#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6619#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6618#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6617#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6616#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6615#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6610#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6611#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6630#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6549#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 6551#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6547#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6548#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 6597#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 6584#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 6582#L370-4 main_~j~0#1 := 0; 6579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6552#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6575#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6573#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6569#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6567#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6557#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6564#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6559#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 6560#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6563#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6542#L378-2 [2022-11-20 11:49:44,219 INFO L750 eck$LassoCheckResult]: Loop: 6542#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 6631#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 6542#L378-2 [2022-11-20 11:49:44,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:44,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1187388804, now seen corresponding path program 9 times [2022-11-20 11:49:44,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:44,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856818319] [2022-11-20 11:49:44,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:44,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:44,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:44,872 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:44,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:44,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856818319] [2022-11-20 11:49:44,873 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856818319] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:44,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1732666952] [2022-11-20 11:49:44,873 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:49:44,873 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:44,873 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:44,882 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:44,907 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-11-20 11:49:45,146 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-11-20 11:49:45,147 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:45,148 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-20 11:49:45,150 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:45,202 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:45,306 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:49:45,306 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:49:45,332 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:49:45,332 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:49:45,536 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:45,538 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:45,538 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:45,742 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:45,745 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:45,808 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:45,808 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1732666952] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:45,808 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:45,808 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-11-20 11:49:45,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235603525] [2022-11-20 11:49:45,809 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:45,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:45,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:45,809 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2022-11-20 11:49:45,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:45,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448292119] [2022-11-20 11:49:45,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:45,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:45,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:45,813 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:45,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:45,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:45,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:45,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-20 11:49:45,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=729, Unknown=0, NotChecked=0, Total=812 [2022-11-20 11:49:45,863 INFO L87 Difference]: Start difference. First operand 107 states and 141 transitions. cyclomatic complexity: 42 Second operand has 29 states, 28 states have (on average 2.1785714285714284) internal successors, (61), 29 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:46,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:46,510 INFO L93 Difference]: Finished difference Result 222 states and 283 transitions. [2022-11-20 11:49:46,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 283 transitions. [2022-11-20 11:49:46,512 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36 [2022-11-20 11:49:46,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 221 states and 282 transitions. [2022-11-20 11:49:46,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2022-11-20 11:49:46,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2022-11-20 11:49:46,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 282 transitions. [2022-11-20 11:49:46,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:46,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 282 transitions. [2022-11-20 11:49:46,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 282 transitions. [2022-11-20 11:49:46,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 121. [2022-11-20 11:49:46,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121 states, 121 states have (on average 1.3553719008264462) internal successors, (164), 120 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:46,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 164 transitions. [2022-11-20 11:49:46,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121 states and 164 transitions. [2022-11-20 11:49:46,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-20 11:49:46,525 INFO L428 stractBuchiCegarLoop]: Abstraction has 121 states and 164 transitions. [2022-11-20 11:49:46,525 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-11-20 11:49:46,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121 states and 164 transitions. [2022-11-20 11:49:46,526 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-11-20 11:49:46,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:46,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:46,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:46,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:46,527 INFO L748 eck$LassoCheckResult]: Stem: 7145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7156#L367 assume !(main_~length~0#1 < 1); 7147#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7148#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7149#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7157#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7191#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7190#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7189#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7188#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7187#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7186#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7184#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7183#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7182#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7181#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7179#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7180#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7192#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7170#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7171#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7227#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7223#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7224#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7244#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7212#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7218#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7243#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7242#L370-4 main_~j~0#1 := 0; 7241#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7237#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7196#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7201#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7198#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7199#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7200#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7153#L378-2 [2022-11-20 11:49:46,527 INFO L750 eck$LassoCheckResult]: Loop: 7153#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7256#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7153#L378-2 [2022-11-20 11:49:46,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:46,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1946926163, now seen corresponding path program 10 times [2022-11-20 11:49:46,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:46,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094671553] [2022-11-20 11:49:46,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:46,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:46,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:47,229 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 3 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:47,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:47,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094671553] [2022-11-20 11:49:47,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094671553] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:47,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1479843912] [2022-11-20 11:49:47,229 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:49:47,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:47,230 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:47,233 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:47,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-11-20 11:49:47,374 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:49:47,374 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:47,376 INFO L263 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-20 11:49:47,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:47,426 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:47,522 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:47,523 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:47,543 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:47,543 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:47,577 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:47,577 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:47,599 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:47,600 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:47,660 INFO L321 Elim1Store]: treesize reduction 23, result has 28.1 percent of original size [2022-11-20 11:49:47,661 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:47,836 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:49:47,840 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 5 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:47,840 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:48,226 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:49:48,229 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:49:48,289 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 2 proven. 105 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-20 11:49:48,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1479843912] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:48,289 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:48,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 17] total 27 [2022-11-20 11:49:48,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261208269] [2022-11-20 11:49:48,290 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:48,290 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:48,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:48,291 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2022-11-20 11:49:48,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:48,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467450834] [2022-11-20 11:49:48,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:48,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:48,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:48,295 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:48,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:48,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:48,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:48,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-20 11:49:48,355 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=666, Unknown=0, NotChecked=0, Total=756 [2022-11-20 11:49:48,355 INFO L87 Difference]: Start difference. First operand 121 states and 164 transitions. cyclomatic complexity: 51 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:48,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:48,848 INFO L93 Difference]: Finished difference Result 130 states and 167 transitions. [2022-11-20 11:49:48,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 167 transitions. [2022-11-20 11:49:48,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:48,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 128 states and 165 transitions. [2022-11-20 11:49:48,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2022-11-20 11:49:48,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-11-20 11:49:48,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 165 transitions. [2022-11-20 11:49:48,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:48,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 165 transitions. [2022-11-20 11:49:48,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 165 transitions. [2022-11-20 11:49:48,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 64. [2022-11-20 11:49:48,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.296875) internal successors, (83), 63 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:48,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 83 transitions. [2022-11-20 11:49:48,855 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64 states and 83 transitions. [2022-11-20 11:49:48,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-11-20 11:49:48,856 INFO L428 stractBuchiCegarLoop]: Abstraction has 64 states and 83 transitions. [2022-11-20 11:49:48,856 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-11-20 11:49:48,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 83 transitions. [2022-11-20 11:49:48,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:49:48,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:48,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:48,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:48,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:49:48,858 INFO L748 eck$LassoCheckResult]: Stem: 7679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 7690#L367 assume !(main_~length~0#1 < 1); 7681#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 7682#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 7683#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7691#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7735#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7733#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7730#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7729#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7728#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7725#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7724#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7722#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7721#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7720#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 7719#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 7699#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 7700#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 7684#L370-4 main_~j~0#1 := 0; 7685#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7713#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7698#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7688#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7712#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7710#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7706#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7705#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7704#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7702#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 7701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7686#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7687#L378-2 [2022-11-20 11:49:48,858 INFO L750 eck$LassoCheckResult]: Loop: 7687#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 7703#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 7687#L378-2 [2022-11-20 11:49:48,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:48,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1036183171, now seen corresponding path program 11 times [2022-11-20 11:49:48,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:48,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978275750] [2022-11-20 11:49:48,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:48,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:48,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:49,431 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:49,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:49,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978275750] [2022-11-20 11:49:49,432 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978275750] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:49,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [341532274] [2022-11-20 11:49:49,432 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:49:49,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:49,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:49,436 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:49,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-11-20 11:49:49,596 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2022-11-20 11:49:49,596 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:49,598 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-20 11:49:49,600 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:49,862 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 11:49:50,432 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:49:50,434 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:49:50,435 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:49:50,439 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:50,439 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:50,663 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:49:50,666 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:49:50,739 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:50,740 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [341532274] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:50,740 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:50,740 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 19] total 40 [2022-11-20 11:49:50,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210759517] [2022-11-20 11:49:50,741 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:50,741 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:50,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:50,741 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2022-11-20 11:49:50,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:50,742 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138631942] [2022-11-20 11:49:50,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:50,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:50,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:50,745 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:50,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:50,748 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:50,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:50,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 11:49:50,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=1488, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 11:49:50,804 INFO L87 Difference]: Start difference. First operand 64 states and 83 transitions. cyclomatic complexity: 24 Second operand has 41 states, 40 states have (on average 2.15) internal successors, (86), 41 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:51,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:49:51,645 INFO L93 Difference]: Finished difference Result 121 states and 153 transitions. [2022-11-20 11:49:51,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 153 transitions. [2022-11-20 11:49:51,646 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17 [2022-11-20 11:49:51,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 120 states and 152 transitions. [2022-11-20 11:49:51,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2022-11-20 11:49:51,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36 [2022-11-20 11:49:51,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 152 transitions. [2022-11-20 11:49:51,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:49:51,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 152 transitions. [2022-11-20 11:49:51,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 152 transitions. [2022-11-20 11:49:51,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 103. [2022-11-20 11:49:51,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.2912621359223302) internal successors, (133), 102 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:49:51,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 133 transitions. [2022-11-20 11:49:51,651 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-20 11:49:51,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 11:49:51,652 INFO L428 stractBuchiCegarLoop]: Abstraction has 103 states and 133 transitions. [2022-11-20 11:49:51,652 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-11-20 11:49:51,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 133 transitions. [2022-11-20 11:49:51,653 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:49:51,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:49:51,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:49:51,653 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:49:51,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:49:51,654 INFO L748 eck$LassoCheckResult]: Stem: 8162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8173#L367 assume !(main_~length~0#1 < 1); 8164#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8165#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8166#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8174#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8177#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8207#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8206#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8205#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8204#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8203#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8202#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8201#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8200#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8198#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8197#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8195#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8193#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8179#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8175#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8176#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8234#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8232#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8231#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8230#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8228#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8227#L370-4 main_~j~0#1 := 0; 8226#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8225#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8224#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8223#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8222#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8221#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8220#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8219#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8218#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8217#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8211#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8254#L378-2 [2022-11-20 11:49:51,654 INFO L750 eck$LassoCheckResult]: Loop: 8254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8256#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8257#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8258#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8254#L378-2 [2022-11-20 11:49:51,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:51,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1469153072, now seen corresponding path program 12 times [2022-11-20 11:49:51,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:51,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303338293] [2022-11-20 11:49:51,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:51,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:51,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:49:52,361 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:52,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:49:52,362 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303338293] [2022-11-20 11:49:52,362 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303338293] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:49:52,362 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1540492525] [2022-11-20 11:49:52,362 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:49:52,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:49:52,363 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:49:52,370 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:49:52,386 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-11-20 11:49:52,684 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2022-11-20 11:49:52,684 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:49:52,688 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-20 11:49:52,691 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:49:52,982 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:49:53,072 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,073 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:53,088 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,089 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:49:53,232 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,233 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,235 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,238 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:49:53,238 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 38 [2022-11-20 11:49:53,911 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:49:53,916 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:49:53,916 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 24 treesize of output 10 [2022-11-20 11:49:53,949 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:49:53,949 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:49:59,115 WARN L837 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_302| Int) (v_ArrVal_917 Int)) (or (< (select (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~arr~0#1.base|) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |c_ULTIMATE.start_main_~i~0#1| 4)) 0) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_302| 4)) v_ArrVal_917) (+ |c_ULTIMATE.start_main_~arr~0#1.offset| 20)) 1) (not (<= (+ |c_ULTIMATE.start_main_~i~0#1| 1) |v_ULTIMATE.start_main_~i~0#1_302|)))) is different from false [2022-11-20 11:49:59,413 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 28 [2022-11-20 11:49:59,419 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 472 treesize of output 456 [2022-11-20 11:49:59,641 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 103 refuted. 3 times theorem prover too weak. 0 trivial. 15 not checked. [2022-11-20 11:49:59,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1540492525] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:49:59,641 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:49:59,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 20, 19] total 48 [2022-11-20 11:49:59,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183305988] [2022-11-20 11:49:59,642 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:49:59,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:49:59,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:49:59,643 INFO L85 PathProgramCache]: Analyzing trace with hash 2219337, now seen corresponding path program 1 times [2022-11-20 11:49:59,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:49:59,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378878888] [2022-11-20 11:49:59,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:49:59,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:49:59,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:59,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:49:59,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:49:59,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:49:59,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:49:59,762 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-20 11:49:59,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=2044, Unknown=6, NotChecked=92, Total=2352 [2022-11-20 11:49:59,763 INFO L87 Difference]: Start difference. First operand 103 states and 133 transitions. cyclomatic complexity: 37 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:19,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:19,352 INFO L93 Difference]: Finished difference Result 224 states and 274 transitions. [2022-11-20 11:50:19,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224 states and 274 transitions. [2022-11-20 11:50:19,354 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-11-20 11:50:19,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224 states to 222 states and 270 transitions. [2022-11-20 11:50:19,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2022-11-20 11:50:19,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2022-11-20 11:50:19,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 270 transitions. [2022-11-20 11:50:19,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:19,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 270 transitions. [2022-11-20 11:50:19,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 270 transitions. [2022-11-20 11:50:19,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 112. [2022-11-20 11:50:19,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 112 states have (on average 1.3125) internal successors, (147), 111 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:19,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 147 transitions. [2022-11-20 11:50:19,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 112 states and 147 transitions. [2022-11-20 11:50:19,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-11-20 11:50:19,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 112 states and 147 transitions. [2022-11-20 11:50:19,361 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-11-20 11:50:19,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112 states and 147 transitions. [2022-11-20 11:50:19,361 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:50:19,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:19,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:19,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 6, 5, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:19,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:19,363 INFO L748 eck$LassoCheckResult]: Stem: 8839#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 8850#L367 assume !(main_~length~0#1 < 1); 8841#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 8842#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 8843#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8851#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8907#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8906#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8905#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8904#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8903#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8902#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8901#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8900#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8899#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8898#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8897#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8895#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8894#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8889#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 8888#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8887#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8885#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8882#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8879#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 8881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 8922#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 8921#L370-4 main_~j~0#1 := 0; 8920#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8919#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8918#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8917#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8916#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8915#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8914#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8862#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8865#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8863#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 8864#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8866#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8845#L378-2 [2022-11-20 11:50:19,363 INFO L750 eck$LassoCheckResult]: Loop: 8845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 8859#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 8845#L378-2 [2022-11-20 11:50:19,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:19,363 INFO L85 PathProgramCache]: Analyzing trace with hash -1585891152, now seen corresponding path program 13 times [2022-11-20 11:50:19,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:19,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836029125] [2022-11-20 11:50:19,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:19,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:19,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:19,985 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:19,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:19,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836029125] [2022-11-20 11:50:19,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836029125] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:19,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1163499990] [2022-11-20 11:50:19,986 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:50:19,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:19,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:19,994 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:20,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-11-20 11:50:20,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:20,134 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-20 11:50:20,136 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:20,365 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:20,486 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:20,487 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:20,498 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:20,499 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:20,548 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:20,549 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:20,560 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:50:20,872 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:50:20,874 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:20,874 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:21,343 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-20 11:50:21,347 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 129 [2022-11-20 11:50:21,443 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:21,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1163499990] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:21,443 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:21,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20, 20] total 42 [2022-11-20 11:50:21,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262786729] [2022-11-20 11:50:21,444 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:21,445 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:21,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:21,446 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2022-11-20 11:50:21,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:21,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287582360] [2022-11-20 11:50:21,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:21,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:21,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:21,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:21,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:21,451 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:21,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:21,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-11-20 11:50:21,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=1630, Unknown=0, NotChecked=0, Total=1806 [2022-11-20 11:50:21,498 INFO L87 Difference]: Start difference. First operand 112 states and 147 transitions. cyclomatic complexity: 44 Second operand has 43 states, 42 states have (on average 2.1666666666666665) internal successors, (91), 43 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:23,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:23,016 INFO L93 Difference]: Finished difference Result 359 states and 432 transitions. [2022-11-20 11:50:23,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 359 states and 432 transitions. [2022-11-20 11:50:23,018 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22 [2022-11-20 11:50:23,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 359 states to 353 states and 426 transitions. [2022-11-20 11:50:23,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2022-11-20 11:50:23,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2022-11-20 11:50:23,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 426 transitions. [2022-11-20 11:50:23,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:23,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 426 transitions. [2022-11-20 11:50:23,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 426 transitions. [2022-11-20 11:50:23,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 133. [2022-11-20 11:50:23,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 133 states have (on average 1.368421052631579) internal successors, (182), 132 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:23,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 182 transitions. [2022-11-20 11:50:23,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 133 states and 182 transitions. [2022-11-20 11:50:23,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-20 11:50:23,031 INFO L428 stractBuchiCegarLoop]: Abstraction has 133 states and 182 transitions. [2022-11-20 11:50:23,031 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-11-20 11:50:23,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 133 states and 182 transitions. [2022-11-20 11:50:23,033 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:50:23,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:23,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:23,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 7, 7, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:23,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:23,035 INFO L748 eck$LassoCheckResult]: Stem: 9663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 9674#L367 assume !(main_~length~0#1 < 1); 9665#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 9666#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 9667#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9675#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9744#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9743#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9742#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9741#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9740#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9739#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9737#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9735#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9734#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9732#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9726#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9727#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9792#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 9793#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 9681#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 9682#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 9708#L370-4 main_~j~0#1 := 0; 9789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9788#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9680#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9672#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9673#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9767#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9766#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9765#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9764#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9763#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9749#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9687#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9690#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9688#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 9689#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9691#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9671#L378-2 [2022-11-20 11:50:23,035 INFO L750 eck$LassoCheckResult]: Loop: 9671#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 9684#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 9671#L378-2 [2022-11-20 11:50:23,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:23,035 INFO L85 PathProgramCache]: Analyzing trace with hash 660388610, now seen corresponding path program 14 times [2022-11-20 11:50:23,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:23,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528204372] [2022-11-20 11:50:23,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:23,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:23,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:23,321 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:23,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:23,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528204372] [2022-11-20 11:50:23,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528204372] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:23,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [957986984] [2022-11-20 11:50:23,322 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:50:23,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:23,322 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:23,326 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:23,342 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-11-20 11:50:23,459 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:50:23,459 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:23,461 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-20 11:50:23,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:23,723 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:23,723 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:23,924 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:23,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [957986984] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:23,924 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:23,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 29 [2022-11-20 11:50:23,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65834705] [2022-11-20 11:50:23,924 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:23,925 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:23,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:23,925 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2022-11-20 11:50:23,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:23,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430193866] [2022-11-20 11:50:23,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:23,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:23,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:23,933 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:23,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:23,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:23,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:23,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-11-20 11:50:23,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=618, Unknown=0, NotChecked=0, Total=812 [2022-11-20 11:50:23,990 INFO L87 Difference]: Start difference. First operand 133 states and 182 transitions. cyclomatic complexity: 58 Second operand has 29 states, 29 states have (on average 2.310344827586207) internal successors, (67), 29 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:24,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:24,202 INFO L93 Difference]: Finished difference Result 155 states and 205 transitions. [2022-11-20 11:50:24,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 205 transitions. [2022-11-20 11:50:24,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:50:24,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 139 states and 187 transitions. [2022-11-20 11:50:24,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2022-11-20 11:50:24,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2022-11-20 11:50:24,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 187 transitions. [2022-11-20 11:50:24,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:24,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 139 states and 187 transitions. [2022-11-20 11:50:24,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 187 transitions. [2022-11-20 11:50:24,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2022-11-20 11:50:24,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 135 states, 135 states have (on average 1.348148148148148) internal successors, (182), 134 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:24,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 182 transitions. [2022-11-20 11:50:24,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 135 states and 182 transitions. [2022-11-20 11:50:24,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-11-20 11:50:24,217 INFO L428 stractBuchiCegarLoop]: Abstraction has 135 states and 182 transitions. [2022-11-20 11:50:24,217 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-11-20 11:50:24,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135 states and 182 transitions. [2022-11-20 11:50:24,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:50:24,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:24,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:24,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 6, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:24,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:24,220 INFO L748 eck$LassoCheckResult]: Stem: 10259#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10270#L367 assume !(main_~length~0#1 < 1); 10261#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10262#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10263#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10271#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10362#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10361#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10360#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10359#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10358#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10357#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10356#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10355#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10354#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10353#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10352#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10350#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10349#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10348#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10346#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10342#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10343#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10364#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10334#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10315#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10313#L370-4 main_~j~0#1 := 0; 10310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10274#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10307#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10305#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10299#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10297#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10286#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10287#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10291#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10265#L378-2 [2022-11-20 11:50:24,220 INFO L750 eck$LassoCheckResult]: Loop: 10265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10382#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10265#L378-2 [2022-11-20 11:50:24,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:24,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1228711609, now seen corresponding path program 15 times [2022-11-20 11:50:24,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:24,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001700988] [2022-11-20 11:50:24,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:24,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:24,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:24,847 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:24,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:24,847 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001700988] [2022-11-20 11:50:24,847 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001700988] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:24,847 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [389622715] [2022-11-20 11:50:24,848 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:50:24,848 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:24,848 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:24,854 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:24,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-11-20 11:50:25,177 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2022-11-20 11:50:25,177 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:25,179 INFO L263 TraceCheckSpWp]: Trace formula consists of 246 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-20 11:50:25,181 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:25,244 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:25,357 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:50:25,358 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:50:25,384 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:50:25,384 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:50:25,645 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:50:25,648 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:25,648 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:25,872 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:50:25,875 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:50:25,939 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:25,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [389622715] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:25,939 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:25,939 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-11-20 11:50:25,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897234983] [2022-11-20 11:50:25,939 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:25,940 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:25,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:25,940 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2022-11-20 11:50:25,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:25,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601166565] [2022-11-20 11:50:25,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:25,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:25,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:25,943 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:25,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:25,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:25,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:25,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-20 11:50:25,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=901, Unknown=0, NotChecked=0, Total=992 [2022-11-20 11:50:25,991 INFO L87 Difference]: Start difference. First operand 135 states and 182 transitions. cyclomatic complexity: 56 Second operand has 32 states, 31 states have (on average 2.193548387096774) internal successors, (68), 32 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:26,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:26,738 INFO L93 Difference]: Finished difference Result 202 states and 259 transitions. [2022-11-20 11:50:26,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202 states and 259 transitions. [2022-11-20 11:50:26,739 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 18 [2022-11-20 11:50:26,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202 states to 201 states and 258 transitions. [2022-11-20 11:50:26,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2022-11-20 11:50:26,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2022-11-20 11:50:26,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 258 transitions. [2022-11-20 11:50:26,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:26,741 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 258 transitions. [2022-11-20 11:50:26,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 258 transitions. [2022-11-20 11:50:26,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 143. [2022-11-20 11:50:26,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.3636363636363635) internal successors, (195), 142 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:26,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 195 transitions. [2022-11-20 11:50:26,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 195 transitions. [2022-11-20 11:50:26,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-20 11:50:26,752 INFO L428 stractBuchiCegarLoop]: Abstraction has 143 states and 195 transitions. [2022-11-20 11:50:26,752 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-11-20 11:50:26,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 195 transitions. [2022-11-20 11:50:26,753 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-11-20 11:50:26,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:26,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:26,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:26,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:26,755 INFO L748 eck$LassoCheckResult]: Stem: 10913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 10924#L367 assume !(main_~length~0#1 < 1); 10915#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 10916#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 10917#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10925#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10989#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10988#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10987#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10986#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10985#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10984#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10983#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10982#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10981#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10980#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10978#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10977#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10974#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10975#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11039#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11036#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11037#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10926#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 10927#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 10929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 10931#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 10918#L370-4 main_~j~0#1 := 0; 10919#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10922#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10923#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10930#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10996#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10994#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10935#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10940#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10937#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 10938#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10939#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10921#L378-2 [2022-11-20 11:50:26,755 INFO L750 eck$LassoCheckResult]: Loop: 10921#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 10936#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 10921#L378-2 [2022-11-20 11:50:26,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:26,756 INFO L85 PathProgramCache]: Analyzing trace with hash 663643002, now seen corresponding path program 16 times [2022-11-20 11:50:26,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:26,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004100272] [2022-11-20 11:50:26,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:26,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:26,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:27,334 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:27,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:27,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004100272] [2022-11-20 11:50:27,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004100272] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:27,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [830402503] [2022-11-20 11:50:27,335 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:50:27,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:27,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:27,342 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:27,344 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-11-20 11:50:27,477 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:50:27,477 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:27,479 INFO L263 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 38 conjunts are in the unsatisfiable core [2022-11-20 11:50:27,481 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:27,568 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:27,924 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:50:27,927 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:27,927 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:28,072 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:50:28,074 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:50:28,147 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:28,147 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [830402503] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:28,147 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:28,147 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20, 20] total 31 [2022-11-20 11:50:28,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528694838] [2022-11-20 11:50:28,148 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:28,148 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:28,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:28,148 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2022-11-20 11:50:28,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:28,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069785755] [2022-11-20 11:50:28,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:28,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:28,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:28,151 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:28,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:28,155 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:28,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:28,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-20 11:50:28,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=899, Unknown=0, NotChecked=0, Total=992 [2022-11-20 11:50:28,199 INFO L87 Difference]: Start difference. First operand 143 states and 195 transitions. cyclomatic complexity: 61 Second operand has 32 states, 31 states have (on average 2.225806451612903) internal successors, (69), 32 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:28,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:28,800 INFO L93 Difference]: Finished difference Result 240 states and 318 transitions. [2022-11-20 11:50:28,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240 states and 318 transitions. [2022-11-20 11:50:28,801 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 42 [2022-11-20 11:50:28,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240 states to 239 states and 317 transitions. [2022-11-20 11:50:28,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2022-11-20 11:50:28,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2022-11-20 11:50:28,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 239 states and 317 transitions. [2022-11-20 11:50:28,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:28,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 239 states and 317 transitions. [2022-11-20 11:50:28,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states and 317 transitions. [2022-11-20 11:50:28,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 219. [2022-11-20 11:50:28,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.3470319634703196) internal successors, (295), 218 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:28,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 295 transitions. [2022-11-20 11:50:28,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219 states and 295 transitions. [2022-11-20 11:50:28,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 11:50:28,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 219 states and 295 transitions. [2022-11-20 11:50:28,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-11-20 11:50:28,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 295 transitions. [2022-11-20 11:50:28,812 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 40 [2022-11-20 11:50:28,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:28,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:28,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:28,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:50:28,813 INFO L748 eck$LassoCheckResult]: Stem: 11609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 11620#L367 assume !(main_~length~0#1 < 1); 11611#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 11612#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 11613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11621#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11709#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11707#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11706#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11705#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11704#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11703#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11702#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11701#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11700#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11697#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11693#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11694#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11751#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11750#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11748#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11746#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11744#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11742#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11740#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11738#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 11736#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 11724#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 11721#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 11661#L370-4 main_~j~0#1 := 0; 11719#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11716#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11714#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11710#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11711#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11691#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11692#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11680#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11681#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11673#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11674#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11639#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11640#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11754#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11789#L378-2 [2022-11-20 11:50:28,814 INFO L750 eck$LassoCheckResult]: Loop: 11789#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11806#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 11805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 11788#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 11789#L378-2 [2022-11-20 11:50:28,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:28,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1087248771, now seen corresponding path program 17 times [2022-11-20 11:50:28,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:28,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632082863] [2022-11-20 11:50:28,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:28,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:28,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:29,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:29,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632082863] [2022-11-20 11:50:29,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632082863] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:29,497 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1109101209] [2022-11-20 11:50:29,498 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:50:29,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:29,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:29,501 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:29,522 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-11-20 11:50:29,733 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-11-20 11:50:29,733 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:29,736 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-20 11:50:29,739 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:30,018 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:30,110 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:30,111 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:30,125 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:30,125 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:30,177 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:30,178 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:30,668 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:50:30,670 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:50:30,671 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:50:30,701 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 1 proven. 158 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:30,701 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:45,291 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2022-11-20 11:50:45,295 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 192 treesize of output 178 [2022-11-20 11:50:45,408 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 156 refuted. 2 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-20 11:50:45,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1109101209] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:45,409 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:45,409 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22, 21] total 53 [2022-11-20 11:50:45,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576678263] [2022-11-20 11:50:45,409 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:45,409 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:45,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:45,410 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 2 times [2022-11-20 11:50:45,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:45,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696923618] [2022-11-20 11:50:45,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:45,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:45,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:45,413 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:45,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:45,416 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:45,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:45,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-20 11:50:45,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=205, Invalid=2651, Unknown=6, NotChecked=0, Total=2862 [2022-11-20 11:50:45,501 INFO L87 Difference]: Start difference. First operand 219 states and 295 transitions. cyclomatic complexity: 89 Second operand has 54 states, 53 states have (on average 2.188679245283019) internal successors, (116), 54 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:47,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:47,248 INFO L93 Difference]: Finished difference Result 388 states and 504 transitions. [2022-11-20 11:50:47,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388 states and 504 transitions. [2022-11-20 11:50:47,250 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 68 [2022-11-20 11:50:47,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388 states to 386 states and 502 transitions. [2022-11-20 11:50:47,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119 [2022-11-20 11:50:47,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119 [2022-11-20 11:50:47,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386 states and 502 transitions. [2022-11-20 11:50:47,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:47,253 INFO L218 hiAutomatonCegarLoop]: Abstraction has 386 states and 502 transitions. [2022-11-20 11:50:47,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386 states and 502 transitions. [2022-11-20 11:50:47,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386 to 249. [2022-11-20 11:50:47,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 249 states have (on average 1.3493975903614457) internal successors, (336), 248 states have internal predecessors, (336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:47,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 336 transitions. [2022-11-20 11:50:47,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 249 states and 336 transitions. [2022-11-20 11:50:47,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-11-20 11:50:47,261 INFO L428 stractBuchiCegarLoop]: Abstraction has 249 states and 336 transitions. [2022-11-20 11:50:47,261 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-11-20 11:50:47,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 336 transitions. [2022-11-20 11:50:47,263 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 40 [2022-11-20 11:50:47,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:47,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:47,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:47,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:47,264 INFO L748 eck$LassoCheckResult]: Stem: 12591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 12592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 12602#L367 assume !(main_~length~0#1 < 1); 12593#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 12594#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 12595#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12603#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12639#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12638#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12637#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12636#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12635#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12634#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12633#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12632#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12631#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12630#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12629#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12627#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12626#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12625#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12623#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12622#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12621#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12620#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 12617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12735#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12733#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12732#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12731#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12728#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 12730#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 12780#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 12768#L370-4 main_~j~0#1 := 0; 12779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12778#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12759#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12758#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12757#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12756#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12755#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12648#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12699#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12696#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12659#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12657#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 12658#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12660#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12599#L378-2 [2022-11-20 11:50:47,264 INFO L750 eck$LassoCheckResult]: Loop: 12599#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 12646#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 12599#L378-2 [2022-11-20 11:50:47,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:47,265 INFO L85 PathProgramCache]: Analyzing trace with hash 772882429, now seen corresponding path program 18 times [2022-11-20 11:50:47,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:47,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817035711] [2022-11-20 11:50:47,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:47,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:47,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:47,996 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:47,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:47,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817035711] [2022-11-20 11:50:47,997 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817035711] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:47,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1991197757] [2022-11-20 11:50:47,997 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:50:47,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:47,997 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:47,999 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:48,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-20 11:50:48,372 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2022-11-20 11:50:48,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:48,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-20 11:50:48,377 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:48,633 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:48,760 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:48,761 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:48,774 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:48,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:48,823 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:48,829 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:48,838 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:50:49,365 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:50:49,366 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 10 [2022-11-20 11:50:49,369 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:49,370 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:49,887 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 30 [2022-11-20 11:50:49,891 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 546 treesize of output 530 [2022-11-20 11:50:50,369 INFO L134 CoverageAnalysis]: Checked inductivity of 159 backedges. 2 proven. 157 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:50,370 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1991197757] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:50,370 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:50,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 22, 22] total 54 [2022-11-20 11:50:50,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764131858] [2022-11-20 11:50:50,371 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:50,371 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:50,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:50,371 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2022-11-20 11:50:50,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:50,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989139940] [2022-11-20 11:50:50,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:50,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:50,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:50,374 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:50,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:50,377 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:50,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:50,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-20 11:50:50,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=2699, Unknown=0, NotChecked=0, Total=2970 [2022-11-20 11:50:50,431 INFO L87 Difference]: Start difference. First operand 249 states and 336 transitions. cyclomatic complexity: 103 Second operand has 55 states, 54 states have (on average 2.259259259259259) internal successors, (122), 55 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:53,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:53,009 INFO L93 Difference]: Finished difference Result 557 states and 711 transitions. [2022-11-20 11:50:53,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 711 transitions. [2022-11-20 11:50:53,012 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 96 [2022-11-20 11:50:53,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 552 states and 706 transitions. [2022-11-20 11:50:53,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 164 [2022-11-20 11:50:53,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 164 [2022-11-20 11:50:53,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 706 transitions. [2022-11-20 11:50:53,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:53,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 706 transitions. [2022-11-20 11:50:53,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 706 transitions. [2022-11-20 11:50:53,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 307. [2022-11-20 11:50:53,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307 states, 307 states have (on average 1.3680781758957654) internal successors, (420), 306 states have internal predecessors, (420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:53,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 420 transitions. [2022-11-20 11:50:53,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307 states and 420 transitions. [2022-11-20 11:50:53,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-11-20 11:50:53,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 307 states and 420 transitions. [2022-11-20 11:50:53,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-11-20 11:50:53,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 420 transitions. [2022-11-20 11:50:53,028 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:50:53,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:53,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:53,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 8, 8, 8, 5, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:53,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:53,029 INFO L748 eck$LassoCheckResult]: Stem: 13837#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 13838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 13848#L367 assume !(main_~length~0#1 < 1); 13839#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 13840#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 13841#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13849#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13887#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13886#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13885#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13884#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13883#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13882#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13881#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13880#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13879#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 13878#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13877#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13875#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13874#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13873#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13871#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13870#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 13869#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13867#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 13868#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14038#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14036#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 14034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14035#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 13926#L370-4 main_~j~0#1 := 0; 14069#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14068#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13852#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13844#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13845#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14050#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14041#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14040#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14039#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13895#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13947#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13944#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13902#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13899#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 13900#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 13901#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13843#L378-2 [2022-11-20 11:50:53,029 INFO L750 eck$LassoCheckResult]: Loop: 13843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14099#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 13843#L378-2 [2022-11-20 11:50:53,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:53,030 INFO L85 PathProgramCache]: Analyzing trace with hash 2105768383, now seen corresponding path program 19 times [2022-11-20 11:50:53,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:53,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294999544] [2022-11-20 11:50:53,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:53,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:53,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:53,381 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:53,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:53,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294999544] [2022-11-20 11:50:53,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294999544] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:53,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [27147524] [2022-11-20 11:50:53,381 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:50:53,381 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:53,382 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:53,385 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:53,401 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-11-20 11:50:53,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:53,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 268 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-20 11:50:53,536 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:53,813 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:53,814 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:54,025 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:54,025 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [27147524] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:54,025 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:54,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21] total 32 [2022-11-20 11:50:54,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826394129] [2022-11-20 11:50:54,025 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:54,026 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:54,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:54,026 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2022-11-20 11:50:54,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:54,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399256029] [2022-11-20 11:50:54,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:54,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:54,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:54,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:54,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:54,033 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:54,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:54,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-20 11:50:54,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=235, Invalid=757, Unknown=0, NotChecked=0, Total=992 [2022-11-20 11:50:54,085 INFO L87 Difference]: Start difference. First operand 307 states and 420 transitions. cyclomatic complexity: 132 Second operand has 32 states, 32 states have (on average 2.3125) internal successors, (74), 32 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:54,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:54,378 INFO L93 Difference]: Finished difference Result 327 states and 439 transitions. [2022-11-20 11:50:54,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 439 transitions. [2022-11-20 11:50:54,380 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:50:54,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 309 states and 416 transitions. [2022-11-20 11:50:54,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2022-11-20 11:50:54,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2022-11-20 11:50:54,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 416 transitions. [2022-11-20 11:50:54,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:54,382 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309 states and 416 transitions. [2022-11-20 11:50:54,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 416 transitions. [2022-11-20 11:50:54,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 307. [2022-11-20 11:50:54,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307 states, 307 states have (on average 1.3485342019543973) internal successors, (414), 306 states have internal predecessors, (414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:54,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 414 transitions. [2022-11-20 11:50:54,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307 states and 414 transitions. [2022-11-20 11:50:54,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-20 11:50:54,390 INFO L428 stractBuchiCegarLoop]: Abstraction has 307 states and 414 transitions. [2022-11-20 11:50:54,390 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-11-20 11:50:54,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 414 transitions. [2022-11-20 11:50:54,391 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:50:54,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:54,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:54,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 7, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:54,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:50:54,393 INFO L748 eck$LassoCheckResult]: Stem: 14814#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 14815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 14825#L367 assume !(main_~length~0#1 < 1); 14816#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 14817#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 14818#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14826#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 14834#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 14827#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 14828#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15026#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15023#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15022#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15021#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15019#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15016#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15014#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15036#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15035#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15034#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15004#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15020#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15017#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15027#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15009#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15010#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15006#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 14904#L370-4 main_~j~0#1 := 0; 15047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15046#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14833#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14823#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14824#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15044#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15117#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15116#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15115#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15037#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14844#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14842#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 14843#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 14857#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15056#L378-2 [2022-11-20 11:50:54,393 INFO L750 eck$LassoCheckResult]: Loop: 15056#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15070#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15072#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15055#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15056#L378-2 [2022-11-20 11:50:54,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:54,394 INFO L85 PathProgramCache]: Analyzing trace with hash 2138164678, now seen corresponding path program 20 times [2022-11-20 11:50:54,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:54,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278015982] [2022-11-20 11:50:54,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:54,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:54,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:55,143 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:55,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:55,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278015982] [2022-11-20 11:50:55,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278015982] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:55,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1070297067] [2022-11-20 11:50:55,144 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:50:55,144 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:55,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:55,146 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:55,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-11-20 11:50:55,301 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:50:55,301 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:55,303 INFO L263 TraceCheckSpWp]: Trace formula consists of 279 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-20 11:50:55,305 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:55,625 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:50:55,761 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:55,762 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:55,774 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:50:55,775 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:50:56,230 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:50:56,232 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:56,232 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:50:56,496 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:50:56,500 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:50:56,576 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:56,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1070297067] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:50:56,576 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:50:56,577 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23, 22] total 46 [2022-11-20 11:50:56,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991812614] [2022-11-20 11:50:56,577 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:50:56,577 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:50:56,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:56,577 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 3 times [2022-11-20 11:50:56,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:56,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66517582] [2022-11-20 11:50:56,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:56,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:56,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:56,581 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:50:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:50:56,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:50:56,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:50:56,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-11-20 11:50:56,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1991, Unknown=0, NotChecked=0, Total=2162 [2022-11-20 11:50:56,694 INFO L87 Difference]: Start difference. First operand 307 states and 414 transitions. cyclomatic complexity: 126 Second operand has 47 states, 46 states have (on average 2.217391304347826) internal successors, (102), 47 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:57,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:50:57,753 INFO L93 Difference]: Finished difference Result 392 states and 514 transitions. [2022-11-20 11:50:57,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 514 transitions. [2022-11-20 11:50:57,755 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 78 [2022-11-20 11:50:57,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 390 states and 512 transitions. [2022-11-20 11:50:57,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2022-11-20 11:50:57,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2022-11-20 11:50:57,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390 states and 512 transitions. [2022-11-20 11:50:57,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:50:57,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 390 states and 512 transitions. [2022-11-20 11:50:57,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states and 512 transitions. [2022-11-20 11:50:57,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 260. [2022-11-20 11:50:57,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.3423076923076922) internal successors, (349), 259 states have internal predecessors, (349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:50:57,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 349 transitions. [2022-11-20 11:50:57,764 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 349 transitions. [2022-11-20 11:50:57,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 11:50:57,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 260 states and 349 transitions. [2022-11-20 11:50:57,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-11-20 11:50:57,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 349 transitions. [2022-11-20 11:50:57,768 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:50:57,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:50:57,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:50:57,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:50:57,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:50:57,769 INFO L748 eck$LassoCheckResult]: Stem: 15877#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 15878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 15888#L367 assume !(main_~length~0#1 < 1); 15879#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 15880#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 15881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15889#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15929#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15928#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15927#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15926#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15925#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15924#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15923#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15922#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15921#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15920#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15919#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15917#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15916#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15915#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15913#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15912#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15911#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15910#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15909#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15908#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15906#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15902#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15905#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 15901#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 15893#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 15900#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 15882#L370-4 main_~j~0#1 := 0; 15883#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15886#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15887#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16040#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16038#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16036#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16034#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16032#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15944#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 16000#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15973#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15952#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15953#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 15954#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 15955#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15885#L378-2 [2022-11-20 11:50:57,769 INFO L750 eck$LassoCheckResult]: Loop: 15885#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16073#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 15885#L378-2 [2022-11-20 11:50:57,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:50:57,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1860197447, now seen corresponding path program 21 times [2022-11-20 11:50:57,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:50:57,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934110429] [2022-11-20 11:50:57,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:50:57,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:50:57,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:50:58,418 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:50:58,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:50:58,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934110429] [2022-11-20 11:50:58,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934110429] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:50:58,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1737715841] [2022-11-20 11:50:58,419 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:50:58,419 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:50:58,419 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:50:58,426 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:50:58,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-11-20 11:50:58,873 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-11-20 11:50:58,874 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:50:58,876 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 27 conjunts are in the unsatisfiable core [2022-11-20 11:50:58,877 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:50:59,145 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:00,096 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 11:51:00,096 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 11:51:00,100 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 64 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:00,100 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:01,288 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:51:01,293 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:51:01,539 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 56 proven. 133 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:01,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1737715841] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:01,540 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:01,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 24] total 58 [2022-11-20 11:51:01,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397959247] [2022-11-20 11:51:01,540 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:01,540 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:01,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:01,541 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2022-11-20 11:51:01,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:01,541 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894275838] [2022-11-20 11:51:01,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:01,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:01,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:01,545 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:01,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:01,547 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:01,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:01,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-20 11:51:01,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=3022, Unknown=0, NotChecked=0, Total=3422 [2022-11-20 11:51:01,596 INFO L87 Difference]: Start difference. First operand 260 states and 349 transitions. cyclomatic complexity: 104 Second operand has 59 states, 58 states have (on average 2.086206896551724) internal successors, (121), 59 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:03,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:03,692 INFO L93 Difference]: Finished difference Result 366 states and 472 transitions. [2022-11-20 11:51:03,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 472 transitions. [2022-11-20 11:51:03,694 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:51:03,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 325 states and 428 transitions. [2022-11-20 11:51:03,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79 [2022-11-20 11:51:03,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79 [2022-11-20 11:51:03,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 325 states and 428 transitions. [2022-11-20 11:51:03,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:03,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 325 states and 428 transitions. [2022-11-20 11:51:03,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states and 428 transitions. [2022-11-20 11:51:03,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 297. [2022-11-20 11:51:03,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 297 states, 297 states have (on average 1.3367003367003367) internal successors, (397), 296 states have internal predecessors, (397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:03,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 397 transitions. [2022-11-20 11:51:03,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 297 states and 397 transitions. [2022-11-20 11:51:03,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2022-11-20 11:51:03,702 INFO L428 stractBuchiCegarLoop]: Abstraction has 297 states and 397 transitions. [2022-11-20 11:51:03,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-11-20 11:51:03,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 297 states and 397 transitions. [2022-11-20 11:51:03,703 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52 [2022-11-20 11:51:03,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:03,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:03,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:03,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:03,705 INFO L748 eck$LassoCheckResult]: Stem: 16964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 16965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 16975#L367 assume !(main_~length~0#1 < 1); 16966#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 16967#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 16968#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16976#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17025#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17032#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17031#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17030#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17028#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17027#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17026#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17013#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 17010#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17009#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17007#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17005#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17006#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17044#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 17000#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 17001#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16997#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16996#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16995#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16993#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16990#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16992#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 16989#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 16986#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 16987#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 17128#L370-4 main_~j~0#1 := 0; 17234#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16980#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17232#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17231#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17228#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17226#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17224#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17223#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17221#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17219#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17101#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17098#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17095#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17080#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17090#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17084#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 17083#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 17055#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16970#L378-2 [2022-11-20 11:51:03,705 INFO L750 eck$LassoCheckResult]: Loop: 16970#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 16979#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 16970#L378-2 [2022-11-20 11:51:03,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:03,705 INFO L85 PathProgramCache]: Analyzing trace with hash -68075255, now seen corresponding path program 22 times [2022-11-20 11:51:03,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:03,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282644720] [2022-11-20 11:51:03,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:03,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:03,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:04,382 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:04,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:04,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282644720] [2022-11-20 11:51:04,383 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282644720] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:04,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1811479535] [2022-11-20 11:51:04,383 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:51:04,383 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:04,383 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:04,389 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:04,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-11-20 11:51:04,563 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:51:04,563 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:04,565 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-20 11:51:04,569 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:04,646 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:05,109 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:51:05,112 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:05,112 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:05,278 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:51:05,281 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:51:05,372 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:05,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1811479535] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:05,372 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:05,372 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22] total 34 [2022-11-20 11:51:05,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859746078] [2022-11-20 11:51:05,373 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:05,373 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:05,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:05,373 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2022-11-20 11:51:05,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:05,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409507070] [2022-11-20 11:51:05,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:05,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:05,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:05,377 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:05,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:05,379 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:05,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:05,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-20 11:51:05,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=1088, Unknown=0, NotChecked=0, Total=1190 [2022-11-20 11:51:05,429 INFO L87 Difference]: Start difference. First operand 297 states and 397 transitions. cyclomatic complexity: 115 Second operand has 35 states, 34 states have (on average 2.235294117647059) internal successors, (76), 35 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:06,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:06,186 INFO L93 Difference]: Finished difference Result 450 states and 589 transitions. [2022-11-20 11:51:06,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450 states and 589 transitions. [2022-11-20 11:51:06,190 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 92 [2022-11-20 11:51:06,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450 states to 449 states and 588 transitions. [2022-11-20 11:51:06,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139 [2022-11-20 11:51:06,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139 [2022-11-20 11:51:06,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 588 transitions. [2022-11-20 11:51:06,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:06,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 588 transitions. [2022-11-20 11:51:06,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 588 transitions. [2022-11-20 11:51:06,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 384. [2022-11-20 11:51:06,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.3307291666666667) internal successors, (511), 383 states have internal predecessors, (511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:06,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 511 transitions. [2022-11-20 11:51:06,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 384 states and 511 transitions. [2022-11-20 11:51:06,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-20 11:51:06,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 384 states and 511 transitions. [2022-11-20 11:51:06,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-11-20 11:51:06,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 511 transitions. [2022-11-20 11:51:06,207 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 78 [2022-11-20 11:51:06,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:06,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:06,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 7, 6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:06,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:51:06,208 INFO L748 eck$LassoCheckResult]: Stem: 18057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 18058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 18068#L367 assume !(main_~length~0#1 < 1); 18059#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 18060#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 18061#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18069#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18128#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18126#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18124#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18122#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18120#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18118#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18116#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18114#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18112#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18108#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18109#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18103#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18104#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18099#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18100#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18138#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18140#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18141#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18295#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18294#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18136#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18293#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18292#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18289#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18282#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18280#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18281#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 18327#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 18277#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 18326#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 18324#L370-4 main_~j~0#1 := 0; 18325#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18417#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18416#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18415#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18414#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18413#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18412#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18411#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18410#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18409#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18408#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18406#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18402#L378-2 [2022-11-20 11:51:06,208 INFO L750 eck$LassoCheckResult]: Loop: 18402#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18404#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 18405#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 18407#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 18402#L378-2 [2022-11-20 11:51:06,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:06,209 INFO L85 PathProgramCache]: Analyzing trace with hash -1226720964, now seen corresponding path program 23 times [2022-11-20 11:51:06,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:06,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923030075] [2022-11-20 11:51:06,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:06,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:06,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:07,216 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 18 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:07,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:07,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923030075] [2022-11-20 11:51:07,217 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923030075] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:07,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998262075] [2022-11-20 11:51:07,217 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:51:07,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:07,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:07,221 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:07,237 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-20 11:51:07,549 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-20 11:51:07,549 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:07,552 INFO L263 TraceCheckSpWp]: Trace formula consists of 285 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-20 11:51:07,556 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:07,792 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:07,926 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:51:07,934 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:51:07,984 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:07,984 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:08,043 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:08,044 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:08,105 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:08,108 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:08,119 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:08,119 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:08,172 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:08,174 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:08,614 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:51:08,616 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:51:08,616 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:51:08,620 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 12 proven. 194 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:08,620 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:09,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:51:09,269 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:51:09,326 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 6 proven. 182 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2022-11-20 11:51:09,326 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998262075] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:09,327 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:09,327 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 24, 20] total 48 [2022-11-20 11:51:09,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405347043] [2022-11-20 11:51:09,327 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:09,327 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:09,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:09,328 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 4 times [2022-11-20 11:51:09,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:09,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333331800] [2022-11-20 11:51:09,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:09,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:09,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:09,332 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:09,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:09,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:09,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:09,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-20 11:51:09,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=2115, Unknown=0, NotChecked=0, Total=2352 [2022-11-20 11:51:09,441 INFO L87 Difference]: Start difference. First operand 384 states and 511 transitions. cyclomatic complexity: 148 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:10,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:10,750 INFO L93 Difference]: Finished difference Result 375 states and 477 transitions. [2022-11-20 11:51:10,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 477 transitions. [2022-11-20 11:51:10,752 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 32 [2022-11-20 11:51:10,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 370 states and 472 transitions. [2022-11-20 11:51:10,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2022-11-20 11:51:10,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2022-11-20 11:51:10,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370 states and 472 transitions. [2022-11-20 11:51:10,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:10,756 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370 states and 472 transitions. [2022-11-20 11:51:10,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states and 472 transitions. [2022-11-20 11:51:10,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 210. [2022-11-20 11:51:10,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 210 states have (on average 1.319047619047619) internal successors, (277), 209 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:10,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 277 transitions. [2022-11-20 11:51:10,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 210 states and 277 transitions. [2022-11-20 11:51:10,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-20 11:51:10,762 INFO L428 stractBuchiCegarLoop]: Abstraction has 210 states and 277 transitions. [2022-11-20 11:51:10,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-11-20 11:51:10,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 210 states and 277 transitions. [2022-11-20 11:51:10,763 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-20 11:51:10,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:10,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:10,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 9, 9, 9, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:10,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:10,764 INFO L748 eck$LassoCheckResult]: Stem: 19204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 19205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 19215#L367 assume !(main_~length~0#1 < 1); 19206#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 19207#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 19208#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19216#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19319#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19318#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19317#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19316#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19315#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19313#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19312#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19311#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19309#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19308#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19307#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19352#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19351#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19349#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19350#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19345#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19346#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19340#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 19337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 19220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 19223#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 19213#L370-4 main_~j~0#1 := 0; 19214#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19211#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19212#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19222#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19328#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19327#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19326#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19325#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19324#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19323#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19303#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19276#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19229#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19231#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 19232#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19235#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19210#L378-2 [2022-11-20 11:51:10,764 INFO L750 eck$LassoCheckResult]: Loop: 19210#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 19227#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 19210#L378-2 [2022-11-20 11:51:10,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:10,765 INFO L85 PathProgramCache]: Analyzing trace with hash -995807346, now seen corresponding path program 24 times [2022-11-20 11:51:10,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:10,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23317555] [2022-11-20 11:51:10,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:10,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:10,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:11,150 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:11,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:11,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23317555] [2022-11-20 11:51:11,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23317555] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:11,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [13797546] [2022-11-20 11:51:11,151 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:51:11,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:11,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:11,158 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:11,178 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-11-20 11:51:12,040 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2022-11-20 11:51:12,040 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:12,043 INFO L263 TraceCheckSpWp]: Trace formula consists of 309 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-20 11:51:12,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:12,380 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:12,381 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:12,668 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:12,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [13797546] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:12,669 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:12,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 35 [2022-11-20 11:51:12,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781061323] [2022-11-20 11:51:12,669 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:12,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:12,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:12,670 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2022-11-20 11:51:12,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:12,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873678481] [2022-11-20 11:51:12,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:12,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:12,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:12,673 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:12,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:12,676 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:12,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:12,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-11-20 11:51:12,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=280, Invalid=910, Unknown=0, NotChecked=0, Total=1190 [2022-11-20 11:51:12,732 INFO L87 Difference]: Start difference. First operand 210 states and 277 transitions. cyclomatic complexity: 78 Second operand has 35 states, 35 states have (on average 2.3142857142857145) internal successors, (81), 35 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:13,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:13,035 INFO L93 Difference]: Finished difference Result 237 states and 305 transitions. [2022-11-20 11:51:13,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 237 states and 305 transitions. [2022-11-20 11:51:13,037 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-20 11:51:13,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 237 states to 217 states and 283 transitions. [2022-11-20 11:51:13,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2022-11-20 11:51:13,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2022-11-20 11:51:13,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 283 transitions. [2022-11-20 11:51:13,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:13,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 217 states and 283 transitions. [2022-11-20 11:51:13,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 283 transitions. [2022-11-20 11:51:13,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 177. [2022-11-20 11:51:13,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 177 states have (on average 1.305084745762712) internal successors, (231), 176 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:13,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 231 transitions. [2022-11-20 11:51:13,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177 states and 231 transitions. [2022-11-20 11:51:13,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-20 11:51:13,044 INFO L428 stractBuchiCegarLoop]: Abstraction has 177 states and 231 transitions. [2022-11-20 11:51:13,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2022-11-20 11:51:13,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 231 transitions. [2022-11-20 11:51:13,045 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30 [2022-11-20 11:51:13,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:13,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:13,045 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 7, 7, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:13,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:51:13,046 INFO L748 eck$LassoCheckResult]: Stem: 20029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20040#L367 assume !(main_~length~0#1 < 1); 20031#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20032#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20033#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20041#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20087#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20086#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20085#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20084#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20083#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20082#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20081#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20080#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20079#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20078#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20077#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20075#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20074#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20073#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20072#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20071#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20070#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20069#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20047#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20167#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20164#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20162#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20161#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20159#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20156#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20153#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20151#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20146#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20155#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20145#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20142#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20140#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20139#L370-4 main_~j~0#1 := 0; 20044#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20036#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20037#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20045#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20173#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20172#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20171#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20154#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20152#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20150#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20103#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20098#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20099#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20107#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20181#L378-2 [2022-11-20 11:51:13,046 INFO L750 eck$LassoCheckResult]: Loop: 20181#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20184#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20182#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20180#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20181#L378-2 [2022-11-20 11:51:13,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:13,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1946851207, now seen corresponding path program 25 times [2022-11-20 11:51:13,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:13,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762231199] [2022-11-20 11:51:13,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:13,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:13,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:14,007 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 9 proven. 209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:14,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:14,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762231199] [2022-11-20 11:51:14,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762231199] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:14,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1445377278] [2022-11-20 11:51:14,008 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:51:14,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:14,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:14,009 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:14,012 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-11-20 11:51:14,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:14,193 INFO L263 TraceCheckSpWp]: Trace formula consists of 296 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-20 11:51:14,196 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:14,506 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:14,646 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:51:14,663 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:51:14,718 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:14,718 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:14,776 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:14,776 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:14,784 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:14,785 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:14,841 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:51:15,257 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:51:15,260 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 0 proven. 218 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:15,260 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:16,247 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 45 [2022-11-20 11:51:16,252 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1097 treesize of output 1081 [2022-11-20 11:51:17,606 INFO L134 CoverageAnalysis]: Checked inductivity of 218 backedges. 0 proven. 218 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:17,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1445377278] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:17,607 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:17,607 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24, 26] total 54 [2022-11-20 11:51:17,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503883797] [2022-11-20 11:51:17,607 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:17,607 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:17,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:17,608 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 5 times [2022-11-20 11:51:17,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:17,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140987614] [2022-11-20 11:51:17,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:17,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:17,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:17,613 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:17,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:17,616 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:17,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:17,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2022-11-20 11:51:17,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=295, Invalid=2675, Unknown=0, NotChecked=0, Total=2970 [2022-11-20 11:51:17,717 INFO L87 Difference]: Start difference. First operand 177 states and 231 transitions. cyclomatic complexity: 65 Second operand has 55 states, 54 states have (on average 2.2037037037037037) internal successors, (119), 55 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:19,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:19,565 INFO L93 Difference]: Finished difference Result 330 states and 397 transitions. [2022-11-20 11:51:19,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 397 transitions. [2022-11-20 11:51:19,567 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8 [2022-11-20 11:51:19,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 326 states and 393 transitions. [2022-11-20 11:51:19,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2022-11-20 11:51:19,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2022-11-20 11:51:19,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 393 transitions. [2022-11-20 11:51:19,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:19,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 393 transitions. [2022-11-20 11:51:19,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 393 transitions. [2022-11-20 11:51:19,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 82. [2022-11-20 11:51:19,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2560975609756098) internal successors, (103), 81 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:19,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 103 transitions. [2022-11-20 11:51:19,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 11:51:19,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-11-20 11:51:19,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 82 states and 103 transitions. [2022-11-20 11:51:19,574 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2022-11-20 11:51:19,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 103 transitions. [2022-11-20 11:51:19,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:19,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:19,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:19,576 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 8, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:19,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:19,576 INFO L748 eck$LassoCheckResult]: Stem: 20981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 20982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 20992#L367 assume !(main_~length~0#1 < 1); 20983#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 20984#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 20985#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20993#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21055#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21054#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21053#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21052#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21051#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21050#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21049#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21048#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21047#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21046#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21045#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21043#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21042#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21041#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21039#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21038#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21037#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21036#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21035#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21034#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21032#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21031#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21030#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21029#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 20999#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 20994#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 20995#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21022#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21008#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 20986#L370-4 main_~j~0#1 := 0; 20987#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20990#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 20991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21016#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21015#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21014#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21013#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21012#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21011#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21010#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21006#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21004#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21002#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 20988#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20989#L378-2 [2022-11-20 11:51:19,576 INFO L750 eck$LassoCheckResult]: Loop: 20989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21000#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 20989#L378-2 [2022-11-20 11:51:19,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:19,577 INFO L85 PathProgramCache]: Analyzing trace with hash 307442051, now seen corresponding path program 26 times [2022-11-20 11:51:19,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:19,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597204518] [2022-11-20 11:51:19,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:19,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:19,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:20,378 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:20,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:20,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597204518] [2022-11-20 11:51:20,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597204518] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:20,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [614542502] [2022-11-20 11:51:20,379 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:51:20,379 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:20,379 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:20,384 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:20,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-20 11:51:20,578 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:51:20,578 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:20,580 INFO L263 TraceCheckSpWp]: Trace formula consists of 312 conjuncts, 51 conjunts are in the unsatisfiable core [2022-11-20 11:51:20,582 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:20,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:21,105 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:21,106 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:21,117 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:51:21,118 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:51:21,659 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:51:21,661 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:21,661 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:21,951 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:51:21,954 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:51:22,066 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:22,066 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [614542502] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:22,066 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:22,067 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25, 24] total 50 [2022-11-20 11:51:22,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679883743] [2022-11-20 11:51:22,067 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:22,067 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:22,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:22,068 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2022-11-20 11:51:22,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:22,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039064249] [2022-11-20 11:51:22,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:22,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:22,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:22,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:22,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:22,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:22,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:22,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-11-20 11:51:22,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=185, Invalid=2365, Unknown=0, NotChecked=0, Total=2550 [2022-11-20 11:51:22,133 INFO L87 Difference]: Start difference. First operand 82 states and 103 transitions. cyclomatic complexity: 26 Second operand has 51 states, 50 states have (on average 2.24) internal successors, (112), 51 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:23,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:23,232 INFO L93 Difference]: Finished difference Result 100 states and 121 transitions. [2022-11-20 11:51:23,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 121 transitions. [2022-11-20 11:51:23,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:23,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 99 states and 120 transitions. [2022-11-20 11:51:23,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:51:23,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:51:23,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 120 transitions. [2022-11-20 11:51:23,233 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:23,233 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 120 transitions. [2022-11-20 11:51:23,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 120 transitions. [2022-11-20 11:51:23,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 74. [2022-11-20 11:51:23,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.2432432432432432) internal successors, (92), 73 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:23,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 92 transitions. [2022-11-20 11:51:23,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-20 11:51:23,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-20 11:51:23,243 INFO L428 stractBuchiCegarLoop]: Abstraction has 74 states and 92 transitions. [2022-11-20 11:51:23,243 INFO L335 stractBuchiCegarLoop]: ======== Iteration 44 ============ [2022-11-20 11:51:23,243 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 92 transitions. [2022-11-20 11:51:23,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:23,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:23,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:23,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:23,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:23,245 INFO L748 eck$LassoCheckResult]: Stem: 21563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 21564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 21574#L367 assume !(main_~length~0#1 < 1); 21565#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 21566#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 21567#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21575#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21623#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21622#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21621#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21620#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21619#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21618#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21617#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21616#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21615#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21614#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21613#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21611#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21610#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21609#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21608#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21607#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21606#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21604#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21603#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21602#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21600#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21599#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21598#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21596#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21591#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21593#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 21590#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 21588#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 21585#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 21572#L370-4 main_~j~0#1 := 0; 21573#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21578#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21579#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21570#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21571#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21636#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21635#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21634#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21633#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21632#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21631#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21624#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21595#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21594#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21592#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21589#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21587#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21583#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 21582#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21568#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21569#L378-2 [2022-11-20 11:51:23,245 INFO L750 eck$LassoCheckResult]: Loop: 21569#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 21584#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 21569#L378-2 [2022-11-20 11:51:23,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:23,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1336796612, now seen corresponding path program 27 times [2022-11-20 11:51:23,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:23,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161262580] [2022-11-20 11:51:23,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:23,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:23,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:23,923 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:23,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:23,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161262580] [2022-11-20 11:51:23,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161262580] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:23,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [873918941] [2022-11-20 11:51:23,924 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:51:23,924 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:23,925 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:23,937 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:23,938 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-11-20 11:51:24,450 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-11-20 11:51:24,450 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:24,453 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-20 11:51:24,455 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:24,753 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:26,138 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 11:51:26,138 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 11:51:26,142 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 81 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:26,142 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:28,024 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:51:28,028 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:51:28,322 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 72 proven. 163 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:28,322 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [873918941] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:28,322 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:28,322 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26, 26] total 63 [2022-11-20 11:51:28,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069322737] [2022-11-20 11:51:28,323 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:28,323 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:28,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:28,323 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2022-11-20 11:51:28,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:28,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459656600] [2022-11-20 11:51:28,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:28,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:28,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:28,327 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:28,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:28,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:28,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:28,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-11-20 11:51:28,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=3567, Unknown=1, NotChecked=0, Total=4032 [2022-11-20 11:51:28,380 INFO L87 Difference]: Start difference. First operand 74 states and 92 transitions. cyclomatic complexity: 22 Second operand has 64 states, 63 states have (on average 2.111111111111111) internal successors, (133), 64 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:30,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:30,550 INFO L93 Difference]: Finished difference Result 121 states and 143 transitions. [2022-11-20 11:51:30,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 143 transitions. [2022-11-20 11:51:30,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:30,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 98 states and 118 transitions. [2022-11-20 11:51:30,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-20 11:51:30,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-20 11:51:30,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 118 transitions. [2022-11-20 11:51:30,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:30,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98 states and 118 transitions. [2022-11-20 11:51:30,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 118 transitions. [2022-11-20 11:51:30,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 80. [2022-11-20 11:51:30,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.25) internal successors, (100), 79 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:30,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 100 transitions. [2022-11-20 11:51:30,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-20 11:51:30,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-11-20 11:51:30,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 100 transitions. [2022-11-20 11:51:30,563 INFO L335 stractBuchiCegarLoop]: ======== Iteration 45 ============ [2022-11-20 11:51:30,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 100 transitions. [2022-11-20 11:51:30,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:30,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:30,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:30,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:30,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:30,565 INFO L748 eck$LassoCheckResult]: Stem: 22248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22259#L367 assume !(main_~length~0#1 < 1); 22250#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22251#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22252#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22260#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22263#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22261#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22262#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22325#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22322#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22321#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22320#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22317#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22314#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22312#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22311#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22310#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22308#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22307#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22306#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22304#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22303#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22302#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22299#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22300#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22296#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22297#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22273#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22271#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22267#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22268#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22266#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22253#L370-4 main_~j~0#1 := 0; 22254#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22264#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22265#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22257#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22258#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22295#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22294#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22293#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22292#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22291#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22290#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22289#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22288#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22287#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22286#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22285#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22284#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22283#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22282#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22255#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22256#L378-2 [2022-11-20 11:51:30,565 INFO L750 eck$LassoCheckResult]: Loop: 22256#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22280#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22256#L378-2 [2022-11-20 11:51:30,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:30,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1034942650, now seen corresponding path program 28 times [2022-11-20 11:51:30,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:30,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088295446] [2022-11-20 11:51:30,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:30,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:30,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:31,228 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:31,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:31,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088295446] [2022-11-20 11:51:31,228 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088295446] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:31,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [576964452] [2022-11-20 11:51:31,228 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:51:31,228 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:31,228 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:31,230 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:31,232 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-11-20 11:51:31,412 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:51:31,412 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:31,414 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 46 conjunts are in the unsatisfiable core [2022-11-20 11:51:31,415 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:31,501 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:31,970 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2022-11-20 11:51:31,972 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:31,973 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:32,137 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:51:32,139 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:51:32,246 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:32,247 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [576964452] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:32,247 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:32,247 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24] total 37 [2022-11-20 11:51:32,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664290821] [2022-11-20 11:51:32,247 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:32,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:32,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:32,248 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2022-11-20 11:51:32,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:32,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353614819] [2022-11-20 11:51:32,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:32,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:32,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:32,251 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:32,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:32,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:32,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:32,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 11:51:32,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1295, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 11:51:32,311 INFO L87 Difference]: Start difference. First operand 80 states and 100 transitions. cyclomatic complexity: 24 Second operand has 38 states, 37 states have (on average 2.2432432432432434) internal successors, (83), 38 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:33,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:33,096 INFO L93 Difference]: Finished difference Result 117 states and 143 transitions. [2022-11-20 11:51:33,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 143 transitions. [2022-11-20 11:51:33,097 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:51:33,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 116 states and 142 transitions. [2022-11-20 11:51:33,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2022-11-20 11:51:33,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2022-11-20 11:51:33,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 142 transitions. [2022-11-20 11:51:33,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:33,098 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 142 transitions. [2022-11-20 11:51:33,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 142 transitions. [2022-11-20 11:51:33,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 93. [2022-11-20 11:51:33,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.2580645161290323) internal successors, (117), 92 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:33,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 117 transitions. [2022-11-20 11:51:33,101 INFO L240 hiAutomatonCegarLoop]: Abstraction has 93 states and 117 transitions. [2022-11-20 11:51:33,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-20 11:51:33,107 INFO L428 stractBuchiCegarLoop]: Abstraction has 93 states and 117 transitions. [2022-11-20 11:51:33,107 INFO L335 stractBuchiCegarLoop]: ======== Iteration 46 ============ [2022-11-20 11:51:33,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 117 transitions. [2022-11-20 11:51:33,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:33,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:33,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:33,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 10, 10, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:33,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:33,109 INFO L748 eck$LassoCheckResult]: Stem: 22824#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 22825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 22835#L367 assume !(main_~length~0#1 < 1); 22826#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 22827#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 22828#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22836#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22882#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22881#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22880#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22879#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22878#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22877#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22876#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22875#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22874#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22873#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22872#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22870#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22869#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22868#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22867#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22866#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22865#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22863#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22862#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22861#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22859#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22858#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22857#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22855#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22856#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22915#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 22846#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 22845#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 22843#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 22833#L370-4 main_~j~0#1 := 0; 22834#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22909#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22840#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22831#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22832#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22908#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22907#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22906#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22905#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22904#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22903#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22902#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22901#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22900#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22899#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22898#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22897#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22896#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22895#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22893#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 22892#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22829#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22830#L378-2 [2022-11-20 11:51:33,109 INFO L750 eck$LassoCheckResult]: Loop: 22830#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 22894#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 22830#L378-2 [2022-11-20 11:51:33,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:33,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1852529291, now seen corresponding path program 29 times [2022-11-20 11:51:33,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:33,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904664484] [2022-11-20 11:51:33,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:33,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:33,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:33,549 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:33,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:33,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904664484] [2022-11-20 11:51:33,549 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904664484] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:33,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1563051813] [2022-11-20 11:51:33,550 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:51:33,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:33,550 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:33,554 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:33,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-11-20 11:51:33,866 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2022-11-20 11:51:33,866 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:33,869 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-20 11:51:33,870 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:34,230 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:34,522 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 100 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:34,522 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1563051813] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:34,522 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:34,522 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 38 [2022-11-20 11:51:34,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774917310] [2022-11-20 11:51:34,523 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:34,523 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:34,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:34,523 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2022-11-20 11:51:34,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:34,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364320427] [2022-11-20 11:51:34,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:34,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:34,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:34,526 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:34,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:34,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:34,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:34,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-20 11:51:34,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1077, Unknown=0, NotChecked=0, Total=1406 [2022-11-20 11:51:34,576 INFO L87 Difference]: Start difference. First operand 93 states and 117 transitions. cyclomatic complexity: 29 Second operand has 38 states, 38 states have (on average 2.289473684210526) internal successors, (87), 38 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:34,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:51:34,896 INFO L93 Difference]: Finished difference Result 121 states and 146 transitions. [2022-11-20 11:51:34,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 146 transitions. [2022-11-20 11:51:34,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:34,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 99 states and 124 transitions. [2022-11-20 11:51:34,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:51:34,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:51:34,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 124 transitions. [2022-11-20 11:51:34,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:51:34,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 124 transitions. [2022-11-20 11:51:34,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 124 transitions. [2022-11-20 11:51:34,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 90. [2022-11-20 11:51:34,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.2555555555555555) internal successors, (113), 89 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:51:34,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 113 transitions. [2022-11-20 11:51:34,900 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-20 11:51:34,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-20 11:51:34,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 90 states and 113 transitions. [2022-11-20 11:51:34,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 47 ============ [2022-11-20 11:51:34,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 113 transitions. [2022-11-20 11:51:34,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:51:34,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:51:34,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:51:34,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 9, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:51:34,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:51:34,910 INFO L748 eck$LassoCheckResult]: Stem: 23451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 23452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 23462#L367 assume !(main_~length~0#1 < 1); 23453#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 23454#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 23455#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23463#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23532#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23531#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23530#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23529#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23528#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23527#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23526#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23525#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23524#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23523#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23522#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23521#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23520#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23519#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23518#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23517#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23516#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23514#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23510#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23509#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23508#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23506#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23505#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23504#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23502#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 23503#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23498#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23493#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 23489#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 23469#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 23456#L370-4 main_~j~0#1 := 0; 23457#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23467#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23488#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23487#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23486#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23485#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23484#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23483#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23482#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23481#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23480#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23479#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23478#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23477#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23476#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23475#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23474#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23472#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 23471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23458#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23459#L378-2 [2022-11-20 11:51:34,910 INFO L750 eck$LassoCheckResult]: Loop: 23459#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 23473#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 23459#L378-2 [2022-11-20 11:51:34,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:34,911 INFO L85 PathProgramCache]: Analyzing trace with hash -838679536, now seen corresponding path program 30 times [2022-11-20 11:51:34,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:34,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117364729] [2022-11-20 11:51:34,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:34,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:34,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:51:35,822 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:35,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:51:35,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117364729] [2022-11-20 11:51:35,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117364729] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:51:35,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [935997099] [2022-11-20 11:51:35,823 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:51:35,823 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:51:35,823 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:51:35,827 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:51:35,843 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-11-20 11:51:37,016 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-20 11:51:37,016 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:51:37,020 INFO L263 TraceCheckSpWp]: Trace formula consists of 345 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-20 11:51:37,024 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:51:37,343 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:51:37,956 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 11:51:37,956 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 34 [2022-11-20 11:51:38,054 INFO L321 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-11-20 11:51:38,055 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 47 [2022-11-20 11:51:41,250 INFO L321 Elim1Store]: treesize reduction 12, result has 67.6 percent of original size [2022-11-20 11:51:41,251 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 34 treesize of output 34 [2022-11-20 11:51:41,284 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 81 proven. 185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:51:41,284 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:51:55,988 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:51:55,991 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:51:56,299 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 72 proven. 192 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-20 11:51:56,299 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [935997099] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:51:56,299 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:51:56,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 29, 26] total 67 [2022-11-20 11:51:56,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094512424] [2022-11-20 11:51:56,299 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:51:56,300 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:51:56,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:51:56,300 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2022-11-20 11:51:56,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:51:56,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463501091] [2022-11-20 11:51:56,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:51:56,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:51:56,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:56,303 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:51:56,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:51:56,307 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:51:56,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:51:56,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2022-11-20 11:51:56,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=511, Invalid=4044, Unknown=1, NotChecked=0, Total=4556 [2022-11-20 11:51:56,360 INFO L87 Difference]: Start difference. First operand 90 states and 113 transitions. cyclomatic complexity: 28 Second operand has 68 states, 67 states have (on average 2.1044776119402986) internal successors, (141), 68 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:09,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:09,454 INFO L93 Difference]: Finished difference Result 174 states and 204 transitions. [2022-11-20 11:52:09,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 204 transitions. [2022-11-20 11:52:09,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:52:09,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 127 states and 155 transitions. [2022-11-20 11:52:09,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-11-20 11:52:09,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-11-20 11:52:09,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 155 transitions. [2022-11-20 11:52:09,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:09,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 155 transitions. [2022-11-20 11:52:09,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 155 transitions. [2022-11-20 11:52:09,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 73. [2022-11-20 11:52:09,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2465753424657535) internal successors, (91), 72 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:09,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 91 transitions. [2022-11-20 11:52:09,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 91 transitions. [2022-11-20 11:52:09,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-11-20 11:52:09,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 73 states and 91 transitions. [2022-11-20 11:52:09,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 48 ============ [2022-11-20 11:52:09,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 91 transitions. [2022-11-20 11:52:09,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:09,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:09,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:09,466 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:09,466 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:09,467 INFO L748 eck$LassoCheckResult]: Stem: 24273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24284#L367 assume !(main_~length~0#1 < 1); 24275#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24276#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24277#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24285#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24288#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24286#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24287#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24345#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24344#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24343#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24342#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24341#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24340#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24339#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24338#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24337#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24336#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24335#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24334#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24333#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24332#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24331#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24330#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24329#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24328#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24327#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24326#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24325#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24324#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24323#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24322#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24321#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24320#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24319#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24294#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24292#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 24278#L370-4 main_~j~0#1 := 0; 24279#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24282#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24283#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24289#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24312#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24311#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24310#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24309#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24308#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24307#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24306#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24305#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24304#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24303#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24302#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24301#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24300#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24299#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24298#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24296#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24295#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24280#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24281#L378-2 [2022-11-20 11:52:09,467 INFO L750 eck$LassoCheckResult]: Loop: 24281#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24297#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 24281#L378-2 [2022-11-20 11:52:09,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:09,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485871, now seen corresponding path program 11 times [2022-11-20 11:52:09,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:09,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299932591] [2022-11-20 11:52:09,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:09,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:09,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:10,317 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:10,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:10,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299932591] [2022-11-20 11:52:10,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299932591] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:10,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1359073000] [2022-11-20 11:52:10,317 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:52:10,318 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:10,318 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:10,350 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:10,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-11-20 11:52:10,690 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2022-11-20 11:52:10,690 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:10,693 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-20 11:52:10,695 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:11,161 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-11-20 11:52:12,020 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:52:12,022 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:52:12,022 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:52:12,025 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:12,025 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:12,297 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2022-11-20 11:52:12,300 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 20 [2022-11-20 11:52:12,394 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:12,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1359073000] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:12,394 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:12,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 27] total 56 [2022-11-20 11:52:12,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350688929] [2022-11-20 11:52:12,395 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:12,395 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:12,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:12,395 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2022-11-20 11:52:12,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:12,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419937633] [2022-11-20 11:52:12,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:12,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:12,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:12,419 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:12,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:12,421 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:12,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:12,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2022-11-20 11:52:12,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=2980, Unknown=0, NotChecked=0, Total=3192 [2022-11-20 11:52:12,465 INFO L87 Difference]: Start difference. First operand 73 states and 91 transitions. cyclomatic complexity: 23 Second operand has 57 states, 56 states have (on average 2.25) internal successors, (126), 57 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:13,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:13,815 INFO L93 Difference]: Finished difference Result 149 states and 183 transitions. [2022-11-20 11:52:13,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 183 transitions. [2022-11-20 11:52:13,816 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 25 [2022-11-20 11:52:13,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 148 states and 182 transitions. [2022-11-20 11:52:13,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2022-11-20 11:52:13,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2022-11-20 11:52:13,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 182 transitions. [2022-11-20 11:52:13,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:13,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148 states and 182 transitions. [2022-11-20 11:52:13,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 182 transitions. [2022-11-20 11:52:13,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 124. [2022-11-20 11:52:13,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.2580645161290323) internal successors, (156), 123 states have internal predecessors, (156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:13,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 156 transitions. [2022-11-20 11:52:13,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 156 transitions. [2022-11-20 11:52:13,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-20 11:52:13,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 156 transitions. [2022-11-20 11:52:13,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 49 ============ [2022-11-20 11:52:13,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 156 transitions. [2022-11-20 11:52:13,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2022-11-20 11:52:13,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:13,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:13,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:13,830 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2022-11-20 11:52:13,831 INFO L748 eck$LassoCheckResult]: Stem: 24929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 24930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 24940#L367 assume !(main_~length~0#1 < 1); 24931#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 24932#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 24933#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24941#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24947#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24942#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24943#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24944#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24979#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24978#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24977#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24976#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24975#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24974#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24973#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24972#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24971#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24970#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24969#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24968#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24967#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24966#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24965#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24964#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24963#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24962#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24961#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24960#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24959#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 24958#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 24956#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 24957#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25014#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25012#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25011#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25010#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25009#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25007#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25006#L370-4 main_~j~0#1 := 0; 25005#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25004#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25003#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25002#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25001#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25000#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24999#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24998#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24997#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24996#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24995#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24994#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24990#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24988#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 24980#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 24982#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25034#L378-2 [2022-11-20 11:52:13,831 INFO L750 eck$LassoCheckResult]: Loop: 25034#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25036#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25035#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25033#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25034#L378-2 [2022-11-20 11:52:13,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:13,832 INFO L85 PathProgramCache]: Analyzing trace with hash -696609148, now seen corresponding path program 31 times [2022-11-20 11:52:13,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:13,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297690804] [2022-11-20 11:52:13,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:13,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:13,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:14,721 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:14,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:14,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297690804] [2022-11-20 11:52:14,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297690804] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:14,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522994552] [2022-11-20 11:52:14,722 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-20 11:52:14,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:14,722 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:14,726 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:14,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-11-20 11:52:14,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:14,923 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-20 11:52:14,925 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:15,350 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:15,498 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:52:15,509 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:52:15,568 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2022-11-20 11:52:16,206 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:52:16,209 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:16,209 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:16,720 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 29 [2022-11-20 11:52:16,724 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 129 [2022-11-20 11:52:16,830 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:16,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [522994552] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:16,830 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:16,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28, 28] total 58 [2022-11-20 11:52:16,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878606702] [2022-11-20 11:52:16,830 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:16,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:16,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:16,831 INFO L85 PathProgramCache]: Analyzing trace with hash 2221257, now seen corresponding path program 6 times [2022-11-20 11:52:16,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:16,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751326937] [2022-11-20 11:52:16,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:16,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:16,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:16,835 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:16,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:16,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:16,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:16,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-20 11:52:16,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=3190, Unknown=0, NotChecked=0, Total=3422 [2022-11-20 11:52:16,924 INFO L87 Difference]: Start difference. First operand 124 states and 156 transitions. cyclomatic complexity: 39 Second operand has 59 states, 58 states have (on average 2.2586206896551726) internal successors, (131), 59 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:19,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:19,033 INFO L93 Difference]: Finished difference Result 156 states and 181 transitions. [2022-11-20 11:52:19,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156 states and 181 transitions. [2022-11-20 11:52:19,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-11-20 11:52:19,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156 states to 154 states and 179 transitions. [2022-11-20 11:52:19,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-11-20 11:52:19,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-11-20 11:52:19,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154 states and 179 transitions. [2022-11-20 11:52:19,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:19,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154 states and 179 transitions. [2022-11-20 11:52:19,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states and 179 transitions. [2022-11-20 11:52:19,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 78. [2022-11-20 11:52:19,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2435897435897436) internal successors, (97), 77 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:19,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 97 transitions. [2022-11-20 11:52:19,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 97 transitions. [2022-11-20 11:52:19,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-11-20 11:52:19,043 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 97 transitions. [2022-11-20 11:52:19,043 INFO L335 stractBuchiCegarLoop]: ======== Iteration 50 ============ [2022-11-20 11:52:19,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 97 transitions. [2022-11-20 11:52:19,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:19,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:19,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:19,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:19,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:19,046 INFO L748 eck$LassoCheckResult]: Stem: 25695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 25696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 25706#L367 assume !(main_~length~0#1 < 1); 25697#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 25698#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 25699#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25707#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25712#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25708#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25709#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25772#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25771#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25770#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25769#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25768#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25767#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25766#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25765#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25764#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25763#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25762#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25761#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25760#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25759#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25758#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25757#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25756#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25755#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25754#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25753#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25752#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25751#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25750#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25749#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25748#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25747#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 25737#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 25722#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 25719#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 25704#L370-4 main_~j~0#1 := 0; 25705#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25702#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25703#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25711#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25735#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25734#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25733#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25732#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25731#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25730#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25729#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25728#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25727#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25726#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25725#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25724#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25723#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25721#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25718#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25717#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25716#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25714#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 25713#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25700#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25701#L378-2 [2022-11-20 11:52:19,046 INFO L750 eck$LassoCheckResult]: Loop: 25701#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 25715#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 25701#L378-2 [2022-11-20 11:52:19,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:19,048 INFO L85 PathProgramCache]: Analyzing trace with hash 921784534, now seen corresponding path program 12 times [2022-11-20 11:52:19,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:19,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352158318] [2022-11-20 11:52:19,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:19,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:19,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:19,510 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:19,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:19,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352158318] [2022-11-20 11:52:19,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352158318] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:19,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [247945956] [2022-11-20 11:52:19,511 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:52:19,511 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:19,511 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:19,512 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:19,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-11-20 11:52:20,551 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-11-20 11:52:20,551 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:20,553 INFO L263 TraceCheckSpWp]: Trace formula consists of 319 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-20 11:52:20,555 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:20,987 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:20,987 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:21,320 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:21,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [247945956] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:21,320 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:21,320 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 41 [2022-11-20 11:52:21,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535248026] [2022-11-20 11:52:21,321 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:21,321 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:21,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:21,321 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2022-11-20 11:52:21,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:21,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108360254] [2022-11-20 11:52:21,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:21,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:21,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:21,325 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:21,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:21,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:21,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:21,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-11-20 11:52:21,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=1258, Unknown=0, NotChecked=0, Total=1640 [2022-11-20 11:52:21,374 INFO L87 Difference]: Start difference. First operand 78 states and 97 transitions. cyclomatic complexity: 24 Second operand has 41 states, 41 states have (on average 2.317073170731707) internal successors, (95), 41 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:21,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:21,717 INFO L93 Difference]: Finished difference Result 108 states and 128 transitions. [2022-11-20 11:52:21,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 128 transitions. [2022-11-20 11:52:21,718 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:21,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 84 states and 104 transitions. [2022-11-20 11:52:21,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:52:21,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:52:21,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 104 transitions. [2022-11-20 11:52:21,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:21,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84 states and 104 transitions. [2022-11-20 11:52:21,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 104 transitions. [2022-11-20 11:52:21,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 80. [2022-11-20 11:52:21,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2375) internal successors, (99), 79 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:21,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 99 transitions. [2022-11-20 11:52:21,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 99 transitions. [2022-11-20 11:52:21,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-11-20 11:52:21,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 99 transitions. [2022-11-20 11:52:21,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 51 ============ [2022-11-20 11:52:21,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 99 transitions. [2022-11-20 11:52:21,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:21,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:21,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:21,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:21,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:21,725 INFO L748 eck$LassoCheckResult]: Stem: 26329#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26340#L367 assume !(main_~length~0#1 < 1); 26331#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26332#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26333#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26341#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26344#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26408#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26407#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26406#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26405#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26404#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26403#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26402#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26401#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26400#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26399#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26398#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26397#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26396#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26395#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26394#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26393#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26392#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26391#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26390#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26389#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26388#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26387#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26386#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26385#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26384#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26383#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26382#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26381#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26380#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26346#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26342#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26343#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26369#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26347#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26334#L370-4 main_~j~0#1 := 0; 26335#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26345#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26368#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26367#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26366#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26365#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26364#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26363#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26362#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26361#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26360#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26359#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26358#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26357#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26356#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26355#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26354#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26353#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26352#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26350#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26349#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26336#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26337#L378-2 [2022-11-20 11:52:21,725 INFO L750 eck$LassoCheckResult]: Loop: 26337#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26351#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26337#L378-2 [2022-11-20 11:52:21,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:21,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1897673997, now seen corresponding path program 32 times [2022-11-20 11:52:21,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:21,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895297824] [2022-11-20 11:52:21,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:21,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:21,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:22,712 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:22,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:22,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895297824] [2022-11-20 11:52:22,712 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895297824] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:22,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1570520113] [2022-11-20 11:52:22,713 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-20 11:52:22,713 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:22,713 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:22,718 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:22,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2022-11-20 11:52:22,954 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-20 11:52:22,955 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:22,957 INFO L263 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 59 conjunts are in the unsatisfiable core [2022-11-20 11:52:22,967 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:23,493 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:23,648 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:52:23,649 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:52:23,661 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:52:23,662 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:52:24,393 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-11-20 11:52:24,395 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:24,395 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:24,720 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:52:24,724 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:52:24,825 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:24,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1570520113] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:24,825 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:24,825 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29, 28] total 58 [2022-11-20 11:52:24,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809000395] [2022-11-20 11:52:24,825 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:24,826 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:24,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:24,826 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2022-11-20 11:52:24,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:24,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035646234] [2022-11-20 11:52:24,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:24,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:24,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:24,828 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:24,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:24,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:24,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:24,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-11-20 11:52:24,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=3209, Unknown=0, NotChecked=0, Total=3422 [2022-11-20 11:52:24,874 INFO L87 Difference]: Start difference. First operand 80 states and 99 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:26,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:26,578 INFO L93 Difference]: Finished difference Result 102 states and 121 transitions. [2022-11-20 11:52:26,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 121 transitions. [2022-11-20 11:52:26,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:26,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 101 states and 120 transitions. [2022-11-20 11:52:26,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:52:26,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:52:26,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 120 transitions. [2022-11-20 11:52:26,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:26,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 120 transitions. [2022-11-20 11:52:26,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 120 transitions. [2022-11-20 11:52:26,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 72. [2022-11-20 11:52:26,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2222222222222223) internal successors, (88), 71 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:26,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 88 transitions. [2022-11-20 11:52:26,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72 states and 88 transitions. [2022-11-20 11:52:26,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2022-11-20 11:52:26,582 INFO L428 stractBuchiCegarLoop]: Abstraction has 72 states and 88 transitions. [2022-11-20 11:52:26,582 INFO L335 stractBuchiCegarLoop]: ======== Iteration 52 ============ [2022-11-20 11:52:26,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 88 transitions. [2022-11-20 11:52:26,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:26,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:26,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:26,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:26,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:26,584 INFO L748 eck$LassoCheckResult]: Stem: 26983#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 26984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 26994#L367 assume !(main_~length~0#1 < 1); 26985#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 26986#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 26987#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26995#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 26998#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27041#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27040#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27039#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27038#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27037#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27036#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27035#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27034#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27033#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27032#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27031#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27030#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27029#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27028#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27027#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27026#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27025#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27024#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27023#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27022#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27021#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27020#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27019#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27018#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27017#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27016#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27015#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27014#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27013#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27001#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 26996#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 26997#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27008#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27002#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 26988#L370-4 main_~j~0#1 := 0; 26989#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26999#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27000#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26992#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 26993#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27054#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27053#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27052#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27051#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27050#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27049#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27048#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27047#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27046#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27045#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27044#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27043#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27042#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27010#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27009#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27007#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27005#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27004#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 26990#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26991#L378-2 [2022-11-20 11:52:26,584 INFO L750 eck$LassoCheckResult]: Loop: 26991#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27006#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 26991#L378-2 [2022-11-20 11:52:26,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:26,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1387507918, now seen corresponding path program 33 times [2022-11-20 11:52:26,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:26,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082333849] [2022-11-20 11:52:26,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:26,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:26,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:27,468 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:27,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:27,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082333849] [2022-11-20 11:52:27,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082333849] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:27,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1747485727] [2022-11-20 11:52:27,469 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-20 11:52:27,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:27,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:27,473 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:27,493 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-11-20 11:52:28,227 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2022-11-20 11:52:28,227 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:28,232 INFO L263 TraceCheckSpWp]: Trace formula consists of 341 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-20 11:52:28,234 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:28,654 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:30,559 INFO L321 Elim1Store]: treesize reduction 9, result has 25.0 percent of original size [2022-11-20 11:52:30,559 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 10 [2022-11-20 11:52:30,562 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 121 proven. 221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:30,563 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:32,390 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:52:32,394 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2022-11-20 11:52:32,822 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 110 proven. 232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:32,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1747485727] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:32,822 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:32,822 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 30, 30] total 73 [2022-11-20 11:52:32,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043101232] [2022-11-20 11:52:32,823 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:32,823 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:32,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:32,823 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2022-11-20 11:52:32,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:32,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880373427] [2022-11-20 11:52:32,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:32,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:32,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:32,827 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:32,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:32,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:32,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:32,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2022-11-20 11:52:32,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=607, Invalid=4795, Unknown=0, NotChecked=0, Total=5402 [2022-11-20 11:52:32,878 INFO L87 Difference]: Start difference. First operand 72 states and 88 transitions. cyclomatic complexity: 20 Second operand has 74 states, 73 states have (on average 2.1506849315068495) internal successors, (157), 74 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:36,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:36,025 INFO L93 Difference]: Finished difference Result 127 states and 147 transitions. [2022-11-20 11:52:36,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127 states and 147 transitions. [2022-11-20 11:52:36,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:36,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127 states to 100 states and 118 transitions. [2022-11-20 11:52:36,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2022-11-20 11:52:36,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2022-11-20 11:52:36,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 118 transitions. [2022-11-20 11:52:36,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:36,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 118 transitions. [2022-11-20 11:52:36,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 118 transitions. [2022-11-20 11:52:36,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 78. [2022-11-20 11:52:36,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 77 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:36,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 96 transitions. [2022-11-20 11:52:36,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78 states and 96 transitions. [2022-11-20 11:52:36,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-11-20 11:52:36,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 78 states and 96 transitions. [2022-11-20 11:52:36,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 53 ============ [2022-11-20 11:52:36,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 96 transitions. [2022-11-20 11:52:36,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:36,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:36,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:36,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 11, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:36,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:36,031 INFO L748 eck$LassoCheckResult]: Stem: 27762#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 27763#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 27773#L367 assume !(main_~length~0#1 < 1); 27764#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 27765#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 27766#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27774#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27777#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27775#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27776#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27839#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27838#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27837#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27836#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27835#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27834#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27833#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27832#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27831#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27830#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27829#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27828#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27827#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27826#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27825#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27824#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27823#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27822#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27821#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27820#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27819#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27818#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27817#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27816#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27815#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27795#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27794#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27793#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27791#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27789#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27784#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27786#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 27783#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 27782#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 27780#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 27767#L370-4 main_~j~0#1 := 0; 27768#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27778#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27779#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27771#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27772#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27814#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27813#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27812#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27811#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27810#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27809#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27808#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27807#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27806#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27805#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27804#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27803#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27802#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27801#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27800#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27799#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27798#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 27797#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27769#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 27770#L378-2 [2022-11-20 11:52:36,031 INFO L750 eck$LassoCheckResult]: Loop: 27770#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 27796#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 27770#L378-2 [2022-11-20 11:52:36,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:36,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1286492714, now seen corresponding path program 34 times [2022-11-20 11:52:36,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:36,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739955750] [2022-11-20 11:52:36,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:36,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:36,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:36,969 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:36,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:36,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739955750] [2022-11-20 11:52:36,970 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739955750] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:36,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1783969608] [2022-11-20 11:52:36,970 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-20 11:52:36,970 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:36,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:36,980 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:36,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2022-11-20 11:52:37,273 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-20 11:52:37,273 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:37,275 INFO L263 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 56 conjunts are in the unsatisfiable core [2022-11-20 11:52:37,279 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:37,398 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:37,513 INFO L321 Elim1Store]: treesize reduction 29, result has 27.5 percent of original size [2022-11-20 11:52:37,513 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 26 [2022-11-20 11:52:38,494 INFO L321 Elim1Store]: treesize reduction 7, result has 30.0 percent of original size [2022-11-20 11:52:38,494 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 10 [2022-11-20 11:52:38,533 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:38,533 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:43,506 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 21 [2022-11-20 11:52:43,510 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 130 treesize of output 122 [2022-11-20 11:52:43,638 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:43,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1783969608] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:43,638 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:43,638 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 60 [2022-11-20 11:52:43,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773720630] [2022-11-20 11:52:43,639 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:43,639 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:43,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:43,639 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2022-11-20 11:52:43,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:43,639 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16699174] [2022-11-20 11:52:43,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:43,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:43,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:43,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:43,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:43,645 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:43,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:43,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-11-20 11:52:43,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=198, Invalid=3461, Unknown=1, NotChecked=0, Total=3660 [2022-11-20 11:52:43,690 INFO L87 Difference]: Start difference. First operand 78 states and 96 transitions. cyclomatic complexity: 22 Second operand has 61 states, 60 states have (on average 2.183333333333333) internal successors, (131), 61 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:45,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:45,497 INFO L93 Difference]: Finished difference Result 112 states and 133 transitions. [2022-11-20 11:52:45,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 133 transitions. [2022-11-20 11:52:45,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:45,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 111 states and 132 transitions. [2022-11-20 11:52:45,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:52:45,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:52:45,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 132 transitions. [2022-11-20 11:52:45,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:45,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111 states and 132 transitions. [2022-11-20 11:52:45,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 132 transitions. [2022-11-20 11:52:45,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 90. [2022-11-20 11:52:45,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.2333333333333334) internal successors, (111), 89 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:45,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 111 transitions. [2022-11-20 11:52:45,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90 states and 111 transitions. [2022-11-20 11:52:45,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-11-20 11:52:45,508 INFO L428 stractBuchiCegarLoop]: Abstraction has 90 states and 111 transitions. [2022-11-20 11:52:45,508 INFO L335 stractBuchiCegarLoop]: ======== Iteration 54 ============ [2022-11-20 11:52:45,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 111 transitions. [2022-11-20 11:52:45,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:45,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:45,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:45,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:45,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:45,510 INFO L748 eck$LassoCheckResult]: Stem: 28456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 28457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 28467#L367 assume !(main_~length~0#1 < 1); 28458#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 28459#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 28460#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28468#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28525#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28524#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28523#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28522#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28521#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28520#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28519#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28518#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28517#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28516#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28515#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28514#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28513#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28512#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28511#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28510#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28509#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28508#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28507#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28506#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28505#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28504#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28503#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28502#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28501#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28500#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28499#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28498#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28497#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28495#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28494#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28493#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28492#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28475#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28469#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 28470#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 28484#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 28542#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 28541#L370-4 main_~j~0#1 := 0; 28471#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28463#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28464#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28539#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28538#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28537#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28536#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28535#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28534#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28533#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28532#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28531#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28530#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28529#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28528#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28526#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28491#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28489#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28487#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28482#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28480#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28477#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 28476#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28461#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 28462#L378-2 [2022-11-20 11:52:45,510 INFO L750 eck$LassoCheckResult]: Loop: 28462#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 28478#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 28462#L378-2 [2022-11-20 11:52:45,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:45,511 INFO L85 PathProgramCache]: Analyzing trace with hash -584892840, now seen corresponding path program 35 times [2022-11-20 11:52:45,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:45,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164530533] [2022-11-20 11:52:45,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:45,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:45,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:46,552 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:46,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:46,552 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164530533] [2022-11-20 11:52:46,553 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164530533] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:46,553 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1098624736] [2022-11-20 11:52:46,553 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-20 11:52:46,553 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:46,553 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:46,555 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:46,556 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2022-11-20 11:52:47,097 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2022-11-20 11:52:47,097 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:47,102 INFO L263 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-20 11:52:47,104 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:47,683 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:47,844 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-11-20 11:52:47,844 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2022-11-20 11:52:48,791 INFO L173 IndexEqualityManager]: detected equality via solver [2022-11-20 11:52:48,793 INFO L321 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-11-20 11:52:48,793 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 10 [2022-11-20 11:52:48,796 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:48,797 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:52:49,204 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 19 [2022-11-20 11:52:49,206 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 25 [2022-11-20 11:52:49,314 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:49,314 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1098624736] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:52:49,314 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:52:49,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 32, 31] total 64 [2022-11-20 11:52:49,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136669595] [2022-11-20 11:52:49,314 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:52:49,315 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:52:49,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:49,315 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2022-11-20 11:52:49,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:49,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242140781] [2022-11-20 11:52:49,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:49,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:49,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:49,318 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:52:49,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:52:49,322 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:52:49,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:52:49,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2022-11-20 11:52:49,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=239, Invalid=3921, Unknown=0, NotChecked=0, Total=4160 [2022-11-20 11:52:49,366 INFO L87 Difference]: Start difference. First operand 90 states and 111 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.21875) internal successors, (142), 65 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:51,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:52:51,354 INFO L93 Difference]: Finished difference Result 114 states and 135 transitions. [2022-11-20 11:52:51,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114 states and 135 transitions. [2022-11-20 11:52:51,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:51,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114 states to 113 states and 134 transitions. [2022-11-20 11:52:51,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2022-11-20 11:52:51,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2022-11-20 11:52:51,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 134 transitions. [2022-11-20 11:52:51,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-11-20 11:52:51,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 113 states and 134 transitions. [2022-11-20 11:52:51,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 134 transitions. [2022-11-20 11:52:51,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 80. [2022-11-20 11:52:51,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.225) internal successors, (98), 79 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:52:51,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 98 transitions. [2022-11-20 11:52:51,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-20 11:52:51,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-11-20 11:52:51,363 INFO L428 stractBuchiCegarLoop]: Abstraction has 80 states and 98 transitions. [2022-11-20 11:52:51,363 INFO L335 stractBuchiCegarLoop]: ======== Iteration 55 ============ [2022-11-20 11:52:51,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 98 transitions. [2022-11-20 11:52:51,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-11-20 11:52:51,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-20 11:52:51,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-20 11:52:51,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-20 11:52:51,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-11-20 11:52:51,365 INFO L748 eck$LassoCheckResult]: Stem: 29170#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 29171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet208#1, main_#t~mem209#1, main_#t~post207#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1; 29181#L367 assume !(main_~length~0#1 < 1); 29172#L367-2 call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset; 29173#L369 assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0; 29174#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29182#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29185#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29183#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29184#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29235#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29234#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29233#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29232#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29231#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29230#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29229#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29228#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29227#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29226#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29225#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29224#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29223#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29222#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29221#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29220#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29219#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29218#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29217#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29216#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29215#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29214#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29213#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29212#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29211#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29210#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29209#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29208#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29206#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29204#L372 assume main_#t~mem209#1 > 0;havoc main_#t~mem209#1;call write~int(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29196#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29199#L370-3 assume !!(main_~i~0#1 < main_~length~0#1);call write~int(main_#t~nondet208#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet208#1;call main_#t~mem209#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4); 29195#L372 assume !(main_#t~mem209#1 > 0);havoc main_#t~mem209#1; 29193#L370-2 main_#t~post207#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post207#1;havoc main_#t~post207#1; 29188#L370-3 assume !(main_~i~0#1 < main_~length~0#1); 29175#L370-4 main_~j~0#1 := 0; 29176#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29186#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29187#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29179#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29180#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29249#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29248#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29247#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29246#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29245#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29244#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29243#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29242#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29241#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29240#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29239#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29238#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29237#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29236#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29202#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29200#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29197#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29194#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29192#L378 assume !(main_#t~mem210#1 > 0);havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post212#1;havoc main_#t~post212#1; 29191#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29177#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 29178#L378-2 [2022-11-20 11:52:51,366 INFO L750 eck$LassoCheckResult]: Loop: 29178#L378-2 assume !!(0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1);call main_#t~mem210#1 := read~int(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4); 29190#L378 assume main_#t~mem210#1 > 0;havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := main_#t~post211#1 - 1;havoc main_#t~post211#1; 29178#L378-2 [2022-11-20 11:52:51,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:52:51,369 INFO L85 PathProgramCache]: Analyzing trace with hash 631086363, now seen corresponding path program 36 times [2022-11-20 11:52:51,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:52:51,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810036657] [2022-11-20 11:52:51,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:52:51,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:52:51,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-20 11:52:52,330 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:52:52,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-20 11:52:52,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810036657] [2022-11-20 11:52:52,331 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810036657] provided 0 perfect and 1 imperfect interpolant sequences [2022-11-20 11:52:52,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041786085] [2022-11-20 11:52:52,331 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-20 11:52:52,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-20 11:52:52,331 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 [2022-11-20 11:52:52,338 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-20 11:52:52,354 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2022-11-20 11:52:53,138 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2022-11-20 11:52:53,139 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-20 11:52:53,142 INFO L263 TraceCheckSpWp]: Trace formula consists of 374 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-20 11:52:53,145 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-20 11:52:53,559 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-11-20 11:52:53,656 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:52:53,663 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-11-20 11:52:54,904 INFO L321 Elim1Store]: treesize reduction 43, result has 49.4 percent of original size [2022-11-20 11:52:54,904 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 39 treesize of output 59 [2022-11-20 11:53:02,066 INFO L321 Elim1Store]: treesize reduction 113, result has 65.7 percent of original size [2022-11-20 11:53:02,066 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 125 treesize of output 273 [2022-11-20 11:53:02,358 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 144 proven. 259 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-20 11:53:02,358 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-20 11:53:05,142 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2022-11-20 11:53:05,145 INFO L350 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 20 [2022-11-20 11:53:05,651 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 132 proven. 265 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-20 11:53:05,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041786085] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-20 11:53:05,651 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-11-20 11:53:05,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 34, 30] total 82 [2022-11-20 11:53:05,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160204697] [2022-11-20 11:53:05,651 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-11-20 11:53:05,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-20 11:53:05,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-20 11:53:05,652 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2022-11-20 11:53:05,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-20 11:53:05,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253189226] [2022-11-20 11:53:05,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-20 11:53:05,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-20 11:53:05,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:53:05,655 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-20 11:53:05,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-20 11:53:05,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-20 11:53:05,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-20 11:53:05,703 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2022-11-20 11:53:05,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=737, Invalid=6068, Unknown=1, NotChecked=0, Total=6806 [2022-11-20 11:53:05,703 INFO L87 Difference]: Start difference. First operand 80 states and 98 transitions. cyclomatic complexity: 22 Second operand has 83 states, 82 states have (on average 2.182926829268293) internal successors, (179), 83 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-20 11:54:01,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-20 11:54:01,959 INFO L93 Difference]: Finished difference Result 233 states and 275 transitions. [2022-11-20 11:54:01,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 275 transitions. [2022-11-20 11:54:01,959 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2022-11-20 11:54:01,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 0 states and 0 transitions. [2022-11-20 11:54:01,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2022-11-20 11:54:01,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2022-11-20 11:54:01,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2022-11-20 11:54:01,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-20 11:54:01,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-20 11:54:01,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-20 11:54:01,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2022-11-20 11:54:01,960 INFO L428 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2022-11-20 11:54:01,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 56 ============ [2022-11-20 11:54:01,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2022-11-20 11:54:01,961 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2022-11-20 11:54:01,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2022-11-20 11:54:01,967 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 20.11 11:54:01 BoogieIcfgContainer [2022-11-20 11:54:01,967 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-20 11:54:01,968 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-20 11:54:01,968 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-20 11:54:01,968 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-20 11:54:01,969 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 11:49:07" (3/4) ... [2022-11-20 11:54:01,972 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-20 11:54:01,972 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-20 11:54:01,973 INFO L158 Benchmark]: Toolchain (without parser) took 295203.12ms. Allocated memory was 144.7MB in the beginning and 539.0MB in the end (delta: 394.3MB). Free memory was 115.5MB in the beginning and 311.7MB in the end (delta: -196.2MB). Peak memory consumption was 199.6MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,973 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 113.2MB. Free memory is still 79.8MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-20 11:54:01,973 INFO L158 Benchmark]: CACSL2BoogieTranslator took 460.21ms. Allocated memory is still 144.7MB. Free memory was 115.5MB in the beginning and 98.3MB in the end (delta: 17.2MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,973 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.98ms. Allocated memory is still 144.7MB. Free memory was 98.3MB in the beginning and 96.2MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,974 INFO L158 Benchmark]: Boogie Preprocessor took 22.69ms. Allocated memory is still 144.7MB. Free memory was 96.2MB in the beginning and 94.7MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,974 INFO L158 Benchmark]: RCFGBuilder took 266.37ms. Allocated memory is still 144.7MB. Free memory was 94.7MB in the beginning and 84.3MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,974 INFO L158 Benchmark]: BuchiAutomizer took 294401.43ms. Allocated memory was 144.7MB in the beginning and 539.0MB in the end (delta: 394.3MB). Free memory was 84.3MB in the beginning and 312.7MB in the end (delta: -228.5MB). Peak memory consumption was 166.0MB. Max. memory is 16.1GB. [2022-11-20 11:54:01,975 INFO L158 Benchmark]: Witness Printer took 4.25ms. Allocated memory is still 539.0MB. Free memory was 312.7MB in the beginning and 311.7MB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-20 11:54:01,976 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 113.2MB. Free memory is still 79.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 460.21ms. Allocated memory is still 144.7MB. Free memory was 115.5MB in the beginning and 98.3MB in the end (delta: 17.2MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 39.98ms. Allocated memory is still 144.7MB. Free memory was 98.3MB in the beginning and 96.2MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 22.69ms. Allocated memory is still 144.7MB. Free memory was 96.2MB in the beginning and 94.7MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 266.37ms. Allocated memory is still 144.7MB. Free memory was 94.7MB in the beginning and 84.3MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 294401.43ms. Allocated memory was 144.7MB in the beginning and 539.0MB in the end (delta: 394.3MB). Free memory was 84.3MB in the beginning and 312.7MB in the end (delta: -228.5MB). Peak memory consumption was 166.0MB. Max. memory is 16.1GB. * Witness Printer took 4.25ms. Allocated memory is still 539.0MB. Free memory was 312.7MB in the beginning and 311.7MB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 55 terminating modules (53 trivial, 2 deterministic, 0 nondeterministic). One deterministic module has affine ranking function -4 * i + unknown-#length-unknown[arr] + -1 * arr and consists of 5 locations. One deterministic module has affine ranking function -2 * j + unknown-#length-unknown[__builtin_alloca(length*sizeof(int))] + -1 * arr and consists of 4 locations. 53 modules have a trivial ranking function, the largest among these consists of 83 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 294.3s and 56 iterations. TraceHistogramMax:13. Analysis of lassos took 162.5s. Construction of modules took 21.5s. Büchi inclusion checks took 109.9s. Highest rank in rank-based complementation 3. Minimization of det autom 18. Minimization of nondet autom 37. Automata minimization 0.2s AutomataMinimizationTime, 54 MinimizatonAttempts, 2311 StatesRemovedByMinimization, 51 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4110 SdHoareTripleChecker+Valid, 25.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4109 mSDsluCounter, 9974 SdHoareTripleChecker+Invalid, 21.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 4307 IncrementalHoareTripleChecker+Unchecked, 9334 mSDsCounter, 561 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 42509 IncrementalHoareTripleChecker+Invalid, 47377 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 561 mSolverCounterUnsat, 640 mSDtfsCounter, 42509 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc14 concLT0 SILN0 SILU39 SILI0 SILT0 lasso2 LassoPreprocessingBenchmarks: Lassos: inital138 mio100 ax100 hnf100 lsp93 ukn84 mio100 lsp56 div163 bol100 ite100 ukn100 eq150 hnf93 smp72 dnf100 smp100 tf100 neg98 sie103 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 30ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2022-11-20 11:54:02,003 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:02,203 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:02,403 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:02,604 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:02,803 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Ended with exit code 0 [2022-11-20 11:54:03,004 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:03,203 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:03,404 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Ended with exit code 0 [2022-11-20 11:54:03,604 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2022-11-20 11:54:03,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:04,004 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2022-11-20 11:54:04,205 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2022-11-20 11:54:04,404 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2022-11-20 11:54:04,605 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Ended with exit code 0 [2022-11-20 11:54:04,805 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Ended with exit code 0 [2022-11-20 11:54:05,005 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2022-11-20 11:54:05,205 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:05,406 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2022-11-20 11:54:05,605 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:05,806 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Ended with exit code 0 [2022-11-20 11:54:06,005 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2022-11-20 11:54:06,206 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Ended with exit code 0 [2022-11-20 11:54:06,406 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2022-11-20 11:54:06,606 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:06,806 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:07,006 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2022-11-20 11:54:07,206 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Ended with exit code 0 [2022-11-20 11:54:07,407 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:07,607 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:07,807 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:08,007 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:08,207 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2022-11-20 11:54:08,407 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Ended with exit code 0 [2022-11-20 11:54:08,607 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2022-11-20 11:54:08,808 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:09,008 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2022-11-20 11:54:09,208 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2022-11-20 11:54:09,408 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2022-11-20 11:54:09,608 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:09,809 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:10,008 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:10,209 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:10,409 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2022-11-20 11:54:10,609 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:10,809 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:11,009 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:11,210 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2022-11-20 11:54:11,410 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:11,610 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:11,811 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:12,010 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2022-11-20 11:54:12,211 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-20 11:54:12,488 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d893c492-7216-4f4d-b142-9d5b178faab9/bin/uautomizer-ug76WZFUDN/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE