./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b5237d83 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-b5237d8 [2022-11-21 13:41:48,207 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-21 13:41:48,209 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-21 13:41:48,235 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-21 13:41:48,235 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-21 13:41:48,236 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-21 13:41:48,238 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-21 13:41:48,242 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-21 13:41:48,246 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-21 13:41:48,252 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-21 13:41:48,253 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-21 13:41:48,256 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-21 13:41:48,257 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-21 13:41:48,259 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-21 13:41:48,263 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-21 13:41:48,265 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-21 13:41:48,267 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-21 13:41:48,267 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-21 13:41:48,269 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-21 13:41:48,275 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-21 13:41:48,277 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-21 13:41:48,281 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-21 13:41:48,283 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-21 13:41:48,284 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-21 13:41:48,293 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-21 13:41:48,293 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-21 13:41:48,293 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-21 13:41:48,294 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-21 13:41:48,295 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-21 13:41:48,296 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-21 13:41:48,296 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-21 13:41:48,297 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-21 13:41:48,297 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-21 13:41:48,298 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-21 13:41:48,299 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-21 13:41:48,299 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-21 13:41:48,300 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-21 13:41:48,300 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-21 13:41:48,301 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-21 13:41:48,301 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-21 13:41:48,302 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-21 13:41:48,306 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-21 13:41:48,342 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-21 13:41:48,342 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-21 13:41:48,342 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-21 13:41:48,343 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-21 13:41:48,346 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-21 13:41:48,347 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-21 13:41:48,347 INFO L138 SettingsManager]: * Use SBE=true [2022-11-21 13:41:48,347 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-21 13:41:48,347 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-21 13:41:48,348 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-21 13:41:48,349 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-21 13:41:48,349 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-21 13:41:48,349 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-21 13:41:48,349 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-21 13:41:48,350 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-21 13:41:48,350 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-21 13:41:48,350 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-21 13:41:48,350 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-21 13:41:48,351 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-21 13:41:48,351 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-21 13:41:48,351 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-21 13:41:48,351 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-21 13:41:48,352 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-21 13:41:48,352 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-21 13:41:48,352 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-21 13:41:48,353 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-21 13:41:48,353 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-21 13:41:48,353 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-21 13:41:48,354 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-21 13:41:48,354 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-21 13:41:48,354 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-21 13:41:48,356 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-21 13:41:48,356 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2022-11-21 13:41:48,694 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-21 13:41:48,717 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-21 13:41:48,719 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-21 13:41:48,720 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-21 13:41:48,721 INFO L275 PluginConnector]: CDTParser initialized [2022-11-21 13:41:48,722 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-11-21 13:41:52,130 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-21 13:41:52,432 INFO L351 CDTParser]: Found 1 translation units. [2022-11-21 13:41:52,433 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-11-21 13:41:52,448 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/data/637250a80/48889efb076b4e72ac42550c43cf7069/FLAG697704530 [2022-11-21 13:41:52,470 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/data/637250a80/48889efb076b4e72ac42550c43cf7069 [2022-11-21 13:41:52,474 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-21 13:41:52,476 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-21 13:41:52,481 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-21 13:41:52,481 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-21 13:41:52,485 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-21 13:41:52,486 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 01:41:52" (1/1) ... [2022-11-21 13:41:52,487 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ec34901 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:52, skipping insertion in model container [2022-11-21 13:41:52,488 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 01:41:52" (1/1) ... [2022-11-21 13:41:52,496 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-21 13:41:52,563 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-21 13:41:52,761 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-11-21 13:41:52,944 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-21 13:41:52,959 INFO L203 MainTranslator]: Completed pre-run [2022-11-21 13:41:52,971 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-11-21 13:41:53,033 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-21 13:41:53,059 INFO L208 MainTranslator]: Completed translation [2022-11-21 13:41:53,060 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53 WrapperNode [2022-11-21 13:41:53,060 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-21 13:41:53,061 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-21 13:41:53,062 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-21 13:41:53,062 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-21 13:41:53,069 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,095 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,248 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 302, statements flattened = 4653 [2022-11-21 13:41:53,249 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-21 13:41:53,250 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-21 13:41:53,250 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-21 13:41:53,250 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-21 13:41:53,262 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,262 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,273 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,274 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,326 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,380 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,391 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,404 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,428 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-21 13:41:53,429 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-21 13:41:53,429 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-21 13:41:53,429 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-21 13:41:53,443 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (1/1) ... [2022-11-21 13:41:53,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-21 13:41:53,463 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/z3 [2022-11-21 13:41:53,488 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-21 13:41:53,506 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8d16529b-d550-4a31-9fea-c8cc9cb9aa46/bin/uautomizer-vX5HgA9Q3a/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-21 13:41:53,545 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-21 13:41:53,545 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-21 13:41:53,545 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-21 13:41:53,545 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-21 13:41:53,764 INFO L235 CfgBuilder]: Building ICFG [2022-11-21 13:41:53,781 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-21 13:41:56,448 INFO L276 CfgBuilder]: Performing block encoding [2022-11-21 13:41:56,474 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-21 13:41:56,474 INFO L300 CfgBuilder]: Removed 16 assume(true) statements. [2022-11-21 13:41:56,480 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 01:41:56 BoogieIcfgContainer [2022-11-21 13:41:56,480 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-21 13:41:56,482 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-21 13:41:56,482 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-21 13:41:56,486 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-21 13:41:56,487 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-21 13:41:56,487 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.11 01:41:52" (1/3) ... [2022-11-21 13:41:56,488 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7fbddddb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 01:41:56, skipping insertion in model container [2022-11-21 13:41:56,488 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-21 13:41:56,489 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 01:41:53" (2/3) ... [2022-11-21 13:41:56,491 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7fbddddb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.11 01:41:56, skipping insertion in model container [2022-11-21 13:41:56,491 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-21 13:41:56,491 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 01:41:56" (3/3) ... [2022-11-21 13:41:56,494 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2022-11-21 13:41:56,593 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-21 13:41:56,593 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-21 13:41:56,594 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-21 13:41:56,594 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-21 13:41:56,594 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-21 13:41:56,594 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-21 13:41:56,594 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-21 13:41:56,594 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-21 13:41:56,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:56,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-11-21 13:41:56,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:56,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:56,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:56,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:56,703 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-21 13:41:56,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:56,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-11-21 13:41:56,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:56,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:56,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:56,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:56,806 INFO L748 eck$LassoCheckResult]: Stem: 472#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1942#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1565#L1891true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 826#L895true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1865#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 460#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1624#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 503#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1549#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 821#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 984#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 482#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 374#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1474#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 657#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1538#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 573#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 901#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 356#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1960#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1550#L1279-2true assume !(0 == ~T1_E~0); 159#L1284-1true assume !(0 == ~T2_E~0); 1772#L1289-1true assume !(0 == ~T3_E~0); 570#L1294-1true assume !(0 == ~T4_E~0); 577#L1299-1true assume !(0 == ~T5_E~0); 1856#L1304-1true assume !(0 == ~T6_E~0); 1901#L1309-1true assume !(0 == ~T7_E~0); 1874#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 123#L1319-1true assume !(0 == ~T9_E~0); 1108#L1324-1true assume !(0 == ~T10_E~0); 213#L1329-1true assume !(0 == ~T11_E~0); 1364#L1334-1true assume !(0 == ~T12_E~0); 1803#L1339-1true assume !(0 == ~T13_E~0); 1526#L1344-1true assume !(0 == ~E_M~0); 1958#L1349-1true assume !(0 == ~E_1~0); 707#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1113#L1359-1true assume !(0 == ~E_3~0); 1777#L1364-1true assume !(0 == ~E_4~0); 281#L1369-1true assume !(0 == ~E_5~0); 1089#L1374-1true assume !(0 == ~E_6~0); 711#L1379-1true assume !(0 == ~E_7~0); 770#L1384-1true assume !(0 == ~E_8~0); 2000#L1389-1true assume !(0 == ~E_9~0); 1401#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1872#L1399-1true assume !(0 == ~E_11~0); 1641#L1404-1true assume !(0 == ~E_12~0); 328#L1409-1true assume !(0 == ~E_13~0); 1615#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1954#L628true assume !(1 == ~m_pc~0); 1412#L628-2true is_master_triggered_~__retres1~0#1 := 0; 934#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 769#L640true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1659#L1591true assume !(0 != activate_threads_~tmp~1#1); 1889#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 605#L647true assume 1 == ~t1_pc~0; 238#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 646#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 382#L659true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1638#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1502#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1912#L666true assume 1 == ~t2_pc~0; 158#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 245#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1619#L678true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1531#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 863#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1857#L685true assume !(1 == ~t3_pc~0); 1025#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1685#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 649#L697true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 746#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1064#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 401#L704true assume 1 == ~t4_pc~0; 1245#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 757#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1577#L716true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1773#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 644#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 742#L723true assume !(1 == ~t5_pc~0); 946#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1107#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1532#L735true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 848#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 867#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272#L742true assume 1 == ~t6_pc~0; 958#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 348#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 896#L754true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1356#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 312#L761true assume !(1 == ~t7_pc~0); 317#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 243#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1947#L773true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 748#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1559#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 120#L780true assume 1 == ~t8_pc~0; 578#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 265#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 906#L792true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 718#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 810#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1394#L799true assume 1 == ~t9_pc~0; 910#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 121#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 819#L811true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1000#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1919#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 835#L818true assume !(1 == ~t10_pc~0); 23#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 903#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1743#L830true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 839#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1095#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 872#L837true assume 1 == ~t11_pc~0; 1796#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1576#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1135#L849true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 805#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1860#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 612#L856true assume !(1 == ~t12_pc~0); 1442#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1252#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1794#L868true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1220#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1787#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1556#L875true assume 1 == ~t13_pc~0; 576#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 350#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1634#L887true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 320#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 900#L1695-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L1427true assume !(1 == ~M_E~0); 883#L1427-2true assume !(1 == ~T1_E~0); 305#L1432-1true assume !(1 == ~T2_E~0); 1560#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1123#L1442-1true assume !(1 == ~T4_E~0); 1484#L1447-1true assume !(1 == ~T5_E~0); 954#L1452-1true assume !(1 == ~T6_E~0); 83#L1457-1true assume !(1 == ~T7_E~0); 1159#L1462-1true assume !(1 == ~T8_E~0); 1843#L1467-1true assume !(1 == ~T9_E~0); 1184#L1472-1true assume !(1 == ~T10_E~0); 1370#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 899#L1482-1true assume !(1 == ~T12_E~0); 1298#L1487-1true assume !(1 == ~T13_E~0); 251#L1492-1true assume !(1 == ~E_M~0); 655#L1497-1true assume !(1 == ~E_1~0); 448#L1502-1true assume !(1 == ~E_2~0); 1296#L1507-1true assume !(1 == ~E_3~0); 188#L1512-1true assume !(1 == ~E_4~0); 1278#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1389#L1522-1true assume !(1 == ~E_6~0); 603#L1527-1true assume !(1 == ~E_7~0); 1754#L1532-1true assume !(1 == ~E_8~0); 2013#L1537-1true assume !(1 == ~E_9~0); 761#L1542-1true assume !(1 == ~E_10~0); 629#L1547-1true assume !(1 == ~E_11~0); 1781#L1552-1true assume !(1 == ~E_12~0); 41#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 343#L1562-1true assume { :end_inline_reset_delta_events } true; 741#L1928-2true [2022-11-21 13:41:56,808 INFO L750 eck$LassoCheckResult]: Loop: 741#L1928-2true assume !false; 652#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 488#L1254true assume false; 441#L1269true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 211#L895-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1604#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 462#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 450#L1284-3true assume !(0 == ~T2_E~0); 1668#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 440#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1893#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 705#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1144#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 380#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1970#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1209#L1324-3true assume !(0 == ~T10_E~0); 186#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1822#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 635#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 927#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 869#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 368#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 880#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1855#L1364-3true assume !(0 == ~E_4~0); 1742#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1436#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 253#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1303#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 367#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 543#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1945#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1464#L1404-3true assume !(0 == ~E_12~0); 1388#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1548#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 781#L628-45true assume !(1 == ~m_pc~0); 1316#L628-47true is_master_triggered_~__retres1~0#1 := 0; 1736#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181#L640-15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 388#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1670#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 909#L647-45true assume 1 == ~t1_pc~0; 157#L648-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 717#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 965#L659-15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 216#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1547#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326#L666-45true assume !(1 == ~t2_pc~0); 620#L666-47true is_transmit2_triggered_~__retres1~2#1 := 0; 1691#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1143#L678-15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1015#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1010#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91#L685-45true assume !(1 == ~t3_pc~0); 1415#L685-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1530#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1581#L697-15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1273#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1552#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1637#L704-45true assume 1 == ~t4_pc~0; 1310#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 480#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 720#L716-15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2016#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1979#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 807#L723-45true assume 1 == ~t5_pc~0; 1815#L724-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1702#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509#L735-15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 375#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1928#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1235#L742-45true assume 1 == ~t6_pc~0; 1836#L743-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 878#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1087#L754-15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 914#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1277#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 989#L761-45true assume !(1 == ~t7_pc~0); 1166#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 520#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1041#L773-15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 190#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1953#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1392#L780-45true assume 1 == ~t8_pc~0; 391#L781-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 196#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1955#L792-15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1753#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 178#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 633#L799-45true assume !(1 == ~t9_pc~0); 296#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2006#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1501#L811-15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 955#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1816#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 148#L818-45true assume 1 == ~t10_pc~0; 1057#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 933#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1828#L830-15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 479#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1047#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1522#L837-45true assume !(1 == ~t11_pc~0); 437#L837-47true is_transmit11_triggered_~__retres1~11#1 := 0; 521#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1069#L849-15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1847#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 220#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2025#L856-45true assume 1 == ~t12_pc~0; 1544#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1272#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 191#L868-15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1799#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 716#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1280#L875-45true assume 1 == ~t13_pc~0; 695#L876-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 740#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1850#L887-15true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1483#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1765#L1695-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1362#L1427-3true assume !(1 == ~M_E~0); 566#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1561#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 996#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 706#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1016#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 49#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1978#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1258#L1462-3true assume !(1 == ~T8_E~0); 1680#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1067#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1708#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 169#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 242#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1808#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 331#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1019#L1502-3true assume !(1 == ~E_2~0); 1207#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1917#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 352#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 193#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1681#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 173#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 881#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1573#L1542-3true assume !(1 == ~E_10~0); 1003#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 696#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1397#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 285#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1969#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1413#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 383#L1053-1true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 798#L1947true assume !(0 == start_simulation_~tmp~3#1); 977#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1128#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1627#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1644#L1053-2true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1450#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1172#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 893#L1910true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1714#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 741#L1928-2true [2022-11-21 13:41:56,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:56,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-11-21 13:41:56,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:56,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327702058] [2022-11-21 13:41:56,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:56,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:56,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:57,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:57,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:57,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327702058] [2022-11-21 13:41:57,279 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327702058] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:57,279 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:57,279 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:57,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951417457] [2022-11-21 13:41:57,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:57,294 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:57,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:57,296 INFO L85 PathProgramCache]: Analyzing trace with hash 1651655169, now seen corresponding path program 1 times [2022-11-21 13:41:57,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:57,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229381790] [2022-11-21 13:41:57,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:57,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:57,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:57,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:57,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:57,426 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229381790] [2022-11-21 13:41:57,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229381790] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:57,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:57,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-21 13:41:57,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161389767] [2022-11-21 13:41:57,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:57,430 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:57,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:57,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-21 13:41:57,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-21 13:41:57,470 INFO L87 Difference]: Start difference. First operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:57,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:57,540 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-11-21 13:41:57,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2022-11-21 13:41:57,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:57,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2018 states and 2987 transitions. [2022-11-21 13:41:57,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:57,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:57,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2987 transitions. [2022-11-21 13:41:57,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:57,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-11-21 13:41:57,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2987 transitions. [2022-11-21 13:41:57,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:57,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:57,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2987 transitions. [2022-11-21 13:41:57,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-11-21 13:41:57,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-21 13:41:57,681 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-11-21 13:41:57,682 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-21 13:41:57,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2987 transitions. [2022-11-21 13:41:57,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:57,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:57,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:57,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:57,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:57,697 INFO L748 eck$LassoCheckResult]: Stem: 4971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 6008#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5463#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5464#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4953#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4954#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5020#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5021#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5459#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5460#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4986#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4805#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4806#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5250#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5251#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5126#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5127#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4776#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4777#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6000#L1279-2 assume !(0 == ~T1_E~0); 4399#L1284-1 assume !(0 == ~T2_E~0); 4400#L1289-1 assume !(0 == ~T3_E~0); 5123#L1294-1 assume !(0 == ~T4_E~0); 5124#L1299-1 assume !(0 == ~T5_E~0); 5135#L1304-1 assume !(0 == ~T6_E~0); 6066#L1309-1 assume !(0 == ~T7_E~0); 6067#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4329#L1319-1 assume !(0 == ~T9_E~0); 4330#L1324-1 assume !(0 == ~T10_E~0); 4502#L1329-1 assume !(0 == ~T11_E~0); 4503#L1334-1 assume !(0 == ~T12_E~0); 5907#L1339-1 assume !(0 == ~T13_E~0); 5988#L1344-1 assume !(0 == ~E_M~0); 5989#L1349-1 assume !(0 == ~E_1~0); 5310#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5311#L1359-1 assume !(0 == ~E_3~0); 5740#L1364-1 assume !(0 == ~E_4~0); 4631#L1369-1 assume !(0 == ~E_5~0); 4632#L1374-1 assume !(0 == ~E_6~0); 5315#L1379-1 assume !(0 == ~E_7~0); 5316#L1384-1 assume !(0 == ~E_8~0); 5393#L1389-1 assume !(0 == ~E_9~0); 5926#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5927#L1399-1 assume !(0 == ~E_11~0); 6030#L1404-1 assume !(0 == ~E_12~0); 4724#L1409-1 assume !(0 == ~E_13~0); 4725#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6022#L628 assume !(1 == ~m_pc~0); 4628#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4627#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5391#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5392#L1591 assume !(0 != activate_threads_~tmp~1#1); 6035#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5179#L647 assume 1 == ~t1_pc~0; 4548#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4549#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4820#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4821#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 5975#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5976#L666 assume 1 == ~t2_pc~0; 4396#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4397#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4563#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5992#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5511#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5512#L685 assume !(1 == ~t3_pc~0); 5617#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5616#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5239#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5240#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4847#L704 assume 1 == ~t4_pc~0; 4848#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5372#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5373#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6013#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5232#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5233#L723 assume !(1 == ~t5_pc~0); 5355#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5591#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5735#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5490#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5491#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4613#L742 assume 1 == ~t6_pc~0; 4614#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4762#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4763#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4298#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4299#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4690#L761 assume !(1 == ~t7_pc~0); 4691#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4559#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4560#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5362#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5363#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4323#L780 assume 1 == ~t8_pc~0; 4324#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4599#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4600#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5323#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5324#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5443#L799 assume 1 == ~t9_pc~0; 5555#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4326#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4327#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5455#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5662#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5473#L818 assume !(1 == ~t10_pc~0); 4107#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4108#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5548#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5477#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5478#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5518#L837 assume 1 == ~t11_pc~0; 5519#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5353#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5756#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5436#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5437#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5188#L856 assume !(1 == ~t12_pc~0); 5189#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5842#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5843#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5823#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5824#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6003#L875 assume 1 == ~t13_pc~0; 5133#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4765#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4766#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4705#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4706#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5545#L1427 assume !(1 == ~M_E~0); 5529#L1427-2 assume !(1 == ~T1_E~0); 4677#L1432-1 assume !(1 == ~T2_E~0); 4678#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5746#L1442-1 assume !(1 == ~T4_E~0); 5747#L1447-1 assume !(1 == ~T5_E~0); 5602#L1452-1 assume !(1 == ~T6_E~0); 4242#L1457-1 assume !(1 == ~T7_E~0); 4243#L1462-1 assume !(1 == ~T8_E~0); 5773#L1467-1 assume !(1 == ~T9_E~0); 5791#L1472-1 assume !(1 == ~T10_E~0); 5792#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5543#L1482-1 assume !(1 == ~T12_E~0); 5544#L1487-1 assume !(1 == ~T13_E~0); 4573#L1492-1 assume !(1 == ~E_M~0); 4574#L1497-1 assume !(1 == ~E_1~0); 4935#L1502-1 assume !(1 == ~E_2~0); 4936#L1507-1 assume !(1 == ~E_3~0); 4451#L1512-1 assume !(1 == ~E_4~0); 4452#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5862#L1522-1 assume !(1 == ~E_6~0); 5176#L1527-1 assume !(1 == ~E_7~0); 5177#L1532-1 assume !(1 == ~E_8~0); 6050#L1537-1 assume !(1 == ~E_9~0); 5379#L1542-1 assume !(1 == ~E_10~0); 5210#L1547-1 assume !(1 == ~E_11~0); 5211#L1552-1 assume !(1 == ~E_12~0); 4146#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4147#L1562-1 assume { :end_inline_reset_delta_events } true; 4753#L1928-2 [2022-11-21 13:41:57,698 INFO L750 eck$LassoCheckResult]: Loop: 4753#L1928-2 assume !false; 5244#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4407#L1254 assume !false; 4994#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4481#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4482#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4679#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5850#L1067 assume !(0 != eval_~tmp~0#1); 4920#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4497#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4498#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4957#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4939#L1284-3 assume !(0 == ~T2_E~0); 4940#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4918#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4919#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5306#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5307#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4816#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4817#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5813#L1324-3 assume !(0 == ~T10_E~0); 4448#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4449#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5216#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5217#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5515#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4797#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4798#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5526#L1364-3 assume !(0 == ~E_4~0); 6048#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5944#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4577#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4578#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4795#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4796#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5086#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5954#L1404-3 assume !(0 == ~E_12~0); 5918#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5919#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5405#L628-45 assume 1 == ~m_pc~0; 5083#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5085#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4442#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4443#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4831#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5554#L647-45 assume 1 == ~t1_pc~0; 4393#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4394#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5322#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4507#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4508#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4719#L666-45 assume !(1 == ~t2_pc~0); 4720#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5201#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5763#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5678#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5672#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4257#L685-45 assume 1 == ~t3_pc~0; 4258#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5317#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5991#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5860#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5861#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6001#L704-45 assume 1 == ~t4_pc~0; 5880#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4124#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4983#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5326#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6073#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5438#L723-45 assume 1 == ~t5_pc~0; 5440#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5928#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5030#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4807#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4808#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5832#L742-45 assume 1 == ~t6_pc~0; 5833#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5055#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5524#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5560#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5561#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5649#L761-45 assume !(1 == ~t7_pc~0); 5650#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5048#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5049#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4455#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4456#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5922#L780-45 assume 1 == ~t8_pc~0; 4833#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4467#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4468#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6049#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4437#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4438#L799-45 assume !(1 == ~t9_pc~0); 4658#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4659#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5974#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5603#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5604#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4375#L818-45 assume 1 == ~t10_pc~0; 4376#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4494#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5577#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4981#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4982#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5697#L837-45 assume !(1 == ~t11_pc~0); 4912#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4913#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5050#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5715#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4513#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4514#L856-45 assume !(1 == ~t12_pc~0); 4515#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4516#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4457#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4458#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5320#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5321#L875-45 assume 1 == ~t13_pc~0; 5291#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5292#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5354#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5966#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5967#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5906#L1427-3 assume !(1 == ~M_E~0); 5117#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5118#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5656#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5308#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5309#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4165#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4166#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5848#L1462-3 assume !(1 == ~T8_E~0); 5849#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5712#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5713#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4416#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4417#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4558#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4731#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4732#L1502-3 assume !(1 == ~E_2~0); 5680#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5811#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4769#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4461#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4462#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4426#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4427#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5527#L1542-3 assume !(1 == ~E_10~0); 5665#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5294#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5295#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4637#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4638#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4057#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4822#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4823#L1947 assume !(0 == start_simulation_~tmp~3#1); 5428#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5633#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4694#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 6026#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 5950#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5780#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5539#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5540#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4753#L1928-2 [2022-11-21 13:41:57,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:57,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-11-21 13:41:57,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:57,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779217259] [2022-11-21 13:41:57,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:57,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:57,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:57,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:57,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:57,854 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779217259] [2022-11-21 13:41:57,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779217259] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:57,855 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:57,855 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:57,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223384968] [2022-11-21 13:41:57,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:57,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:57,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:57,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1579703507, now seen corresponding path program 1 times [2022-11-21 13:41:57,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:57,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650181838] [2022-11-21 13:41:57,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:57,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:57,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:58,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:58,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:58,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650181838] [2022-11-21 13:41:58,096 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650181838] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:58,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:58,096 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:58,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351247363] [2022-11-21 13:41:58,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:58,099 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:58,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:58,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:58,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:58,101 INFO L87 Difference]: Start difference. First operand 2018 states and 2987 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:58,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:58,168 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2022-11-21 13:41:58,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2986 transitions. [2022-11-21 13:41:58,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:58,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-11-21 13:41:58,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:58,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:58,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2986 transitions. [2022-11-21 13:41:58,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:58,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-11-21 13:41:58,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2986 transitions. [2022-11-21 13:41:58,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:58,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:58,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-11-21 13:41:58,257 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-11-21 13:41:58,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:41:58,259 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-11-21 13:41:58,260 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-21 13:41:58,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2986 transitions. [2022-11-21 13:41:58,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:58,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:58,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:58,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:58,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:58,283 INFO L748 eck$LassoCheckResult]: Stem: 9014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10051#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9506#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9507#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 8996#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8997#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9063#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9064#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9502#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9503#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9029#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8848#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8849#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9293#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9294#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9169#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9170#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8819#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8820#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10043#L1279-2 assume !(0 == ~T1_E~0); 8442#L1284-1 assume !(0 == ~T2_E~0); 8443#L1289-1 assume !(0 == ~T3_E~0); 9166#L1294-1 assume !(0 == ~T4_E~0); 9167#L1299-1 assume !(0 == ~T5_E~0); 9178#L1304-1 assume !(0 == ~T6_E~0); 10109#L1309-1 assume !(0 == ~T7_E~0); 10110#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8372#L1319-1 assume !(0 == ~T9_E~0); 8373#L1324-1 assume !(0 == ~T10_E~0); 8545#L1329-1 assume !(0 == ~T11_E~0); 8546#L1334-1 assume !(0 == ~T12_E~0); 9950#L1339-1 assume !(0 == ~T13_E~0); 10031#L1344-1 assume !(0 == ~E_M~0); 10032#L1349-1 assume !(0 == ~E_1~0); 9353#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9354#L1359-1 assume !(0 == ~E_3~0); 9783#L1364-1 assume !(0 == ~E_4~0); 8674#L1369-1 assume !(0 == ~E_5~0); 8675#L1374-1 assume !(0 == ~E_6~0); 9358#L1379-1 assume !(0 == ~E_7~0); 9359#L1384-1 assume !(0 == ~E_8~0); 9436#L1389-1 assume !(0 == ~E_9~0); 9969#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9970#L1399-1 assume !(0 == ~E_11~0); 10073#L1404-1 assume !(0 == ~E_12~0); 8767#L1409-1 assume !(0 == ~E_13~0); 8768#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10065#L628 assume !(1 == ~m_pc~0); 8671#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8670#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9434#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9435#L1591 assume !(0 != activate_threads_~tmp~1#1); 10078#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9222#L647 assume 1 == ~t1_pc~0; 8591#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8592#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8863#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8864#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10018#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10019#L666 assume 1 == ~t2_pc~0; 8439#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8440#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8606#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10035#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9554#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9555#L685 assume !(1 == ~t3_pc~0); 9660#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9659#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9282#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9283#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9404#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8890#L704 assume 1 == ~t4_pc~0; 8891#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9415#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9416#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10056#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9275#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9276#L723 assume !(1 == ~t5_pc~0); 9398#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9634#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9778#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9533#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9534#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8656#L742 assume 1 == ~t6_pc~0; 8657#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8805#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8806#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8341#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8342#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8733#L761 assume !(1 == ~t7_pc~0); 8734#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8602#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8603#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9405#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9406#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8366#L780 assume 1 == ~t8_pc~0; 8367#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8642#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8643#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9366#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9367#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9486#L799 assume 1 == ~t9_pc~0; 9598#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8369#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8370#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9498#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9705#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9516#L818 assume !(1 == ~t10_pc~0); 8150#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8151#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9591#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9520#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9521#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9561#L837 assume 1 == ~t11_pc~0; 9562#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9396#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9799#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9479#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9480#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9231#L856 assume !(1 == ~t12_pc~0); 9232#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9885#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9886#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9866#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9867#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10046#L875 assume 1 == ~t13_pc~0; 9176#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8808#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8809#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8748#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8749#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9588#L1427 assume !(1 == ~M_E~0); 9572#L1427-2 assume !(1 == ~T1_E~0); 8720#L1432-1 assume !(1 == ~T2_E~0); 8721#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9789#L1442-1 assume !(1 == ~T4_E~0); 9790#L1447-1 assume !(1 == ~T5_E~0); 9645#L1452-1 assume !(1 == ~T6_E~0); 8285#L1457-1 assume !(1 == ~T7_E~0); 8286#L1462-1 assume !(1 == ~T8_E~0); 9816#L1467-1 assume !(1 == ~T9_E~0); 9834#L1472-1 assume !(1 == ~T10_E~0); 9835#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9586#L1482-1 assume !(1 == ~T12_E~0); 9587#L1487-1 assume !(1 == ~T13_E~0); 8616#L1492-1 assume !(1 == ~E_M~0); 8617#L1497-1 assume !(1 == ~E_1~0); 8978#L1502-1 assume !(1 == ~E_2~0); 8979#L1507-1 assume !(1 == ~E_3~0); 8494#L1512-1 assume !(1 == ~E_4~0); 8495#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9905#L1522-1 assume !(1 == ~E_6~0); 9219#L1527-1 assume !(1 == ~E_7~0); 9220#L1532-1 assume !(1 == ~E_8~0); 10093#L1537-1 assume !(1 == ~E_9~0); 9422#L1542-1 assume !(1 == ~E_10~0); 9253#L1547-1 assume !(1 == ~E_11~0); 9254#L1552-1 assume !(1 == ~E_12~0); 8189#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8190#L1562-1 assume { :end_inline_reset_delta_events } true; 8796#L1928-2 [2022-11-21 13:41:58,283 INFO L750 eck$LassoCheckResult]: Loop: 8796#L1928-2 assume !false; 9287#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8450#L1254 assume !false; 9037#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8524#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8525#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8722#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9893#L1067 assume !(0 != eval_~tmp~0#1); 8963#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8540#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8541#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9000#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8982#L1284-3 assume !(0 == ~T2_E~0); 8983#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8961#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8962#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9349#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9350#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8859#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8860#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9856#L1324-3 assume !(0 == ~T10_E~0); 8491#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8492#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9259#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9260#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9558#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8840#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8841#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9569#L1364-3 assume !(0 == ~E_4~0); 10091#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9987#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8620#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8621#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8838#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8839#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9129#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9997#L1404-3 assume !(0 == ~E_12~0); 9961#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9962#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9448#L628-45 assume 1 == ~m_pc~0; 9126#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9128#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8485#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8486#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8874#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9597#L647-45 assume 1 == ~t1_pc~0; 8436#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8437#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9365#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8550#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8551#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8762#L666-45 assume !(1 == ~t2_pc~0); 8763#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9244#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9806#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9721#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9715#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8300#L685-45 assume 1 == ~t3_pc~0; 8301#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9360#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10034#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9903#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9904#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10044#L704-45 assume 1 == ~t4_pc~0; 9923#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8167#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9026#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9369#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9481#L723-45 assume !(1 == ~t5_pc~0); 9482#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 9971#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9073#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8850#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8851#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9875#L742-45 assume 1 == ~t6_pc~0; 9876#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9098#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9567#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9603#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9604#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9692#L761-45 assume !(1 == ~t7_pc~0); 9693#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9091#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9092#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8498#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8499#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9965#L780-45 assume 1 == ~t8_pc~0; 8876#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8510#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8511#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10092#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8480#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8481#L799-45 assume 1 == ~t9_pc~0; 9257#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8702#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10017#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9646#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9647#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8418#L818-45 assume 1 == ~t10_pc~0; 8419#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8537#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9620#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9024#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9025#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9740#L837-45 assume !(1 == ~t11_pc~0); 8955#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8956#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9093#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9758#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8556#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8557#L856-45 assume 1 == ~t12_pc~0; 10042#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8559#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8500#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8501#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9363#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9364#L875-45 assume 1 == ~t13_pc~0; 9334#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9335#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9397#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10009#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10010#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9949#L1427-3 assume !(1 == ~M_E~0); 9160#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9161#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9699#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9352#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8208#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8209#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9891#L1462-3 assume !(1 == ~T8_E~0); 9892#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9755#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9756#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8459#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8460#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8601#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8774#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8775#L1502-3 assume !(1 == ~E_2~0); 9723#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9854#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8812#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8504#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8505#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8469#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8470#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9570#L1542-3 assume !(1 == ~E_10~0); 9708#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9337#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9338#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8680#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8681#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8100#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8865#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8866#L1947 assume !(0 == start_simulation_~tmp~3#1); 9471#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9676#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8737#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 10069#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 9993#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9823#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9583#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8796#L1928-2 [2022-11-21 13:41:58,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:58,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-11-21 13:41:58,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:58,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810278598] [2022-11-21 13:41:58,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:58,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:58,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:58,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:58,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:58,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810278598] [2022-11-21 13:41:58,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810278598] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:58,421 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:58,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:58,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928202138] [2022-11-21 13:41:58,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:58,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:58,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:58,424 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 1 times [2022-11-21 13:41:58,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:58,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12414546] [2022-11-21 13:41:58,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:58,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:58,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:58,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:58,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:58,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12414546] [2022-11-21 13:41:58,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12414546] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:58,572 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:58,573 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:58,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221157448] [2022-11-21 13:41:58,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:58,575 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:58,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:58,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:58,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:58,576 INFO L87 Difference]: Start difference. First operand 2018 states and 2986 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:58,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:58,671 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2022-11-21 13:41:58,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2985 transitions. [2022-11-21 13:41:58,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:58,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-11-21 13:41:58,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:58,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:58,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2985 transitions. [2022-11-21 13:41:58,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:58,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-11-21 13:41:58,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2985 transitions. [2022-11-21 13:41:58,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:58,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:58,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-11-21 13:41:58,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-11-21 13:41:58,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:41:58,750 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-11-21 13:41:58,750 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-21 13:41:58,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2985 transitions. [2022-11-21 13:41:58,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:58,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:58,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:58,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:58,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:58,766 INFO L748 eck$LassoCheckResult]: Stem: 13057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14094#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13549#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13550#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13039#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13040#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13106#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13107#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13545#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13546#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13072#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12891#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12892#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13336#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13337#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13212#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13213#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12862#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12863#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14086#L1279-2 assume !(0 == ~T1_E~0); 12485#L1284-1 assume !(0 == ~T2_E~0); 12486#L1289-1 assume !(0 == ~T3_E~0); 13209#L1294-1 assume !(0 == ~T4_E~0); 13210#L1299-1 assume !(0 == ~T5_E~0); 13221#L1304-1 assume !(0 == ~T6_E~0); 14152#L1309-1 assume !(0 == ~T7_E~0); 14153#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12415#L1319-1 assume !(0 == ~T9_E~0); 12416#L1324-1 assume !(0 == ~T10_E~0); 12588#L1329-1 assume !(0 == ~T11_E~0); 12589#L1334-1 assume !(0 == ~T12_E~0); 13993#L1339-1 assume !(0 == ~T13_E~0); 14074#L1344-1 assume !(0 == ~E_M~0); 14075#L1349-1 assume !(0 == ~E_1~0); 13396#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13397#L1359-1 assume !(0 == ~E_3~0); 13826#L1364-1 assume !(0 == ~E_4~0); 12717#L1369-1 assume !(0 == ~E_5~0); 12718#L1374-1 assume !(0 == ~E_6~0); 13401#L1379-1 assume !(0 == ~E_7~0); 13402#L1384-1 assume !(0 == ~E_8~0); 13479#L1389-1 assume !(0 == ~E_9~0); 14012#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14013#L1399-1 assume !(0 == ~E_11~0); 14116#L1404-1 assume !(0 == ~E_12~0); 12810#L1409-1 assume !(0 == ~E_13~0); 12811#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14108#L628 assume !(1 == ~m_pc~0); 12714#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12713#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13477#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13478#L1591 assume !(0 != activate_threads_~tmp~1#1); 14121#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13265#L647 assume 1 == ~t1_pc~0; 12634#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12635#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12906#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12907#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14061#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14062#L666 assume 1 == ~t2_pc~0; 12482#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12483#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12649#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14078#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13597#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13598#L685 assume !(1 == ~t3_pc~0); 13703#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13702#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13325#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13326#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13447#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12933#L704 assume 1 == ~t4_pc~0; 12934#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13458#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13459#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14099#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13318#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13319#L723 assume !(1 == ~t5_pc~0); 13441#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13677#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13821#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13576#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13577#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12699#L742 assume 1 == ~t6_pc~0; 12700#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12848#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12849#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12384#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12385#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12776#L761 assume !(1 == ~t7_pc~0); 12777#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12645#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12646#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13448#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13449#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12409#L780 assume 1 == ~t8_pc~0; 12410#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12685#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12686#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13409#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13410#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13529#L799 assume 1 == ~t9_pc~0; 13641#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12412#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12413#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13541#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13748#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13559#L818 assume !(1 == ~t10_pc~0); 12193#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12194#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13634#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13563#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13564#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13604#L837 assume 1 == ~t11_pc~0; 13605#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13439#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13842#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13522#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13523#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13274#L856 assume !(1 == ~t12_pc~0); 13275#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13928#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13929#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13909#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13910#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14089#L875 assume 1 == ~t13_pc~0; 13219#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12851#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12852#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12791#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12792#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13631#L1427 assume !(1 == ~M_E~0); 13615#L1427-2 assume !(1 == ~T1_E~0); 12763#L1432-1 assume !(1 == ~T2_E~0); 12764#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13832#L1442-1 assume !(1 == ~T4_E~0); 13833#L1447-1 assume !(1 == ~T5_E~0); 13688#L1452-1 assume !(1 == ~T6_E~0); 12328#L1457-1 assume !(1 == ~T7_E~0); 12329#L1462-1 assume !(1 == ~T8_E~0); 13859#L1467-1 assume !(1 == ~T9_E~0); 13877#L1472-1 assume !(1 == ~T10_E~0); 13878#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13629#L1482-1 assume !(1 == ~T12_E~0); 13630#L1487-1 assume !(1 == ~T13_E~0); 12659#L1492-1 assume !(1 == ~E_M~0); 12660#L1497-1 assume !(1 == ~E_1~0); 13021#L1502-1 assume !(1 == ~E_2~0); 13022#L1507-1 assume !(1 == ~E_3~0); 12537#L1512-1 assume !(1 == ~E_4~0); 12538#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 13948#L1522-1 assume !(1 == ~E_6~0); 13262#L1527-1 assume !(1 == ~E_7~0); 13263#L1532-1 assume !(1 == ~E_8~0); 14136#L1537-1 assume !(1 == ~E_9~0); 13465#L1542-1 assume !(1 == ~E_10~0); 13296#L1547-1 assume !(1 == ~E_11~0); 13297#L1552-1 assume !(1 == ~E_12~0); 12232#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12233#L1562-1 assume { :end_inline_reset_delta_events } true; 12839#L1928-2 [2022-11-21 13:41:58,766 INFO L750 eck$LassoCheckResult]: Loop: 12839#L1928-2 assume !false; 13330#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12493#L1254 assume !false; 13080#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12567#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12568#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12765#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13936#L1067 assume !(0 != eval_~tmp~0#1); 13006#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12583#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12584#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13043#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13025#L1284-3 assume !(0 == ~T2_E~0); 13026#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13004#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13005#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13392#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13393#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12902#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12903#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13899#L1324-3 assume !(0 == ~T10_E~0); 12534#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12535#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13302#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13303#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13601#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12883#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12884#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13612#L1364-3 assume !(0 == ~E_4~0); 14134#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14030#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12663#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12664#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12881#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12882#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13172#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14040#L1404-3 assume !(0 == ~E_12~0); 14004#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14005#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13491#L628-45 assume 1 == ~m_pc~0; 13169#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13171#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12528#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12529#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12917#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13640#L647-45 assume !(1 == ~t1_pc~0); 12481#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 12480#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13408#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12594#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12805#L666-45 assume !(1 == ~t2_pc~0); 12806#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13287#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13849#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13764#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13758#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12343#L685-45 assume 1 == ~t3_pc~0; 12344#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13403#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14077#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13946#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13947#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14087#L704-45 assume !(1 == ~t4_pc~0); 12209#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 12210#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13069#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13412#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14159#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13524#L723-45 assume !(1 == ~t5_pc~0); 13525#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 14014#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13116#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12893#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12894#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13918#L742-45 assume !(1 == ~t6_pc~0); 13140#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13141#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13610#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13646#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13647#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13735#L761-45 assume !(1 == ~t7_pc~0); 13736#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13134#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13135#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12541#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12542#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14008#L780-45 assume 1 == ~t8_pc~0; 12919#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12553#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12554#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14135#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12523#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12524#L799-45 assume 1 == ~t9_pc~0; 13300#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12745#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14060#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13689#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13690#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12461#L818-45 assume 1 == ~t10_pc~0; 12462#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12580#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13663#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13067#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13068#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13783#L837-45 assume !(1 == ~t11_pc~0); 12998#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12999#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13136#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13801#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12599#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12600#L856-45 assume 1 == ~t12_pc~0; 14085#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12602#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12543#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12544#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13406#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13407#L875-45 assume 1 == ~t13_pc~0; 13377#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13378#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13440#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14052#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14053#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13992#L1427-3 assume !(1 == ~M_E~0); 13203#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13204#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13742#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13394#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13395#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12251#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12252#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13934#L1462-3 assume !(1 == ~T8_E~0); 13935#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13798#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13799#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12502#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12503#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12644#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12817#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12818#L1502-3 assume !(1 == ~E_2~0); 13766#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13897#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12855#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12547#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12548#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12512#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12513#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13613#L1542-3 assume !(1 == ~E_10~0); 13751#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13380#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13381#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12723#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12724#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12143#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12908#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12909#L1947 assume !(0 == start_simulation_~tmp~3#1); 13514#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13719#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12780#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14112#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 14036#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13866#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13625#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13626#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12839#L1928-2 [2022-11-21 13:41:58,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:58,768 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-11-21 13:41:58,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:58,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092911396] [2022-11-21 13:41:58,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:58,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:58,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:58,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:58,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:58,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092911396] [2022-11-21 13:41:58,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092911396] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:58,864 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:58,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:58,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232708120] [2022-11-21 13:41:58,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:58,870 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:58,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:58,870 INFO L85 PathProgramCache]: Analyzing trace with hash 975518447, now seen corresponding path program 1 times [2022-11-21 13:41:58,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:58,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903700124] [2022-11-21 13:41:58,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:58,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:58,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:58,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:58,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:58,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903700124] [2022-11-21 13:41:58,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903700124] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:58,994 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:58,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:58,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443294661] [2022-11-21 13:41:58,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:58,995 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:58,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:58,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:58,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:58,997 INFO L87 Difference]: Start difference. First operand 2018 states and 2985 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:59,049 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2022-11-21 13:41:59,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2984 transitions. [2022-11-21 13:41:59,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-11-21 13:41:59,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:59,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:59,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2984 transitions. [2022-11-21 13:41:59,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:59,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-11-21 13:41:59,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2984 transitions. [2022-11-21 13:41:59,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:59,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-11-21 13:41:59,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-11-21 13:41:59,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:41:59,124 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-11-21 13:41:59,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-21 13:41:59,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2984 transitions. [2022-11-21 13:41:59,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:59,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:59,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,140 INFO L748 eck$LassoCheckResult]: Stem: 17100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 18137#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17592#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17593#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17082#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17083#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17149#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17150#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17588#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17589#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17115#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16934#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16935#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17379#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17380#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17255#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17256#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16905#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16906#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18129#L1279-2 assume !(0 == ~T1_E~0); 16528#L1284-1 assume !(0 == ~T2_E~0); 16529#L1289-1 assume !(0 == ~T3_E~0); 17252#L1294-1 assume !(0 == ~T4_E~0); 17253#L1299-1 assume !(0 == ~T5_E~0); 17264#L1304-1 assume !(0 == ~T6_E~0); 18195#L1309-1 assume !(0 == ~T7_E~0); 18196#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16458#L1319-1 assume !(0 == ~T9_E~0); 16459#L1324-1 assume !(0 == ~T10_E~0); 16631#L1329-1 assume !(0 == ~T11_E~0); 16632#L1334-1 assume !(0 == ~T12_E~0); 18036#L1339-1 assume !(0 == ~T13_E~0); 18117#L1344-1 assume !(0 == ~E_M~0); 18118#L1349-1 assume !(0 == ~E_1~0); 17439#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17440#L1359-1 assume !(0 == ~E_3~0); 17869#L1364-1 assume !(0 == ~E_4~0); 16760#L1369-1 assume !(0 == ~E_5~0); 16761#L1374-1 assume !(0 == ~E_6~0); 17444#L1379-1 assume !(0 == ~E_7~0); 17445#L1384-1 assume !(0 == ~E_8~0); 17522#L1389-1 assume !(0 == ~E_9~0); 18055#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18056#L1399-1 assume !(0 == ~E_11~0); 18159#L1404-1 assume !(0 == ~E_12~0); 16853#L1409-1 assume !(0 == ~E_13~0); 16854#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18151#L628 assume !(1 == ~m_pc~0); 16757#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16756#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17520#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17521#L1591 assume !(0 != activate_threads_~tmp~1#1); 18164#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17308#L647 assume 1 == ~t1_pc~0; 16677#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16678#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16949#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16950#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18104#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18105#L666 assume 1 == ~t2_pc~0; 16525#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16526#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16692#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18121#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17640#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17641#L685 assume !(1 == ~t3_pc~0); 17746#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17745#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17368#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17369#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17490#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16976#L704 assume 1 == ~t4_pc~0; 16977#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17501#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17502#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18142#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17361#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17362#L723 assume !(1 == ~t5_pc~0); 17484#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17720#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17864#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17619#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17620#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16742#L742 assume 1 == ~t6_pc~0; 16743#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16891#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16892#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16427#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16428#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16819#L761 assume !(1 == ~t7_pc~0); 16820#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16688#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16689#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17491#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17492#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16452#L780 assume 1 == ~t8_pc~0; 16453#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16728#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16729#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17452#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17453#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17572#L799 assume 1 == ~t9_pc~0; 17684#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16455#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16456#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17584#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17791#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17602#L818 assume !(1 == ~t10_pc~0); 16236#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16237#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17677#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17606#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17607#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17647#L837 assume 1 == ~t11_pc~0; 17648#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17482#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17885#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17565#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17566#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17317#L856 assume !(1 == ~t12_pc~0); 17318#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17971#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17972#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 17953#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18132#L875 assume 1 == ~t13_pc~0; 17262#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16894#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16895#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16834#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16835#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17674#L1427 assume !(1 == ~M_E~0); 17658#L1427-2 assume !(1 == ~T1_E~0); 16806#L1432-1 assume !(1 == ~T2_E~0); 16807#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17875#L1442-1 assume !(1 == ~T4_E~0); 17876#L1447-1 assume !(1 == ~T5_E~0); 17731#L1452-1 assume !(1 == ~T6_E~0); 16371#L1457-1 assume !(1 == ~T7_E~0); 16372#L1462-1 assume !(1 == ~T8_E~0); 17902#L1467-1 assume !(1 == ~T9_E~0); 17920#L1472-1 assume !(1 == ~T10_E~0); 17921#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17672#L1482-1 assume !(1 == ~T12_E~0); 17673#L1487-1 assume !(1 == ~T13_E~0); 16702#L1492-1 assume !(1 == ~E_M~0); 16703#L1497-1 assume !(1 == ~E_1~0); 17064#L1502-1 assume !(1 == ~E_2~0); 17065#L1507-1 assume !(1 == ~E_3~0); 16580#L1512-1 assume !(1 == ~E_4~0); 16581#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 17991#L1522-1 assume !(1 == ~E_6~0); 17305#L1527-1 assume !(1 == ~E_7~0); 17306#L1532-1 assume !(1 == ~E_8~0); 18179#L1537-1 assume !(1 == ~E_9~0); 17508#L1542-1 assume !(1 == ~E_10~0); 17339#L1547-1 assume !(1 == ~E_11~0); 17340#L1552-1 assume !(1 == ~E_12~0); 16275#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16276#L1562-1 assume { :end_inline_reset_delta_events } true; 16882#L1928-2 [2022-11-21 13:41:59,140 INFO L750 eck$LassoCheckResult]: Loop: 16882#L1928-2 assume !false; 17373#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16536#L1254 assume !false; 17123#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16610#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16611#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16808#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17979#L1067 assume !(0 != eval_~tmp~0#1); 17049#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16626#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16627#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17086#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17068#L1284-3 assume !(0 == ~T2_E~0); 17069#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17047#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17048#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17435#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17436#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16945#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16946#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17942#L1324-3 assume !(0 == ~T10_E~0); 16577#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16578#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17345#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17346#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17644#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16927#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17655#L1364-3 assume !(0 == ~E_4~0); 18177#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18073#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16706#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16707#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16924#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16925#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17215#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18083#L1404-3 assume !(0 == ~E_12~0); 18047#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18048#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17534#L628-45 assume 1 == ~m_pc~0; 17212#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17214#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16571#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16572#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16960#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17683#L647-45 assume 1 == ~t1_pc~0; 16522#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16523#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17451#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16636#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16637#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16848#L666-45 assume !(1 == ~t2_pc~0); 16849#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17330#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17892#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17807#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17801#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16386#L685-45 assume 1 == ~t3_pc~0; 16387#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17446#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18120#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17989#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17990#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18130#L704-45 assume 1 == ~t4_pc~0; 18009#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16253#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17112#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17455#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18202#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17567#L723-45 assume !(1 == ~t5_pc~0); 17568#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18057#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17159#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16936#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 16937#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17961#L742-45 assume 1 == ~t6_pc~0; 17962#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17184#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17653#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17689#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17690#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17778#L761-45 assume !(1 == ~t7_pc~0); 17779#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17177#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17178#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16584#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16585#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18051#L780-45 assume 1 == ~t8_pc~0; 16962#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16596#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16597#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18178#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16566#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16567#L799-45 assume !(1 == ~t9_pc~0); 16787#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16788#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18103#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17732#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17733#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16504#L818-45 assume 1 == ~t10_pc~0; 16505#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16623#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17706#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17110#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17111#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17826#L837-45 assume !(1 == ~t11_pc~0); 17041#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17042#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17179#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17844#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16642#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16643#L856-45 assume 1 == ~t12_pc~0; 18128#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16645#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16586#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16587#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17449#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17450#L875-45 assume 1 == ~t13_pc~0; 17420#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17421#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17483#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18095#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18096#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18035#L1427-3 assume !(1 == ~M_E~0); 17246#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17247#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17785#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17437#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17438#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16294#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16295#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17977#L1462-3 assume !(1 == ~T8_E~0); 17978#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17841#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17842#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16545#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16546#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16687#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16860#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16861#L1502-3 assume !(1 == ~E_2~0); 17809#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17940#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16898#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16590#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16591#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16555#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16556#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17656#L1542-3 assume !(1 == ~E_10~0); 17794#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17423#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17424#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16766#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16767#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16186#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16951#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16952#L1947 assume !(0 == start_simulation_~tmp~3#1); 17557#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17762#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16823#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 18155#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 18079#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17909#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17668#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17669#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1928-2 [2022-11-21 13:41:59,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,141 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-11-21 13:41:59,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357562824] [2022-11-21 13:41:59,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357562824] [2022-11-21 13:41:59,210 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357562824] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,211 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,211 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213200734] [2022-11-21 13:41:59,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,212 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:59,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1433001491, now seen corresponding path program 1 times [2022-11-21 13:41:59,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555792848] [2022-11-21 13:41:59,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,330 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555792848] [2022-11-21 13:41:59,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555792848] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,331 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990149618] [2022-11-21 13:41:59,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,332 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:59,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:59,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:59,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:59,333 INFO L87 Difference]: Start difference. First operand 2018 states and 2984 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:59,375 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2022-11-21 13:41:59,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2983 transitions. [2022-11-21 13:41:59,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-11-21 13:41:59,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:59,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:59,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2983 transitions. [2022-11-21 13:41:59,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:59,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-11-21 13:41:59,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2983 transitions. [2022-11-21 13:41:59,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:59,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-11-21 13:41:59,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-11-21 13:41:59,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:41:59,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-11-21 13:41:59,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-21 13:41:59,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2983 transitions. [2022-11-21 13:41:59,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:59,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:59,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,459 INFO L748 eck$LassoCheckResult]: Stem: 21143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22180#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21635#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21636#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21125#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21126#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21192#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21193#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21631#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21632#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21158#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20978#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21422#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21423#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21298#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21299#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20948#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20949#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22172#L1279-2 assume !(0 == ~T1_E~0); 20571#L1284-1 assume !(0 == ~T2_E~0); 20572#L1289-1 assume !(0 == ~T3_E~0); 21295#L1294-1 assume !(0 == ~T4_E~0); 21296#L1299-1 assume !(0 == ~T5_E~0); 21307#L1304-1 assume !(0 == ~T6_E~0); 22238#L1309-1 assume !(0 == ~T7_E~0); 22239#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20501#L1319-1 assume !(0 == ~T9_E~0); 20502#L1324-1 assume !(0 == ~T10_E~0); 20674#L1329-1 assume !(0 == ~T11_E~0); 20675#L1334-1 assume !(0 == ~T12_E~0); 22079#L1339-1 assume !(0 == ~T13_E~0); 22160#L1344-1 assume !(0 == ~E_M~0); 22161#L1349-1 assume !(0 == ~E_1~0); 21482#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21483#L1359-1 assume !(0 == ~E_3~0); 21912#L1364-1 assume !(0 == ~E_4~0); 20803#L1369-1 assume !(0 == ~E_5~0); 20804#L1374-1 assume !(0 == ~E_6~0); 21487#L1379-1 assume !(0 == ~E_7~0); 21488#L1384-1 assume !(0 == ~E_8~0); 21565#L1389-1 assume !(0 == ~E_9~0); 22098#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22099#L1399-1 assume !(0 == ~E_11~0); 22202#L1404-1 assume !(0 == ~E_12~0); 20896#L1409-1 assume !(0 == ~E_13~0); 20897#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22194#L628 assume !(1 == ~m_pc~0); 20800#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20799#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21563#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21564#L1591 assume !(0 != activate_threads_~tmp~1#1); 22207#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21351#L647 assume 1 == ~t1_pc~0; 20720#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20721#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20992#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20993#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22147#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22148#L666 assume 1 == ~t2_pc~0; 20568#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20569#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20735#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22164#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21683#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21684#L685 assume !(1 == ~t3_pc~0); 21789#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21788#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21411#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21412#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21533#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21019#L704 assume 1 == ~t4_pc~0; 21020#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21544#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21545#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22185#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21404#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21405#L723 assume !(1 == ~t5_pc~0); 21527#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21763#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21907#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21662#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21663#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20785#L742 assume 1 == ~t6_pc~0; 20786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20934#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20935#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20470#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20471#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20862#L761 assume !(1 == ~t7_pc~0); 20863#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20731#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20732#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21534#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21535#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20495#L780 assume 1 == ~t8_pc~0; 20496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20771#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20772#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21495#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21496#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21615#L799 assume 1 == ~t9_pc~0; 21727#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20499#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21627#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21834#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21645#L818 assume !(1 == ~t10_pc~0); 20279#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20280#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21720#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21649#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21650#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21690#L837 assume 1 == ~t11_pc~0; 21691#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21525#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21928#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21608#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21609#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21360#L856 assume !(1 == ~t12_pc~0); 21361#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22014#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22015#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21995#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 21996#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22175#L875 assume 1 == ~t13_pc~0; 21305#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20937#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20938#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20877#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 20878#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21717#L1427 assume !(1 == ~M_E~0); 21701#L1427-2 assume !(1 == ~T1_E~0); 20849#L1432-1 assume !(1 == ~T2_E~0); 20850#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21918#L1442-1 assume !(1 == ~T4_E~0); 21919#L1447-1 assume !(1 == ~T5_E~0); 21774#L1452-1 assume !(1 == ~T6_E~0); 20414#L1457-1 assume !(1 == ~T7_E~0); 20415#L1462-1 assume !(1 == ~T8_E~0); 21945#L1467-1 assume !(1 == ~T9_E~0); 21963#L1472-1 assume !(1 == ~T10_E~0); 21964#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21715#L1482-1 assume !(1 == ~T12_E~0); 21716#L1487-1 assume !(1 == ~T13_E~0); 20745#L1492-1 assume !(1 == ~E_M~0); 20746#L1497-1 assume !(1 == ~E_1~0); 21107#L1502-1 assume !(1 == ~E_2~0); 21108#L1507-1 assume !(1 == ~E_3~0); 20623#L1512-1 assume !(1 == ~E_4~0); 20624#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22034#L1522-1 assume !(1 == ~E_6~0); 21348#L1527-1 assume !(1 == ~E_7~0); 21349#L1532-1 assume !(1 == ~E_8~0); 22222#L1537-1 assume !(1 == ~E_9~0); 21551#L1542-1 assume !(1 == ~E_10~0); 21382#L1547-1 assume !(1 == ~E_11~0); 21383#L1552-1 assume !(1 == ~E_12~0); 20318#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20319#L1562-1 assume { :end_inline_reset_delta_events } true; 20925#L1928-2 [2022-11-21 13:41:59,459 INFO L750 eck$LassoCheckResult]: Loop: 20925#L1928-2 assume !false; 21416#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20579#L1254 assume !false; 21166#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20653#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20654#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20851#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22022#L1067 assume !(0 != eval_~tmp~0#1); 21092#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20669#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20670#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21129#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21111#L1284-3 assume !(0 == ~T2_E~0); 21112#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21090#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21091#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21478#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21479#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20988#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20989#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21985#L1324-3 assume !(0 == ~T10_E~0); 20620#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20621#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21388#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21389#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21687#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20969#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20970#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21698#L1364-3 assume !(0 == ~E_4~0); 22220#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22116#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20749#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20750#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20967#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20968#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21258#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22126#L1404-3 assume !(0 == ~E_12~0); 22090#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22091#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21577#L628-45 assume 1 == ~m_pc~0; 21255#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21257#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20614#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20615#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21003#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21726#L647-45 assume 1 == ~t1_pc~0; 20565#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20566#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21494#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20679#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20680#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20891#L666-45 assume !(1 == ~t2_pc~0); 20892#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21373#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21935#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21850#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21844#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20429#L685-45 assume 1 == ~t3_pc~0; 20430#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21489#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22163#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22032#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22033#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22173#L704-45 assume 1 == ~t4_pc~0; 22052#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20296#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21155#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21498#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22245#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21610#L723-45 assume !(1 == ~t5_pc~0); 21611#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22100#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21202#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20979#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 20980#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22004#L742-45 assume 1 == ~t6_pc~0; 22005#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21227#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21696#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21732#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21733#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21821#L761-45 assume !(1 == ~t7_pc~0); 21822#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21220#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21221#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20627#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20628#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22094#L780-45 assume 1 == ~t8_pc~0; 21005#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20639#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20640#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22221#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20609#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20610#L799-45 assume 1 == ~t9_pc~0; 21386#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20831#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22146#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21775#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21776#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20547#L818-45 assume 1 == ~t10_pc~0; 20548#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20666#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21749#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21153#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21154#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21869#L837-45 assume !(1 == ~t11_pc~0); 21084#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21085#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21222#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21887#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20685#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20686#L856-45 assume 1 == ~t12_pc~0; 22171#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20688#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20629#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20630#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21492#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21493#L875-45 assume 1 == ~t13_pc~0; 21463#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21464#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21526#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22138#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22139#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22078#L1427-3 assume !(1 == ~M_E~0); 21289#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21290#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21828#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21480#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21481#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20337#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20338#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22020#L1462-3 assume !(1 == ~T8_E~0); 22021#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21884#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21885#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20588#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20589#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20730#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20903#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20904#L1502-3 assume !(1 == ~E_2~0); 21852#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21983#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20941#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20633#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20634#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20598#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20599#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21699#L1542-3 assume !(1 == ~E_10~0); 21837#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21466#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21467#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20809#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20810#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20229#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20994#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20995#L1947 assume !(0 == start_simulation_~tmp~3#1); 21600#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21805#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20866#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22198#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 22122#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21952#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21711#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21712#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 20925#L1928-2 [2022-11-21 13:41:59,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-11-21 13:41:59,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229743187] [2022-11-21 13:41:59,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229743187] [2022-11-21 13:41:59,549 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229743187] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,549 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,549 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353317837] [2022-11-21 13:41:59,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,556 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:59,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,559 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 2 times [2022-11-21 13:41:59,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606118233] [2022-11-21 13:41:59,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606118233] [2022-11-21 13:41:59,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606118233] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369030214] [2022-11-21 13:41:59,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,676 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:59,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:59,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:59,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:59,677 INFO L87 Difference]: Start difference. First operand 2018 states and 2983 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:41:59,728 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2022-11-21 13:41:59,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2982 transitions. [2022-11-21 13:41:59,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-11-21 13:41:59,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:41:59,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:41:59,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2982 transitions. [2022-11-21 13:41:59,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:41:59,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-11-21 13:41:59,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2982 transitions. [2022-11-21 13:41:59,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:41:59,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:41:59,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-11-21 13:41:59,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-11-21 13:41:59,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:41:59,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-11-21 13:41:59,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-21 13:41:59,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2982 transitions. [2022-11-21 13:41:59,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:41:59,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:41:59,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:41:59,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:41:59,820 INFO L748 eck$LassoCheckResult]: Stem: 25186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 26223#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25678#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25679#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25168#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25169#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25235#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25236#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25674#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25675#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25201#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25020#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25021#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25465#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25466#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25341#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25342#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 24991#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24992#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26215#L1279-2 assume !(0 == ~T1_E~0); 24614#L1284-1 assume !(0 == ~T2_E~0); 24615#L1289-1 assume !(0 == ~T3_E~0); 25338#L1294-1 assume !(0 == ~T4_E~0); 25339#L1299-1 assume !(0 == ~T5_E~0); 25350#L1304-1 assume !(0 == ~T6_E~0); 26281#L1309-1 assume !(0 == ~T7_E~0); 26282#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24544#L1319-1 assume !(0 == ~T9_E~0); 24545#L1324-1 assume !(0 == ~T10_E~0); 24717#L1329-1 assume !(0 == ~T11_E~0); 24718#L1334-1 assume !(0 == ~T12_E~0); 26122#L1339-1 assume !(0 == ~T13_E~0); 26203#L1344-1 assume !(0 == ~E_M~0); 26204#L1349-1 assume !(0 == ~E_1~0); 25525#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25526#L1359-1 assume !(0 == ~E_3~0); 25955#L1364-1 assume !(0 == ~E_4~0); 24846#L1369-1 assume !(0 == ~E_5~0); 24847#L1374-1 assume !(0 == ~E_6~0); 25530#L1379-1 assume !(0 == ~E_7~0); 25531#L1384-1 assume !(0 == ~E_8~0); 25608#L1389-1 assume !(0 == ~E_9~0); 26141#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26142#L1399-1 assume !(0 == ~E_11~0); 26245#L1404-1 assume !(0 == ~E_12~0); 24939#L1409-1 assume !(0 == ~E_13~0); 24940#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26237#L628 assume !(1 == ~m_pc~0); 24843#L628-2 is_master_triggered_~__retres1~0#1 := 0; 24842#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25606#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25607#L1591 assume !(0 != activate_threads_~tmp~1#1); 26250#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25394#L647 assume 1 == ~t1_pc~0; 24763#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24764#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25035#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25036#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26190#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26191#L666 assume 1 == ~t2_pc~0; 24611#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24612#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24778#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26207#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25726#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25727#L685 assume !(1 == ~t3_pc~0); 25832#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25831#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25454#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25455#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25576#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25062#L704 assume 1 == ~t4_pc~0; 25063#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25587#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25588#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26228#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25447#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25448#L723 assume !(1 == ~t5_pc~0); 25570#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25806#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25950#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25705#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25706#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24828#L742 assume 1 == ~t6_pc~0; 24829#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24977#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24978#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24513#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24514#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24905#L761 assume !(1 == ~t7_pc~0); 24906#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24774#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24775#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25577#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25578#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24538#L780 assume 1 == ~t8_pc~0; 24539#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24814#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24815#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25538#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25539#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25658#L799 assume 1 == ~t9_pc~0; 25770#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24541#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24542#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25670#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 25877#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25688#L818 assume !(1 == ~t10_pc~0); 24322#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24323#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25763#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25692#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25693#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25733#L837 assume 1 == ~t11_pc~0; 25734#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25568#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25971#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25651#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25652#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25403#L856 assume !(1 == ~t12_pc~0); 25404#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26057#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26058#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26038#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26039#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26218#L875 assume 1 == ~t13_pc~0; 25348#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 24980#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24981#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24920#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 24921#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25760#L1427 assume !(1 == ~M_E~0); 25744#L1427-2 assume !(1 == ~T1_E~0); 24892#L1432-1 assume !(1 == ~T2_E~0); 24893#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25961#L1442-1 assume !(1 == ~T4_E~0); 25962#L1447-1 assume !(1 == ~T5_E~0); 25817#L1452-1 assume !(1 == ~T6_E~0); 24457#L1457-1 assume !(1 == ~T7_E~0); 24458#L1462-1 assume !(1 == ~T8_E~0); 25988#L1467-1 assume !(1 == ~T9_E~0); 26006#L1472-1 assume !(1 == ~T10_E~0); 26007#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25758#L1482-1 assume !(1 == ~T12_E~0); 25759#L1487-1 assume !(1 == ~T13_E~0); 24788#L1492-1 assume !(1 == ~E_M~0); 24789#L1497-1 assume !(1 == ~E_1~0); 25150#L1502-1 assume !(1 == ~E_2~0); 25151#L1507-1 assume !(1 == ~E_3~0); 24666#L1512-1 assume !(1 == ~E_4~0); 24667#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26077#L1522-1 assume !(1 == ~E_6~0); 25391#L1527-1 assume !(1 == ~E_7~0); 25392#L1532-1 assume !(1 == ~E_8~0); 26265#L1537-1 assume !(1 == ~E_9~0); 25594#L1542-1 assume !(1 == ~E_10~0); 25425#L1547-1 assume !(1 == ~E_11~0); 25426#L1552-1 assume !(1 == ~E_12~0); 24361#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24362#L1562-1 assume { :end_inline_reset_delta_events } true; 24968#L1928-2 [2022-11-21 13:41:59,821 INFO L750 eck$LassoCheckResult]: Loop: 24968#L1928-2 assume !false; 25459#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24622#L1254 assume !false; 25209#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24696#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24697#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24894#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26065#L1067 assume !(0 != eval_~tmp~0#1); 25135#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24712#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24713#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25172#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25154#L1284-3 assume !(0 == ~T2_E~0); 25155#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25133#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25134#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25521#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25522#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25031#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25032#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26028#L1324-3 assume !(0 == ~T10_E~0); 24663#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24664#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25431#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25432#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25730#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25012#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25013#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25741#L1364-3 assume !(0 == ~E_4~0); 26263#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26159#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24792#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24793#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25010#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25011#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25301#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26169#L1404-3 assume !(0 == ~E_12~0); 26133#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26134#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25620#L628-45 assume 1 == ~m_pc~0; 25298#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25300#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24657#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24658#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25046#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25769#L647-45 assume 1 == ~t1_pc~0; 24608#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24609#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25537#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24722#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24723#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24934#L666-45 assume !(1 == ~t2_pc~0); 24935#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25416#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25978#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25893#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25887#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24472#L685-45 assume 1 == ~t3_pc~0; 24473#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25532#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26206#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26075#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26076#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26216#L704-45 assume !(1 == ~t4_pc~0); 24338#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24339#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25198#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25541#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26288#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25653#L723-45 assume !(1 == ~t5_pc~0); 25654#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 26143#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25245#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25022#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25023#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26047#L742-45 assume 1 == ~t6_pc~0; 26048#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25270#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25739#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25775#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25776#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25864#L761-45 assume !(1 == ~t7_pc~0); 25865#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25263#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25264#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24670#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24671#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26137#L780-45 assume 1 == ~t8_pc~0; 25048#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24682#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24683#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26264#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24652#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24653#L799-45 assume 1 == ~t9_pc~0; 25429#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24874#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26189#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25818#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25819#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24590#L818-45 assume !(1 == ~t10_pc~0); 24592#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24709#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25792#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25196#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25197#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25912#L837-45 assume !(1 == ~t11_pc~0); 25127#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25128#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25265#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25930#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24728#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24729#L856-45 assume 1 == ~t12_pc~0; 26214#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24731#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24672#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24673#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25535#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25536#L875-45 assume 1 == ~t13_pc~0; 25506#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25507#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25569#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26181#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26182#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26121#L1427-3 assume !(1 == ~M_E~0); 25332#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25333#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25871#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25523#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25524#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24380#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24381#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26063#L1462-3 assume !(1 == ~T8_E~0); 26064#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25927#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25928#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24631#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24632#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24773#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24946#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24947#L1502-3 assume !(1 == ~E_2~0); 25895#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26026#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24984#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24676#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24677#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24641#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24642#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25742#L1542-3 assume !(1 == ~E_10~0); 25880#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25509#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25510#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24852#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24853#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24272#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25037#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25038#L1947 assume !(0 == start_simulation_~tmp~3#1); 25643#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25848#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24909#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26241#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 26165#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25995#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25754#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25755#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 24968#L1928-2 [2022-11-21 13:41:59,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,822 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-11-21 13:41:59,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827047787] [2022-11-21 13:41:59,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827047787] [2022-11-21 13:41:59,880 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827047787] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,880 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,881 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968045812] [2022-11-21 13:41:59,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,881 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:41:59,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:41:59,882 INFO L85 PathProgramCache]: Analyzing trace with hash -130029202, now seen corresponding path program 1 times [2022-11-21 13:41:59,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:41:59,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053699512] [2022-11-21 13:41:59,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:41:59,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:41:59,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:41:59,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:41:59,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:41:59,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053699512] [2022-11-21 13:41:59,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053699512] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:41:59,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:41:59,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:41:59,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865977748] [2022-11-21 13:41:59,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:41:59,959 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:41:59,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:41:59,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:41:59,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:41:59,960 INFO L87 Difference]: Start difference. First operand 2018 states and 2982 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:00,036 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2022-11-21 13:42:00,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2981 transitions. [2022-11-21 13:42:00,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-11-21 13:42:00,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:00,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:00,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2981 transitions. [2022-11-21 13:42:00,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:00,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-11-21 13:42:00,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2981 transitions. [2022-11-21 13:42:00,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:00,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-11-21 13:42:00,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-11-21 13:42:00,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:00,095 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-11-21 13:42:00,096 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-21 13:42:00,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2981 transitions. [2022-11-21 13:42:00,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:00,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:00,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,107 INFO L748 eck$LassoCheckResult]: Stem: 29229#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29230#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30266#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29721#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29722#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29211#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29212#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29278#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29279#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29717#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29718#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29244#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29063#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29064#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29508#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29509#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29384#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29385#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29034#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29035#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30258#L1279-2 assume !(0 == ~T1_E~0); 28657#L1284-1 assume !(0 == ~T2_E~0); 28658#L1289-1 assume !(0 == ~T3_E~0); 29381#L1294-1 assume !(0 == ~T4_E~0); 29382#L1299-1 assume !(0 == ~T5_E~0); 29393#L1304-1 assume !(0 == ~T6_E~0); 30324#L1309-1 assume !(0 == ~T7_E~0); 30325#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28587#L1319-1 assume !(0 == ~T9_E~0); 28588#L1324-1 assume !(0 == ~T10_E~0); 28760#L1329-1 assume !(0 == ~T11_E~0); 28761#L1334-1 assume !(0 == ~T12_E~0); 30165#L1339-1 assume !(0 == ~T13_E~0); 30246#L1344-1 assume !(0 == ~E_M~0); 30247#L1349-1 assume !(0 == ~E_1~0); 29568#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29569#L1359-1 assume !(0 == ~E_3~0); 29998#L1364-1 assume !(0 == ~E_4~0); 28889#L1369-1 assume !(0 == ~E_5~0); 28890#L1374-1 assume !(0 == ~E_6~0); 29573#L1379-1 assume !(0 == ~E_7~0); 29574#L1384-1 assume !(0 == ~E_8~0); 29651#L1389-1 assume !(0 == ~E_9~0); 30184#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30185#L1399-1 assume !(0 == ~E_11~0); 30288#L1404-1 assume !(0 == ~E_12~0); 28982#L1409-1 assume !(0 == ~E_13~0); 28983#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30280#L628 assume !(1 == ~m_pc~0); 28886#L628-2 is_master_triggered_~__retres1~0#1 := 0; 28885#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29649#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29650#L1591 assume !(0 != activate_threads_~tmp~1#1); 30293#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29437#L647 assume 1 == ~t1_pc~0; 28806#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28807#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29078#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29079#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30233#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30234#L666 assume 1 == ~t2_pc~0; 28654#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28655#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28821#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30250#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29769#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29770#L685 assume !(1 == ~t3_pc~0); 29875#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29874#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29497#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29498#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29619#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29105#L704 assume 1 == ~t4_pc~0; 29106#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29630#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29631#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30271#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29490#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29491#L723 assume !(1 == ~t5_pc~0); 29613#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29849#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29993#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29748#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29749#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28871#L742 assume 1 == ~t6_pc~0; 28872#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29020#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29021#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28556#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28557#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28948#L761 assume !(1 == ~t7_pc~0); 28949#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28817#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28818#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29620#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29621#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28581#L780 assume 1 == ~t8_pc~0; 28582#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28857#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28858#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29581#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29582#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29701#L799 assume 1 == ~t9_pc~0; 29813#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28584#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28585#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29713#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 29920#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29731#L818 assume !(1 == ~t10_pc~0); 28365#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28366#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29806#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29735#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29736#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29776#L837 assume 1 == ~t11_pc~0; 29777#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29611#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30014#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29694#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29695#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29446#L856 assume !(1 == ~t12_pc~0); 29447#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30100#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30101#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30081#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30082#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30261#L875 assume 1 == ~t13_pc~0; 29391#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29023#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29024#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28963#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 28964#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29803#L1427 assume !(1 == ~M_E~0); 29787#L1427-2 assume !(1 == ~T1_E~0); 28935#L1432-1 assume !(1 == ~T2_E~0); 28936#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30004#L1442-1 assume !(1 == ~T4_E~0); 30005#L1447-1 assume !(1 == ~T5_E~0); 29860#L1452-1 assume !(1 == ~T6_E~0); 28500#L1457-1 assume !(1 == ~T7_E~0); 28501#L1462-1 assume !(1 == ~T8_E~0); 30031#L1467-1 assume !(1 == ~T9_E~0); 30049#L1472-1 assume !(1 == ~T10_E~0); 30050#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29801#L1482-1 assume !(1 == ~T12_E~0); 29802#L1487-1 assume !(1 == ~T13_E~0); 28831#L1492-1 assume !(1 == ~E_M~0); 28832#L1497-1 assume !(1 == ~E_1~0); 29193#L1502-1 assume !(1 == ~E_2~0); 29194#L1507-1 assume !(1 == ~E_3~0); 28709#L1512-1 assume !(1 == ~E_4~0); 28710#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30120#L1522-1 assume !(1 == ~E_6~0); 29434#L1527-1 assume !(1 == ~E_7~0); 29435#L1532-1 assume !(1 == ~E_8~0); 30308#L1537-1 assume !(1 == ~E_9~0); 29637#L1542-1 assume !(1 == ~E_10~0); 29468#L1547-1 assume !(1 == ~E_11~0); 29469#L1552-1 assume !(1 == ~E_12~0); 28404#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28405#L1562-1 assume { :end_inline_reset_delta_events } true; 29011#L1928-2 [2022-11-21 13:42:00,108 INFO L750 eck$LassoCheckResult]: Loop: 29011#L1928-2 assume !false; 29502#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28665#L1254 assume !false; 29252#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28739#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28740#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28937#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30108#L1067 assume !(0 != eval_~tmp~0#1); 29178#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28755#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28756#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29215#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29197#L1284-3 assume !(0 == ~T2_E~0); 29198#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29176#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29177#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29564#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29565#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29074#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29075#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30071#L1324-3 assume !(0 == ~T10_E~0); 28706#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28707#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29474#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29475#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29773#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29055#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29056#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29784#L1364-3 assume !(0 == ~E_4~0); 30306#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30202#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28835#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28836#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29053#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29054#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29344#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30212#L1404-3 assume !(0 == ~E_12~0); 30176#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30177#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29663#L628-45 assume 1 == ~m_pc~0; 29341#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29343#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28700#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28701#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29089#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29812#L647-45 assume 1 == ~t1_pc~0; 28651#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28652#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29580#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28765#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28766#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28977#L666-45 assume !(1 == ~t2_pc~0); 28978#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29459#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30021#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29936#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29930#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28515#L685-45 assume 1 == ~t3_pc~0; 28516#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29575#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30249#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30118#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30119#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30259#L704-45 assume 1 == ~t4_pc~0; 30138#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28382#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29241#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29584#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30331#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29696#L723-45 assume !(1 == ~t5_pc~0); 29697#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30186#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29288#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29065#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29066#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30090#L742-45 assume !(1 == ~t6_pc~0); 29312#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29313#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29782#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29818#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29819#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29907#L761-45 assume !(1 == ~t7_pc~0); 29908#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29306#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29307#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28713#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28714#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30180#L780-45 assume 1 == ~t8_pc~0; 29091#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28725#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28726#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30307#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28695#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28696#L799-45 assume 1 == ~t9_pc~0; 29472#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28917#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30232#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29861#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29862#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28633#L818-45 assume 1 == ~t10_pc~0; 28634#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28752#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29835#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29239#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29240#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29955#L837-45 assume !(1 == ~t11_pc~0); 29170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29171#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29308#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29973#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28771#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28772#L856-45 assume 1 == ~t12_pc~0; 30257#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28774#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28715#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28716#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29578#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29579#L875-45 assume 1 == ~t13_pc~0; 29549#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29550#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29612#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30224#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30225#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30164#L1427-3 assume !(1 == ~M_E~0); 29375#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29376#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29914#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29566#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29567#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28423#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28424#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30106#L1462-3 assume !(1 == ~T8_E~0); 30107#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29970#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29971#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28674#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28675#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 28816#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28989#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28990#L1502-3 assume !(1 == ~E_2~0); 29938#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30069#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29027#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28719#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28720#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28684#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28685#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29785#L1542-3 assume !(1 == ~E_10~0); 29923#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29552#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29553#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28895#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28896#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28315#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29080#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29081#L1947 assume !(0 == start_simulation_~tmp~3#1); 29686#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29891#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28952#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30284#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 30208#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30038#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29797#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29798#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29011#L1928-2 [2022-11-21 13:42:00,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-11-21 13:42:00,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870075111] [2022-11-21 13:42:00,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870075111] [2022-11-21 13:42:00,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870075111] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618908414] [2022-11-21 13:42:00,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,169 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:00,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,169 INFO L85 PathProgramCache]: Analyzing trace with hash -864361555, now seen corresponding path program 1 times [2022-11-21 13:42:00,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799049427] [2022-11-21 13:42:00,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799049427] [2022-11-21 13:42:00,250 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799049427] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,250 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,250 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859469610] [2022-11-21 13:42:00,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,251 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:00,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:00,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:00,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:00,252 INFO L87 Difference]: Start difference. First operand 2018 states and 2981 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:00,294 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2022-11-21 13:42:00,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2980 transitions. [2022-11-21 13:42:00,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-11-21 13:42:00,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:00,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:00,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2980 transitions. [2022-11-21 13:42:00,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:00,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-11-21 13:42:00,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2980 transitions. [2022-11-21 13:42:00,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:00,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-11-21 13:42:00,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-11-21 13:42:00,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:00,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-11-21 13:42:00,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-21 13:42:00,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2980 transitions. [2022-11-21 13:42:00,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:00,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:00,364 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,365 INFO L748 eck$LassoCheckResult]: Stem: 33272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 34309#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33764#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33765#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33254#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33255#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33321#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33322#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33760#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33761#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33287#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33106#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33107#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33551#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33552#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33427#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33428#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33077#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33078#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34301#L1279-2 assume !(0 == ~T1_E~0); 32700#L1284-1 assume !(0 == ~T2_E~0); 32701#L1289-1 assume !(0 == ~T3_E~0); 33424#L1294-1 assume !(0 == ~T4_E~0); 33425#L1299-1 assume !(0 == ~T5_E~0); 33436#L1304-1 assume !(0 == ~T6_E~0); 34367#L1309-1 assume !(0 == ~T7_E~0); 34368#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32630#L1319-1 assume !(0 == ~T9_E~0); 32631#L1324-1 assume !(0 == ~T10_E~0); 32803#L1329-1 assume !(0 == ~T11_E~0); 32804#L1334-1 assume !(0 == ~T12_E~0); 34208#L1339-1 assume !(0 == ~T13_E~0); 34289#L1344-1 assume !(0 == ~E_M~0); 34290#L1349-1 assume !(0 == ~E_1~0); 33611#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33612#L1359-1 assume !(0 == ~E_3~0); 34041#L1364-1 assume !(0 == ~E_4~0); 32932#L1369-1 assume !(0 == ~E_5~0); 32933#L1374-1 assume !(0 == ~E_6~0); 33616#L1379-1 assume !(0 == ~E_7~0); 33617#L1384-1 assume !(0 == ~E_8~0); 33694#L1389-1 assume !(0 == ~E_9~0); 34227#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34228#L1399-1 assume !(0 == ~E_11~0); 34331#L1404-1 assume !(0 == ~E_12~0); 33025#L1409-1 assume !(0 == ~E_13~0); 33026#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34323#L628 assume !(1 == ~m_pc~0); 32929#L628-2 is_master_triggered_~__retres1~0#1 := 0; 32928#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33692#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33693#L1591 assume !(0 != activate_threads_~tmp~1#1); 34336#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33480#L647 assume 1 == ~t1_pc~0; 32849#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32850#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33121#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33122#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34276#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34277#L666 assume 1 == ~t2_pc~0; 32697#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32698#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32864#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34293#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 33812#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33813#L685 assume !(1 == ~t3_pc~0); 33918#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33917#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33540#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33541#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33662#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33148#L704 assume 1 == ~t4_pc~0; 33149#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33673#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33674#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34314#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33533#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33534#L723 assume !(1 == ~t5_pc~0); 33656#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33892#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34036#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33791#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 33792#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32914#L742 assume 1 == ~t6_pc~0; 32915#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33063#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33064#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32599#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32600#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32991#L761 assume !(1 == ~t7_pc~0); 32992#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32860#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32861#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33663#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33664#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32624#L780 assume 1 == ~t8_pc~0; 32625#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32900#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32901#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33624#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33625#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33744#L799 assume 1 == ~t9_pc~0; 33856#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32627#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32628#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33756#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 33963#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33774#L818 assume !(1 == ~t10_pc~0); 32408#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32409#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33849#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33778#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33779#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33819#L837 assume 1 == ~t11_pc~0; 33820#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33654#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34057#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33737#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33738#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33489#L856 assume !(1 == ~t12_pc~0); 33490#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34143#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34144#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34124#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34125#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34304#L875 assume 1 == ~t13_pc~0; 33434#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33066#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33067#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33006#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33007#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33846#L1427 assume !(1 == ~M_E~0); 33830#L1427-2 assume !(1 == ~T1_E~0); 32978#L1432-1 assume !(1 == ~T2_E~0); 32979#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34047#L1442-1 assume !(1 == ~T4_E~0); 34048#L1447-1 assume !(1 == ~T5_E~0); 33903#L1452-1 assume !(1 == ~T6_E~0); 32543#L1457-1 assume !(1 == ~T7_E~0); 32544#L1462-1 assume !(1 == ~T8_E~0); 34074#L1467-1 assume !(1 == ~T9_E~0); 34092#L1472-1 assume !(1 == ~T10_E~0); 34093#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33844#L1482-1 assume !(1 == ~T12_E~0); 33845#L1487-1 assume !(1 == ~T13_E~0); 32874#L1492-1 assume !(1 == ~E_M~0); 32875#L1497-1 assume !(1 == ~E_1~0); 33236#L1502-1 assume !(1 == ~E_2~0); 33237#L1507-1 assume !(1 == ~E_3~0); 32752#L1512-1 assume !(1 == ~E_4~0); 32753#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34163#L1522-1 assume !(1 == ~E_6~0); 33477#L1527-1 assume !(1 == ~E_7~0); 33478#L1532-1 assume !(1 == ~E_8~0); 34351#L1537-1 assume !(1 == ~E_9~0); 33680#L1542-1 assume !(1 == ~E_10~0); 33511#L1547-1 assume !(1 == ~E_11~0); 33512#L1552-1 assume !(1 == ~E_12~0); 32447#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32448#L1562-1 assume { :end_inline_reset_delta_events } true; 33054#L1928-2 [2022-11-21 13:42:00,366 INFO L750 eck$LassoCheckResult]: Loop: 33054#L1928-2 assume !false; 33545#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32708#L1254 assume !false; 33295#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32782#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32783#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32980#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34151#L1067 assume !(0 != eval_~tmp~0#1); 33221#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32798#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32799#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33258#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33240#L1284-3 assume !(0 == ~T2_E~0); 33241#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33219#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33220#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33607#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33608#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33117#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33118#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34114#L1324-3 assume !(0 == ~T10_E~0); 32749#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32750#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33517#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33518#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33816#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33098#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33099#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33827#L1364-3 assume !(0 == ~E_4~0); 34349#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34245#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32878#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32879#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33096#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33097#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33387#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34255#L1404-3 assume !(0 == ~E_12~0); 34219#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34220#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33706#L628-45 assume 1 == ~m_pc~0; 33384#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33386#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32743#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32744#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33132#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33855#L647-45 assume 1 == ~t1_pc~0; 32694#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32695#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33623#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32808#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32809#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33020#L666-45 assume !(1 == ~t2_pc~0); 33021#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33502#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34064#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33979#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33973#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32558#L685-45 assume !(1 == ~t3_pc~0); 32560#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 33618#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34292#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34161#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34162#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34302#L704-45 assume 1 == ~t4_pc~0; 34181#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32425#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33627#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34374#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33739#L723-45 assume !(1 == ~t5_pc~0); 33740#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34229#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33331#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33108#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33109#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34133#L742-45 assume 1 == ~t6_pc~0; 34134#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33356#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33825#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33861#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33862#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33950#L761-45 assume 1 == ~t7_pc~0; 33952#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33349#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33350#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32756#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32757#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34223#L780-45 assume 1 == ~t8_pc~0; 33134#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32768#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32769#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34350#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32738#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32739#L799-45 assume 1 == ~t9_pc~0; 33515#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32960#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34275#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33904#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33905#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32676#L818-45 assume 1 == ~t10_pc~0; 32677#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32795#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33878#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33282#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33283#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33998#L837-45 assume !(1 == ~t11_pc~0); 33213#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33214#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33351#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34016#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32814#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32815#L856-45 assume !(1 == ~t12_pc~0); 32816#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 32817#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32758#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32759#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33621#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33622#L875-45 assume 1 == ~t13_pc~0; 33592#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33593#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33655#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34267#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34268#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34207#L1427-3 assume !(1 == ~M_E~0); 33418#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33419#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33957#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33609#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33610#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32466#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32467#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34149#L1462-3 assume !(1 == ~T8_E~0); 34150#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34013#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34014#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32717#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32718#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 32859#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33032#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33033#L1502-3 assume !(1 == ~E_2~0); 33981#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34112#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33070#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32762#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32763#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32727#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32728#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33828#L1542-3 assume !(1 == ~E_10~0); 33966#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33595#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33596#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32938#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32939#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32358#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33123#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33124#L1947 assume !(0 == start_simulation_~tmp~3#1); 33729#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33934#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32995#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34327#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 34251#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34081#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33840#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33841#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33054#L1928-2 [2022-11-21 13:42:00,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-11-21 13:42:00,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471271771] [2022-11-21 13:42:00,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471271771] [2022-11-21 13:42:00,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471271771] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,422 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547246229] [2022-11-21 13:42:00,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:00,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1275216595, now seen corresponding path program 1 times [2022-11-21 13:42:00,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894658439] [2022-11-21 13:42:00,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894658439] [2022-11-21 13:42:00,505 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894658439] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280364039] [2022-11-21 13:42:00,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:00,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:00,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:00,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:00,508 INFO L87 Difference]: Start difference. First operand 2018 states and 2980 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:00,549 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2022-11-21 13:42:00,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2979 transitions. [2022-11-21 13:42:00,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-11-21 13:42:00,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:00,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:00,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2979 transitions. [2022-11-21 13:42:00,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:00,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-11-21 13:42:00,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2979 transitions. [2022-11-21 13:42:00,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:00,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-11-21 13:42:00,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-11-21 13:42:00,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:00,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-11-21 13:42:00,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-21 13:42:00,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2979 transitions. [2022-11-21 13:42:00,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:00,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:00,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:00,690 INFO L748 eck$LassoCheckResult]: Stem: 37315#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38352#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37807#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37808#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37297#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37298#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37364#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37365#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37803#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37804#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37330#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37149#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37150#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37594#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37595#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37470#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37471#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37120#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37121#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38344#L1279-2 assume !(0 == ~T1_E~0); 36743#L1284-1 assume !(0 == ~T2_E~0); 36744#L1289-1 assume !(0 == ~T3_E~0); 37467#L1294-1 assume !(0 == ~T4_E~0); 37468#L1299-1 assume !(0 == ~T5_E~0); 37479#L1304-1 assume !(0 == ~T6_E~0); 38410#L1309-1 assume !(0 == ~T7_E~0); 38411#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36673#L1319-1 assume !(0 == ~T9_E~0); 36674#L1324-1 assume !(0 == ~T10_E~0); 36846#L1329-1 assume !(0 == ~T11_E~0); 36847#L1334-1 assume !(0 == ~T12_E~0); 38251#L1339-1 assume !(0 == ~T13_E~0); 38332#L1344-1 assume !(0 == ~E_M~0); 38333#L1349-1 assume !(0 == ~E_1~0); 37654#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37655#L1359-1 assume !(0 == ~E_3~0); 38084#L1364-1 assume !(0 == ~E_4~0); 36975#L1369-1 assume !(0 == ~E_5~0); 36976#L1374-1 assume !(0 == ~E_6~0); 37659#L1379-1 assume !(0 == ~E_7~0); 37660#L1384-1 assume !(0 == ~E_8~0); 37737#L1389-1 assume !(0 == ~E_9~0); 38270#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38271#L1399-1 assume !(0 == ~E_11~0); 38374#L1404-1 assume !(0 == ~E_12~0); 37068#L1409-1 assume !(0 == ~E_13~0); 37069#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38366#L628 assume !(1 == ~m_pc~0); 36972#L628-2 is_master_triggered_~__retres1~0#1 := 0; 36971#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37735#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37736#L1591 assume !(0 != activate_threads_~tmp~1#1); 38379#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37523#L647 assume 1 == ~t1_pc~0; 36892#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36893#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37164#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37165#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38319#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38320#L666 assume 1 == ~t2_pc~0; 36740#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36741#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36907#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38336#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 37855#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37856#L685 assume !(1 == ~t3_pc~0); 37961#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37960#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37583#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37584#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37705#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37191#L704 assume 1 == ~t4_pc~0; 37192#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37716#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37717#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38357#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37576#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37577#L723 assume !(1 == ~t5_pc~0); 37699#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37935#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38079#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37834#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 37835#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36957#L742 assume 1 == ~t6_pc~0; 36958#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37106#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37107#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36642#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36643#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37034#L761 assume !(1 == ~t7_pc~0); 37035#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36903#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36904#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37706#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37707#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36667#L780 assume 1 == ~t8_pc~0; 36668#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36943#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36944#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37667#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37668#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37787#L799 assume 1 == ~t9_pc~0; 37899#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36670#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36671#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37799#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 38006#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37817#L818 assume !(1 == ~t10_pc~0); 36451#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36452#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37892#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37821#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37822#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37862#L837 assume 1 == ~t11_pc~0; 37863#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37697#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38100#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37780#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 37781#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37532#L856 assume !(1 == ~t12_pc~0); 37533#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38186#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38187#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38167#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38168#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38347#L875 assume 1 == ~t13_pc~0; 37477#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37109#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37110#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37049#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37050#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37889#L1427 assume !(1 == ~M_E~0); 37873#L1427-2 assume !(1 == ~T1_E~0); 37021#L1432-1 assume !(1 == ~T2_E~0); 37022#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38090#L1442-1 assume !(1 == ~T4_E~0); 38091#L1447-1 assume !(1 == ~T5_E~0); 37946#L1452-1 assume !(1 == ~T6_E~0); 36586#L1457-1 assume !(1 == ~T7_E~0); 36587#L1462-1 assume !(1 == ~T8_E~0); 38117#L1467-1 assume !(1 == ~T9_E~0); 38135#L1472-1 assume !(1 == ~T10_E~0); 38136#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37887#L1482-1 assume !(1 == ~T12_E~0); 37888#L1487-1 assume !(1 == ~T13_E~0); 36917#L1492-1 assume !(1 == ~E_M~0); 36918#L1497-1 assume !(1 == ~E_1~0); 37279#L1502-1 assume !(1 == ~E_2~0); 37280#L1507-1 assume !(1 == ~E_3~0); 36795#L1512-1 assume !(1 == ~E_4~0); 36796#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38206#L1522-1 assume !(1 == ~E_6~0); 37520#L1527-1 assume !(1 == ~E_7~0); 37521#L1532-1 assume !(1 == ~E_8~0); 38394#L1537-1 assume !(1 == ~E_9~0); 37723#L1542-1 assume !(1 == ~E_10~0); 37554#L1547-1 assume !(1 == ~E_11~0); 37555#L1552-1 assume !(1 == ~E_12~0); 36490#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36491#L1562-1 assume { :end_inline_reset_delta_events } true; 37097#L1928-2 [2022-11-21 13:42:00,691 INFO L750 eck$LassoCheckResult]: Loop: 37097#L1928-2 assume !false; 37588#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36751#L1254 assume !false; 37338#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36825#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36826#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37023#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38194#L1067 assume !(0 != eval_~tmp~0#1); 37264#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36841#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36842#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37301#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37283#L1284-3 assume !(0 == ~T2_E~0); 37284#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37262#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37263#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37650#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37651#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37160#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37161#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38157#L1324-3 assume !(0 == ~T10_E~0); 36792#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36793#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37560#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37561#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37859#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37141#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37142#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37870#L1364-3 assume !(0 == ~E_4~0); 38392#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38288#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36921#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36922#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37139#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37140#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37430#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38298#L1404-3 assume !(0 == ~E_12~0); 38262#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38263#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37749#L628-45 assume 1 == ~m_pc~0; 37427#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37429#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36786#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36787#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37175#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37898#L647-45 assume 1 == ~t1_pc~0; 36737#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36738#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37666#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36851#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36852#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37063#L666-45 assume !(1 == ~t2_pc~0); 37064#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37545#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38107#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38022#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38016#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36601#L685-45 assume 1 == ~t3_pc~0; 36602#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37661#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38335#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38204#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38205#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38345#L704-45 assume 1 == ~t4_pc~0; 38224#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36468#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37327#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37670#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38417#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37782#L723-45 assume !(1 == ~t5_pc~0); 37783#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38272#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37374#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37151#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37152#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38176#L742-45 assume 1 == ~t6_pc~0; 38177#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37399#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37868#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37904#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37905#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37993#L761-45 assume !(1 == ~t7_pc~0); 37994#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37392#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37393#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36799#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36800#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38266#L780-45 assume 1 == ~t8_pc~0; 37177#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36811#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36812#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38393#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36781#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36782#L799-45 assume 1 == ~t9_pc~0; 37558#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37003#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38318#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37947#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37948#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36719#L818-45 assume 1 == ~t10_pc~0; 36720#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36838#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37921#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37325#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37326#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38041#L837-45 assume !(1 == ~t11_pc~0); 37256#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37257#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37394#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38059#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36857#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36858#L856-45 assume 1 == ~t12_pc~0; 38343#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36860#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36801#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36802#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37664#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37665#L875-45 assume 1 == ~t13_pc~0; 37635#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37636#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37698#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38310#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38311#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38250#L1427-3 assume !(1 == ~M_E~0); 37461#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37462#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38000#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37652#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37653#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36509#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36510#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38192#L1462-3 assume !(1 == ~T8_E~0); 38193#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38056#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38057#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36760#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36761#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 36902#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37075#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37076#L1502-3 assume !(1 == ~E_2~0); 38024#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38155#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37113#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36805#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36806#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36770#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36771#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37871#L1542-3 assume !(1 == ~E_10~0); 38009#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37638#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37639#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 36981#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36982#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36401#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37166#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37167#L1947 assume !(0 == start_simulation_~tmp~3#1); 37772#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37977#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37038#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38370#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 38294#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38124#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37883#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37884#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37097#L1928-2 [2022-11-21 13:42:00,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,692 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-11-21 13:42:00,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713308246] [2022-11-21 13:42:00,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713308246] [2022-11-21 13:42:00,763 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713308246] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,763 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,763 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045803132] [2022-11-21 13:42:00,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,764 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:00,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:00,765 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 3 times [2022-11-21 13:42:00,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:00,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628811191] [2022-11-21 13:42:00,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:00,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:00,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:00,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:00,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:00,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628811191] [2022-11-21 13:42:00,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628811191] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:00,866 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:00,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:00,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473187885] [2022-11-21 13:42:00,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:00,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:00,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:00,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:00,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:00,870 INFO L87 Difference]: Start difference. First operand 2018 states and 2979 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:00,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:00,927 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2022-11-21 13:42:00,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2978 transitions. [2022-11-21 13:42:00,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:00,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-11-21 13:42:00,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:00,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:00,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2978 transitions. [2022-11-21 13:42:00,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:00,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-11-21 13:42:00,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2978 transitions. [2022-11-21 13:42:00,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:00,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-11-21 13:42:01,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-11-21 13:42:01,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:01,004 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-11-21 13:42:01,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-21 13:42:01,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2978 transitions. [2022-11-21 13:42:01,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:01,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:01,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,018 INFO L748 eck$LassoCheckResult]: Stem: 41358#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42395#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41850#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41851#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41340#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41341#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41407#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41408#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41846#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41847#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41373#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41192#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41637#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41638#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41513#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41514#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41163#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41164#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42387#L1279-2 assume !(0 == ~T1_E~0); 40786#L1284-1 assume !(0 == ~T2_E~0); 40787#L1289-1 assume !(0 == ~T3_E~0); 41510#L1294-1 assume !(0 == ~T4_E~0); 41511#L1299-1 assume !(0 == ~T5_E~0); 41522#L1304-1 assume !(0 == ~T6_E~0); 42453#L1309-1 assume !(0 == ~T7_E~0); 42454#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40716#L1319-1 assume !(0 == ~T9_E~0); 40717#L1324-1 assume !(0 == ~T10_E~0); 40889#L1329-1 assume !(0 == ~T11_E~0); 40890#L1334-1 assume !(0 == ~T12_E~0); 42294#L1339-1 assume !(0 == ~T13_E~0); 42375#L1344-1 assume !(0 == ~E_M~0); 42376#L1349-1 assume !(0 == ~E_1~0); 41697#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41698#L1359-1 assume !(0 == ~E_3~0); 42127#L1364-1 assume !(0 == ~E_4~0); 41018#L1369-1 assume !(0 == ~E_5~0); 41019#L1374-1 assume !(0 == ~E_6~0); 41702#L1379-1 assume !(0 == ~E_7~0); 41703#L1384-1 assume !(0 == ~E_8~0); 41780#L1389-1 assume !(0 == ~E_9~0); 42313#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42314#L1399-1 assume !(0 == ~E_11~0); 42417#L1404-1 assume !(0 == ~E_12~0); 41111#L1409-1 assume !(0 == ~E_13~0); 41112#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42409#L628 assume !(1 == ~m_pc~0); 41015#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41014#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41778#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41779#L1591 assume !(0 != activate_threads_~tmp~1#1); 42422#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41566#L647 assume 1 == ~t1_pc~0; 40935#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40936#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41207#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41208#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42362#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42363#L666 assume 1 == ~t2_pc~0; 40783#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40784#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40950#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42379#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 41898#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41899#L685 assume !(1 == ~t3_pc~0); 42004#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42003#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41626#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41627#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41748#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41234#L704 assume 1 == ~t4_pc~0; 41235#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41759#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41760#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42400#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41619#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41620#L723 assume !(1 == ~t5_pc~0); 41742#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41978#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42122#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41877#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 41878#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41000#L742 assume 1 == ~t6_pc~0; 41001#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41149#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41150#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40685#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40686#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41077#L761 assume !(1 == ~t7_pc~0); 41078#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40946#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40947#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41749#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 41750#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40710#L780 assume 1 == ~t8_pc~0; 40711#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40986#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40987#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41710#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 41711#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41830#L799 assume 1 == ~t9_pc~0; 41942#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40713#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40714#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41842#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42049#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41860#L818 assume !(1 == ~t10_pc~0); 40494#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40495#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41935#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41864#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41865#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41905#L837 assume 1 == ~t11_pc~0; 41906#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41740#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42143#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41823#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 41824#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41575#L856 assume !(1 == ~t12_pc~0); 41576#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42229#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42230#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42210#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42211#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42390#L875 assume 1 == ~t13_pc~0; 41520#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41152#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41153#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41092#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41093#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41932#L1427 assume !(1 == ~M_E~0); 41916#L1427-2 assume !(1 == ~T1_E~0); 41064#L1432-1 assume !(1 == ~T2_E~0); 41065#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42133#L1442-1 assume !(1 == ~T4_E~0); 42134#L1447-1 assume !(1 == ~T5_E~0); 41989#L1452-1 assume !(1 == ~T6_E~0); 40629#L1457-1 assume !(1 == ~T7_E~0); 40630#L1462-1 assume !(1 == ~T8_E~0); 42160#L1467-1 assume !(1 == ~T9_E~0); 42178#L1472-1 assume !(1 == ~T10_E~0); 42179#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41930#L1482-1 assume !(1 == ~T12_E~0); 41931#L1487-1 assume !(1 == ~T13_E~0); 40960#L1492-1 assume !(1 == ~E_M~0); 40961#L1497-1 assume !(1 == ~E_1~0); 41322#L1502-1 assume !(1 == ~E_2~0); 41323#L1507-1 assume !(1 == ~E_3~0); 40838#L1512-1 assume !(1 == ~E_4~0); 40839#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42249#L1522-1 assume !(1 == ~E_6~0); 41563#L1527-1 assume !(1 == ~E_7~0); 41564#L1532-1 assume !(1 == ~E_8~0); 42437#L1537-1 assume !(1 == ~E_9~0); 41766#L1542-1 assume !(1 == ~E_10~0); 41597#L1547-1 assume !(1 == ~E_11~0); 41598#L1552-1 assume !(1 == ~E_12~0); 40533#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40534#L1562-1 assume { :end_inline_reset_delta_events } true; 41140#L1928-2 [2022-11-21 13:42:01,018 INFO L750 eck$LassoCheckResult]: Loop: 41140#L1928-2 assume !false; 41631#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40794#L1254 assume !false; 41381#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40868#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40869#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41066#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42237#L1067 assume !(0 != eval_~tmp~0#1); 41307#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40884#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40885#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41344#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41326#L1284-3 assume !(0 == ~T2_E~0); 41327#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41305#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41306#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41693#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41694#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41203#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41204#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42200#L1324-3 assume !(0 == ~T10_E~0); 40835#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40836#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41603#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41604#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41902#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41913#L1364-3 assume !(0 == ~E_4~0); 42435#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42331#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40964#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40965#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41473#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42341#L1404-3 assume !(0 == ~E_12~0); 42305#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42306#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41792#L628-45 assume 1 == ~m_pc~0; 41470#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41472#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40829#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40830#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41218#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41941#L647-45 assume 1 == ~t1_pc~0; 40780#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40781#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41709#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40894#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40895#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41106#L666-45 assume !(1 == ~t2_pc~0); 41107#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41588#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42150#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42065#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42059#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40644#L685-45 assume 1 == ~t3_pc~0; 40645#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41704#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42378#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42247#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42248#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42388#L704-45 assume 1 == ~t4_pc~0; 42267#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40511#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41370#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41713#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42460#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41825#L723-45 assume !(1 == ~t5_pc~0); 41826#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42315#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41417#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41194#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41195#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42219#L742-45 assume !(1 == ~t6_pc~0); 41441#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 41442#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41911#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41947#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41948#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42036#L761-45 assume !(1 == ~t7_pc~0); 42037#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 41435#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41436#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40842#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40843#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42309#L780-45 assume 1 == ~t8_pc~0; 41220#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40854#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40855#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42436#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40824#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40825#L799-45 assume 1 == ~t9_pc~0; 41601#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41046#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42361#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41990#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41991#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40762#L818-45 assume 1 == ~t10_pc~0; 40763#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40881#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41964#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41368#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41369#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42084#L837-45 assume !(1 == ~t11_pc~0); 41299#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41300#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41437#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42102#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40900#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40901#L856-45 assume 1 == ~t12_pc~0; 42386#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40903#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40844#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40845#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41707#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41708#L875-45 assume !(1 == ~t13_pc~0); 41680#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 41679#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41741#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42353#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42354#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42293#L1427-3 assume !(1 == ~M_E~0); 41504#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41505#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42043#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41695#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41696#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40552#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40553#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42235#L1462-3 assume !(1 == ~T8_E~0); 42236#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42099#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42100#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40803#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40804#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 40945#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41118#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41119#L1502-3 assume !(1 == ~E_2~0); 42067#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42198#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41156#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40848#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40849#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40813#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40814#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41914#L1542-3 assume !(1 == ~E_10~0); 42052#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41681#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41682#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41024#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41025#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40444#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41209#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41210#L1947 assume !(0 == start_simulation_~tmp~3#1); 41815#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42020#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41081#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42413#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 42337#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42167#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41926#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41927#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41140#L1928-2 [2022-11-21 13:42:01,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,020 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-11-21 13:42:01,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914718982] [2022-11-21 13:42:01,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,086 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914718982] [2022-11-21 13:42:01,086 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914718982] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,086 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,086 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242777901] [2022-11-21 13:42:01,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,087 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:01,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1537163566, now seen corresponding path program 1 times [2022-11-21 13:42:01,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281878481] [2022-11-21 13:42:01,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,171 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281878481] [2022-11-21 13:42:01,171 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281878481] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,171 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,171 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120897728] [2022-11-21 13:42:01,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,172 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:01,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:01,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:01,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:01,173 INFO L87 Difference]: Start difference. First operand 2018 states and 2978 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:01,218 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2022-11-21 13:42:01,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2977 transitions. [2022-11-21 13:42:01,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-11-21 13:42:01,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:01,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:01,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2977 transitions. [2022-11-21 13:42:01,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:01,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-11-21 13:42:01,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2977 transitions. [2022-11-21 13:42:01,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:01,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-11-21 13:42:01,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-11-21 13:42:01,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:01,286 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-11-21 13:42:01,286 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-21 13:42:01,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2977 transitions. [2022-11-21 13:42:01,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:01,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:01,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,300 INFO L748 eck$LassoCheckResult]: Stem: 45401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46438#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45893#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45894#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45383#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45384#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45450#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45451#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45889#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45890#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45416#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45235#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45236#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45680#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45681#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45556#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45557#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45206#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45207#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46430#L1279-2 assume !(0 == ~T1_E~0); 44829#L1284-1 assume !(0 == ~T2_E~0); 44830#L1289-1 assume !(0 == ~T3_E~0); 45553#L1294-1 assume !(0 == ~T4_E~0); 45554#L1299-1 assume !(0 == ~T5_E~0); 45565#L1304-1 assume !(0 == ~T6_E~0); 46496#L1309-1 assume !(0 == ~T7_E~0); 46497#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44759#L1319-1 assume !(0 == ~T9_E~0); 44760#L1324-1 assume !(0 == ~T10_E~0); 44932#L1329-1 assume !(0 == ~T11_E~0); 44933#L1334-1 assume !(0 == ~T12_E~0); 46337#L1339-1 assume !(0 == ~T13_E~0); 46418#L1344-1 assume !(0 == ~E_M~0); 46419#L1349-1 assume !(0 == ~E_1~0); 45740#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45741#L1359-1 assume !(0 == ~E_3~0); 46170#L1364-1 assume !(0 == ~E_4~0); 45061#L1369-1 assume !(0 == ~E_5~0); 45062#L1374-1 assume !(0 == ~E_6~0); 45745#L1379-1 assume !(0 == ~E_7~0); 45746#L1384-1 assume !(0 == ~E_8~0); 45823#L1389-1 assume !(0 == ~E_9~0); 46356#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46357#L1399-1 assume !(0 == ~E_11~0); 46460#L1404-1 assume !(0 == ~E_12~0); 45154#L1409-1 assume !(0 == ~E_13~0); 45155#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46452#L628 assume !(1 == ~m_pc~0); 45058#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45057#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45821#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45822#L1591 assume !(0 != activate_threads_~tmp~1#1); 46465#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45609#L647 assume 1 == ~t1_pc~0; 44978#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44979#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45250#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45251#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46405#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46406#L666 assume 1 == ~t2_pc~0; 44826#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44827#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44993#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46422#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 45941#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45942#L685 assume !(1 == ~t3_pc~0); 46047#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46046#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45669#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45670#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45791#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45277#L704 assume 1 == ~t4_pc~0; 45278#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45802#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45803#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46443#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45662#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45663#L723 assume !(1 == ~t5_pc~0); 45785#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46021#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46165#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45920#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 45921#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45043#L742 assume 1 == ~t6_pc~0; 45044#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45192#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45193#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44728#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 44729#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45120#L761 assume !(1 == ~t7_pc~0); 45121#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44989#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44990#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45792#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 45793#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44753#L780 assume 1 == ~t8_pc~0; 44754#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45029#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45030#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45753#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 45754#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45873#L799 assume 1 == ~t9_pc~0; 45985#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44756#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44757#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45885#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46092#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45903#L818 assume !(1 == ~t10_pc~0); 44537#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44538#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45978#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45907#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45908#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45948#L837 assume 1 == ~t11_pc~0; 45949#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45783#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46186#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45866#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 45867#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45618#L856 assume !(1 == ~t12_pc~0); 45619#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46272#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46273#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46253#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46254#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46433#L875 assume 1 == ~t13_pc~0; 45563#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45195#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45196#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45135#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45136#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45975#L1427 assume !(1 == ~M_E~0); 45959#L1427-2 assume !(1 == ~T1_E~0); 45107#L1432-1 assume !(1 == ~T2_E~0); 45108#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46176#L1442-1 assume !(1 == ~T4_E~0); 46177#L1447-1 assume !(1 == ~T5_E~0); 46032#L1452-1 assume !(1 == ~T6_E~0); 44672#L1457-1 assume !(1 == ~T7_E~0); 44673#L1462-1 assume !(1 == ~T8_E~0); 46203#L1467-1 assume !(1 == ~T9_E~0); 46221#L1472-1 assume !(1 == ~T10_E~0); 46222#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45973#L1482-1 assume !(1 == ~T12_E~0); 45974#L1487-1 assume !(1 == ~T13_E~0); 45003#L1492-1 assume !(1 == ~E_M~0); 45004#L1497-1 assume !(1 == ~E_1~0); 45365#L1502-1 assume !(1 == ~E_2~0); 45366#L1507-1 assume !(1 == ~E_3~0); 44881#L1512-1 assume !(1 == ~E_4~0); 44882#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46292#L1522-1 assume !(1 == ~E_6~0); 45606#L1527-1 assume !(1 == ~E_7~0); 45607#L1532-1 assume !(1 == ~E_8~0); 46480#L1537-1 assume !(1 == ~E_9~0); 45809#L1542-1 assume !(1 == ~E_10~0); 45640#L1547-1 assume !(1 == ~E_11~0); 45641#L1552-1 assume !(1 == ~E_12~0); 44576#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44577#L1562-1 assume { :end_inline_reset_delta_events } true; 45183#L1928-2 [2022-11-21 13:42:01,300 INFO L750 eck$LassoCheckResult]: Loop: 45183#L1928-2 assume !false; 45674#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44837#L1254 assume !false; 45424#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44911#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44912#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45109#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46280#L1067 assume !(0 != eval_~tmp~0#1); 45350#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44927#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44928#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45387#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45369#L1284-3 assume !(0 == ~T2_E~0); 45370#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45348#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45349#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45736#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45737#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45246#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45247#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46243#L1324-3 assume !(0 == ~T10_E~0); 44878#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44879#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45646#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45647#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45945#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45227#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45228#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45956#L1364-3 assume !(0 == ~E_4~0); 46478#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46374#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45007#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45008#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45225#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45226#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45516#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46384#L1404-3 assume !(0 == ~E_12~0); 46348#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46349#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45835#L628-45 assume 1 == ~m_pc~0; 45513#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45515#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44872#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44873#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45261#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45984#L647-45 assume 1 == ~t1_pc~0; 44823#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44824#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45752#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44937#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44938#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45149#L666-45 assume !(1 == ~t2_pc~0); 45150#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45631#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46193#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46108#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46102#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44687#L685-45 assume 1 == ~t3_pc~0; 44688#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45747#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46421#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46290#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46291#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46431#L704-45 assume 1 == ~t4_pc~0; 46310#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44554#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45413#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45756#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46503#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45868#L723-45 assume !(1 == ~t5_pc~0); 45869#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46358#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45460#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45237#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45238#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46262#L742-45 assume 1 == ~t6_pc~0; 46263#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45485#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45954#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45990#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45991#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46079#L761-45 assume !(1 == ~t7_pc~0); 46080#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45478#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45479#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44885#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44886#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46352#L780-45 assume !(1 == ~t8_pc~0); 45264#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 44897#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44898#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46479#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44867#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44868#L799-45 assume !(1 == ~t9_pc~0); 45088#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 45089#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46404#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46033#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46034#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44805#L818-45 assume 1 == ~t10_pc~0; 44806#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44924#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46007#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45411#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45412#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46127#L837-45 assume 1 == ~t11_pc~0; 46416#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45343#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45480#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46145#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44943#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44944#L856-45 assume !(1 == ~t12_pc~0); 44945#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 44946#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44887#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44888#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45750#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45751#L875-45 assume 1 == ~t13_pc~0; 45721#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45722#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45784#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46396#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46397#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46336#L1427-3 assume !(1 == ~M_E~0); 45547#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45548#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46086#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45738#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45739#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44595#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44596#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46278#L1462-3 assume !(1 == ~T8_E~0); 46279#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46142#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46143#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44846#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44847#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 44988#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45161#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45162#L1502-3 assume !(1 == ~E_2~0); 46110#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46241#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45199#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44891#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44892#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44856#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44857#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45957#L1542-3 assume !(1 == ~E_10~0); 46095#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45724#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45725#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45067#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45068#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44487#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45252#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45253#L1947 assume !(0 == start_simulation_~tmp~3#1); 45858#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46063#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45124#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46456#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 46380#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46210#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45969#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45970#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45183#L1928-2 [2022-11-21 13:42:01,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-11-21 13:42:01,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722492437] [2022-11-21 13:42:01,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722492437] [2022-11-21 13:42:01,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722492437] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,369 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,369 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583913123] [2022-11-21 13:42:01,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,370 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:01,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1777204334, now seen corresponding path program 1 times [2022-11-21 13:42:01,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652550999] [2022-11-21 13:42:01,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652550999] [2022-11-21 13:42:01,457 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652550999] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,457 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107470415] [2022-11-21 13:42:01,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,458 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:01,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:01,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:01,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:01,460 INFO L87 Difference]: Start difference. First operand 2018 states and 2977 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:01,565 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2022-11-21 13:42:01,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2976 transitions. [2022-11-21 13:42:01,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-11-21 13:42:01,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:01,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:01,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2976 transitions. [2022-11-21 13:42:01,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:01,588 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-11-21 13:42:01,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2976 transitions. [2022-11-21 13:42:01,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:01,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-11-21 13:42:01,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-11-21 13:42:01,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:01,629 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-11-21 13:42:01,629 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-21 13:42:01,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2976 transitions. [2022-11-21 13:42:01,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:01,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:01,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,642 INFO L748 eck$LassoCheckResult]: Stem: 49444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50481#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49936#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49937#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49426#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49427#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49493#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49494#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49932#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49933#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49459#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49278#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49279#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49723#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49724#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49599#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49600#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49249#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49250#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50473#L1279-2 assume !(0 == ~T1_E~0); 48872#L1284-1 assume !(0 == ~T2_E~0); 48873#L1289-1 assume !(0 == ~T3_E~0); 49596#L1294-1 assume !(0 == ~T4_E~0); 49597#L1299-1 assume !(0 == ~T5_E~0); 49608#L1304-1 assume !(0 == ~T6_E~0); 50539#L1309-1 assume !(0 == ~T7_E~0); 50540#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48802#L1319-1 assume !(0 == ~T9_E~0); 48803#L1324-1 assume !(0 == ~T10_E~0); 48975#L1329-1 assume !(0 == ~T11_E~0); 48976#L1334-1 assume !(0 == ~T12_E~0); 50380#L1339-1 assume !(0 == ~T13_E~0); 50461#L1344-1 assume !(0 == ~E_M~0); 50462#L1349-1 assume !(0 == ~E_1~0); 49783#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49784#L1359-1 assume !(0 == ~E_3~0); 50213#L1364-1 assume !(0 == ~E_4~0); 49104#L1369-1 assume !(0 == ~E_5~0); 49105#L1374-1 assume !(0 == ~E_6~0); 49788#L1379-1 assume !(0 == ~E_7~0); 49789#L1384-1 assume !(0 == ~E_8~0); 49866#L1389-1 assume !(0 == ~E_9~0); 50399#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50400#L1399-1 assume !(0 == ~E_11~0); 50503#L1404-1 assume !(0 == ~E_12~0); 49197#L1409-1 assume !(0 == ~E_13~0); 49198#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50495#L628 assume !(1 == ~m_pc~0); 49101#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49100#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49864#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49865#L1591 assume !(0 != activate_threads_~tmp~1#1); 50508#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49652#L647 assume 1 == ~t1_pc~0; 49021#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49022#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49293#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49294#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50448#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50449#L666 assume 1 == ~t2_pc~0; 48869#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48870#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49036#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50465#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 49984#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49985#L685 assume !(1 == ~t3_pc~0); 50090#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50089#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49712#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49713#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49834#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49320#L704 assume 1 == ~t4_pc~0; 49321#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49845#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49846#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50486#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 49705#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49706#L723 assume !(1 == ~t5_pc~0); 49828#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50064#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50208#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49963#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 49964#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49086#L742 assume 1 == ~t6_pc~0; 49087#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49235#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49236#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48771#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 48772#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49163#L761 assume !(1 == ~t7_pc~0); 49164#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49032#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49033#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49835#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 49836#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48796#L780 assume 1 == ~t8_pc~0; 48797#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49072#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49073#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49796#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 49797#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49916#L799 assume 1 == ~t9_pc~0; 50028#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48799#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48800#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49928#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50135#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49946#L818 assume !(1 == ~t10_pc~0); 48580#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48581#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50021#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49950#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49951#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49991#L837 assume 1 == ~t11_pc~0; 49992#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49826#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50229#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49909#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 49910#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49661#L856 assume !(1 == ~t12_pc~0); 49662#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50315#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50316#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50296#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50297#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50476#L875 assume 1 == ~t13_pc~0; 49606#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49238#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49239#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49178#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49179#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50018#L1427 assume !(1 == ~M_E~0); 50002#L1427-2 assume !(1 == ~T1_E~0); 49150#L1432-1 assume !(1 == ~T2_E~0); 49151#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50219#L1442-1 assume !(1 == ~T4_E~0); 50220#L1447-1 assume !(1 == ~T5_E~0); 50075#L1452-1 assume !(1 == ~T6_E~0); 48715#L1457-1 assume !(1 == ~T7_E~0); 48716#L1462-1 assume !(1 == ~T8_E~0); 50246#L1467-1 assume !(1 == ~T9_E~0); 50264#L1472-1 assume !(1 == ~T10_E~0); 50265#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50016#L1482-1 assume !(1 == ~T12_E~0); 50017#L1487-1 assume !(1 == ~T13_E~0); 49046#L1492-1 assume !(1 == ~E_M~0); 49047#L1497-1 assume !(1 == ~E_1~0); 49408#L1502-1 assume !(1 == ~E_2~0); 49409#L1507-1 assume !(1 == ~E_3~0); 48924#L1512-1 assume !(1 == ~E_4~0); 48925#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50335#L1522-1 assume !(1 == ~E_6~0); 49649#L1527-1 assume !(1 == ~E_7~0); 49650#L1532-1 assume !(1 == ~E_8~0); 50523#L1537-1 assume !(1 == ~E_9~0); 49852#L1542-1 assume !(1 == ~E_10~0); 49683#L1547-1 assume !(1 == ~E_11~0); 49684#L1552-1 assume !(1 == ~E_12~0); 48619#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48620#L1562-1 assume { :end_inline_reset_delta_events } true; 49226#L1928-2 [2022-11-21 13:42:01,642 INFO L750 eck$LassoCheckResult]: Loop: 49226#L1928-2 assume !false; 49717#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48880#L1254 assume !false; 49467#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48954#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48955#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49152#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50323#L1067 assume !(0 != eval_~tmp~0#1); 49393#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48970#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48971#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49430#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49412#L1284-3 assume !(0 == ~T2_E~0); 49413#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49391#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49392#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49779#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49780#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49289#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49290#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50286#L1324-3 assume !(0 == ~T10_E~0); 48921#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48922#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49689#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49690#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49988#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49270#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49271#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49999#L1364-3 assume !(0 == ~E_4~0); 50521#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50417#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49050#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49051#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49268#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49269#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49559#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50427#L1404-3 assume !(0 == ~E_12~0); 50391#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50392#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49878#L628-45 assume 1 == ~m_pc~0; 49556#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49558#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48915#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48916#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49304#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50027#L647-45 assume 1 == ~t1_pc~0; 48866#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48867#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49795#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48980#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48981#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49192#L666-45 assume !(1 == ~t2_pc~0); 49193#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49674#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50236#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50151#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50145#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48730#L685-45 assume 1 == ~t3_pc~0; 48731#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49790#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50464#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50333#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50334#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50474#L704-45 assume 1 == ~t4_pc~0; 50353#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48597#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49456#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49799#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50546#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49911#L723-45 assume !(1 == ~t5_pc~0); 49912#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50401#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49503#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49280#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49281#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50305#L742-45 assume 1 == ~t6_pc~0; 50306#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49528#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49997#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50033#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50034#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50122#L761-45 assume !(1 == ~t7_pc~0); 50123#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49521#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49522#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48928#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48929#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50395#L780-45 assume 1 == ~t8_pc~0; 49306#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48940#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48941#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50522#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48910#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48911#L799-45 assume 1 == ~t9_pc~0; 49687#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49132#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50447#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50076#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50077#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48848#L818-45 assume 1 == ~t10_pc~0; 48849#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48967#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50050#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49454#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49455#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50170#L837-45 assume !(1 == ~t11_pc~0); 49385#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49386#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49523#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50188#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48986#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48987#L856-45 assume 1 == ~t12_pc~0; 50472#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48989#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48930#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48931#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49793#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49794#L875-45 assume 1 == ~t13_pc~0; 49764#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49765#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49827#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50439#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50440#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50379#L1427-3 assume !(1 == ~M_E~0); 49590#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49591#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50129#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49781#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49782#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48638#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48639#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50321#L1462-3 assume !(1 == ~T8_E~0); 50322#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50185#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50186#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48889#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48890#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49031#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49204#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49205#L1502-3 assume !(1 == ~E_2~0); 50153#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50284#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49242#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48934#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48935#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48899#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48900#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50000#L1542-3 assume !(1 == ~E_10~0); 50138#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49767#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49768#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49110#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49111#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48530#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49295#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 49296#L1947 assume !(0 == start_simulation_~tmp~3#1); 49901#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50106#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49167#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50499#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 50423#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50253#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50012#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50013#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49226#L1928-2 [2022-11-21 13:42:01,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,643 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-11-21 13:42:01,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108983101] [2022-11-21 13:42:01,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108983101] [2022-11-21 13:42:01,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108983101] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,707 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,707 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418545534] [2022-11-21 13:42:01,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,709 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:01,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,710 INFO L85 PathProgramCache]: Analyzing trace with hash 522319724, now seen corresponding path program 4 times [2022-11-21 13:42:01,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686329154] [2022-11-21 13:42:01,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:01,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:01,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:01,805 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686329154] [2022-11-21 13:42:01,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686329154] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:01,806 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:01,806 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:01,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630613233] [2022-11-21 13:42:01,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:01,807 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:01,807 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:01,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:01,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:01,809 INFO L87 Difference]: Start difference. First operand 2018 states and 2976 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:01,850 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2022-11-21 13:42:01,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2975 transitions. [2022-11-21 13:42:01,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-11-21 13:42:01,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-11-21 13:42:01,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-11-21 13:42:01,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2975 transitions. [2022-11-21 13:42:01,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:01,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-11-21 13:42:01,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2975 transitions. [2022-11-21 13:42:01,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-11-21 13:42:01,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:01,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-11-21 13:42:01,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-11-21 13:42:01,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:01,914 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-11-21 13:42:01,915 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-21 13:42:01,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2975 transitions. [2022-11-21 13:42:01,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-11-21 13:42:01,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:01,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:01,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:01,926 INFO L748 eck$LassoCheckResult]: Stem: 53487#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54524#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53979#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53980#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53469#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53470#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53536#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53537#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53975#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53976#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53502#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53321#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53322#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53766#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53767#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53642#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53643#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53292#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53293#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54516#L1279-2 assume !(0 == ~T1_E~0); 52915#L1284-1 assume !(0 == ~T2_E~0); 52916#L1289-1 assume !(0 == ~T3_E~0); 53639#L1294-1 assume !(0 == ~T4_E~0); 53640#L1299-1 assume !(0 == ~T5_E~0); 53651#L1304-1 assume !(0 == ~T6_E~0); 54582#L1309-1 assume !(0 == ~T7_E~0); 54583#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52845#L1319-1 assume !(0 == ~T9_E~0); 52846#L1324-1 assume !(0 == ~T10_E~0); 53018#L1329-1 assume !(0 == ~T11_E~0); 53019#L1334-1 assume !(0 == ~T12_E~0); 54423#L1339-1 assume !(0 == ~T13_E~0); 54504#L1344-1 assume !(0 == ~E_M~0); 54505#L1349-1 assume !(0 == ~E_1~0); 53826#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53827#L1359-1 assume !(0 == ~E_3~0); 54256#L1364-1 assume !(0 == ~E_4~0); 53147#L1369-1 assume !(0 == ~E_5~0); 53148#L1374-1 assume !(0 == ~E_6~0); 53831#L1379-1 assume !(0 == ~E_7~0); 53832#L1384-1 assume !(0 == ~E_8~0); 53909#L1389-1 assume !(0 == ~E_9~0); 54442#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54443#L1399-1 assume !(0 == ~E_11~0); 54546#L1404-1 assume !(0 == ~E_12~0); 53240#L1409-1 assume !(0 == ~E_13~0); 53241#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54538#L628 assume !(1 == ~m_pc~0); 53144#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53143#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53907#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53908#L1591 assume !(0 != activate_threads_~tmp~1#1); 54551#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53695#L647 assume 1 == ~t1_pc~0; 53064#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53065#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53336#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53337#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54491#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54492#L666 assume 1 == ~t2_pc~0; 52912#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52913#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53079#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54508#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54027#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54028#L685 assume !(1 == ~t3_pc~0); 54133#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54132#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53755#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53756#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53877#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53363#L704 assume 1 == ~t4_pc~0; 53364#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53888#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53889#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54529#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 53748#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53749#L723 assume !(1 == ~t5_pc~0); 53871#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54107#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54251#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54006#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54007#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53129#L742 assume 1 == ~t6_pc~0; 53130#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53278#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53279#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52814#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 52815#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53206#L761 assume !(1 == ~t7_pc~0); 53207#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53075#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53076#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53878#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 53879#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52839#L780 assume 1 == ~t8_pc~0; 52840#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53115#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53116#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53839#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 53840#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53959#L799 assume 1 == ~t9_pc~0; 54071#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52842#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52843#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53971#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54178#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53989#L818 assume !(1 == ~t10_pc~0); 52623#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52624#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54064#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53993#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53994#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54034#L837 assume 1 == ~t11_pc~0; 54035#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53869#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54272#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53952#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 53953#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53704#L856 assume !(1 == ~t12_pc~0); 53705#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54358#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54359#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54339#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54340#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54519#L875 assume 1 == ~t13_pc~0; 53649#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53281#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53282#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53221#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53222#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54061#L1427 assume !(1 == ~M_E~0); 54045#L1427-2 assume !(1 == ~T1_E~0); 53193#L1432-1 assume !(1 == ~T2_E~0); 53194#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54262#L1442-1 assume !(1 == ~T4_E~0); 54263#L1447-1 assume !(1 == ~T5_E~0); 54118#L1452-1 assume !(1 == ~T6_E~0); 52758#L1457-1 assume !(1 == ~T7_E~0); 52759#L1462-1 assume !(1 == ~T8_E~0); 54289#L1467-1 assume !(1 == ~T9_E~0); 54307#L1472-1 assume !(1 == ~T10_E~0); 54308#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54059#L1482-1 assume !(1 == ~T12_E~0); 54060#L1487-1 assume !(1 == ~T13_E~0); 53089#L1492-1 assume !(1 == ~E_M~0); 53090#L1497-1 assume !(1 == ~E_1~0); 53451#L1502-1 assume !(1 == ~E_2~0); 53452#L1507-1 assume !(1 == ~E_3~0); 52967#L1512-1 assume !(1 == ~E_4~0); 52968#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54378#L1522-1 assume !(1 == ~E_6~0); 53692#L1527-1 assume !(1 == ~E_7~0); 53693#L1532-1 assume !(1 == ~E_8~0); 54566#L1537-1 assume !(1 == ~E_9~0); 53895#L1542-1 assume !(1 == ~E_10~0); 53726#L1547-1 assume !(1 == ~E_11~0); 53727#L1552-1 assume !(1 == ~E_12~0); 52662#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 52663#L1562-1 assume { :end_inline_reset_delta_events } true; 53269#L1928-2 [2022-11-21 13:42:01,926 INFO L750 eck$LassoCheckResult]: Loop: 53269#L1928-2 assume !false; 53760#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52923#L1254 assume !false; 53510#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52997#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52998#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53195#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54366#L1067 assume !(0 != eval_~tmp~0#1); 53436#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53013#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53014#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53473#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53455#L1284-3 assume !(0 == ~T2_E~0); 53456#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53434#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53435#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53822#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53823#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53332#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53333#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54329#L1324-3 assume !(0 == ~T10_E~0); 52964#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52965#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53732#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53733#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54031#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53313#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53314#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54042#L1364-3 assume !(0 == ~E_4~0); 54564#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54460#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53093#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53094#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53311#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53312#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53602#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54470#L1404-3 assume !(0 == ~E_12~0); 54434#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54435#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53921#L628-45 assume !(1 == ~m_pc~0); 53600#L628-47 is_master_triggered_~__retres1~0#1 := 0; 53601#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52958#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52959#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53347#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54070#L647-45 assume 1 == ~t1_pc~0; 52909#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52910#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53838#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53023#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53024#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53235#L666-45 assume !(1 == ~t2_pc~0); 53236#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53717#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54279#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54194#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54188#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52773#L685-45 assume 1 == ~t3_pc~0; 52774#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53833#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54507#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54376#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54377#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54517#L704-45 assume 1 == ~t4_pc~0; 54396#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52640#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53499#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53842#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54589#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53954#L723-45 assume !(1 == ~t5_pc~0); 53955#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54444#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53546#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53323#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53324#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54348#L742-45 assume !(1 == ~t6_pc~0); 53570#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 53571#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54040#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54076#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54077#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54165#L761-45 assume !(1 == ~t7_pc~0); 54166#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53564#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53565#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52971#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52972#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54438#L780-45 assume 1 == ~t8_pc~0; 53349#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52983#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52984#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54565#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52953#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52954#L799-45 assume 1 == ~t9_pc~0; 53730#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53175#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54490#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54119#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54120#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52891#L818-45 assume 1 == ~t10_pc~0; 52892#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53010#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54093#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53497#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53498#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54213#L837-45 assume !(1 == ~t11_pc~0); 53428#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53429#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53566#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54231#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53029#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53030#L856-45 assume 1 == ~t12_pc~0; 54515#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53032#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52973#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52974#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53836#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53837#L875-45 assume !(1 == ~t13_pc~0); 53809#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 53808#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53870#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54482#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54483#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54422#L1427-3 assume !(1 == ~M_E~0); 53633#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53634#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54172#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53824#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53825#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52681#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52682#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54364#L1462-3 assume !(1 == ~T8_E~0); 54365#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54228#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54229#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52932#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52933#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53074#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53247#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53248#L1502-3 assume !(1 == ~E_2~0); 54196#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54327#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53285#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52977#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52978#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52942#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52943#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54043#L1542-3 assume !(1 == ~E_10~0); 54181#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53810#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53811#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53153#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53154#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52573#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53338#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53339#L1947 assume !(0 == start_simulation_~tmp~3#1); 53944#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54149#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53210#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54542#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 54466#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54296#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54055#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54056#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53269#L1928-2 [2022-11-21 13:42:01,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:01,927 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-11-21 13:42:01,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:01,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531291016] [2022-11-21 13:42:01,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:01,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:01,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:02,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:02,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:02,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531291016] [2022-11-21 13:42:02,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531291016] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:02,006 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:02,007 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-21 13:42:02,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857375471] [2022-11-21 13:42:02,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:02,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:02,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:02,010 INFO L85 PathProgramCache]: Analyzing trace with hash -242294545, now seen corresponding path program 1 times [2022-11-21 13:42:02,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:02,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135956320] [2022-11-21 13:42:02,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:02,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:02,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:02,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:02,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:02,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135956320] [2022-11-21 13:42:02,080 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135956320] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:02,080 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:02,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:02,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087270946] [2022-11-21 13:42:02,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:02,082 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:02,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:02,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:02,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:02,083 INFO L87 Difference]: Start difference. First operand 2018 states and 2975 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:02,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:02,198 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2022-11-21 13:42:02,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5528 transitions. [2022-11-21 13:42:02,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:02,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-11-21 13:42:02,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-11-21 13:42:02,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-11-21 13:42:02,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5528 transitions. [2022-11-21 13:42:02,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:02,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-11-21 13:42:02,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5528 transitions. [2022-11-21 13:42:02,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-11-21 13:42:02,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:02,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-11-21 13:42:02,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-11-21 13:42:02,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:02,331 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-11-21 13:42:02,331 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-21 13:42:02,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5528 transitions. [2022-11-21 13:42:02,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:02,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:02,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:02,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:02,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:02,355 INFO L748 eck$LassoCheckResult]: Stem: 59274#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59275#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60384#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59775#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59776#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59258#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59259#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59324#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59325#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59773#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59774#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59292#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59108#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59109#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59559#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59560#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59436#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59437#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59079#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59080#L1279 assume !(0 == ~M_E~0); 60372#L1279-2 assume !(0 == ~T1_E~0); 58701#L1284-1 assume !(0 == ~T2_E~0); 58702#L1289-1 assume !(0 == ~T3_E~0); 59428#L1294-1 assume !(0 == ~T4_E~0); 59429#L1299-1 assume !(0 == ~T5_E~0); 59440#L1304-1 assume !(0 == ~T6_E~0); 60481#L1309-1 assume !(0 == ~T7_E~0); 60484#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58631#L1319-1 assume !(0 == ~T9_E~0); 58632#L1324-1 assume !(0 == ~T10_E~0); 58804#L1329-1 assume !(0 == ~T11_E~0); 58805#L1334-1 assume !(0 == ~T12_E~0); 60253#L1339-1 assume !(0 == ~T13_E~0); 60356#L1344-1 assume !(0 == ~E_M~0); 60357#L1349-1 assume !(0 == ~E_1~0); 59620#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 59621#L1359-1 assume !(0 == ~E_3~0); 60060#L1364-1 assume !(0 == ~E_4~0); 58934#L1369-1 assume !(0 == ~E_5~0); 58935#L1374-1 assume !(0 == ~E_6~0); 59626#L1379-1 assume !(0 == ~E_7~0); 59627#L1384-1 assume !(0 == ~E_8~0); 59703#L1389-1 assume !(0 == ~E_9~0); 60278#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60279#L1399-1 assume !(0 == ~E_11~0); 60415#L1404-1 assume !(0 == ~E_12~0); 59027#L1409-1 assume !(0 == ~E_13~0); 59028#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60406#L628 assume !(1 == ~m_pc~0); 58931#L628-2 is_master_triggered_~__retres1~0#1 := 0; 58930#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59701#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59702#L1591 assume !(0 != activate_threads_~tmp~1#1); 60422#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59485#L647 assume 1 == ~t1_pc~0; 58850#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58851#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59123#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59124#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60339#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60340#L666 assume 1 == ~t2_pc~0; 58698#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58699#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58865#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60362#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 59824#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59825#L685 assume !(1 == ~t3_pc~0); 59933#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59932#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59548#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59549#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59671#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59150#L704 assume 1 == ~t4_pc~0; 59151#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59682#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59683#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60390#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59539#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59540#L723 assume !(1 == ~t5_pc~0); 59667#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59905#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60054#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59806#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 59807#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58917#L742 assume 1 == ~t6_pc~0; 58918#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59065#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59066#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58602#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 58603#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58993#L761 assume !(1 == ~t7_pc~0); 58994#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58863#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58864#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59673#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 59674#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58625#L780 assume 1 == ~t8_pc~0; 58626#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58902#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58903#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59633#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 59634#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59755#L799 assume 1 == ~t9_pc~0; 59872#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58628#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58629#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59767#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 59980#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59787#L818 assume !(1 == ~t10_pc~0); 58411#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58412#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59862#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59790#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59791#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59832#L837 assume 1 == ~t11_pc~0; 59833#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59664#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60079#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59748#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 59749#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59496#L856 assume !(1 == ~t12_pc~0); 59497#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60174#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60175#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60156#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60157#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60378#L875 assume 1 == ~t13_pc~0; 59438#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59068#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59069#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59008#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59009#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59859#L1427 assume !(1 == ~M_E~0); 59845#L1427-2 assume !(1 == ~T1_E~0); 58980#L1432-1 assume !(1 == ~T2_E~0); 58981#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60067#L1442-1 assume !(1 == ~T4_E~0); 60068#L1447-1 assume !(1 == ~T5_E~0); 59918#L1452-1 assume !(1 == ~T6_E~0); 58544#L1457-1 assume !(1 == ~T7_E~0); 58545#L1462-1 assume !(1 == ~T8_E~0); 60099#L1467-1 assume !(1 == ~T9_E~0); 60119#L1472-1 assume !(1 == ~T10_E~0); 60120#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59857#L1482-1 assume !(1 == ~T12_E~0); 59858#L1487-1 assume !(1 == ~T13_E~0); 58877#L1492-1 assume !(1 == ~E_M~0); 58878#L1497-1 assume !(1 == ~E_1~0); 59238#L1502-1 assume !(1 == ~E_2~0); 59239#L1507-1 assume !(1 == ~E_3~0); 58753#L1512-1 assume !(1 == ~E_4~0); 58754#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60199#L1522-1 assume !(1 == ~E_6~0); 59482#L1527-1 assume !(1 == ~E_7~0); 59483#L1532-1 assume !(1 == ~E_8~0); 60461#L1537-1 assume !(1 == ~E_9~0); 59689#L1542-1 assume !(1 == ~E_10~0); 59518#L1547-1 assume !(1 == ~E_11~0); 59519#L1552-1 assume !(1 == ~E_12~0); 58448#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58449#L1562-1 assume { :end_inline_reset_delta_events } true; 59056#L1928-2 [2022-11-21 13:42:02,356 INFO L750 eck$LassoCheckResult]: Loop: 59056#L1928-2 assume !false; 59551#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58709#L1254 assume !false; 59298#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58783#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58784#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58982#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60183#L1067 assume !(0 != eval_~tmp~0#1); 59223#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58802#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58803#L1279-3 assume !(0 == ~M_E~0); 60604#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60603#L1284-3 assume !(0 == ~T2_E~0); 60425#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59221#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59222#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59616#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59617#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59119#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59120#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60502#L1324-3 assume !(0 == ~T10_E~0); 60598#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60597#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60596#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 60595#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60594#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60593#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60592#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60591#L1364-3 assume !(0 == ~E_4~0); 60455#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60456#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60590#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60216#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59098#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59099#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59390#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60498#L1404-3 assume !(0 == ~E_12~0); 60268#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60269#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60586#L628-45 assume 1 == ~m_pc~0; 59387#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59389#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60585#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60584#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60427#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59868#L647-45 assume 1 == ~t1_pc~0; 58695#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58696#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59632#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58809#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58810#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60577#L666-45 assume 1 == ~t2_pc~0; 60576#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60436#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60437#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60574#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60573#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60572#L685-45 assume 1 == ~t3_pc~0; 60570#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60360#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60361#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60196#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60197#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60413#L704-45 assume !(1 == ~t4_pc~0); 58425#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 58426#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59287#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59636#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60504#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59750#L723-45 assume !(1 == ~t5_pc~0); 59751#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 60280#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60560#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60559#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 60558#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60164#L742-45 assume 1 == ~t6_pc~0; 60165#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59359#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59838#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59874#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59875#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60552#L761-45 assume 1 == ~t7_pc~0; 60550#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60549#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60548#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60547#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60546#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60272#L780-45 assume 1 == ~t8_pc~0; 60273#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60545#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60544#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60543#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60542#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60541#L799-45 assume !(1 == ~t9_pc~0); 60539#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 60538#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60338#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59916#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59917#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58675#L818-45 assume 1 == ~t10_pc~0; 58676#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58796#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59891#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59284#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59285#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60016#L837-45 assume 1 == ~t11_pc~0; 60528#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60526#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60525#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60524#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60523#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60522#L856-45 assume 1 == ~t12_pc~0; 60369#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58818#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60521#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60520#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60519#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60200#L875-45 assume 1 == ~t13_pc~0; 59601#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59602#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59662#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60479#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60514#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60252#L1427-3 assume !(1 == ~M_E~0); 59421#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59422#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59974#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59618#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59619#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58467#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58468#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60181#L1462-3 assume !(1 == ~T8_E~0); 60182#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60031#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60032#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58718#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58719#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58860#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59034#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59035#L1502-3 assume !(1 == ~E_2~0); 59999#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60142#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59072#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58763#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58764#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58728#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58729#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59841#L1542-3 assume !(1 == ~E_10~0); 59983#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59604#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 59605#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58940#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58941#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58359#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59125#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59126#L1947 assume !(0 == start_simulation_~tmp~3#1); 59740#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59947#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60647#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60645#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 60643#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60641#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60640#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 60442#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59056#L1928-2 [2022-11-21 13:42:02,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:02,357 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-11-21 13:42:02,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:02,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189868138] [2022-11-21 13:42:02,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:02,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:02,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:02,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:02,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:02,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189868138] [2022-11-21 13:42:02,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189868138] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:02,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:02,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:02,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787817019] [2022-11-21 13:42:02,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:02,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:02,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:02,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1659409239, now seen corresponding path program 1 times [2022-11-21 13:42:02,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:02,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771789944] [2022-11-21 13:42:02,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:02,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:02,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:02,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:02,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:02,599 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771789944] [2022-11-21 13:42:02,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771789944] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:02,600 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:02,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:02,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583627614] [2022-11-21 13:42:02,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:02,601 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:02,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:02,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-21 13:42:02,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-21 13:42:02,601 INFO L87 Difference]: Start difference. First operand 3761 states and 5528 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:02,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:02,760 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2022-11-21 13:42:02,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5496 states and 8063 transitions. [2022-11-21 13:42:02,783 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5301 [2022-11-21 13:42:02,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5496 states to 5496 states and 8063 transitions. [2022-11-21 13:42:02,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5496 [2022-11-21 13:42:02,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5496 [2022-11-21 13:42:02,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5496 states and 8063 transitions. [2022-11-21 13:42:02,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:02,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5496 states and 8063 transitions. [2022-11-21 13:42:02,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5496 states and 8063 transitions. [2022-11-21 13:42:02,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5496 to 3761. [2022-11-21 13:42:02,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:02,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5525 transitions. [2022-11-21 13:42:02,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-11-21 13:42:02,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-21 13:42:02,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-11-21 13:42:02,891 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-21 13:42:02,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5525 transitions. [2022-11-21 13:42:02,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:02,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:02,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:02,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:02,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:02,908 INFO L748 eck$LassoCheckResult]: Stem: 68542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69580#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69033#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69034#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 68524#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68525#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68589#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68590#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69031#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69032#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68557#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68374#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68375#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68819#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68820#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68700#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68701#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68345#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68346#L1279 assume !(0 == ~M_E~0); 69571#L1279-2 assume !(0 == ~T1_E~0); 67968#L1284-1 assume !(0 == ~T2_E~0); 67969#L1289-1 assume !(0 == ~T3_E~0); 68692#L1294-1 assume !(0 == ~T4_E~0); 68693#L1299-1 assume !(0 == ~T5_E~0); 68704#L1304-1 assume !(0 == ~T6_E~0); 69641#L1309-1 assume !(0 == ~T7_E~0); 69642#L1314-1 assume !(0 == ~T8_E~0); 67900#L1319-1 assume !(0 == ~T9_E~0); 67901#L1324-1 assume !(0 == ~T10_E~0); 68071#L1329-1 assume !(0 == ~T11_E~0); 68072#L1334-1 assume !(0 == ~T12_E~0); 69477#L1339-1 assume !(0 == ~T13_E~0); 69560#L1344-1 assume !(0 == ~E_M~0); 69561#L1349-1 assume !(0 == ~E_1~0); 68881#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68882#L1359-1 assume !(0 == ~E_3~0); 69310#L1364-1 assume !(0 == ~E_4~0); 68200#L1369-1 assume !(0 == ~E_5~0); 68201#L1374-1 assume !(0 == ~E_6~0); 68887#L1379-1 assume !(0 == ~E_7~0); 68888#L1384-1 assume !(0 == ~E_8~0); 68963#L1389-1 assume !(0 == ~E_9~0); 69496#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69497#L1399-1 assume !(0 == ~E_11~0); 69603#L1404-1 assume !(0 == ~E_12~0); 68293#L1409-1 assume !(0 == ~E_13~0); 68294#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69594#L628 assume !(1 == ~m_pc~0); 68197#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68196#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68961#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68962#L1591 assume !(0 != activate_threads_~tmp~1#1); 69609#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68748#L647 assume 1 == ~t1_pc~0; 68117#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68118#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68389#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68390#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 69546#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69547#L666 assume 1 == ~t2_pc~0; 67965#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67966#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68136#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69563#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69081#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69082#L685 assume !(1 == ~t3_pc~0); 69189#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69188#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68810#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68811#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68931#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68416#L704 assume 1 == ~t4_pc~0; 68417#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68942#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68943#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69585#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 68801#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68802#L723 assume !(1 == ~t5_pc~0); 68927#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69163#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69305#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69063#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69064#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68183#L742 assume 1 == ~t6_pc~0; 68184#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68331#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68332#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67869#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 67870#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68259#L761 assume !(1 == ~t7_pc~0); 68260#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68130#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68131#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68933#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 68934#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67892#L780 assume 1 == ~t8_pc~0; 67893#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68169#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68170#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68894#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 68895#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69016#L799 assume 1 == ~t9_pc~0; 69128#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 67895#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67896#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69025#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69234#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69044#L818 assume !(1 == ~t10_pc~0); 67678#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 67679#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69120#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69047#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69048#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69088#L837 assume 1 == ~t11_pc~0; 69089#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68924#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69326#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69006#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69007#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68762#L856 assume !(1 == ~t12_pc~0); 68763#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69412#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69413#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69394#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69395#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69574#L875 assume 1 == ~t13_pc~0; 68702#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68334#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68335#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68274#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68275#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69115#L1427 assume !(1 == ~M_E~0); 69101#L1427-2 assume !(1 == ~T1_E~0); 68246#L1432-1 assume !(1 == ~T2_E~0); 68247#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69316#L1442-1 assume !(1 == ~T4_E~0); 69317#L1447-1 assume !(1 == ~T5_E~0); 69174#L1452-1 assume !(1 == ~T6_E~0); 67811#L1457-1 assume !(1 == ~T7_E~0); 67812#L1462-1 assume !(1 == ~T8_E~0); 69343#L1467-1 assume !(1 == ~T9_E~0); 69361#L1472-1 assume !(1 == ~T10_E~0); 69362#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69113#L1482-1 assume !(1 == ~T12_E~0); 69114#L1487-1 assume !(1 == ~T13_E~0); 68144#L1492-1 assume !(1 == ~E_M~0); 68145#L1497-1 assume !(1 == ~E_1~0); 68504#L1502-1 assume !(1 == ~E_2~0); 68505#L1507-1 assume !(1 == ~E_3~0); 68020#L1512-1 assume !(1 == ~E_4~0); 68021#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69432#L1522-1 assume !(1 == ~E_6~0); 68746#L1527-1 assume !(1 == ~E_7~0); 68747#L1532-1 assume !(1 == ~E_8~0); 69626#L1537-1 assume !(1 == ~E_9~0); 68951#L1542-1 assume !(1 == ~E_10~0); 68780#L1547-1 assume !(1 == ~E_11~0); 68781#L1552-1 assume !(1 == ~E_12~0); 67717#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 67718#L1562-1 assume { :end_inline_reset_delta_events } true; 68322#L1928-2 [2022-11-21 13:42:02,909 INFO L750 eck$LassoCheckResult]: Loop: 68322#L1928-2 assume !false; 68813#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67976#L1254 assume !false; 68563#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68050#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68051#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68248#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69420#L1067 assume !(0 != eval_~tmp~0#1); 68491#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68066#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68067#L1279-3 assume !(0 == ~M_E~0); 68526#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68508#L1284-3 assume !(0 == ~T2_E~0); 68509#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68487#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68488#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68876#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68877#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68385#L1314-3 assume !(0 == ~T8_E~0); 68386#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69383#L1324-3 assume !(0 == ~T10_E~0); 68017#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68018#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68785#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68786#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69085#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68366#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68367#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69096#L1364-3 assume !(0 == ~E_4~0); 69623#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69514#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68146#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68147#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68364#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68365#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68655#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69524#L1404-3 assume !(0 == ~E_12~0); 69488#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69489#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68975#L628-45 assume !(1 == ~m_pc~0); 68653#L628-47 is_master_triggered_~__retres1~0#1 := 0; 68654#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68011#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68012#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68400#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69124#L647-45 assume 1 == ~t1_pc~0; 67962#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67963#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68892#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68076#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68077#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68288#L666-45 assume !(1 == ~t2_pc~0); 68289#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 68770#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69333#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69248#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69242#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67826#L685-45 assume 1 == ~t3_pc~0; 67827#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68886#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69562#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69430#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69431#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69572#L704-45 assume 1 == ~t4_pc~0; 69450#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67696#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68552#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68896#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69648#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69008#L723-45 assume !(1 == ~t5_pc~0); 69009#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 69498#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68599#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68376#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68377#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69402#L742-45 assume !(1 == ~t6_pc~0); 68624#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 68625#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69094#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69130#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69131#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69219#L761-45 assume 1 == ~t7_pc~0; 69221#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68618#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68619#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68026#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68027#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69492#L780-45 assume !(1 == ~t8_pc~0); 68403#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68038#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68039#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69624#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68006#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68007#L799-45 assume !(1 == ~t9_pc~0); 68230#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68231#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69545#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69172#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69173#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67944#L818-45 assume 1 == ~t10_pc~0; 67945#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68065#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69147#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68550#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68551#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69267#L837-45 assume !(1 == ~t11_pc~0); 68480#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 68481#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68617#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69285#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68082#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68083#L856-45 assume 1 == ~t12_pc~0; 69570#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68085#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68024#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68025#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68889#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68890#L875-45 assume 1 == ~t13_pc~0; 68861#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68862#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68922#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69534#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69535#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69476#L1427-3 assume !(1 == ~M_E~0); 68686#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68687#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69226#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68878#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68879#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67734#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67735#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69418#L1462-3 assume !(1 == ~T8_E~0); 69419#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69282#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69283#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67985#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67986#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68127#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68295#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68296#L1502-3 assume !(1 == ~E_2~0); 69250#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69381#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68338#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68030#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68031#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67995#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67996#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69097#L1542-3 assume !(1 == ~E_10~0); 69235#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68864#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68865#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68206#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68207#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67626#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68391#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68392#L1947 assume !(0 == start_simulation_~tmp~3#1); 68998#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69203#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68263#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69598#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 69520#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69347#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69109#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69110#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68322#L1928-2 [2022-11-21 13:42:02,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:02,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2022-11-21 13:42:02,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:02,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045290594] [2022-11-21 13:42:02,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:02,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:02,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:02,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:02,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:02,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045290594] [2022-11-21 13:42:02,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2045290594] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:02,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:02,999 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-21 13:42:02,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281215607] [2022-11-21 13:42:02,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:02,999 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:03,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:03,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1614179627, now seen corresponding path program 1 times [2022-11-21 13:42:03,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:03,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443682493] [2022-11-21 13:42:03,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:03,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:03,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:03,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:03,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:03,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [443682493] [2022-11-21 13:42:03,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [443682493] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:03,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:03,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:03,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065307706] [2022-11-21 13:42:03,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:03,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:03,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:03,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:03,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:03,077 INFO L87 Difference]: Start difference. First operand 3761 states and 5525 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:03,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:03,174 INFO L93 Difference]: Finished difference Result 3761 states and 5487 transitions. [2022-11-21 13:42:03,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5487 transitions. [2022-11-21 13:42:03,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:03,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-11-21 13:42:03,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-11-21 13:42:03,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-11-21 13:42:03,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5487 transitions. [2022-11-21 13:42:03,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:03,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-11-21 13:42:03,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5487 transitions. [2022-11-21 13:42:03,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-11-21 13:42:03,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:03,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-11-21 13:42:03,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-11-21 13:42:03,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:03,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-11-21 13:42:03,315 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-21 13:42:03,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5487 transitions. [2022-11-21 13:42:03,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:03,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:03,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:03,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:03,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:03,333 INFO L748 eck$LassoCheckResult]: Stem: 76067#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77180#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76567#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76568#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 76050#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76051#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76115#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76116#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76565#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76566#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76083#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75899#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75900#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76349#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76350#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76228#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76229#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75870#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75871#L1279 assume !(0 == ~M_E~0); 77168#L1279-2 assume !(0 == ~T1_E~0); 75495#L1284-1 assume !(0 == ~T2_E~0); 75496#L1289-1 assume !(0 == ~T3_E~0); 76220#L1294-1 assume !(0 == ~T4_E~0); 76221#L1299-1 assume !(0 == ~T5_E~0); 76232#L1304-1 assume !(0 == ~T6_E~0); 77279#L1309-1 assume !(0 == ~T7_E~0); 77281#L1314-1 assume !(0 == ~T8_E~0); 75428#L1319-1 assume !(0 == ~T9_E~0); 75429#L1324-1 assume !(0 == ~T10_E~0); 75598#L1329-1 assume !(0 == ~T11_E~0); 75599#L1334-1 assume !(0 == ~T12_E~0); 77050#L1339-1 assume !(0 == ~T13_E~0); 77153#L1344-1 assume !(0 == ~E_M~0); 77154#L1349-1 assume !(0 == ~E_1~0); 76413#L1354-1 assume !(0 == ~E_2~0); 76414#L1359-1 assume !(0 == ~E_3~0); 76857#L1364-1 assume !(0 == ~E_4~0); 75726#L1369-1 assume !(0 == ~E_5~0); 75727#L1374-1 assume !(0 == ~E_6~0); 76418#L1379-1 assume !(0 == ~E_7~0); 76419#L1384-1 assume !(0 == ~E_8~0); 76495#L1389-1 assume !(0 == ~E_9~0); 77073#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77074#L1399-1 assume !(0 == ~E_11~0); 77212#L1404-1 assume !(0 == ~E_12~0); 75818#L1409-1 assume !(0 == ~E_13~0); 75819#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77202#L628 assume !(1 == ~m_pc~0); 75723#L628-2 is_master_triggered_~__retres1~0#1 := 0; 75722#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76493#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76494#L1591 assume !(0 != activate_threads_~tmp~1#1); 77218#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76276#L647 assume 1 == ~t1_pc~0; 75643#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75644#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75914#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75915#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 77132#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77133#L666 assume !(1 == ~t2_pc~0); 75494#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75658#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75659#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77158#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 76616#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76617#L685 assume !(1 == ~t3_pc~0); 76728#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76727#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76339#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76340#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76463#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75941#L704 assume 1 == ~t4_pc~0; 75942#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76474#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76475#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77186#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 76330#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76331#L723 assume !(1 == ~t5_pc~0); 76459#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76702#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76852#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76598#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 76599#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75709#L742 assume 1 == ~t6_pc~0; 75710#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75856#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75857#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75397#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 75398#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75785#L761 assume !(1 == ~t7_pc~0); 75786#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 75656#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75657#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76465#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 76466#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75420#L780 assume 1 == ~t8_pc~0; 75421#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75695#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75696#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76426#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 76427#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76550#L799 assume 1 == ~t9_pc~0; 76664#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75423#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75424#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76559#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 76775#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76578#L818 assume !(1 == ~t10_pc~0); 75207#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75208#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76654#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76581#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76582#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76623#L837 assume 1 == ~t11_pc~0; 76624#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76456#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76875#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76540#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 76541#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76290#L856 assume !(1 == ~t12_pc~0); 76291#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76971#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76972#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 76953#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77173#L875 assume 1 == ~t13_pc~0; 76230#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75859#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75860#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75800#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 75801#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76651#L1427 assume !(1 == ~M_E~0); 76637#L1427-2 assume !(1 == ~T1_E~0); 75772#L1432-1 assume !(1 == ~T2_E~0); 75773#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76864#L1442-1 assume !(1 == ~T4_E~0); 76865#L1447-1 assume !(1 == ~T5_E~0); 76713#L1452-1 assume !(1 == ~T6_E~0); 75339#L1457-1 assume !(1 == ~T7_E~0); 75340#L1462-1 assume !(1 == ~T8_E~0); 76898#L1467-1 assume !(1 == ~T9_E~0); 76919#L1472-1 assume !(1 == ~T10_E~0); 76920#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76649#L1482-1 assume !(1 == ~T12_E~0); 76650#L1487-1 assume !(1 == ~T13_E~0); 75671#L1492-1 assume !(1 == ~E_M~0); 75672#L1497-1 assume !(1 == ~E_1~0); 76030#L1502-1 assume !(1 == ~E_2~0); 76031#L1507-1 assume !(1 == ~E_3~0); 75547#L1512-1 assume !(1 == ~E_4~0); 75548#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 76995#L1522-1 assume !(1 == ~E_6~0); 76274#L1527-1 assume !(1 == ~E_7~0); 76275#L1532-1 assume !(1 == ~E_8~0); 77257#L1537-1 assume !(1 == ~E_9~0); 76481#L1542-1 assume !(1 == ~E_10~0); 76308#L1547-1 assume !(1 == ~E_11~0); 76309#L1552-1 assume !(1 == ~E_12~0); 75246#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 75247#L1562-1 assume { :end_inline_reset_delta_events } true; 75847#L1928-2 [2022-11-21 13:42:03,333 INFO L750 eck$LassoCheckResult]: Loop: 75847#L1928-2 assume !false; 76342#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75503#L1254 assume !false; 76092#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75577#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75578#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75774#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76980#L1067 assume !(0 != eval_~tmp~0#1); 76015#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75596#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75597#L1279-3 assume !(0 == ~M_E~0); 77397#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77396#L1284-3 assume !(0 == ~T2_E~0); 77221#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76013#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76014#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76408#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76409#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75910#L1314-3 assume !(0 == ~T8_E~0); 75911#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77295#L1324-3 assume !(0 == ~T10_E~0); 77391#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77390#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77389#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77388#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77387#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77386#L1354-3 assume !(0 == ~E_2~0); 77385#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77384#L1364-3 assume !(0 == ~E_4~0); 77252#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77253#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77383#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77013#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 75890#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 75891#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76182#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77293#L1404-3 assume !(0 == ~E_12~0); 77063#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77064#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77379#L628-45 assume 1 == ~m_pc~0; 76179#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76181#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77378#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77377#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77222#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76660#L647-45 assume 1 == ~t1_pc~0; 75490#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75491#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76424#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75602#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75603#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77369#L666-45 assume !(1 == ~t2_pc~0); 77368#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 77234#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77235#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77367#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77366#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77365#L685-45 assume 1 == ~t3_pc~0; 77363#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77156#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77157#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76992#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76993#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77211#L704-45 assume !(1 == ~t4_pc~0); 75221#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 75222#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76078#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76428#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77296#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76542#L723-45 assume 1 == ~t5_pc~0; 76544#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77075#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77353#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77352#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 77351#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76960#L742-45 assume 1 == ~t6_pc~0; 76961#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76151#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76630#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76666#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76667#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77345#L761-45 assume !(1 == ~t7_pc~0); 77344#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 77342#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77341#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77340#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77339#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77067#L780-45 assume !(1 == ~t8_pc~0); 77069#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77338#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77337#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77336#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77335#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77334#L799-45 assume 1 == ~t9_pc~0; 77333#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77331#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77131#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76711#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76712#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75472#L818-45 assume 1 == ~t10_pc~0; 75473#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75590#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76684#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76075#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76076#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76809#L837-45 assume 1 == ~t11_pc~0; 77321#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77319#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77318#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77317#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77316#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77315#L856-45 assume !(1 == ~t12_pc~0); 75610#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 75611#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77314#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77313#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77312#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76996#L875-45 assume 1 == ~t13_pc~0; 76391#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76392#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76454#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77277#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77307#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77049#L1427-3 assume !(1 == ~M_E~0); 76213#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76214#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76766#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76767#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77909#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77771#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77766#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77762#L1462-3 assume !(1 == ~T8_E~0); 77228#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 76826#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76827#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75512#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 75513#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 75653#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75825#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75826#L1502-3 assume !(1 == ~E_2~0); 76792#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76939#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75863#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75557#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75558#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75522#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75523#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 76633#L1542-3 assume !(1 == ~E_10~0); 76776#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76394#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 76395#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 75732#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75733#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75155#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77708#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77706#L1947 assume !(0 == start_simulation_~tmp~3#1); 77703#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77455#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77442#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77440#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 77438#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77436#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77435#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77242#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 75847#L1928-2 [2022-11-21 13:42:03,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:03,334 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2022-11-21 13:42:03,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:03,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350614754] [2022-11-21 13:42:03,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:03,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:03,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:03,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:03,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:03,439 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350614754] [2022-11-21 13:42:03,439 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350614754] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:03,439 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:03,439 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:03,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473793458] [2022-11-21 13:42:03,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:03,440 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:03,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:03,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1240720921, now seen corresponding path program 1 times [2022-11-21 13:42:03,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:03,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652836481] [2022-11-21 13:42:03,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:03,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:03,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:03,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:03,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:03,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652836481] [2022-11-21 13:42:03,516 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652836481] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:03,516 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:03,516 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:03,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712330794] [2022-11-21 13:42:03,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:03,517 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:03,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:03,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-21 13:42:03,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-21 13:42:03,518 INFO L87 Difference]: Start difference. First operand 3761 states and 5487 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:03,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:03,742 INFO L93 Difference]: Finished difference Result 5381 states and 7833 transitions. [2022-11-21 13:42:03,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5381 states and 7833 transitions. [2022-11-21 13:42:03,766 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5201 [2022-11-21 13:42:03,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5381 states to 5381 states and 7833 transitions. [2022-11-21 13:42:03,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5381 [2022-11-21 13:42:03,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5381 [2022-11-21 13:42:03,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5381 states and 7833 transitions. [2022-11-21 13:42:03,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:03,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5381 states and 7833 transitions. [2022-11-21 13:42:03,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5381 states and 7833 transitions. [2022-11-21 13:42:03,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5381 to 3761. [2022-11-21 13:42:03,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:03,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5484 transitions. [2022-11-21 13:42:03,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-11-21 13:42:03,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-21 13:42:03,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-11-21 13:42:03,866 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-21 13:42:03,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5484 transitions. [2022-11-21 13:42:03,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-11-21 13:42:03,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:03,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:03,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:03,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:03,882 INFO L748 eck$LassoCheckResult]: Stem: 85220#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86274#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85715#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85716#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85202#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85203#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85267#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85268#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85713#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 85714#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85235#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85051#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85052#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85497#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85498#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85378#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85379#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85023#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85024#L1279 assume !(0 == ~M_E~0); 86266#L1279-2 assume !(0 == ~T1_E~0); 84647#L1284-1 assume !(0 == ~T2_E~0); 84648#L1289-1 assume !(0 == ~T3_E~0); 85370#L1294-1 assume !(0 == ~T4_E~0); 85371#L1299-1 assume !(0 == ~T5_E~0); 85382#L1304-1 assume !(0 == ~T6_E~0); 86339#L1309-1 assume !(0 == ~T7_E~0); 86340#L1314-1 assume !(0 == ~T8_E~0); 84580#L1319-1 assume !(0 == ~T9_E~0); 84581#L1324-1 assume !(0 == ~T10_E~0); 84750#L1329-1 assume !(0 == ~T11_E~0); 84751#L1334-1 assume !(0 == ~T12_E~0); 86170#L1339-1 assume !(0 == ~T13_E~0); 86255#L1344-1 assume !(0 == ~E_M~0); 86256#L1349-1 assume !(0 == ~E_1~0); 85560#L1354-1 assume !(0 == ~E_2~0); 85561#L1359-1 assume !(0 == ~E_3~0); 85999#L1364-1 assume !(0 == ~E_4~0); 84878#L1369-1 assume !(0 == ~E_5~0); 84879#L1374-1 assume !(0 == ~E_6~0); 85567#L1379-1 assume !(0 == ~E_7~0); 85568#L1384-1 assume !(0 == ~E_8~0); 85645#L1389-1 assume !(0 == ~E_9~0); 86189#L1394-1 assume !(0 == ~E_10~0); 86190#L1399-1 assume !(0 == ~E_11~0); 86298#L1404-1 assume !(0 == ~E_12~0); 84971#L1409-1 assume !(0 == ~E_13~0); 84972#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86288#L628 assume !(1 == ~m_pc~0); 84875#L628-2 is_master_triggered_~__retres1~0#1 := 0; 84874#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85643#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85644#L1591 assume !(0 != activate_threads_~tmp~1#1); 86304#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85426#L647 assume 1 == ~t1_pc~0; 84795#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84796#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85066#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85067#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86241#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86242#L666 assume !(1 == ~t2_pc~0); 84646#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84814#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84815#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86258#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 85764#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85765#L685 assume !(1 == ~t3_pc~0); 85873#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85872#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85488#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85489#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85613#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85093#L704 assume 1 == ~t4_pc~0; 85094#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85624#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85625#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86279#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 85479#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85480#L723 assume !(1 == ~t5_pc~0); 85609#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85847#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85994#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85746#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 85747#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84861#L742 assume 1 == ~t6_pc~0; 84862#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85009#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85010#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84549#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 84550#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84938#L761 assume !(1 == ~t7_pc~0); 84939#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 84808#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84809#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85615#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 85616#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84572#L780 assume 1 == ~t8_pc~0; 84573#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84847#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84848#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85574#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 85575#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85698#L799 assume 1 == ~t9_pc~0; 85812#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84575#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84576#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85707#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 85918#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85726#L818 assume !(1 == ~t10_pc~0); 84359#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84360#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85804#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85729#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85730#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85771#L837 assume 1 == ~t11_pc~0; 85772#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85606#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86015#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85688#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 85689#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85440#L856 assume !(1 == ~t12_pc~0); 85441#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86104#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86105#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86086#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86087#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86269#L875 assume 1 == ~t13_pc~0; 85380#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85012#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85013#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84953#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 84954#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85798#L1427 assume !(1 == ~M_E~0); 85784#L1427-2 assume !(1 == ~T1_E~0); 84924#L1432-1 assume !(1 == ~T2_E~0); 84925#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86005#L1442-1 assume !(1 == ~T4_E~0); 86006#L1447-1 assume !(1 == ~T5_E~0); 85858#L1452-1 assume !(1 == ~T6_E~0); 84491#L1457-1 assume !(1 == ~T7_E~0); 84492#L1462-1 assume !(1 == ~T8_E~0); 86033#L1467-1 assume !(1 == ~T9_E~0); 86051#L1472-1 assume !(1 == ~T10_E~0); 86052#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85796#L1482-1 assume !(1 == ~T12_E~0); 85797#L1487-1 assume !(1 == ~T13_E~0); 84823#L1492-1 assume !(1 == ~E_M~0); 84824#L1497-1 assume !(1 == ~E_1~0); 85181#L1502-1 assume !(1 == ~E_2~0); 85182#L1507-1 assume !(1 == ~E_3~0); 84699#L1512-1 assume !(1 == ~E_4~0); 84700#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86124#L1522-1 assume !(1 == ~E_6~0); 85424#L1527-1 assume !(1 == ~E_7~0); 85425#L1532-1 assume !(1 == ~E_8~0); 86322#L1537-1 assume !(1 == ~E_9~0); 85633#L1542-1 assume !(1 == ~E_10~0); 85458#L1547-1 assume !(1 == ~E_11~0); 85459#L1552-1 assume !(1 == ~E_12~0); 84398#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 84399#L1562-1 assume { :end_inline_reset_delta_events } true; 85000#L1928-2 [2022-11-21 13:42:03,883 INFO L750 eck$LassoCheckResult]: Loop: 85000#L1928-2 assume !false; 85491#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84655#L1254 assume !false; 85241#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84729#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84730#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84926#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86112#L1067 assume !(0 != eval_~tmp~0#1); 85168#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84748#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84749#L1279-3 assume !(0 == ~M_E~0); 85204#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85185#L1284-3 assume !(0 == ~T2_E~0); 85186#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85164#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85165#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85555#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85556#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85062#L1314-3 assume !(0 == ~T8_E~0); 85063#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86075#L1324-3 assume !(0 == ~T10_E~0); 84696#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 84697#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85463#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85464#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85768#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85044#L1354-3 assume !(0 == ~E_2~0); 85045#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85779#L1364-3 assume !(0 == ~E_4~0); 86319#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86208#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 84825#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84826#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85042#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85043#L1394-3 assume !(0 == ~E_10~0); 85333#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86220#L1404-3 assume !(0 == ~E_12~0); 86181#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86182#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85657#L628-45 assume !(1 == ~m_pc~0); 85331#L628-47 is_master_triggered_~__retres1~0#1 := 0; 85332#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84690#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84691#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85077#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85808#L647-45 assume 1 == ~t1_pc~0; 84642#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84643#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85572#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84754#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84755#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84966#L666-45 assume !(1 == ~t2_pc~0); 84967#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 85448#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86022#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85932#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85926#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84506#L685-45 assume 1 == ~t3_pc~0; 84507#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85566#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86257#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86122#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86123#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86267#L704-45 assume !(1 == ~t4_pc~0); 84376#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 84377#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85230#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85576#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86349#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85690#L723-45 assume !(1 == ~t5_pc~0); 85691#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86191#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85278#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85053#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85054#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86094#L742-45 assume !(1 == ~t6_pc~0); 85302#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 85303#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85777#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85814#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85815#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85903#L761-45 assume 1 == ~t7_pc~0; 85905#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85296#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85297#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84705#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 84706#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86185#L780-45 assume 1 == ~t8_pc~0; 85079#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84717#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84718#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86320#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84685#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84686#L799-45 assume 1 == ~t9_pc~0; 85461#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84905#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86238#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85856#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85857#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84621#L818-45 assume !(1 == ~t10_pc~0); 84623#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 84742#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85831#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85225#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85226#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85953#L837-45 assume !(1 == ~t11_pc~0); 85157#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 85158#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85295#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85972#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84760#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84761#L856-45 assume 1 == ~t12_pc~0; 86265#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84763#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84703#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84704#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85569#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85570#L875-45 assume 1 == ~t13_pc~0; 85540#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85541#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85604#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86230#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86231#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86169#L1427-3 assume !(1 == ~M_E~0); 85364#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85365#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85910#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85557#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85558#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84415#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84416#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86110#L1462-3 assume !(1 == ~T8_E~0); 86111#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85969#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85970#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 84664#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84665#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 84805#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84978#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84979#L1502-3 assume !(1 == ~E_2~0); 85934#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86073#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85016#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84709#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 84710#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 84674#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 84675#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85780#L1542-3 assume !(1 == ~E_10~0); 85919#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85543#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85544#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 84884#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84885#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84307#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85068#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 85069#L1947 assume !(0 == start_simulation_~tmp~3#1); 85680#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85887#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84942#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86294#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 86216#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86040#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85792#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85793#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85000#L1928-2 [2022-11-21 13:42:03,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:03,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2022-11-21 13:42:03,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:03,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883834352] [2022-11-21 13:42:03,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:03,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:03,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:03,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:03,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:03,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883834352] [2022-11-21 13:42:03,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883834352] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:03,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:03,978 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:03,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294660337] [2022-11-21 13:42:03,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:03,979 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:03,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:03,980 INFO L85 PathProgramCache]: Analyzing trace with hash -996224665, now seen corresponding path program 1 times [2022-11-21 13:42:03,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:03,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637598829] [2022-11-21 13:42:03,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:03,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:03,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:04,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:04,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:04,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637598829] [2022-11-21 13:42:04,112 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637598829] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:04,112 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:04,113 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:04,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626150177] [2022-11-21 13:42:04,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:04,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:04,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:04,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-21 13:42:04,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-21 13:42:04,115 INFO L87 Difference]: Start difference. First operand 3761 states and 5484 transitions. cyclomatic complexity: 1724 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:04,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:04,540 INFO L93 Difference]: Finished difference Result 10616 states and 15321 transitions. [2022-11-21 13:42:04,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10616 states and 15321 transitions. [2022-11-21 13:42:04,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10233 [2022-11-21 13:42:04,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10616 states to 10616 states and 15321 transitions. [2022-11-21 13:42:04,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10616 [2022-11-21 13:42:04,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10616 [2022-11-21 13:42:04,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10616 states and 15321 transitions. [2022-11-21 13:42:04,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:04,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10616 states and 15321 transitions. [2022-11-21 13:42:04,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10616 states and 15321 transitions. [2022-11-21 13:42:04,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10616 to 10232. [2022-11-21 13:42:04,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10232 states, 10232 states have (on average 1.44517200938233) internal successors, (14787), 10231 states have internal predecessors, (14787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:04,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10232 states to 10232 states and 14787 transitions. [2022-11-21 13:42:04,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10232 states and 14787 transitions. [2022-11-21 13:42:04,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-21 13:42:04,864 INFO L428 stractBuchiCegarLoop]: Abstraction has 10232 states and 14787 transitions. [2022-11-21 13:42:04,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-21 13:42:04,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10232 states and 14787 transitions. [2022-11-21 13:42:04,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10049 [2022-11-21 13:42:04,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:04,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:04,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:04,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:04,902 INFO L748 eck$LassoCheckResult]: Stem: 99621#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 99622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 100943#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100169#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100170#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 99601#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99602#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99679#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99680#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100162#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100163#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99639#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99443#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99444#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 99928#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 99929#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99793#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 99794#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 99414#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99415#L1279 assume !(0 == ~M_E~0); 100929#L1279-2 assume !(0 == ~T1_E~0); 99040#L1284-1 assume !(0 == ~T2_E~0); 99041#L1289-1 assume !(0 == ~T3_E~0); 99790#L1294-1 assume !(0 == ~T4_E~0); 99791#L1299-1 assume !(0 == ~T5_E~0); 99803#L1304-1 assume !(0 == ~T6_E~0); 101121#L1309-1 assume !(0 == ~T7_E~0); 101126#L1314-1 assume !(0 == ~T8_E~0); 98969#L1319-1 assume !(0 == ~T9_E~0); 98970#L1324-1 assume !(0 == ~T10_E~0); 99144#L1329-1 assume !(0 == ~T11_E~0); 99145#L1334-1 assume !(0 == ~T12_E~0); 100773#L1339-1 assume !(0 == ~T13_E~0); 100909#L1344-1 assume !(0 == ~E_M~0); 100910#L1349-1 assume !(0 == ~E_1~0); 99995#L1354-1 assume !(0 == ~E_2~0); 99996#L1359-1 assume !(0 == ~E_3~0); 100513#L1364-1 assume !(0 == ~E_4~0); 99268#L1369-1 assume !(0 == ~E_5~0); 99269#L1374-1 assume !(0 == ~E_6~0); 100000#L1379-1 assume !(0 == ~E_7~0); 100001#L1384-1 assume !(0 == ~E_8~0); 100084#L1389-1 assume !(0 == ~E_9~0); 100805#L1394-1 assume !(0 == ~E_10~0); 100806#L1399-1 assume !(0 == ~E_11~0); 100992#L1404-1 assume !(0 == ~E_12~0); 99362#L1409-1 assume !(0 == ~E_13~0); 99363#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100974#L628 assume !(1 == ~m_pc~0); 100812#L628-2 is_master_triggered_~__retres1~0#1 := 0; 100309#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100082#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100083#L1591 assume !(0 != activate_threads_~tmp~1#1); 101002#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99852#L647 assume !(1 == ~t1_pc~0); 99853#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99913#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99458#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99459#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 100894#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100895#L666 assume !(1 == ~t2_pc~0); 99039#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99201#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99202#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100915#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 100229#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100230#L685 assume !(1 == ~t3_pc~0); 100350#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100349#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99917#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99918#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100051#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99487#L704 assume 1 == ~t4_pc~0; 99488#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 100064#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100065#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100951#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 99909#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99910#L723 assume !(1 == ~t5_pc~0); 100046#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100323#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100508#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100204#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 100205#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99254#L742 assume 1 == ~t6_pc~0; 99255#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99399#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99400#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98937#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 98938#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99327#L761 assume !(1 == ~t7_pc~0); 99328#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 99199#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99200#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100054#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 100055#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98963#L780 assume 1 == ~t8_pc~0; 98964#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99241#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99242#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100009#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 100010#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100145#L799 assume 1 == ~t9_pc~0; 100283#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98966#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98967#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100158#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 100403#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100183#L818 assume !(1 == ~t10_pc~0); 98745#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 98746#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100274#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100187#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100188#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100237#L837 assume 1 == ~t11_pc~0; 100238#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 100041#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100532#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100138#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 100139#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99862#L856 assume !(1 == ~t12_pc~0); 99863#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 100668#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 100669#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100632#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 100633#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100937#L875 assume 1 == ~t13_pc~0; 99801#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 99402#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 99403#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99343#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 99344#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100271#L1427 assume !(1 == ~M_E~0); 100251#L1427-2 assume !(1 == ~T1_E~0); 99314#L1432-1 assume !(1 == ~T2_E~0); 99315#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100520#L1442-1 assume !(1 == ~T4_E~0); 100521#L1447-1 assume !(1 == ~T5_E~0); 100336#L1452-1 assume !(1 == ~T6_E~0); 98879#L1457-1 assume !(1 == ~T7_E~0); 98880#L1462-1 assume !(1 == ~T8_E~0); 100565#L1467-1 assume !(1 == ~T9_E~0); 100592#L1472-1 assume !(1 == ~T10_E~0); 100593#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100269#L1482-1 assume !(1 == ~T12_E~0); 100270#L1487-1 assume !(1 == ~T13_E~0); 99214#L1492-1 assume !(1 == ~E_M~0); 99215#L1497-1 assume !(1 == ~E_1~0); 99582#L1502-1 assume !(1 == ~E_2~0); 99583#L1507-1 assume !(1 == ~E_3~0); 99093#L1512-1 assume !(1 == ~E_4~0); 99094#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 100694#L1522-1 assume !(1 == ~E_6~0); 99849#L1527-1 assume !(1 == ~E_7~0); 99850#L1532-1 assume !(1 == ~E_8~0); 101060#L1537-1 assume !(1 == ~E_9~0); 100071#L1542-1 assume !(1 == ~E_10~0); 99886#L1547-1 assume !(1 == ~E_11~0); 99887#L1552-1 assume !(1 == ~E_12~0); 98784#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 98785#L1562-1 assume { :end_inline_reset_delta_events } true; 99391#L1928-2 [2022-11-21 13:42:04,902 INFO L750 eck$LassoCheckResult]: Loop: 99391#L1928-2 assume !false; 99922#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99049#L1254 assume !false; 99647#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100277#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107217#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100955#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 100956#L1067 assume !(0 != eval_~tmp~0#1); 107215#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107214#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100968#L1279-3 assume !(0 == ~M_E~0); 100969#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99586#L1284-3 assume !(0 == ~T2_E~0); 99587#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99565#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99566#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101137#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100542#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100543#L1314-3 assume !(0 == ~T8_E~0); 101167#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 101168#L1324-3 assume !(0 == ~T10_E~0); 99090#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 99091#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99893#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 99894#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100305#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99436#L1354-3 assume !(0 == ~E_2~0); 99437#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101119#L1364-3 assume !(0 == ~E_4~0); 101120#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100838#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100839#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100720#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 100721#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99748#L1394-3 assume !(0 == ~E_10~0); 99749#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 100859#L1404-3 assume !(0 == ~E_12~0); 100860#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 100927#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100928#L628-45 assume !(1 == ~m_pc~0); 100730#L628-47 is_master_triggered_~__retres1~0#1 := 0; 100731#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108644#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99469#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99470#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101012#L647-45 assume !(1 == ~t1_pc~0); 108638#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 108636#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108633#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99148#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99149#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99357#L666-45 assume !(1 == ~t2_pc~0); 99358#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 99875#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100541#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100423#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100415#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98895#L685-45 assume !(1 == ~t3_pc~0); 98897#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 100002#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100914#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100689#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100690#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100932#L704-45 assume !(1 == ~t4_pc~0); 100991#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 108607#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108606#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108605#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108604#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108603#L723-45 assume 1 == ~t5_pc~0; 108601#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 108600#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108599#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108598#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 108597#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108596#L742-45 assume !(1 == ~t6_pc~0); 99716#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 99717#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100244#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100288#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100289#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100386#L761-45 assume !(1 == ~t7_pc~0); 100387#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 108588#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108586#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99097#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99098#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108502#L780-45 assume !(1 == ~t8_pc~0); 108501#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 108499#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108496#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 101058#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101059#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99888#L799-45 assume !(1 == ~t9_pc~0); 99889#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 101181#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100891#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100334#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100335#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99014#L818-45 assume 1 == ~t10_pc~0; 99015#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 99135#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100308#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99630#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99631#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100450#L837-45 assume !(1 == ~t11_pc~0); 99557#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 99558#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99710#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100470#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 99154#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99155#L856-45 assume !(1 == ~t12_pc~0); 99156#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 99157#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99099#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 99100#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100004#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100005#L875-45 assume 1 == ~t13_pc~0; 99976#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 99977#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 100039#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 100879#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 100880#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100771#L1427-3 assume !(1 == ~M_E~0); 100772#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100940#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100396#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99993#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99994#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98803#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98804#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100675#L1462-3 assume !(1 == ~T8_E~0); 100676#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100467#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100468#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99058#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 99059#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 99196#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 99364#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99365#L1502-3 assume !(1 == ~E_2~0); 100427#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108503#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 108494#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 108495#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 108125#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99068#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99069#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100249#L1542-3 assume !(1 == ~E_10~0); 100406#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 99979#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 99980#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 99274#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99275#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98696#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 99460#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 99461#L1947 assume !(0 == start_simulation_~tmp~3#1); 100128#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100367#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 99331#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 107271#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 107269#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100576#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100577#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 107236#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 99391#L1928-2 [2022-11-21 13:42:04,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:04,904 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2022-11-21 13:42:04,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:04,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165930127] [2022-11-21 13:42:04,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:04,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:04,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:04,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:04,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:04,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165930127] [2022-11-21 13:42:04,995 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165930127] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:04,995 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:04,996 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:04,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694098245] [2022-11-21 13:42:04,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:04,997 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:04,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:04,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1817548587, now seen corresponding path program 1 times [2022-11-21 13:42:04,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:04,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539810333] [2022-11-21 13:42:04,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:05,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:05,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:05,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:05,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:05,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539810333] [2022-11-21 13:42:05,058 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539810333] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:05,058 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:05,058 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:05,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181914611] [2022-11-21 13:42:05,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:05,060 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:05,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:05,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-21 13:42:05,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-21 13:42:05,061 INFO L87 Difference]: Start difference. First operand 10232 states and 14787 transitions. cyclomatic complexity: 4557 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:05,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:05,615 INFO L93 Difference]: Finished difference Result 28024 states and 40569 transitions. [2022-11-21 13:42:05,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28024 states and 40569 transitions. [2022-11-21 13:42:05,733 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27620 [2022-11-21 13:42:05,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28024 states to 28024 states and 40569 transitions. [2022-11-21 13:42:05,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28024 [2022-11-21 13:42:05,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28024 [2022-11-21 13:42:05,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28024 states and 40569 transitions. [2022-11-21 13:42:05,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:05,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28024 states and 40569 transitions. [2022-11-21 13:42:05,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28024 states and 40569 transitions. [2022-11-21 13:42:06,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28024 to 10496. [2022-11-21 13:42:06,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10496 states, 10496 states have (on average 1.4339748475609757) internal successors, (15051), 10495 states have internal predecessors, (15051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:06,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10496 states to 10496 states and 15051 transitions. [2022-11-21 13:42:06,117 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10496 states and 15051 transitions. [2022-11-21 13:42:06,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-21 13:42:06,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 10496 states and 15051 transitions. [2022-11-21 13:42:06,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-21 13:42:06,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10496 states and 15051 transitions. [2022-11-21 13:42:06,150 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10310 [2022-11-21 13:42:06,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:06,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:06,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:06,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:06,154 INFO L748 eck$LassoCheckResult]: Stem: 137878#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 137879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 139051#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138400#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 138401#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 137862#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137863#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137931#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 137932#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138396#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 138397#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 137897#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137706#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137707#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 138170#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 138171#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 138046#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 138047#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 137678#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137679#L1279 assume !(0 == ~M_E~0); 139042#L1279-2 assume !(0 == ~T1_E~0); 137306#L1284-1 assume !(0 == ~T2_E~0); 137307#L1289-1 assume !(0 == ~T3_E~0); 138038#L1294-1 assume !(0 == ~T4_E~0); 138039#L1299-1 assume !(0 == ~T5_E~0); 138050#L1304-1 assume !(0 == ~T6_E~0); 139167#L1309-1 assume !(0 == ~T7_E~0); 139170#L1314-1 assume !(0 == ~T8_E~0); 137236#L1319-1 assume !(0 == ~T9_E~0); 137237#L1324-1 assume !(0 == ~T10_E~0); 137409#L1329-1 assume !(0 == ~T11_E~0); 137410#L1334-1 assume !(0 == ~T12_E~0); 138920#L1339-1 assume !(0 == ~T13_E~0); 139026#L1344-1 assume !(0 == ~E_M~0); 139027#L1349-1 assume !(0 == ~E_1~0); 138237#L1354-1 assume !(0 == ~E_2~0); 138238#L1359-1 assume !(0 == ~E_3~0); 138717#L1364-1 assume !(0 == ~E_4~0); 137533#L1369-1 assume !(0 == ~E_5~0); 137534#L1374-1 assume !(0 == ~E_6~0); 138243#L1379-1 assume !(0 == ~E_7~0); 138244#L1384-1 assume !(0 == ~E_8~0); 138325#L1389-1 assume !(0 == ~E_9~0); 138946#L1394-1 assume !(0 == ~E_10~0); 138947#L1399-1 assume !(0 == ~E_11~0); 139090#L1404-1 assume !(0 == ~E_12~0); 137628#L1409-1 assume !(0 == ~E_13~0); 137629#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139078#L628 assume !(1 == ~m_pc~0); 138950#L628-2 is_master_triggered_~__retres1~0#1 := 0; 138525#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138323#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138324#L1591 assume !(0 != activate_threads_~tmp~1#1); 139098#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138097#L647 assume !(1 == ~t1_pc~0); 138098#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 138155#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137721#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137722#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 139012#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139013#L666 assume !(1 == ~t2_pc~0); 137305#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137467#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137468#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 139030#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 138452#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138453#L685 assume !(1 == ~t3_pc~0); 138571#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138648#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139107#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138289#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 138290#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137753#L704 assume 1 == ~t4_pc~0; 137754#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 138303#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138304#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 139057#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 138151#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138152#L723 assume !(1 == ~t5_pc~0); 138285#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 138540#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138711#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 138431#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 138432#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137520#L742 assume 1 == ~t6_pc~0; 137521#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 137664#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137665#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137206#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 137207#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137594#L761 assume !(1 == ~t7_pc~0); 137595#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 137465#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137466#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138292#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 138293#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 137230#L780 assume 1 == ~t8_pc~0; 137231#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 137506#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137507#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138251#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 138252#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138380#L799 assume 1 == ~t9_pc~0; 138500#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 137233#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137234#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138392#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 138622#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138411#L818 assume !(1 == ~t10_pc~0); 137014#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137015#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138492#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138414#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138415#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138461#L837 assume 1 == ~t11_pc~0; 138462#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 138282#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 138735#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138373#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 138374#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138109#L856 assume !(1 == ~t12_pc~0); 138110#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 138842#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138843#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138817#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 138818#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 139045#L875 assume 1 == ~t13_pc~0; 138048#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 137667#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 137668#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 137610#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 137611#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138489#L1427 assume !(1 == ~M_E~0); 138474#L1427-2 assume !(1 == ~T1_E~0); 137581#L1432-1 assume !(1 == ~T2_E~0); 137582#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138724#L1442-1 assume !(1 == ~T4_E~0); 138725#L1447-1 assume !(1 == ~T5_E~0); 138555#L1452-1 assume !(1 == ~T6_E~0); 137148#L1457-1 assume !(1 == ~T7_E~0); 137149#L1462-1 assume !(1 == ~T8_E~0); 138761#L1467-1 assume !(1 == ~T9_E~0); 138782#L1472-1 assume !(1 == ~T10_E~0); 138783#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138487#L1482-1 assume !(1 == ~T12_E~0); 138488#L1487-1 assume !(1 == ~T13_E~0); 137480#L1492-1 assume !(1 == ~E_M~0); 137481#L1497-1 assume !(1 == ~E_1~0); 137841#L1502-1 assume !(1 == ~E_2~0); 137842#L1507-1 assume !(1 == ~E_3~0); 137359#L1512-1 assume !(1 == ~E_4~0); 137360#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 138864#L1522-1 assume !(1 == ~E_6~0); 138094#L1527-1 assume !(1 == ~E_7~0); 138095#L1532-1 assume !(1 == ~E_8~0); 139135#L1537-1 assume !(1 == ~E_9~0); 138310#L1542-1 assume !(1 == ~E_10~0); 138130#L1547-1 assume !(1 == ~E_11~0); 138131#L1552-1 assume !(1 == ~E_12~0); 137053#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 137054#L1562-1 assume { :end_inline_reset_delta_events } true; 137656#L1928-2 [2022-11-21 13:42:06,154 INFO L750 eck$LassoCheckResult]: Loop: 137656#L1928-2 assume !false; 138164#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137314#L1254 assume !false; 137903#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 137388#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 137389#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 137583#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 138850#L1067 assume !(0 != eval_~tmp~0#1); 137826#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 137407#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 137408#L1279-3 assume !(0 == ~M_E~0); 137864#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 137845#L1284-3 assume !(0 == ~T2_E~0); 137846#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 137824#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 137825#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138233#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138234#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 137717#L1314-3 assume !(0 == ~T8_E~0); 137718#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 138805#L1324-3 assume !(0 == ~T10_E~0); 137356#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 137357#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 138138#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 138139#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 138458#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 137699#L1354-3 assume !(0 == ~E_2~0); 137700#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138469#L1364-3 assume !(0 == ~E_4~0); 139131#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138973#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 137482#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 137483#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 137697#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 137698#L1394-3 assume !(0 == ~E_10~0); 137998#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 138984#L1404-3 assume !(0 == ~E_12~0); 138935#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 138936#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138340#L628-45 assume !(1 == ~m_pc~0); 138341#L628-47 is_master_triggered_~__retres1~0#1 := 0; 138883#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137350#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137351#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 137732#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138498#L647-45 assume !(1 == ~t1_pc~0); 138499#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 138249#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138250#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137414#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 137415#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137621#L666-45 assume !(1 == ~t2_pc~0); 137622#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 138120#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138742#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138638#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138632#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137160#L685-45 assume !(1 == ~t3_pc~0); 137162#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 138954#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139029#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138862#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 138863#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139043#L704-45 assume 1 == ~t4_pc~0; 138882#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 137031#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137892#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138254#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 139187#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138375#L723-45 assume !(1 == ~t5_pc~0); 138376#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 138948#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137942#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137708#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 137709#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138827#L742-45 assume !(1 == ~t6_pc~0); 137966#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 137967#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138467#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 138505#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138506#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138606#L761-45 assume 1 == ~t7_pc~0; 138608#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 137960#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137961#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 137363#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 137364#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138939#L780-45 assume 1 == ~t8_pc~0; 137735#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 137374#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137375#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 139133#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 137344#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 137345#L799-45 assume 1 == ~t9_pc~0; 138133#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 137562#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 139011#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138553#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 138554#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 137280#L818-45 assume !(1 == ~t10_pc~0); 137282#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 137401#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138524#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 137889#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137890#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138666#L837-45 assume 1 == ~t11_pc~0; 139024#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 137818#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 137962#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138686#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 137420#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 137421#L856-45 assume 1 == ~t12_pc~0; 139041#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 137423#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 137365#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 137366#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138246#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 138247#L875-45 assume 1 == ~t13_pc~0; 138218#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 138219#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138280#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 138997#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 138998#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138917#L1427-3 assume !(1 == ~M_E~0); 138918#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139048#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 138616#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138235#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138236#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 138639#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 147011#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 147010#L1462-3 assume !(1 == ~T8_E~0); 147008#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 147005#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 147003#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 147002#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 147001#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 147000#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146999#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 138641#L1502-3 assume !(1 == ~E_2~0); 138642#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 146957#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 146956#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146955#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146954#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146953#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 146952#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 146951#L1542-3 assume !(1 == ~E_10~0); 146950#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 146949#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 146948#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 146947#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 146945#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 138951#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 138952#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 138363#L1947 assume !(0 == start_simulation_~tmp~3#1); 138365#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 138587#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 137598#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 139086#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 138979#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138769#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138483#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 138484#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 137656#L1928-2 [2022-11-21 13:42:06,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:06,155 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2022-11-21 13:42:06,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:06,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997392396] [2022-11-21 13:42:06,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:06,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:06,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:06,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:06,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:06,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997392396] [2022-11-21 13:42:06,261 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997392396] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:06,261 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:06,261 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-21 13:42:06,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767193110] [2022-11-21 13:42:06,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:06,262 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:06,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:06,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1022329943, now seen corresponding path program 1 times [2022-11-21 13:42:06,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:06,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107581176] [2022-11-21 13:42:06,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:06,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:06,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:06,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:06,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:06,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107581176] [2022-11-21 13:42:06,352 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107581176] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:06,353 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:06,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:06,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030834402] [2022-11-21 13:42:06,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:06,353 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:06,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:06,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:06,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:06,354 INFO L87 Difference]: Start difference. First operand 10496 states and 15051 transitions. cyclomatic complexity: 4557 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:06,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:06,585 INFO L93 Difference]: Finished difference Result 20116 states and 28733 transitions. [2022-11-21 13:42:06,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20116 states and 28733 transitions. [2022-11-21 13:42:06,663 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19909 [2022-11-21 13:42:06,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20116 states to 20116 states and 28733 transitions. [2022-11-21 13:42:06,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20116 [2022-11-21 13:42:06,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20116 [2022-11-21 13:42:06,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20116 states and 28733 transitions. [2022-11-21 13:42:06,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:06,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20116 states and 28733 transitions. [2022-11-21 13:42:06,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20116 states and 28733 transitions. [2022-11-21 13:42:06,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20116 to 20104. [2022-11-21 13:42:07,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20104 states, 20104 states have (on average 1.4286211699164346) internal successors, (28721), 20103 states have internal predecessors, (28721), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:07,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20104 states to 20104 states and 28721 transitions. [2022-11-21 13:42:07,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20104 states and 28721 transitions. [2022-11-21 13:42:07,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:07,048 INFO L428 stractBuchiCegarLoop]: Abstraction has 20104 states and 28721 transitions. [2022-11-21 13:42:07,048 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-21 13:42:07,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20104 states and 28721 transitions. [2022-11-21 13:42:07,112 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19897 [2022-11-21 13:42:07,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:07,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:07,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:07,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:07,115 INFO L748 eck$LassoCheckResult]: Stem: 168493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 168494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 169673#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169005#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169006#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 168477#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168478#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168542#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168543#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169001#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169002#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 168511#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 168327#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168328#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168783#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 168784#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 168657#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 168658#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 168299#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168300#L1279 assume !(0 == ~M_E~0); 169665#L1279-2 assume !(0 == ~T1_E~0); 167929#L1284-1 assume !(0 == ~T2_E~0); 167930#L1289-1 assume !(0 == ~T3_E~0); 168649#L1294-1 assume !(0 == ~T4_E~0); 168650#L1299-1 assume !(0 == ~T5_E~0); 168661#L1304-1 assume !(0 == ~T6_E~0); 169791#L1309-1 assume !(0 == ~T7_E~0); 169795#L1314-1 assume !(0 == ~T8_E~0); 167858#L1319-1 assume !(0 == ~T9_E~0); 167859#L1324-1 assume !(0 == ~T10_E~0); 168031#L1329-1 assume !(0 == ~T11_E~0); 168032#L1334-1 assume !(0 == ~T12_E~0); 169541#L1339-1 assume !(0 == ~T13_E~0); 169645#L1344-1 assume !(0 == ~E_M~0); 169646#L1349-1 assume !(0 == ~E_1~0); 168845#L1354-1 assume !(0 == ~E_2~0); 168846#L1359-1 assume !(0 == ~E_3~0); 169316#L1364-1 assume !(0 == ~E_4~0); 168155#L1369-1 assume !(0 == ~E_5~0); 168156#L1374-1 assume !(0 == ~E_6~0); 168851#L1379-1 assume !(0 == ~E_7~0); 168852#L1384-1 assume !(0 == ~E_8~0); 168931#L1389-1 assume !(0 == ~E_9~0); 169561#L1394-1 assume !(0 == ~E_10~0); 169562#L1399-1 assume !(0 == ~E_11~0); 169709#L1404-1 assume !(0 == ~E_12~0); 168248#L1409-1 assume !(0 == ~E_13~0); 168249#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169695#L628 assume !(1 == ~m_pc~0); 169567#L628-2 is_master_triggered_~__retres1~0#1 := 0; 169130#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168929#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168930#L1591 assume !(0 != activate_threads_~tmp~1#1); 169716#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168708#L647 assume !(1 == ~t1_pc~0); 168709#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168767#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168342#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168343#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 169628#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169629#L666 assume !(1 == ~t2_pc~0); 167928#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 168088#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168089#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169649#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 169058#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169059#L685 assume !(1 == ~t3_pc~0); 169174#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169245#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169724#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 168899#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 168900#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168369#L704 assume !(1 == ~t4_pc~0); 168370#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168911#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168912#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169678#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 168763#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168764#L723 assume !(1 == ~t5_pc~0); 168895#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169145#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169310#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 169038#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 169039#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168141#L742 assume 1 == ~t6_pc~0; 168142#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168284#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168285#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 167828#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 167829#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168215#L761 assume !(1 == ~t7_pc~0); 168216#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 168086#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168087#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168902#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 168903#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 167852#L780 assume 1 == ~t8_pc~0; 167853#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168127#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168128#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 168859#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 168860#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168985#L799 assume 1 == ~t9_pc~0; 169105#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 167855#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 167856#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168997#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 169222#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169016#L818 assume !(1 == ~t10_pc~0); 167635#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 167636#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169097#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 169019#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 169020#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169067#L837 assume 1 == ~t11_pc~0; 169068#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168891#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 169336#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168978#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 168979#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168720#L856 assume !(1 == ~t12_pc~0); 168721#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 169444#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 169445#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 169419#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 169420#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 169668#L875 assume 1 == ~t13_pc~0; 168659#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 168288#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 168289#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 168230#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 168231#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169094#L1427 assume !(1 == ~M_E~0); 169080#L1427-2 assume !(1 == ~T1_E~0); 168202#L1432-1 assume !(1 == ~T2_E~0); 168203#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169326#L1442-1 assume !(1 == ~T4_E~0); 169327#L1447-1 assume !(1 == ~T5_E~0); 169159#L1452-1 assume !(1 == ~T6_E~0); 167770#L1457-1 assume !(1 == ~T7_E~0); 167771#L1462-1 assume !(1 == ~T8_E~0); 169362#L1467-1 assume !(1 == ~T9_E~0); 169380#L1472-1 assume !(1 == ~T10_E~0); 169381#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 169092#L1482-1 assume !(1 == ~T12_E~0); 169093#L1487-1 assume !(1 == ~T13_E~0); 168101#L1492-1 assume !(1 == ~E_M~0); 168102#L1497-1 assume !(1 == ~E_1~0); 168457#L1502-1 assume !(1 == ~E_2~0); 168458#L1507-1 assume !(1 == ~E_3~0); 167981#L1512-1 assume !(1 == ~E_4~0); 167982#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 169475#L1522-1 assume !(1 == ~E_6~0); 168704#L1527-1 assume !(1 == ~E_7~0); 168705#L1532-1 assume !(1 == ~E_8~0); 169754#L1537-1 assume !(1 == ~E_9~0); 168918#L1542-1 assume !(1 == ~E_10~0); 168741#L1547-1 assume !(1 == ~E_11~0); 168742#L1552-1 assume !(1 == ~E_12~0); 167674#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 167675#L1562-1 assume { :end_inline_reset_delta_events } true; 168276#L1928-2 [2022-11-21 13:42:07,116 INFO L750 eck$LassoCheckResult]: Loop: 168276#L1928-2 assume !false; 186522#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 186519#L1254 assume !false; 186518#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 186511#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186503#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 185563#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 169455#L1067 assume !(0 != eval_~tmp~0#1); 169457#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 186396#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 186394#L1279-3 assume !(0 == ~M_E~0); 186395#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 186451#L1284-3 assume !(0 == ~T2_E~0); 186450#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 186449#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 186448#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 186447#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 186446#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 186445#L1314-3 assume !(0 == ~T8_E~0); 186444#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 186443#L1324-3 assume !(0 == ~T10_E~0); 186442#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 186441#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 186440#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 186439#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 186438#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 186437#L1354-3 assume !(0 == ~E_2~0); 186436#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 186435#L1364-3 assume !(0 == ~E_4~0); 186434#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 186432#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 186431#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 186430#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 186429#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 186428#L1394-3 assume !(0 == ~E_10~0); 186427#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 186426#L1404-3 assume !(0 == ~E_12~0); 169552#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 169553#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186375#L628-45 assume !(1 == ~m_pc~0); 186371#L628-47 is_master_triggered_~__retres1~0#1 := 0; 186367#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186363#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186360#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 186357#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186355#L647-45 assume !(1 == ~t1_pc~0); 186353#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 186351#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186350#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 186349#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186348#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186344#L666-45 assume !(1 == ~t2_pc~0); 186342#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 186340#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186339#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 186337#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 186334#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186305#L685-45 assume 1 == ~t3_pc~0; 186303#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 186304#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186310#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 186293#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 186291#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186289#L704-45 assume !(1 == ~t4_pc~0); 186287#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 186285#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186283#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 186280#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 186278#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186276#L723-45 assume 1 == ~t5_pc~0; 186274#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 186271#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186269#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 186267#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 186266#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 186265#L742-45 assume 1 == ~t6_pc~0; 186263#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 186260#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186258#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 186256#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 186254#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186252#L761-45 assume !(1 == ~t7_pc~0); 186250#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 186246#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186244#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 186242#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 186240#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 186238#L780-45 assume !(1 == ~t8_pc~0); 186234#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 186231#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186229#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169752#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 167967#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 167968#L799-45 assume !(1 == ~t9_pc~0); 168744#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 186216#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169626#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 169627#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 186005#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 186000#L818-45 assume !(1 == ~t10_pc~0); 186002#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 185866#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 185867#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 168502#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 168503#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 186191#L837-45 assume !(1 == ~t11_pc~0); 186186#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 168573#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168574#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 169786#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 168041#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168042#L856-45 assume !(1 == ~t12_pc~0); 186170#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 169469#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 169470#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 169769#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 169770#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 186160#L875-45 assume 1 == ~t13_pc~0; 168826#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 168827#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 169790#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 169615#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 169616#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169539#L1427-3 assume !(1 == ~M_E~0); 169540#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 186588#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 186587#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 186586#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 186585#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 186584#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 186583#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 186582#L1462-3 assume !(1 == ~T8_E~0); 186581#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 186580#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 186579#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 186578#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 186577#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 186576#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 186575#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 186574#L1502-3 assume !(1 == ~E_2~0); 186573#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 186572#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 186571#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 186570#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 186569#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 186568#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 186567#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 186566#L1542-3 assume !(1 == ~E_10~0); 186565#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 186564#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 186563#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 186562#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 186560#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186547#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 186546#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 186545#L1947 assume !(0 == start_simulation_~tmp~3#1); 186543#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 186541#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186528#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 186527#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 186526#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 186525#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 186524#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 186523#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 168276#L1928-2 [2022-11-21 13:42:07,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:07,117 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2022-11-21 13:42:07,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:07,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830538901] [2022-11-21 13:42:07,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:07,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:07,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:07,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:07,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:07,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830538901] [2022-11-21 13:42:07,249 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830538901] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:07,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:07,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:07,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493613374] [2022-11-21 13:42:07,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:07,250 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:07,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:07,250 INFO L85 PathProgramCache]: Analyzing trace with hash -2084156374, now seen corresponding path program 1 times [2022-11-21 13:42:07,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:07,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335458730] [2022-11-21 13:42:07,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:07,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:07,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:07,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:07,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:07,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335458730] [2022-11-21 13:42:07,417 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335458730] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:07,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:07,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:07,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008236722] [2022-11-21 13:42:07,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:07,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:07,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:07,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-21 13:42:07,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-21 13:42:07,419 INFO L87 Difference]: Start difference. First operand 20104 states and 28721 transitions. cyclomatic complexity: 8621 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:07,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:07,943 INFO L93 Difference]: Finished difference Result 57725 states and 81880 transitions. [2022-11-21 13:42:07,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57725 states and 81880 transitions. [2022-11-21 13:42:08,198 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 56583 [2022-11-21 13:42:08,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57725 states to 57725 states and 81880 transitions. [2022-11-21 13:42:08,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57725 [2022-11-21 13:42:08,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57725 [2022-11-21 13:42:08,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57725 states and 81880 transitions. [2022-11-21 13:42:08,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:08,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57725 states and 81880 transitions. [2022-11-21 13:42:08,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57725 states and 81880 transitions. [2022-11-21 13:42:09,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57725 to 56169. [2022-11-21 13:42:09,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56169 states, 56169 states have (on average 1.420000356068294) internal successors, (79760), 56168 states have internal predecessors, (79760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:09,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56169 states to 56169 states and 79760 transitions. [2022-11-21 13:42:09,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56169 states and 79760 transitions. [2022-11-21 13:42:09,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-21 13:42:09,794 INFO L428 stractBuchiCegarLoop]: Abstraction has 56169 states and 79760 transitions. [2022-11-21 13:42:09,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-21 13:42:09,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56169 states and 79760 transitions. [2022-11-21 13:42:10,152 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 55899 [2022-11-21 13:42:10,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:10,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:10,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:10,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:10,157 INFO L748 eck$LassoCheckResult]: Stem: 246336#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 246337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 247685#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 246896#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246897#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 246317#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246318#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246389#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246390#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246892#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246893#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 246353#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 246170#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 246171#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 246647#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 246648#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 246516#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 246517#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 246142#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 246143#L1279 assume !(0 == ~M_E~0); 247674#L1279-2 assume !(0 == ~T1_E~0); 245768#L1284-1 assume !(0 == ~T2_E~0); 245769#L1289-1 assume !(0 == ~T3_E~0); 246513#L1294-1 assume !(0 == ~T4_E~0); 246514#L1299-1 assume !(0 == ~T5_E~0); 246525#L1304-1 assume !(0 == ~T6_E~0); 247880#L1309-1 assume !(0 == ~T7_E~0); 247885#L1314-1 assume !(0 == ~T8_E~0); 245697#L1319-1 assume !(0 == ~T9_E~0); 245698#L1324-1 assume !(0 == ~T10_E~0); 245875#L1329-1 assume !(0 == ~T11_E~0); 245876#L1334-1 assume !(0 == ~T12_E~0); 247518#L1339-1 assume !(0 == ~T13_E~0); 247649#L1344-1 assume !(0 == ~E_M~0); 247650#L1349-1 assume !(0 == ~E_1~0); 246719#L1354-1 assume !(0 == ~E_2~0); 246720#L1359-1 assume !(0 == ~E_3~0); 247254#L1364-1 assume !(0 == ~E_4~0); 245999#L1369-1 assume !(0 == ~E_5~0); 246000#L1374-1 assume !(0 == ~E_6~0); 246724#L1379-1 assume !(0 == ~E_7~0); 246725#L1384-1 assume !(0 == ~E_8~0); 246812#L1389-1 assume !(0 == ~E_9~0); 247547#L1394-1 assume !(0 == ~E_10~0); 247548#L1399-1 assume !(0 == ~E_11~0); 247743#L1404-1 assume !(0 == ~E_12~0); 246092#L1409-1 assume !(0 == ~E_13~0); 246093#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247720#L628 assume !(1 == ~m_pc~0); 247555#L628-2 is_master_triggered_~__retres1~0#1 := 0; 247039#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246810#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 246811#L1591 assume !(0 != activate_threads_~tmp~1#1); 247757#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246573#L647 assume !(1 == ~t1_pc~0); 246574#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 246631#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246185#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 246186#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 247629#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247630#L666 assume !(1 == ~t2_pc~0); 245767#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245933#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245934#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247654#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 246952#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 246953#L685 assume !(1 == ~t3_pc~0); 247087#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247173#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247772#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 246774#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 246775#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246212#L704 assume !(1 == ~t4_pc~0); 246213#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 246792#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246793#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247692#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 246627#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 246628#L723 assume !(1 == ~t5_pc~0); 246768#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 247054#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247247#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246930#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 246931#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245985#L742 assume !(1 == ~t6_pc~0); 245986#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 246128#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246129#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 245665#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 245666#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246059#L761 assume !(1 == ~t7_pc~0); 246060#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 245929#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245930#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246778#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 246779#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 245691#L780 assume 1 == ~t8_pc~0; 245692#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 245972#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 245973#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 246734#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 246735#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 246874#L799 assume 1 == ~t9_pc~0; 247009#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 245694#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 245695#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 246888#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 247144#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 246908#L818 assume !(1 == ~t10_pc~0); 245477#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 245478#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 247000#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246912#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246913#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 246962#L837 assume 1 == ~t11_pc~0; 246963#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 246765#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 247278#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246866#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 246867#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246583#L856 assume !(1 == ~t12_pc~0); 246584#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 247409#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 247410#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 247375#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 247376#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 247679#L875 assume 1 == ~t13_pc~0; 246523#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 246131#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 246132#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246074#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 246075#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246997#L1427 assume !(1 == ~M_E~0); 246976#L1427-2 assume !(1 == ~T1_E~0); 246046#L1432-1 assume !(1 == ~T2_E~0); 246047#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 247264#L1442-1 assume !(1 == ~T4_E~0); 247265#L1447-1 assume !(1 == ~T5_E~0); 247070#L1452-1 assume !(1 == ~T6_E~0); 245611#L1457-1 assume !(1 == ~T7_E~0); 245612#L1462-1 assume !(1 == ~T8_E~0); 247306#L1467-1 assume !(1 == ~T9_E~0); 247330#L1472-1 assume !(1 == ~T10_E~0); 247331#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246995#L1482-1 assume !(1 == ~T12_E~0); 246996#L1487-1 assume !(1 == ~T13_E~0); 245944#L1492-1 assume !(1 == ~E_M~0); 245945#L1497-1 assume !(1 == ~E_1~0); 246299#L1502-1 assume !(1 == ~E_2~0); 246300#L1507-1 assume !(1 == ~E_3~0); 245822#L1512-1 assume !(1 == ~E_4~0); 245823#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 247438#L1522-1 assume !(1 == ~E_6~0); 246569#L1527-1 assume !(1 == ~E_7~0); 246570#L1532-1 assume !(1 == ~E_8~0); 247821#L1537-1 assume !(1 == ~E_9~0); 246799#L1542-1 assume !(1 == ~E_10~0); 246605#L1547-1 assume !(1 == ~E_11~0); 246606#L1552-1 assume !(1 == ~E_12~0); 245516#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 245517#L1562-1 assume { :end_inline_reset_delta_events } true; 246120#L1928-2 [2022-11-21 13:42:10,158 INFO L750 eck$LassoCheckResult]: Loop: 246120#L1928-2 assume !false; 246767#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 246361#L1254 assume !false; 246362#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 295122#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 295112#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 247694#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 247420#L1067 assume !(0 != eval_~tmp~0#1); 247421#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 297209#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 297208#L1279-3 assume !(0 == ~M_E~0); 297207#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 297206#L1284-3 assume !(0 == ~T2_E~0); 297205#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 297204#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 297203#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 297202#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 297201#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 297200#L1314-3 assume !(0 == ~T8_E~0); 297199#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 297198#L1324-3 assume !(0 == ~T10_E~0); 297197#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 297196#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 297195#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 297194#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 297193#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 297192#L1354-3 assume !(0 == ~E_2~0); 297191#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 297190#L1364-3 assume !(0 == ~E_4~0); 297189#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 297188#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 297187#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 297186#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 297185#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 297184#L1394-3 assume !(0 == ~E_10~0); 297183#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 297182#L1404-3 assume !(0 == ~E_12~0); 297181#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 297180#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297179#L628-45 assume !(1 == ~m_pc~0); 297178#L628-47 is_master_triggered_~__retres1~0#1 := 0; 297177#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 297176#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 297175#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 297174#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297173#L647-45 assume !(1 == ~t1_pc~0); 297172#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 297171#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297170#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 297169#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 297168#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 297166#L666-45 assume !(1 == ~t2_pc~0); 297165#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 297164#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 297163#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 297162#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 297161#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297160#L685-45 assume !(1 == ~t3_pc~0); 297158#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 297156#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297154#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 297153#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 297151#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 297150#L704-45 assume !(1 == ~t4_pc~0); 297149#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 297148#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 297147#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 297146#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 297145#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 297144#L723-45 assume 1 == ~t5_pc~0; 297142#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 297141#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 297140#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 297139#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 297138#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 297137#L742-45 assume !(1 == ~t6_pc~0); 297136#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 297135#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 297134#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 297133#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 297132#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 297131#L761-45 assume 1 == ~t7_pc~0; 297129#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 297128#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 297127#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 297126#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 297125#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 297124#L780-45 assume 1 == ~t8_pc~0; 297122#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 297121#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 297120#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 297119#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 297118#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 297117#L799-45 assume 1 == ~t9_pc~0; 297116#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 297114#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 297113#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 297112#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 297111#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 297110#L818-45 assume 1 == ~t10_pc~0; 297108#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 297107#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 297106#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 297105#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 297104#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 297103#L837-45 assume !(1 == ~t11_pc~0); 297101#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 297100#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 297099#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 297098#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 297097#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 297096#L856-45 assume 1 == ~t12_pc~0; 297094#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 297093#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 297092#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 297091#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 297090#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 297089#L875-45 assume 1 == ~t13_pc~0; 297088#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 297086#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 297085#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 297084#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 297083#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297082#L1427-3 assume !(1 == ~M_E~0); 296351#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 297081#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 297080#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 297079#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 297078#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 297077#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 297076#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 297075#L1462-3 assume !(1 == ~T8_E~0); 297074#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 297073#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 297072#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 297071#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 297070#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 297069#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 297068#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 297067#L1502-3 assume !(1 == ~E_2~0); 297066#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 297065#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 297064#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 297063#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 297062#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 297061#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 297060#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 297059#L1542-3 assume !(1 == ~E_10~0); 297058#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 297057#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 297056#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 297055#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 297053#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 297040#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 297039#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 297038#L1947 assume !(0 == start_simulation_~tmp~3#1); 247105#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 247106#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 297764#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 297763#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 297762#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 297761#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 297760#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 297759#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 246120#L1928-2 [2022-11-21 13:42:10,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:10,158 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2022-11-21 13:42:10,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:10,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184483398] [2022-11-21 13:42:10,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:10,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:10,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:10,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:10,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:10,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184483398] [2022-11-21 13:42:10,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184483398] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:10,236 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:10,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-21 13:42:10,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499251161] [2022-11-21 13:42:10,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:10,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:10,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:10,237 INFO L85 PathProgramCache]: Analyzing trace with hash 960748457, now seen corresponding path program 1 times [2022-11-21 13:42:10,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:10,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970611189] [2022-11-21 13:42:10,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:10,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:10,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:10,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:10,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:10,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970611189] [2022-11-21 13:42:10,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970611189] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:10,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:10,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:10,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355034152] [2022-11-21 13:42:10,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:10,290 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:10,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:10,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-21 13:42:10,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-21 13:42:10,291 INFO L87 Difference]: Start difference. First operand 56169 states and 79760 transitions. cyclomatic complexity: 23599 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:10,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:10,938 INFO L93 Difference]: Finished difference Result 108069 states and 152952 transitions. [2022-11-21 13:42:10,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108069 states and 152952 transitions. [2022-11-21 13:42:11,724 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107632 [2022-11-21 13:42:12,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108069 states to 108069 states and 152952 transitions. [2022-11-21 13:42:12,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108069 [2022-11-21 13:42:12,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108069 [2022-11-21 13:42:12,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108069 states and 152952 transitions. [2022-11-21 13:42:12,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:12,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108069 states and 152952 transitions. [2022-11-21 13:42:12,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108069 states and 152952 transitions. [2022-11-21 13:42:13,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108069 to 107997. [2022-11-21 13:42:13,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107997 states, 107997 states have (on average 1.4155948776354899) internal successors, (152880), 107996 states have internal predecessors, (152880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:14,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107997 states to 107997 states and 152880 transitions. [2022-11-21 13:42:14,464 INFO L240 hiAutomatonCegarLoop]: Abstraction has 107997 states and 152880 transitions. [2022-11-21 13:42:14,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-21 13:42:14,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 107997 states and 152880 transitions. [2022-11-21 13:42:14,465 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-21 13:42:14,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107997 states and 152880 transitions. [2022-11-21 13:42:15,031 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107560 [2022-11-21 13:42:15,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:15,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:15,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:15,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:15,035 INFO L748 eck$LassoCheckResult]: Stem: 410575#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 410576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 411801#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 411104#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 411105#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 410557#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 410558#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 410627#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 410628#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 411100#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 411101#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 410593#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 410406#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 410407#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 410872#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 410873#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 410743#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 410744#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 410377#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 410378#L1279 assume !(0 == ~M_E~0); 411790#L1279-2 assume !(0 == ~T1_E~0); 410011#L1284-1 assume !(0 == ~T2_E~0); 410012#L1289-1 assume !(0 == ~T3_E~0); 410740#L1294-1 assume !(0 == ~T4_E~0); 410741#L1299-1 assume !(0 == ~T5_E~0); 410752#L1304-1 assume !(0 == ~T6_E~0); 411942#L1309-1 assume !(0 == ~T7_E~0); 411944#L1314-1 assume !(0 == ~T8_E~0); 409941#L1319-1 assume !(0 == ~T9_E~0); 409942#L1324-1 assume !(0 == ~T10_E~0); 410115#L1329-1 assume !(0 == ~T11_E~0); 410116#L1334-1 assume !(0 == ~T12_E~0); 411658#L1339-1 assume !(0 == ~T13_E~0); 411772#L1344-1 assume !(0 == ~E_M~0); 411773#L1349-1 assume !(0 == ~E_1~0); 410933#L1354-1 assume !(0 == ~E_2~0); 410934#L1359-1 assume !(0 == ~E_3~0); 411430#L1364-1 assume !(0 == ~E_4~0); 410236#L1369-1 assume !(0 == ~E_5~0); 410237#L1374-1 assume !(0 == ~E_6~0); 410939#L1379-1 assume !(0 == ~E_7~0); 410940#L1384-1 assume !(0 == ~E_8~0); 411027#L1389-1 assume !(0 == ~E_9~0); 411688#L1394-1 assume !(0 == ~E_10~0); 411689#L1399-1 assume !(0 == ~E_11~0); 411841#L1404-1 assume !(0 == ~E_12~0); 410328#L1409-1 assume !(0 == ~E_13~0); 410329#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 411826#L628 assume !(1 == ~m_pc~0); 411693#L628-2 is_master_triggered_~__retres1~0#1 := 0; 411234#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 411025#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 411026#L1591 assume !(0 != activate_threads_~tmp~1#1); 411852#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 410798#L647 assume !(1 == ~t1_pc~0); 410799#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 410857#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 410421#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 410422#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 411756#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 411757#L666 assume !(1 == ~t2_pc~0); 410010#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 410172#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 410173#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 411778#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 411156#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 411157#L685 assume !(1 == ~t3_pc~0); 411277#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 411358#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411863#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 410992#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 410993#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 410451#L704 assume !(1 == ~t4_pc~0); 410452#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 411005#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 411006#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 411805#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 410853#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410854#L723 assume !(1 == ~t5_pc~0); 410986#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 411248#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 411425#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 411135#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 411136#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 410223#L742 assume !(1 == ~t6_pc~0); 410224#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 410363#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 410364#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 409910#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 409911#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410295#L761 assume !(1 == ~t7_pc~0); 410296#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 410168#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 410169#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 410994#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 410995#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 409936#L780 assume !(1 == ~t8_pc~0); 409937#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 410210#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 410211#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 410950#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 410951#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 411083#L799 assume 1 == ~t9_pc~0; 411206#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 409938#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 409939#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 411096#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 411330#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 411115#L818 assume !(1 == ~t10_pc~0); 409721#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 409722#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 411198#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 411119#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 411120#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 411165#L837 assume 1 == ~t11_pc~0; 411166#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 410983#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 411449#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 411076#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 411077#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 410808#L856 assume !(1 == ~t12_pc~0); 410809#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 411569#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 411570#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 411537#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 411538#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 411795#L875 assume 1 == ~t13_pc~0; 410750#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 410366#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 410367#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 410310#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 410311#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 411195#L1427 assume !(1 == ~M_E~0); 411177#L1427-2 assume !(1 == ~T1_E~0); 410282#L1432-1 assume !(1 == ~T2_E~0); 410283#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 411437#L1442-1 assume !(1 == ~T4_E~0); 411438#L1447-1 assume !(1 == ~T5_E~0); 411262#L1452-1 assume !(1 == ~T6_E~0); 409855#L1457-1 assume !(1 == ~T7_E~0); 409856#L1462-1 assume !(1 == ~T8_E~0); 411478#L1467-1 assume !(1 == ~T9_E~0); 411497#L1472-1 assume !(1 == ~T10_E~0); 411498#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 411193#L1482-1 assume !(1 == ~T12_E~0); 411194#L1487-1 assume !(1 == ~T13_E~0); 410184#L1492-1 assume !(1 == ~E_M~0); 410185#L1497-1 assume !(1 == ~E_1~0); 410538#L1502-1 assume !(1 == ~E_2~0); 410539#L1507-1 assume !(1 == ~E_3~0); 410064#L1512-1 assume !(1 == ~E_4~0); 410065#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 411593#L1522-1 assume !(1 == ~E_6~0); 410795#L1527-1 assume !(1 == ~E_7~0); 410796#L1532-1 assume !(1 == ~E_8~0); 411893#L1537-1 assume !(1 == ~E_9~0); 411012#L1542-1 assume !(1 == ~E_10~0); 410831#L1547-1 assume !(1 == ~E_11~0); 410832#L1552-1 assume !(1 == ~E_12~0); 409760#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 409761#L1562-1 assume { :end_inline_reset_delta_events } true; 410355#L1928-2 [2022-11-21 13:42:15,036 INFO L750 eck$LassoCheckResult]: Loop: 410355#L1928-2 assume !false; 449454#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 449449#L1254 assume !false; 449448#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 449441#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 449433#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 449432#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 449430#L1067 assume !(0 != eval_~tmp~0#1); 449429#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 449428#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 449427#L1279-3 assume !(0 == ~M_E~0); 449426#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 449425#L1284-3 assume !(0 == ~T2_E~0); 449423#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 449422#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 449421#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 449417#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 449415#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 449413#L1314-3 assume !(0 == ~T8_E~0); 449411#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 449408#L1324-3 assume !(0 == ~T10_E~0); 449406#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 449404#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 449402#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 449400#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 449398#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 449396#L1354-3 assume !(0 == ~E_2~0); 449394#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 449392#L1364-3 assume !(0 == ~E_4~0); 449389#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 449387#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 449385#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 449383#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 449381#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 449379#L1394-3 assume !(0 == ~E_10~0); 449378#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 449376#L1404-3 assume !(0 == ~E_12~0); 449374#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 449372#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 449370#L628-45 assume !(1 == ~m_pc~0); 449368#L628-47 is_master_triggered_~__retres1~0#1 := 0; 449365#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 449363#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 449361#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 449359#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 449357#L647-45 assume !(1 == ~t1_pc~0); 449355#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 449352#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 449350#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 449348#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 449346#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 449342#L666-45 assume !(1 == ~t2_pc~0); 449339#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 449337#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 449335#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 449333#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 449331#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 447710#L685-45 assume 1 == ~t3_pc~0; 447708#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 447709#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 447744#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 447698#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 447696#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 447694#L704-45 assume !(1 == ~t4_pc~0); 447693#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 447690#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447688#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 447686#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 447684#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 447682#L723-45 assume !(1 == ~t5_pc~0); 447680#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 447676#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 447674#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 447672#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 447670#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 447668#L742-45 assume !(1 == ~t6_pc~0); 447666#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 447663#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 447661#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 447659#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 447657#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 447655#L761-45 assume 1 == ~t7_pc~0; 447422#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 447417#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 447412#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 447406#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 447400#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 447393#L780-45 assume !(1 == ~t8_pc~0); 447387#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 447381#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 447375#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 447369#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 447363#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 447356#L799-45 assume !(1 == ~t9_pc~0); 447348#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 447341#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 447334#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 447328#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 447326#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 447325#L818-45 assume 1 == ~t10_pc~0; 447272#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 447264#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 447257#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 447248#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 447241#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 447235#L837-45 assume !(1 == ~t11_pc~0); 447228#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 447221#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 447213#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 447206#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 447198#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 447191#L856-45 assume !(1 == ~t12_pc~0); 447184#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 447175#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 447168#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 447161#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 447154#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 447146#L875-45 assume 1 == ~t13_pc~0; 447138#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 447127#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 447118#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 447111#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 447104#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 447096#L1427-3 assume !(1 == ~M_E~0); 446602#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 447082#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 447074#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 447067#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 447060#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 447052#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 447044#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 447034#L1462-3 assume !(1 == ~T8_E~0); 447025#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 447017#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 447010#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 447003#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 446996#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 446987#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 446979#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 446972#L1502-3 assume !(1 == ~E_2~0); 446965#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 446957#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 446949#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 446940#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 446932#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 446924#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 446917#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 446909#L1542-3 assume !(1 == ~E_10~0); 446902#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 446894#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 446887#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 446884#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 446827#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 446809#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 446794#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 446790#L1947 assume !(0 == start_simulation_~tmp~3#1); 446791#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 449490#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 449474#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 449472#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 449470#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 449469#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 449464#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 449459#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 410355#L1928-2 [2022-11-21 13:42:15,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:15,037 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2022-11-21 13:42:15,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:15,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631533500] [2022-11-21 13:42:15,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:15,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:15,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:15,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:15,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:15,129 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631533500] [2022-11-21 13:42:15,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631533500] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:15,130 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:15,130 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:15,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696415848] [2022-11-21 13:42:15,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:15,131 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:15,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:15,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1719558058, now seen corresponding path program 1 times [2022-11-21 13:42:15,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:15,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085760343] [2022-11-21 13:42:15,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:15,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:15,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:15,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:15,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:15,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085760343] [2022-11-21 13:42:15,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085760343] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:15,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:15,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-21 13:42:15,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200369596] [2022-11-21 13:42:15,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:15,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:15,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:15,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-21 13:42:15,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-21 13:42:15,185 INFO L87 Difference]: Start difference. First operand 107997 states and 152880 transitions. cyclomatic complexity: 44899 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:17,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:17,009 INFO L93 Difference]: Finished difference Result 309396 states and 435421 transitions. [2022-11-21 13:42:17,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309396 states and 435421 transitions. [2022-11-21 13:42:18,684 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 304880 [2022-11-21 13:42:19,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309396 states to 309396 states and 435421 transitions. [2022-11-21 13:42:19,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309396 [2022-11-21 13:42:20,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309396 [2022-11-21 13:42:20,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309396 states and 435421 transitions. [2022-11-21 13:42:20,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:20,180 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309396 states and 435421 transitions. [2022-11-21 13:42:20,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309396 states and 435421 transitions. [2022-11-21 13:42:23,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309396 to 303172. [2022-11-21 13:42:23,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303172 states, 303172 states have (on average 1.4087217816948794) internal successors, (427085), 303171 states have internal predecessors, (427085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:24,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303172 states to 303172 states and 427085 transitions. [2022-11-21 13:42:24,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 303172 states and 427085 transitions. [2022-11-21 13:42:24,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-21 13:42:24,819 INFO L428 stractBuchiCegarLoop]: Abstraction has 303172 states and 427085 transitions. [2022-11-21 13:42:24,819 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-21 13:42:24,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303172 states and 427085 transitions. [2022-11-21 13:42:25,571 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 302288 [2022-11-21 13:42:25,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-21 13:42:25,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-21 13:42:25,573 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:25,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-21 13:42:25,574 INFO L748 eck$LassoCheckResult]: Stem: 827996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 827997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 829273#L1891 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 828550#L895 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 828551#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 827974#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 827975#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 828046#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 828047#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 828548#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 828549#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 828011#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 827820#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 827821#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 828306#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 828307#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 828175#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 828176#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 827790#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 827791#L1279 assume !(0 == ~M_E~0); 829265#L1279-2 assume !(0 == ~T1_E~0); 827417#L1284-1 assume !(0 == ~T2_E~0); 827418#L1289-1 assume !(0 == ~T3_E~0); 828163#L1294-1 assume !(0 == ~T4_E~0); 828164#L1299-1 assume !(0 == ~T5_E~0); 828179#L1304-1 assume !(0 == ~T6_E~0); 829413#L1309-1 assume !(0 == ~T7_E~0); 829417#L1314-1 assume !(0 == ~T8_E~0); 827346#L1319-1 assume !(0 == ~T9_E~0); 827347#L1324-1 assume !(0 == ~T10_E~0); 827520#L1329-1 assume !(0 == ~T11_E~0); 827521#L1334-1 assume !(0 == ~T12_E~0); 829119#L1339-1 assume !(0 == ~T13_E~0); 829245#L1344-1 assume !(0 == ~E_M~0); 829246#L1349-1 assume !(0 == ~E_1~0); 828378#L1354-1 assume !(0 == ~E_2~0); 828379#L1359-1 assume !(0 == ~E_3~0); 828884#L1364-1 assume !(0 == ~E_4~0); 827644#L1369-1 assume !(0 == ~E_5~0); 827645#L1374-1 assume !(0 == ~E_6~0); 828385#L1379-1 assume !(0 == ~E_7~0); 828386#L1384-1 assume !(0 == ~E_8~0); 828467#L1389-1 assume !(0 == ~E_9~0); 829149#L1394-1 assume !(0 == ~E_10~0); 829150#L1399-1 assume !(0 == ~E_11~0); 829310#L1404-1 assume !(0 == ~E_12~0); 827738#L1409-1 assume !(0 == ~E_13~0); 827739#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 829295#L628 assume !(1 == ~m_pc~0); 829154#L628-2 is_master_triggered_~__retres1~0#1 := 0; 828686#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 828465#L640 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 828466#L1591 assume !(0 != activate_threads_~tmp~1#1); 829319#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 828226#L647 assume !(1 == ~t1_pc~0); 828227#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 828290#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 827835#L659 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 827836#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 829226#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829227#L666 assume !(1 == ~t2_pc~0); 827416#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 827583#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827584#L678 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829250#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 828605#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 828606#L685 assume !(1 == ~t3_pc~0); 828734#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 828809#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 829330#L697 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 828434#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 828435#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 827865#L704 assume !(1 == ~t4_pc~0); 827866#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 828447#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 828448#L716 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829279#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 828286#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 828287#L723 assume !(1 == ~t5_pc~0); 828429#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 828702#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828878#L735 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 828587#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 828588#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 827632#L742 assume !(1 == ~t6_pc~0); 827633#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 827776#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 827777#L754 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 827316#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 827317#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 827704#L761 assume !(1 == ~t7_pc~0); 827705#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 827577#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 827578#L773 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 828437#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 828438#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 827339#L780 assume !(1 == ~t8_pc~0); 827340#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 827618#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 827619#L792 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 828392#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 828393#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 828527#L799 assume !(1 == ~t9_pc~0); 827844#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 827341#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 827342#L811 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 828540#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 828784#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 828561#L818 assume !(1 == ~t10_pc~0); 827126#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 827127#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 828653#L830 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 828564#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 828565#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 828615#L837 assume 1 == ~t11_pc~0; 828616#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 828425#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 828904#L849 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 828516#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 828517#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 828242#L856 assume !(1 == ~t12_pc~0); 828243#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 829020#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 829021#L868 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 828995#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 828996#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 829268#L875 assume 1 == ~t13_pc~0; 828177#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 827779#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 827780#L887 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 827720#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 827721#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828647#L1427 assume !(1 == ~M_E~0); 828632#L1427-2 assume !(1 == ~T1_E~0); 827691#L1432-1 assume !(1 == ~T2_E~0); 827692#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 828891#L1442-1 assume !(1 == ~T4_E~0); 828892#L1447-1 assume !(1 == ~T5_E~0); 828716#L1452-1 assume !(1 == ~T6_E~0); 827258#L1457-1 assume !(1 == ~T7_E~0); 827259#L1462-1 assume !(1 == ~T8_E~0); 828933#L1467-1 assume !(1 == ~T9_E~0); 828953#L1472-1 assume !(1 == ~T10_E~0); 828954#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 828645#L1482-1 assume !(1 == ~T12_E~0); 828646#L1487-1 assume !(1 == ~T13_E~0); 827592#L1492-1 assume !(1 == ~E_M~0); 827593#L1497-1 assume !(1 == ~E_1~0); 827953#L1502-1 assume !(1 == ~E_2~0); 827954#L1507-1 assume !(1 == ~E_3~0); 827471#L1512-1 assume !(1 == ~E_4~0); 827472#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 829047#L1522-1 assume !(1 == ~E_6~0); 828224#L1527-1 assume !(1 == ~E_7~0); 828225#L1532-1 assume !(1 == ~E_8~0); 829366#L1537-1 assume !(1 == ~E_9~0); 828455#L1542-1 assume !(1 == ~E_10~0); 828263#L1547-1 assume !(1 == ~E_11~0); 828264#L1552-1 assume !(1 == ~E_12~0); 827164#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 827165#L1562-1 assume { :end_inline_reset_delta_events } true; 827768#L1928-2 [2022-11-21 13:42:25,575 INFO L750 eck$LassoCheckResult]: Loop: 827768#L1928-2 assume !false; 994920#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 994911#L1254 assume !false; 994904#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 992760#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 992750#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 992748#L1053 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 992745#L1067 assume !(0 != eval_~tmp~0#1); 992746#L1269 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 995945#L895-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 995943#L1279-3 assume !(0 == ~M_E~0); 995941#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 995940#L1284-3 assume !(0 == ~T2_E~0); 995938#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 995936#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 995934#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 995932#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 995930#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 995927#L1314-3 assume !(0 == ~T8_E~0); 995925#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 995923#L1324-3 assume !(0 == ~T10_E~0); 995921#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 995919#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 995917#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 995914#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 995912#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 995910#L1354-3 assume !(0 == ~E_2~0); 995908#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 995906#L1364-3 assume !(0 == ~E_4~0); 995904#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 995901#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 995899#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 995897#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 995895#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 995893#L1394-3 assume !(0 == ~E_10~0); 995891#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 995888#L1404-3 assume !(0 == ~E_12~0); 995886#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 995884#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995882#L628-45 assume !(1 == ~m_pc~0); 995880#L628-47 is_master_triggered_~__retres1~0#1 := 0; 995879#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 995878#L640-15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 995877#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 995876#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 995875#L647-45 assume !(1 == ~t1_pc~0); 995874#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 995873#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 995872#L659-15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 995871#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 995870#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995868#L666-45 assume !(1 == ~t2_pc~0); 995867#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 995866#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995865#L678-15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 995864#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 995863#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 995862#L685-45 assume 1 == ~t3_pc~0; 995861#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 995859#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 995857#L697-15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 995854#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 995853#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 995852#L704-45 assume !(1 == ~t4_pc~0); 995851#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 995850#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995848#L716-15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 995847#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 995846#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 995845#L723-45 assume !(1 == ~t5_pc~0); 995844#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 995842#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 995841#L735-15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 995839#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 995837#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 995835#L742-45 assume !(1 == ~t6_pc~0); 995833#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 995831#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 995829#L754-15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 995827#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 995826#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 995824#L761-45 assume !(1 == ~t7_pc~0); 995822#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 995819#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 995817#L773-15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 995814#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 995812#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 995810#L780-45 assume !(1 == ~t8_pc~0); 995808#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 995806#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 995804#L792-15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 995800#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 995798#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 995796#L799-45 assume !(1 == ~t9_pc~0); 995794#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 995791#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 995789#L811-15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 995787#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 995785#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 995783#L818-45 assume !(1 == ~t10_pc~0); 995781#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 995778#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 995776#L830-15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 995774#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 995771#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 995769#L837-45 assume 1 == ~t11_pc~0; 995767#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 995764#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 995762#L849-15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 995760#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 995758#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 995756#L856-45 assume !(1 == ~t12_pc~0); 995754#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 995751#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 995749#L868-15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 995747#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 995744#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 995742#L875-45 assume 1 == ~t13_pc~0; 995740#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 995737#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 995735#L887-15 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 995733#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 995730#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 995438#L1427-3 assume !(1 == ~M_E~0); 995435#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 995433#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 995431#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 995429#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 995427#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 995425#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 995422#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 995420#L1462-3 assume !(1 == ~T8_E~0); 995418#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 995416#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 995414#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 995411#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 995409#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 995407#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 995405#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 995403#L1502-3 assume !(1 == ~E_2~0); 995401#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 995399#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 995397#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 995395#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 995393#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 995391#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 995389#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 995387#L1542-3 assume !(1 == ~E_10~0); 995385#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 995383#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 995381#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 995379#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 995373#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 995359#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 995357#L1053-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 995263#L1947 assume !(0 == start_simulation_~tmp~3#1); 995256#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 994948#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 994933#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 994931#L1053-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 994929#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 994927#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 994925#L1910 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 994923#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 827768#L1928-2 [2022-11-21 13:42:25,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:25,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2022-11-21 13:42:25,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:25,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684353170] [2022-11-21 13:42:25,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:25,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:25,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:25,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:25,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:25,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684353170] [2022-11-21 13:42:25,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1684353170] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:25,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:25,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:25,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089376184] [2022-11-21 13:42:25,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:25,652 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-21 13:42:25,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-21 13:42:25,653 INFO L85 PathProgramCache]: Analyzing trace with hash 1728383979, now seen corresponding path program 1 times [2022-11-21 13:42:25,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-21 13:42:25,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72717985] [2022-11-21 13:42:25,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-21 13:42:25,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-21 13:42:25,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-21 13:42:25,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-21 13:42:25,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-21 13:42:25,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72717985] [2022-11-21 13:42:25,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72717985] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-21 13:42:25,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-21 13:42:25,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-21 13:42:25,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235980610] [2022-11-21 13:42:25,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-21 13:42:25,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-21 13:42:25,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-21 13:42:25,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-21 13:42:25,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-21 13:42:25,722 INFO L87 Difference]: Start difference. First operand 303172 states and 427085 transitions. cyclomatic complexity: 123945 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-21 13:42:29,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-21 13:42:29,253 INFO L93 Difference]: Finished difference Result 709361 states and 1009908 transitions. [2022-11-21 13:42:29,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 709361 states and 1009908 transitions. [2022-11-21 13:42:33,641 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 707004 [2022-11-21 13:42:35,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 709361 states to 709361 states and 1009908 transitions. [2022-11-21 13:42:35,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 709361 [2022-11-21 13:42:36,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 709361 [2022-11-21 13:42:36,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 709361 states and 1009908 transitions. [2022-11-21 13:42:36,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-21 13:42:36,471 INFO L218 hiAutomatonCegarLoop]: Abstraction has 709361 states and 1009908 transitions. [2022-11-21 13:42:36,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709361 states and 1009908 transitions. [2022-11-21 13:42:40,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709361 to 310819. [2022-11-21 13:42:40,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 310819 states, 310819 states have (on average 1.3986661047104585) internal successors, (434732), 310818 states have internal predecessors, (434732), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)