./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu2.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-25 17:58:13,549 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-25 17:58:13,552 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-25 17:58:13,596 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-25 17:58:13,596 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-25 17:58:13,600 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-25 17:58:13,603 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-25 17:58:13,604 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-25 17:58:13,606 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-25 17:58:13,607 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-25 17:58:13,608 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-25 17:58:13,609 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-25 17:58:13,609 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-25 17:58:13,611 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-25 17:58:13,612 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-25 17:58:13,613 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-25 17:58:13,614 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-25 17:58:13,617 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-25 17:58:13,619 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-25 17:58:13,621 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-25 17:58:13,623 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-25 17:58:13,624 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-25 17:58:13,625 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-25 17:58:13,626 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-25 17:58:13,630 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-25 17:58:13,630 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-25 17:58:13,631 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-25 17:58:13,632 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-25 17:58:13,632 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-25 17:58:13,633 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-25 17:58:13,634 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-25 17:58:13,635 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-25 17:58:13,635 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-25 17:58:13,652 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-25 17:58:13,653 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-25 17:58:13,653 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-25 17:58:13,654 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-25 17:58:13,654 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-25 17:58:13,654 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-25 17:58:13,655 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-25 17:58:13,656 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-25 17:58:13,657 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-25 17:58:13,688 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-25 17:58:13,692 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-25 17:58:13,694 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-25 17:58:13,694 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-25 17:58:13,695 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-25 17:58:13,696 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-25 17:58:13,696 INFO L138 SettingsManager]: * Use SBE=true [2022-11-25 17:58:13,696 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-25 17:58:13,696 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-25 17:58:13,697 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-25 17:58:13,698 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-25 17:58:13,698 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-25 17:58:13,698 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-25 17:58:13,699 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-25 17:58:13,699 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-25 17:58:13,699 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-25 17:58:13,699 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-25 17:58:13,699 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-25 17:58:13,700 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-25 17:58:13,700 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-25 17:58:13,700 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-25 17:58:13,700 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-25 17:58:13,701 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-25 17:58:13,701 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-25 17:58:13,701 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-25 17:58:13,701 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-25 17:58:13,702 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-25 17:58:13,702 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-25 17:58:13,702 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-25 17:58:13,703 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-25 17:58:13,703 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-25 17:58:13,705 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-25 17:58:13,705 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2022-11-25 17:58:14,083 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-25 17:58:14,115 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-25 17:58:14,118 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-25 17:58:14,119 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-25 17:58:14,120 INFO L275 PluginConnector]: CDTParser initialized [2022-11-25 17:58:14,121 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/../../sv-benchmarks/c/systemc/kundu2.cil.c [2022-11-25 17:58:17,269 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-25 17:58:17,500 INFO L351 CDTParser]: Found 1 translation units. [2022-11-25 17:58:17,500 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/sv-benchmarks/c/systemc/kundu2.cil.c [2022-11-25 17:58:17,510 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/data/e4c4a46b4/9d13f4b7f5cc4b129574fd1a39295189/FLAG61991796e [2022-11-25 17:58:17,528 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/data/e4c4a46b4/9d13f4b7f5cc4b129574fd1a39295189 [2022-11-25 17:58:17,531 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-25 17:58:17,532 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-25 17:58:17,534 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-25 17:58:17,535 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-25 17:58:17,539 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-25 17:58:17,540 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:58:17" (1/1) ... [2022-11-25 17:58:17,541 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@482b5cec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:17, skipping insertion in model container [2022-11-25 17:58:17,541 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:58:17" (1/1) ... [2022-11-25 17:58:17,550 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-25 17:58:17,578 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-25 17:58:17,821 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2022-11-25 17:58:17,929 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:58:17,949 INFO L203 MainTranslator]: Completed pre-run [2022-11-25 17:58:17,964 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/sv-benchmarks/c/systemc/kundu2.cil.c[636,649] [2022-11-25 17:58:17,991 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:58:18,007 INFO L208 MainTranslator]: Completed translation [2022-11-25 17:58:18,007 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18 WrapperNode [2022-11-25 17:58:18,008 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-25 17:58:18,009 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-25 17:58:18,009 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-25 17:58:18,009 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-25 17:58:18,017 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,026 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,057 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 529 [2022-11-25 17:58:18,057 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-25 17:58:18,058 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-25 17:58:18,058 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-25 17:58:18,059 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-25 17:58:18,071 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,075 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,078 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,088 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,094 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,113 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,116 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,117 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,121 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-25 17:58:18,136 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-25 17:58:18,136 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-25 17:58:18,136 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-25 17:58:18,137 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (1/1) ... [2022-11-25 17:58:18,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-25 17:58:18,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 17:58:18,180 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-25 17:58:18,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-25 17:58:18,239 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-25 17:58:18,240 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-25 17:58:18,240 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-25 17:58:18,241 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-25 17:58:18,374 INFO L235 CfgBuilder]: Building ICFG [2022-11-25 17:58:18,377 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-25 17:58:18,953 INFO L276 CfgBuilder]: Performing block encoding [2022-11-25 17:58:18,963 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-25 17:58:18,963 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-11-25 17:58:18,966 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:58:18 BoogieIcfgContainer [2022-11-25 17:58:18,966 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-25 17:58:18,968 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-25 17:58:18,968 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-25 17:58:18,972 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-25 17:58:18,973 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:58:18,974 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 05:58:17" (1/3) ... [2022-11-25 17:58:18,975 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5544bbb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:58:18, skipping insertion in model container [2022-11-25 17:58:18,975 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:58:18,975 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:58:18" (2/3) ... [2022-11-25 17:58:18,976 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5544bbb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:58:18, skipping insertion in model container [2022-11-25 17:58:18,976 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:58:18,976 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:58:18" (3/3) ... [2022-11-25 17:58:18,978 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2022-11-25 17:58:19,049 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-25 17:58:19,049 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-25 17:58:19,050 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-25 17:58:19,050 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-25 17:58:19,050 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-25 17:58:19,050 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-25 17:58:19,050 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-25 17:58:19,051 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-25 17:58:19,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:19,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2022-11-25 17:58:19,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:19,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:19,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,100 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-25 17:58:19,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:19,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 153 [2022-11-25 17:58:19,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:19,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:19,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,121 INFO L748 eck$LassoCheckResult]: Stem: 175#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 69#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 97#L599true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62#L297true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 149#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 143#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 34#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 91#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35#L423true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 9#L117true assume !(1 == ~P_1_pc~0); 41#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 86#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 170#L129true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 53#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 130#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 150#L185true assume 1 == ~P_2_pc~0; 101#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 102#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 117#L197true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 144#L485true assume !(0 != activate_threads_~tmp___0~1#1); 10#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 43#L267true assume 1 == ~C_1_pc~0; 39#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 49#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 64#L289true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27#L493true assume !(0 != activate_threads_~tmp___1~1#1); 93#L493-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182#L431true assume { :end_inline_reset_delta_events } true; 81#L547-2true [2022-11-25 17:58:19,123 INFO L750 eck$LassoCheckResult]: Loop: 81#L547-2true assume !false; 98#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 138#L396true assume !true; 94#L412true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L297-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99#L423-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 65#L117-6true assume !(1 == ~P_1_pc~0); 70#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 188#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 22#L129-2true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 44#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 104#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 71#L185-6true assume 1 == ~P_2_pc~0; 14#L186-2true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 180#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 160#L197-2true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 179#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 131#L267-6true assume 1 == ~C_1_pc~0; 152#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 79#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 24#L289-2true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 80#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 57#L493-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8#L431-1true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 162#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 164#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 125#L345-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 165#L566true assume !(0 == start_simulation_~tmp~3#1); 75#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 66#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 121#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 171#L345-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 142#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137#L529true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 18#L579true assume !(0 != start_simulation_~tmp___0~2#1); 81#L547-2true [2022-11-25 17:58:19,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:19,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2022-11-25 17:58:19,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:19,142 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348575359] [2022-11-25 17:58:19,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:19,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:19,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:19,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:19,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:19,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348575359] [2022-11-25 17:58:19,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348575359] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:19,382 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:19,383 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:19,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637955580] [2022-11-25 17:58:19,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:19,392 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:19,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:19,396 INFO L85 PathProgramCache]: Analyzing trace with hash -224400385, now seen corresponding path program 1 times [2022-11-25 17:58:19,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:19,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664498386] [2022-11-25 17:58:19,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:19,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:19,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:19,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:19,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:19,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664498386] [2022-11-25 17:58:19,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664498386] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:19,476 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:19,476 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:58:19,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880328705] [2022-11-25 17:58:19,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:19,478 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:19,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:19,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:19,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:19,529 INFO L87 Difference]: Start difference. First operand has 190 states, 189 states have (on average 1.5026455026455026) internal successors, (284), 189 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:19,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:19,608 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2022-11-25 17:58:19,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2022-11-25 17:58:19,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-11-25 17:58:19,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2022-11-25 17:58:19,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2022-11-25 17:58:19,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2022-11-25 17:58:19,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2022-11-25 17:58:19,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:19,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-11-25 17:58:19,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2022-11-25 17:58:19,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2022-11-25 17:58:19,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:19,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2022-11-25 17:58:19,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-11-25 17:58:19,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:19,702 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2022-11-25 17:58:19,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-25 17:58:19,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2022-11-25 17:58:19,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-11-25 17:58:19,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:19,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:19,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:19,717 INFO L748 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 499#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 500#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 490#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 491#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 554#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 453#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 454#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 455#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 401#L117 assume !(1 == ~P_1_pc~0); 402#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 464#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 521#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 479#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 480#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 549#L185 assume 1 == ~P_2_pc~0; 530#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 508#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 531#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 541#L485 assume !(0 != activate_threads_~tmp___0~1#1); 406#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 407#L267 assume 1 == ~C_1_pc~0; 460#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 461#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 478#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 444#L493 assume !(0 != activate_threads_~tmp___1~1#1); 445#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 524#L431 assume { :end_inline_reset_delta_events } true; 425#L547-2 [2022-11-25 17:58:19,721 INFO L750 eck$LassoCheckResult]: Loop: 425#L547-2 assume !false; 517#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 527#L396 assume !false; 522#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 456#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 418#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 482#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 542#L361 assume !(0 != eval_~tmp___2~0#1); 525#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 488#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 489#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 494#L117-6 assume 1 == ~P_1_pc~0; 496#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 501#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 433#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 434#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 465#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 502#L185-6 assume !(1 == ~P_2_pc~0); 416#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 415#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 560#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 513#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 514#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 550#L267-6 assume 1 == ~C_1_pc~0; 551#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 386#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 437#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 438#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 484#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 400#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 475#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 545#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 546#L566 assume !(0 == start_simulation_~tmp~3#1); 509#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 492#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 486#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 544#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 553#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 505#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 506#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 424#L579 assume !(0 != start_simulation_~tmp___0~2#1); 425#L547-2 [2022-11-25 17:58:19,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:19,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2022-11-25 17:58:19,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:19,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600528991] [2022-11-25 17:58:19,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:19,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:19,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:19,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:19,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:19,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600528991] [2022-11-25 17:58:19,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600528991] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:19,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:19,824 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:19,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785846387] [2022-11-25 17:58:19,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:19,825 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:19,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:19,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1683132646, now seen corresponding path program 1 times [2022-11-25 17:58:19,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:19,829 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285144914] [2022-11-25 17:58:19,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:19,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:19,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285144914] [2022-11-25 17:58:20,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285144914] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:20,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206835575] [2022-11-25 17:58:20,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,021 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:20,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:20,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:20,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:20,022 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:20,056 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2022-11-25 17:58:20,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2022-11-25 17:58:20,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-11-25 17:58:20,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2022-11-25 17:58:20,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2022-11-25 17:58:20,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2022-11-25 17:58:20,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2022-11-25 17:58:20,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:20,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-11-25 17:58:20,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2022-11-25 17:58:20,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2022-11-25 17:58:20,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2022-11-25 17:58:20,073 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-11-25 17:58:20,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:20,074 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2022-11-25 17:58:20,074 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-25 17:58:20,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2022-11-25 17:58:20,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2022-11-25 17:58:20,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:20,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:20,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,080 INFO L748 eck$LassoCheckResult]: Stem: 927#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 865#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 856#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 919#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 817#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 818#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 819#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 766#L117 assume !(1 == ~P_1_pc~0); 767#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 829#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 885#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 844#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 845#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 914#L185 assume 1 == ~P_2_pc~0; 894#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 873#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 895#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 906#L485 assume !(0 != activate_threads_~tmp___0~1#1); 769#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 770#L267 assume 1 == ~C_1_pc~0; 825#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 826#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 838#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 809#L493 assume !(0 != activate_threads_~tmp___1~1#1); 810#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 889#L431 assume { :end_inline_reset_delta_events } true; 790#L547-2 [2022-11-25 17:58:20,080 INFO L750 eck$LassoCheckResult]: Loop: 790#L547-2 assume !false; 880#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 892#L396 assume !false; 887#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 821#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 783#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 847#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 907#L361 assume !(0 != eval_~tmp___2~0#1); 890#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 852#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 853#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 857#L117-6 assume !(1 == ~P_1_pc~0); 858#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 866#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 798#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 799#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 830#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 867#L185-6 assume 1 == ~P_2_pc~0; 779#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 780#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 925#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 878#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 879#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 915#L267-6 assume 1 == ~C_1_pc~0; 916#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 754#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 802#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 803#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 849#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 764#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 765#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 841#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 910#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 911#L566 assume !(0 == start_simulation_~tmp~3#1); 874#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 860#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 851#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 909#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 918#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 870#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 871#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 789#L579 assume !(0 != start_simulation_~tmp___0~2#1); 790#L547-2 [2022-11-25 17:58:20,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2022-11-25 17:58:20,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075550008] [2022-11-25 17:58:20,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075550008] [2022-11-25 17:58:20,221 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075550008] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,221 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,222 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:20,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465019444] [2022-11-25 17:58:20,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,222 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:20,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1396999590, now seen corresponding path program 1 times [2022-11-25 17:58:20,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479319473] [2022-11-25 17:58:20,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479319473] [2022-11-25 17:58:20,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479319473] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:20,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528354479] [2022-11-25 17:58:20,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,347 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:20,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:20,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:58:20,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:58:20,349 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:20,531 INFO L93 Difference]: Finished difference Result 480 states and 697 transitions. [2022-11-25 17:58:20,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 697 transitions. [2022-11-25 17:58:20,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2022-11-25 17:58:20,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 697 transitions. [2022-11-25 17:58:20,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2022-11-25 17:58:20,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2022-11-25 17:58:20,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 697 transitions. [2022-11-25 17:58:20,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:20,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 480 states and 697 transitions. [2022-11-25 17:58:20,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 697 transitions. [2022-11-25 17:58:20,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 190. [2022-11-25 17:58:20,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2022-11-25 17:58:20,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2022-11-25 17:58:20,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:58:20,552 INFO L428 stractBuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2022-11-25 17:58:20,552 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-25 17:58:20,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2022-11-25 17:58:20,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-11-25 17:58:20,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:20,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:20,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,555 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,555 INFO L748 eck$LassoCheckResult]: Stem: 1611#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1539#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1529#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1530#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1599#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1491#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1492#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1493#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1439#L117 assume !(1 == ~P_1_pc~0); 1440#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1502#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1560#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1518#L477 assume !(0 != activate_threads_~tmp~1#1); 1519#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1591#L185 assume 1 == ~P_2_pc~0; 1570#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1547#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1571#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1583#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1444#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1445#L267 assume 1 == ~C_1_pc~0; 1498#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1499#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1517#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1482#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1483#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1565#L431 assume { :end_inline_reset_delta_events } true; 1463#L547-2 [2022-11-25 17:58:20,555 INFO L750 eck$LassoCheckResult]: Loop: 1463#L547-2 assume !false; 1556#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1567#L396 assume !false; 1561#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1494#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1456#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1521#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1581#L361 assume !(0 != eval_~tmp___2~0#1); 1564#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1526#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1527#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1531#L117-6 assume !(1 == ~P_1_pc~0); 1532#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 1540#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1612#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1503#L477-6 assume !(0 != activate_threads_~tmp~1#1); 1504#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1541#L185-6 assume 1 == ~P_2_pc~0; 1452#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1453#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1607#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1552#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1553#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1592#L267-6 assume 1 == ~C_1_pc~0; 1593#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1427#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1475#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1476#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1523#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1438#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1514#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1586#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1587#L566 assume !(0 == start_simulation_~tmp~3#1); 1548#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1534#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1525#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1584#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1598#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1544#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1545#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1462#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1463#L547-2 [2022-11-25 17:58:20,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,556 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2022-11-25 17:58:20,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364429551] [2022-11-25 17:58:20,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364429551] [2022-11-25 17:58:20,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364429551] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,608 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 17:58:20,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657682248] [2022-11-25 17:58:20,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,609 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:20,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,609 INFO L85 PathProgramCache]: Analyzing trace with hash 526228444, now seen corresponding path program 1 times [2022-11-25 17:58:20,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880593778] [2022-11-25 17:58:20,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880593778] [2022-11-25 17:58:20,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880593778] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,660 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:20,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401849711] [2022-11-25 17:58:20,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,661 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:20,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:20,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:58:20,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:58:20,662 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:20,751 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2022-11-25 17:58:20,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2022-11-25 17:58:20,755 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2022-11-25 17:58:20,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2022-11-25 17:58:20,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2022-11-25 17:58:20,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2022-11-25 17:58:20,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2022-11-25 17:58:20,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:20,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 665 transitions. [2022-11-25 17:58:20,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2022-11-25 17:58:20,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2022-11-25 17:58:20,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:20,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2022-11-25 17:58:20,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 610 transitions. [2022-11-25 17:58:20,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:58:20,777 INFO L428 stractBuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2022-11-25 17:58:20,778 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-25 17:58:20,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2022-11-25 17:58:20,780 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2022-11-25 17:58:20,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:20,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:20,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,781 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:20,782 INFO L748 eck$LassoCheckResult]: Stem: 2288#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2216#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2207#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2208#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2280#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2167#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2168#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2169#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2115#L117 assume !(1 == ~P_1_pc~0); 2116#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2179#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2238#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2195#L477 assume !(0 != activate_threads_~tmp~1#1); 2196#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2272#L185 assume !(1 == ~P_2_pc~0); 2224#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 2225#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2252#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2263#L485 assume !(0 != activate_threads_~tmp___0~1#1); 2117#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2118#L267 assume 1 == ~C_1_pc~0; 2175#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2176#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2190#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2156#L493 assume !(0 != activate_threads_~tmp___1~1#1); 2157#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2246#L431 assume { :end_inline_reset_delta_events } true; 2138#L547-2 [2022-11-25 17:58:20,782 INFO L750 eck$LassoCheckResult]: Loop: 2138#L547-2 assume !false; 2232#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2250#L396 assume !false; 2241#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2171#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2131#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2199#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2264#L361 assume !(0 != eval_~tmp___2~0#1); 2247#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2204#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2205#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2209#L117-6 assume !(1 == ~P_1_pc~0); 2210#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 2217#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2145#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2146#L477-6 assume !(0 != activate_threads_~tmp~1#1); 2180#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2218#L185-6 assume !(1 == ~P_2_pc~0); 2219#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 2249#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2286#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2230#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2231#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2273#L267-6 assume 1 == ~C_1_pc~0; 2274#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2105#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2151#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2152#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2201#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2113#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2114#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2193#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2268#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2269#L566 assume !(0 == start_simulation_~tmp~3#1); 2226#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2211#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2203#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2266#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2279#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2222#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2223#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2137#L579 assume !(0 != start_simulation_~tmp___0~2#1); 2138#L547-2 [2022-11-25 17:58:20,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,783 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2022-11-25 17:58:20,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910199175] [2022-11-25 17:58:20,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910199175] [2022-11-25 17:58:20,833 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910199175] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,833 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,833 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 17:58:20,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673671463] [2022-11-25 17:58:20,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,834 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:20,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:20,834 INFO L85 PathProgramCache]: Analyzing trace with hash -1531375587, now seen corresponding path program 1 times [2022-11-25 17:58:20,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:20,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961411420] [2022-11-25 17:58:20,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:20,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:20,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:20,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:20,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:20,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961411420] [2022-11-25 17:58:20,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961411420] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:20,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:20,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:20,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292423634] [2022-11-25 17:58:20,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:20,884 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:20,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:20,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:58:20,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:58:20,885 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:21,067 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2022-11-25 17:58:21,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2022-11-25 17:58:21,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2022-11-25 17:58:21,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2022-11-25 17:58:21,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2022-11-25 17:58:21,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2022-11-25 17:58:21,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2022-11-25 17:58:21,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:21,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2022-11-25 17:58:21,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2022-11-25 17:58:21,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2022-11-25 17:58:21,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2022-11-25 17:58:21,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2022-11-25 17:58:21,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:58:21,153 INFO L428 stractBuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2022-11-25 17:58:21,153 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-25 17:58:21,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2022-11-25 17:58:21,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2022-11-25 17:58:21,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:21,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:21,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,162 INFO L748 eck$LassoCheckResult]: Stem: 3932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3842#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3831#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3832#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3915#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3793#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3794#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3795#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3740#L117 assume !(1 == ~P_1_pc~0); 3741#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3802#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3863#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3818#L477 assume !(0 != activate_threads_~tmp~1#1); 3819#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3908#L185 assume !(1 == ~P_2_pc~0); 3850#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3851#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3880#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3895#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3742#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3743#L267 assume !(1 == ~C_1_pc~0); 3803#L267-2 assume 2 == ~C_1_pc~0; 3910#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3812#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3813#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3781#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3782#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3874#L431 assume { :end_inline_reset_delta_events } true; 3933#L547-2 [2022-11-25 17:58:21,163 INFO L750 eck$LassoCheckResult]: Loop: 3933#L547-2 assume !false; 4614#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4612#L396 assume !false; 4611#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4608#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4605#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4603#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4601#L361 assume !(0 != eval_~tmp___2~0#1); 3875#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3827#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3828#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3833#L117-6 assume !(1 == ~P_1_pc~0); 3834#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 3843#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3770#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3771#L477-6 assume !(0 != activate_threads_~tmp~1#1); 3804#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3844#L185-6 assume !(1 == ~P_2_pc~0); 3845#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 3877#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3927#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3856#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 3857#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3909#L267-6 assume !(1 == ~C_1_pc~0); 3883#L267-8 assume 2 == ~C_1_pc~0; 3729#L278-2 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3730#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3774#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3775#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 3824#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3738#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3739#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3815#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3928#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4642#L566 assume !(0 == start_simulation_~tmp~3#1); 4637#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4632#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4628#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4624#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4622#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4620#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4618#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4617#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3933#L547-2 [2022-11-25 17:58:21,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,164 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2022-11-25 17:58:21,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447079131] [2022-11-25 17:58:21,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:21,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:21,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:21,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447079131] [2022-11-25 17:58:21,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447079131] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:21,237 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:21,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:21,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769517069] [2022-11-25 17:58:21,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:21,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:21,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,239 INFO L85 PathProgramCache]: Analyzing trace with hash 221061876, now seen corresponding path program 1 times [2022-11-25 17:58:21,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179193329] [2022-11-25 17:58:21,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:21,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:21,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:21,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179193329] [2022-11-25 17:58:21,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179193329] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:21,358 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:21,359 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:21,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464489761] [2022-11-25 17:58:21,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:21,359 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:21,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:21,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:21,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:21,360 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:21,422 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2022-11-25 17:58:21,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2022-11-25 17:58:21,437 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2022-11-25 17:58:21,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2022-11-25 17:58:21,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2022-11-25 17:58:21,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2022-11-25 17:58:21,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2022-11-25 17:58:21,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:21,452 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2022-11-25 17:58:21,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2022-11-25 17:58:21,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2022-11-25 17:58:21,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2022-11-25 17:58:21,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2022-11-25 17:58:21,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:21,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2022-11-25 17:58:21,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-25 17:58:21,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2022-11-25 17:58:21,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2022-11-25 17:58:21,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:21,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:21,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,493 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,493 INFO L748 eck$LassoCheckResult]: Stem: 6559#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6462#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6447#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6448#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6540#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6408#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6409#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6410#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6357#L117 assume !(1 == ~P_1_pc~0); 6358#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6417#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6487#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6435#L477 assume !(0 != activate_threads_~tmp~1#1); 6436#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6531#L185 assume !(1 == ~P_2_pc~0); 6470#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6471#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6501#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6516#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6359#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6360#L267 assume !(1 == ~C_1_pc~0); 6418#L267-2 assume !(2 == ~C_1_pc~0); 6500#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6430#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6431#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6397#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6398#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6496#L431 assume { :end_inline_reset_delta_events } true; 6560#L547-2 [2022-11-25 17:58:21,494 INFO L750 eck$LassoCheckResult]: Loop: 6560#L547-2 assume !false; 7640#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7638#L396 assume !false; 7635#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7631#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7627#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7624#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7620#L361 assume !(0 != eval_~tmp___2~0#1); 6497#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6444#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6445#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6454#L117-6 assume !(1 == ~P_1_pc~0); 6455#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 6463#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6564#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6419#L477-6 assume !(0 != activate_threads_~tmp~1#1); 6420#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6464#L185-6 assume !(1 == ~P_2_pc~0); 6465#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 7764#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7762#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7761#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7750#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7749#L267-6 assume !(1 == ~C_1_pc~0); 7748#L267-8 assume !(2 == ~C_1_pc~0); 7746#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 7744#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7726#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6480#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6441#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6355#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6356#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6433#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6524#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6525#L566 assume !(0 == start_simulation_~tmp~3#1); 6472#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6452#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6443#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6520#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7650#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7649#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7648#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7646#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6560#L547-2 [2022-11-25 17:58:21,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2022-11-25 17:58:21,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928545968] [2022-11-25 17:58:21,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:21,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:21,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:21,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:21,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1212226549, now seen corresponding path program 1 times [2022-11-25 17:58:21,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554906456] [2022-11-25 17:58:21,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:21,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:21,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:21,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554906456] [2022-11-25 17:58:21,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554906456] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:21,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:21,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:58:21,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536819494] [2022-11-25 17:58:21,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:21,652 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:21,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:21,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:58:21,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:58:21,653 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:21,761 INFO L93 Difference]: Finished difference Result 2589 states and 3511 transitions. [2022-11-25 17:58:21,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2589 states and 3511 transitions. [2022-11-25 17:58:21,782 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2524 [2022-11-25 17:58:21,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2589 states to 2589 states and 3511 transitions. [2022-11-25 17:58:21,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2589 [2022-11-25 17:58:21,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2589 [2022-11-25 17:58:21,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2589 states and 3511 transitions. [2022-11-25 17:58:21,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:21,805 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2589 states and 3511 transitions. [2022-11-25 17:58:21,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2589 states and 3511 transitions. [2022-11-25 17:58:21,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2589 to 1500. [2022-11-25 17:58:21,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2022-11-25 17:58:21,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2022-11-25 17:58:21,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-25 17:58:21,864 INFO L428 stractBuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2022-11-25 17:58:21,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-25 17:58:21,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2022-11-25 17:58:21,878 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2022-11-25 17:58:21,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:21,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:21,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:21,880 INFO L748 eck$LassoCheckResult]: Stem: 10639#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10535#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10520#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10521#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10621#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10480#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10481#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10482#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10426#L117 assume !(1 == ~P_1_pc~0); 10427#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 10488#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10564#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10506#L477 assume !(0 != activate_threads_~tmp~1#1); 10507#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10613#L185 assume !(1 == ~P_2_pc~0); 10544#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 10545#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10583#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10604#L485 assume !(0 != activate_threads_~tmp___0~1#1); 10431#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10432#L267 assume !(1 == ~C_1_pc~0); 10491#L267-2 assume !(2 == ~C_1_pc~0); 10580#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 10504#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10505#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10467#L493 assume !(0 != activate_threads_~tmp___1~1#1); 10468#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10574#L431 assume { :end_inline_reset_delta_events } true; 10450#L547-2 [2022-11-25 17:58:21,880 INFO L750 eck$LassoCheckResult]: Loop: 10450#L547-2 assume !false; 10558#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10579#L396 assume !false; 10619#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11796#L327 assume !(0 == ~P_1_st~0); 11789#L331 assume !(0 == ~P_2_st~0); 11786#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11784#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11783#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11583#L361 assume !(0 != eval_~tmp___2~0#1); 10572#L412 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10573#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10577#L423-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10578#L117-6 assume !(1 == ~P_1_pc~0); 10536#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 10537#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10456#L129-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10457#L477-6 assume !(0 != activate_threads_~tmp~1#1); 10584#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10585#L185-6 assume !(1 == ~P_2_pc~0); 11909#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 10643#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10644#L197-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10552#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10553#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10642#L267-6 assume !(1 == ~C_1_pc~0); 10588#L267-8 assume !(2 == ~C_1_pc~0); 10589#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10551#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10460#L289-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10461#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10513#L493-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10514#L431-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11906#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11839#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11838#L345-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11836#L566 assume !(0 == start_simulation_~tmp~3#1); 11834#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10527#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10516#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10605#L345-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10620#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10542#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10543#L529 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10449#L579 assume !(0 != start_simulation_~tmp___0~2#1); 10450#L547-2 [2022-11-25 17:58:21,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2022-11-25 17:58:21,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803002931] [2022-11-25 17:58:21,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:21,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:21,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:21,899 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:21,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:21,900 INFO L85 PathProgramCache]: Analyzing trace with hash 1972558684, now seen corresponding path program 1 times [2022-11-25 17:58:21,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:21,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794039193] [2022-11-25 17:58:21,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:21,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:21,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:21,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:21,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:21,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794039193] [2022-11-25 17:58:21,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794039193] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:21,927 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:21,928 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:21,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292453185] [2022-11-25 17:58:21,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:21,928 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:58:21,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:21,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:21,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:21,929 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:21,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:21,974 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2022-11-25 17:58:21,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2022-11-25 17:58:21,993 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2022-11-25 17:58:22,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2022-11-25 17:58:22,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2022-11-25 17:58:22,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2022-11-25 17:58:22,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2022-11-25 17:58:22,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:22,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-11-25 17:58:22,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2022-11-25 17:58:22,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2022-11-25 17:58:22,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:22,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2022-11-25 17:58:22,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-11-25 17:58:22,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:22,051 INFO L428 stractBuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2022-11-25 17:58:22,051 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-25 17:58:22,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2022-11-25 17:58:22,063 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2022-11-25 17:58:22,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:22,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:22,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,065 INFO L748 eck$LassoCheckResult]: Stem: 14471#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14365#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14366#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14351#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14352#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14449#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14312#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14313#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14314#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14257#L117 assume !(1 == ~P_1_pc~0); 14258#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 14321#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14397#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14337#L477 assume !(0 != activate_threads_~tmp~1#1); 14338#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14440#L185 assume !(1 == ~P_2_pc~0); 14374#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 14375#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14411#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14429#L485 assume !(0 != activate_threads_~tmp___0~1#1); 14262#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14263#L267 assume !(1 == ~C_1_pc~0); 14323#L267-2 assume !(2 == ~C_1_pc~0); 14409#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 14335#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14336#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14298#L493 assume !(0 != activate_threads_~tmp___1~1#1); 14299#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14405#L431 assume { :end_inline_reset_delta_events } true; 14473#L547-2 assume !false; 16047#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 16045#L396 [2022-11-25 17:58:22,065 INFO L750 eck$LassoCheckResult]: Loop: 16045#L396 assume !false; 16044#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16043#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16041#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16040#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16038#L361 assume 0 != eval_~tmp___2~0#1; 16034#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16030#L370 assume !(0 != eval_~tmp~0#1); 16032#L366 assume !(0 == ~P_2_st~0); 16050#L381 assume !(0 == ~C_1_st~0); 16045#L396 [2022-11-25 17:58:22,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,065 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2022-11-25 17:58:22,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034061109] [2022-11-25 17:58:22,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,080 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:22,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,096 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:22,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,100 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2022-11-25 17:58:22,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234729564] [2022-11-25 17:58:22,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:22,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:22,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2022-11-25 17:58:22,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470884358] [2022-11-25 17:58:22,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:22,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:22,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:22,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470884358] [2022-11-25 17:58:22,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470884358] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:22,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:22,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:22,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885155841] [2022-11-25 17:58:22,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:22,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:22,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:22,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:22,291 INFO L87 Difference]: Start difference. First operand 2325 states and 3118 transitions. cyclomatic complexity: 800 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:22,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:22,357 INFO L93 Difference]: Finished difference Result 3877 states and 5120 transitions. [2022-11-25 17:58:22,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3877 states and 5120 transitions. [2022-11-25 17:58:22,397 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3725 [2022-11-25 17:58:22,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3877 states to 3877 states and 5120 transitions. [2022-11-25 17:58:22,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3877 [2022-11-25 17:58:22,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3877 [2022-11-25 17:58:22,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3877 states and 5120 transitions. [2022-11-25 17:58:22,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:22,426 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3877 states and 5120 transitions. [2022-11-25 17:58:22,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3877 states and 5120 transitions. [2022-11-25 17:58:22,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3877 to 3793. [2022-11-25 17:58:22,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3229633535460057) internal successors, (5018), 3792 states have internal predecessors, (5018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:22,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5018 transitions. [2022-11-25 17:58:22,531 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2022-11-25 17:58:22,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:22,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2022-11-25 17:58:22,533 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-25 17:58:22,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5018 transitions. [2022-11-25 17:58:22,551 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-11-25 17:58:22,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:22,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:22,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,552 INFO L748 eck$LassoCheckResult]: Stem: 20701#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20578#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20562#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20563#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20669#L304-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20670#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 20613#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20614#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 20467#L117 assume !(1 == ~P_1_pc~0); 20468#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 20604#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 20605#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20549#L477 assume !(0 != activate_threads_~tmp~1#1); 20550#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 20678#L185 assume !(1 == ~P_2_pc~0); 20679#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 20626#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 20627#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20671#L485 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20469#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20470#L267 assume !(1 == ~C_1_pc~0); 20661#L267-2 assume !(2 == ~C_1_pc~0); 20662#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 20543#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20544#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20506#L493 assume !(0 != activate_threads_~tmp___1~1#1); 20507#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20703#L431 assume { :end_inline_reset_delta_events } true; 20704#L547-2 assume !false; 23362#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 21817#L396 [2022-11-25 17:58:22,552 INFO L750 eck$LassoCheckResult]: Loop: 21817#L396 assume !false; 23358#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23355#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22021#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22022#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22011#L361 assume 0 != eval_~tmp___2~0#1; 22012#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22002#L370 assume !(0 != eval_~tmp~0#1); 22004#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 21825#L385 assume !(0 != eval_~tmp___0~0#1); 21818#L381 assume !(0 == ~C_1_st~0); 21817#L396 [2022-11-25 17:58:22,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,553 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2022-11-25 17:58:22,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958427000] [2022-11-25 17:58:22,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:22,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:22,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:22,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958427000] [2022-11-25 17:58:22,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958427000] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:22,574 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:22,574 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:58:22,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218925085] [2022-11-25 17:58:22,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:22,574 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:58:22,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 1 times [2022-11-25 17:58:22,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843777984] [2022-11-25 17:58:22,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,579 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:22,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:22,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:22,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:22,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:22,697 INFO L87 Difference]: Start difference. First operand 3793 states and 5018 transitions. cyclomatic complexity: 1232 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:22,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:22,721 INFO L93 Difference]: Finished difference Result 3768 states and 4990 transitions. [2022-11-25 17:58:22,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3768 states and 4990 transitions. [2022-11-25 17:58:22,744 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-11-25 17:58:22,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3768 states to 3768 states and 4990 transitions. [2022-11-25 17:58:22,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3768 [2022-11-25 17:58:22,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3768 [2022-11-25 17:58:22,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3768 states and 4990 transitions. [2022-11-25 17:58:22,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:22,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-11-25 17:58:22,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3768 states and 4990 transitions. [2022-11-25 17:58:22,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3768 to 3768. [2022-11-25 17:58:22,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3768 states, 3768 states have (on average 1.3243099787685775) internal successors, (4990), 3767 states have internal predecessors, (4990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:22,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 4990 transitions. [2022-11-25 17:58:22,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-11-25 17:58:22,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:22,863 INFO L428 stractBuchiCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2022-11-25 17:58:22,863 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-25 17:58:22,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3768 states and 4990 transitions. [2022-11-25 17:58:22,881 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2022-11-25 17:58:22,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:22,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:22,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:22,882 INFO L748 eck$LassoCheckResult]: Stem: 28243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28138#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28125#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28126#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28219#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28087#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28088#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28089#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28034#L117 assume !(1 == ~P_1_pc~0); 28035#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 28097#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28167#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28112#L477 assume !(0 != activate_threads_~tmp~1#1); 28113#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28210#L185 assume !(1 == ~P_2_pc~0); 28146#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 28147#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28183#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28201#L485 assume !(0 != activate_threads_~tmp___0~1#1); 28038#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28039#L267 assume !(1 == ~C_1_pc~0); 28099#L267-2 assume !(2 == ~C_1_pc~0); 28180#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 28110#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28111#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28073#L493 assume !(0 != activate_threads_~tmp___1~1#1); 28074#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28176#L431 assume { :end_inline_reset_delta_events } true; 28248#L547-2 assume !false; 31202#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29491#L396 [2022-11-25 17:58:22,882 INFO L750 eck$LassoCheckResult]: Loop: 29491#L396 assume !false; 31198#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31195#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31193#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31191#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31189#L361 assume 0 != eval_~tmp___2~0#1; 31187#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31185#L370 assume !(0 != eval_~tmp~0#1); 30647#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30645#L385 assume !(0 != eval_~tmp___0~0#1); 29493#L381 assume !(0 == ~C_1_st~0); 29491#L396 [2022-11-25 17:58:22,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,882 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2022-11-25 17:58:22,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413303224] [2022-11-25 17:58:22,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,904 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:22,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:22,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 2 times [2022-11-25 17:58:22,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680526111] [2022-11-25 17:58:22,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:22,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:22,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:22,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:22,939 INFO L85 PathProgramCache]: Analyzing trace with hash 940874940, now seen corresponding path program 1 times [2022-11-25 17:58:22,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:22,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791665561] [2022-11-25 17:58:22,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:22,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:22,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:58:22,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:58:22,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:58:22,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791665561] [2022-11-25 17:58:22,971 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791665561] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:58:22,971 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:58:22,971 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:58:22,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141394689] [2022-11-25 17:58:22,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:58:23,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:58:23,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:58:23,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:58:23,070 INFO L87 Difference]: Start difference. First operand 3768 states and 4990 transitions. cyclomatic complexity: 1229 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:23,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:58:23,178 INFO L93 Difference]: Finished difference Result 6578 states and 8632 transitions. [2022-11-25 17:58:23,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6578 states and 8632 transitions. [2022-11-25 17:58:23,216 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2022-11-25 17:58:23,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6578 states to 6578 states and 8632 transitions. [2022-11-25 17:58:23,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6578 [2022-11-25 17:58:23,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6578 [2022-11-25 17:58:23,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6578 states and 8632 transitions. [2022-11-25 17:58:23,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:58:23,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-11-25 17:58:23,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6578 states and 8632 transitions. [2022-11-25 17:58:23,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6578 to 6578. [2022-11-25 17:58:23,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6578 states, 6578 states have (on average 1.3122529644268774) internal successors, (8632), 6577 states have internal predecessors, (8632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:58:23,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6578 states to 6578 states and 8632 transitions. [2022-11-25 17:58:23,400 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-11-25 17:58:23,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:58:23,400 INFO L428 stractBuchiCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2022-11-25 17:58:23,401 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-25 17:58:23,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6578 states and 8632 transitions. [2022-11-25 17:58:23,457 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2022-11-25 17:58:23,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:58:23,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:58:23,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:23,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:58:23,458 INFO L748 eck$LassoCheckResult]: Stem: 38604#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38493#L599 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38479#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38480#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38575#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38442#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38443#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38444#L423 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38389#L117 assume !(1 == ~P_1_pc~0); 38390#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 38451#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38524#L129 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38466#L477 assume !(0 != activate_threads_~tmp~1#1); 38467#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38567#L185 assume !(1 == ~P_2_pc~0); 38502#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 38503#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38540#L197 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38558#L485 assume !(0 != activate_threads_~tmp___0~1#1); 38393#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38394#L267 assume !(1 == ~C_1_pc~0); 38453#L267-2 assume !(2 == ~C_1_pc~0); 38538#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 38464#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38465#L289 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38428#L493 assume !(0 != activate_threads_~tmp___1~1#1); 38429#L493-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38533#L431 assume { :end_inline_reset_delta_events } true; 38609#L547-2 assume !false; 39451#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39452#L396 [2022-11-25 17:58:23,458 INFO L750 eck$LassoCheckResult]: Loop: 39452#L396 assume !false; 40073#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40072#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40071#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40070#L345 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40069#L361 assume 0 != eval_~tmp___2~0#1; 40068#L361-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40066#L370 assume !(0 != eval_~tmp~0#1); 40065#L366 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 40030#L385 assume !(0 != eval_~tmp___0~0#1); 40064#L381 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40074#L400 assume !(0 != eval_~tmp___1~0#1); 39452#L396 [2022-11-25 17:58:23,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:23,459 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2022-11-25 17:58:23,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:23,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375081680] [2022-11-25 17:58:23,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:23,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:23,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,470 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:23,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:23,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:23,491 INFO L85 PathProgramCache]: Analyzing trace with hash -1270750753, now seen corresponding path program 1 times [2022-11-25 17:58:23,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:23,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677670999] [2022-11-25 17:58:23,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:23,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:23,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,498 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:23,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,503 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:23,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:58:23,504 INFO L85 PathProgramCache]: Analyzing trace with hash -897649908, now seen corresponding path program 1 times [2022-11-25 17:58:23,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:58:23,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268174369] [2022-11-25 17:58:23,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:58:23,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:58:23,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,515 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:23,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:23,530 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:58:24,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:24,766 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:58:24,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:58:24,930 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 05:58:24 BoogieIcfgContainer [2022-11-25 17:58:24,936 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-25 17:58:24,945 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-25 17:58:24,945 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-25 17:58:24,945 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-25 17:58:24,946 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:58:18" (3/4) ... [2022-11-25 17:58:24,948 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-25 17:58:25,021 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/witness.graphml [2022-11-25 17:58:25,021 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-25 17:58:25,022 INFO L158 Benchmark]: Toolchain (without parser) took 7489.88ms. Allocated memory was 159.4MB in the beginning and 239.1MB in the end (delta: 79.7MB). Free memory was 124.8MB in the beginning and 163.8MB in the end (delta: -39.0MB). Peak memory consumption was 40.6MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,022 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 98.6MB. Free memory was 67.1MB in the beginning and 67.0MB in the end (delta: 80.3kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-25 17:58:25,023 INFO L158 Benchmark]: CACSL2BoogieTranslator took 474.05ms. Allocated memory is still 159.4MB. Free memory was 124.8MB in the beginning and 123.5MB in the end (delta: 1.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,023 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.99ms. Allocated memory is still 159.4MB. Free memory was 123.0MB in the beginning and 120.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,023 INFO L158 Benchmark]: Boogie Preprocessor took 76.42ms. Allocated memory is still 159.4MB. Free memory was 120.1MB in the beginning and 118.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,024 INFO L158 Benchmark]: RCFGBuilder took 830.97ms. Allocated memory is still 159.4MB. Free memory was 118.0MB in the beginning and 92.1MB in the end (delta: 25.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,024 INFO L158 Benchmark]: BuchiAutomizer took 5968.63ms. Allocated memory was 159.4MB in the beginning and 239.1MB in the end (delta: 79.7MB). Free memory was 92.1MB in the beginning and 169.0MB in the end (delta: -77.0MB). Peak memory consumption was 111.2MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,025 INFO L158 Benchmark]: Witness Printer took 76.83ms. Allocated memory is still 239.1MB. Free memory was 169.0MB in the beginning and 163.8MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-25 17:58:25,027 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 98.6MB. Free memory was 67.1MB in the beginning and 67.0MB in the end (delta: 80.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 474.05ms. Allocated memory is still 159.4MB. Free memory was 124.8MB in the beginning and 123.5MB in the end (delta: 1.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.99ms. Allocated memory is still 159.4MB. Free memory was 123.0MB in the beginning and 120.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 76.42ms. Allocated memory is still 159.4MB. Free memory was 120.1MB in the beginning and 118.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 830.97ms. Allocated memory is still 159.4MB. Free memory was 118.0MB in the beginning and 92.1MB in the end (delta: 25.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5968.63ms. Allocated memory was 159.4MB in the beginning and 239.1MB in the end (delta: 79.7MB). Free memory was 92.1MB in the beginning and 169.0MB in the end (delta: -77.0MB). Peak memory consumption was 111.2MB. Max. memory is 16.1GB. * Witness Printer took 76.83ms. Allocated memory is still 239.1MB. Free memory was 169.0MB in the beginning and 163.8MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6578 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.7s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.4s. Construction of modules took 0.4s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 11 MinimizatonAttempts, 1588 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3924 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3924 mSDsluCounter, 6157 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3339 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 397 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2818 mSDtfsCounter, 282 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L195] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L287] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L127] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L129] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L195] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L197] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L287] __retres1 = 0 VAL [__retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L289] return (__retres1); VAL [\result=0, __retres1=0, C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-25 17:58:25,077 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2981d67c-0b01-4025-adc4-3773db7d491b/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)