./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-25 17:17:50,008 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-25 17:17:50,010 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-25 17:17:50,048 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-25 17:17:50,049 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-25 17:17:50,052 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-25 17:17:50,055 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-25 17:17:50,058 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-25 17:17:50,063 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-25 17:17:50,068 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-25 17:17:50,069 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-25 17:17:50,071 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-25 17:17:50,071 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-25 17:17:50,072 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-25 17:17:50,074 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-25 17:17:50,075 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-25 17:17:50,076 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-25 17:17:50,077 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-25 17:17:50,078 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-25 17:17:50,085 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-25 17:17:50,087 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-25 17:17:50,090 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-25 17:17:50,091 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-25 17:17:50,093 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-25 17:17:50,102 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-25 17:17:50,103 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-25 17:17:50,104 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-25 17:17:50,105 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-25 17:17:50,106 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-25 17:17:50,109 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-25 17:17:50,109 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-25 17:17:50,110 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-25 17:17:50,112 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-25 17:17:50,113 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-25 17:17:50,115 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-25 17:17:50,115 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-25 17:17:50,116 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-25 17:17:50,116 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-25 17:17:50,116 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-25 17:17:50,117 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-25 17:17:50,118 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-25 17:17:50,119 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-25 17:17:50,166 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-25 17:17:50,166 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-25 17:17:50,167 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-25 17:17:50,167 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-25 17:17:50,168 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-25 17:17:50,168 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-25 17:17:50,169 INFO L138 SettingsManager]: * Use SBE=true [2022-11-25 17:17:50,169 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-25 17:17:50,169 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-25 17:17:50,169 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-25 17:17:50,170 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-25 17:17:50,170 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-25 17:17:50,171 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-25 17:17:50,171 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-25 17:17:50,171 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-25 17:17:50,171 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-25 17:17:50,171 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-25 17:17:50,172 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-25 17:17:50,173 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-25 17:17:50,173 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-25 17:17:50,173 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-25 17:17:50,173 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-25 17:17:50,173 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-25 17:17:50,173 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-25 17:17:50,174 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-25 17:17:50,174 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-25 17:17:50,175 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-25 17:17:50,175 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2022-11-25 17:17:50,451 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-25 17:17:50,524 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-25 17:17:50,527 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-25 17:17:50,528 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-25 17:17:50,529 INFO L275 PluginConnector]: CDTParser initialized [2022-11-25 17:17:50,530 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2022-11-25 17:17:53,530 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-25 17:17:53,789 INFO L351 CDTParser]: Found 1 translation units. [2022-11-25 17:17:53,791 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2022-11-25 17:17:53,804 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/data/0f10f107c/09dfac569ea74f6ab63348e9083c4944/FLAGfd00ae787 [2022-11-25 17:17:53,823 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/data/0f10f107c/09dfac569ea74f6ab63348e9083c4944 [2022-11-25 17:17:53,826 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-25 17:17:53,828 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-25 17:17:53,831 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-25 17:17:53,831 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-25 17:17:53,835 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-25 17:17:53,836 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:17:53" (1/1) ... [2022-11-25 17:17:53,837 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@127c34be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:53, skipping insertion in model container [2022-11-25 17:17:53,837 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:17:53" (1/1) ... [2022-11-25 17:17:53,845 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-25 17:17:53,891 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-25 17:17:54,054 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2022-11-25 17:17:54,095 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:17:54,108 INFO L203 MainTranslator]: Completed pre-run [2022-11-25 17:17:54,121 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2022-11-25 17:17:54,156 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:17:54,181 INFO L208 MainTranslator]: Completed translation [2022-11-25 17:17:54,193 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54 WrapperNode [2022-11-25 17:17:54,193 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-25 17:17:54,194 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-25 17:17:54,194 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-25 17:17:54,195 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-25 17:17:54,200 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,208 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,237 INFO L138 Inliner]: procedures = 29, calls = 31, calls flagged for inlining = 26, calls inlined = 27, statements flattened = 303 [2022-11-25 17:17:54,238 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-25 17:17:54,238 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-25 17:17:54,239 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-25 17:17:54,239 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-25 17:17:54,248 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,249 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,251 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,252 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,258 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,264 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,266 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,268 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,275 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-25 17:17:54,277 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-25 17:17:54,277 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-25 17:17:54,277 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-25 17:17:54,278 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (1/1) ... [2022-11-25 17:17:54,284 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-25 17:17:54,297 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 17:17:54,320 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-25 17:17:54,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-25 17:17:54,364 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-25 17:17:54,365 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-25 17:17:54,365 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-25 17:17:54,365 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-25 17:17:54,484 INFO L235 CfgBuilder]: Building ICFG [2022-11-25 17:17:54,504 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-25 17:17:54,984 INFO L276 CfgBuilder]: Performing block encoding [2022-11-25 17:17:54,992 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-25 17:17:54,992 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-11-25 17:17:54,995 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:17:54 BoogieIcfgContainer [2022-11-25 17:17:54,995 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-25 17:17:54,996 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-25 17:17:54,996 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-25 17:17:55,000 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-25 17:17:55,001 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:55,001 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 05:17:53" (1/3) ... [2022-11-25 17:17:55,002 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e851f3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:17:55, skipping insertion in model container [2022-11-25 17:17:55,003 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:55,003 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:54" (2/3) ... [2022-11-25 17:17:55,003 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e851f3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:17:55, skipping insertion in model container [2022-11-25 17:17:55,003 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:55,004 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:17:54" (3/3) ... [2022-11-25 17:17:55,005 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2022-11-25 17:17:55,065 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-25 17:17:55,066 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-25 17:17:55,066 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-25 17:17:55,066 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-25 17:17:55,066 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-25 17:17:55,066 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-25 17:17:55,067 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-25 17:17:55,067 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-25 17:17:55,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2022-11-25 17:17:55,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:55,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:55,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,104 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-25 17:17:55,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2022-11-25 17:17:55,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:55,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:55,112 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,120 INFO L748 eck$LassoCheckResult]: Stem: 98#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 29#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 63#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 30#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 36#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85#L275true assume !(0 == ~q_read_ev~0); 92#L275-2true assume !(0 == ~q_write_ev~0); 22#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 104#L65true assume !(1 == ~p_dw_pc~0); 28#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 52#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 62#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 33#L315true assume !(0 != activate_threads_~tmp~1#1); 64#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 96#L84true assume 1 == ~c_dr_pc~0; 24#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 70#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 89#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 45#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 34#L298-1true assume { :end_inline_reset_delta_events } true; 10#L419-2true [2022-11-25 17:17:55,121 INFO L750 eck$LassoCheckResult]: Loop: 10#L419-2true assume !false; 26#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 100#L364true assume false; 59#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81#L222-3true assume !(1 == ~q_req_up~0); 31#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 37#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 51#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 60#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 93#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 71#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 38#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 82#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 56#L84-3true assume 1 == ~c_dr_pc~0; 40#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 77#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 57#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 102#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 76#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume !(1 == ~q_write_ev~0); 50#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 23#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 25#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 54#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 27#L436true assume !(0 != start_simulation_~tmp~4#1); 10#L419-2true [2022-11-25 17:17:55,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:55,127 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2022-11-25 17:17:55,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:55,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309309405] [2022-11-25 17:17:55,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:55,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:55,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:55,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:55,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:55,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309309405] [2022-11-25 17:17:55,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309309405] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:55,349 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:55,350 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:55,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576673919] [2022-11-25 17:17:55,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:55,359 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:55,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:55,363 INFO L85 PathProgramCache]: Analyzing trace with hash 774851143, now seen corresponding path program 1 times [2022-11-25 17:17:55,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:55,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009053685] [2022-11-25 17:17:55,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:55,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:55,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:55,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:55,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:55,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009053685] [2022-11-25 17:17:55,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009053685] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:55,413 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:55,413 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:55,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165797363] [2022-11-25 17:17:55,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:55,415 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:55,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:55,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:55,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:55,452 INFO L87 Difference]: Start difference. First operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:55,482 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2022-11-25 17:17:55,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2022-11-25 17:17:55,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-11-25 17:17:55,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2022-11-25 17:17:55,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2022-11-25 17:17:55,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2022-11-25 17:17:55,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2022-11-25 17:17:55,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:55,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-11-25 17:17:55,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2022-11-25 17:17:55,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2022-11-25 17:17:55,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2022-11-25 17:17:55,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-11-25 17:17:55,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:55,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-11-25 17:17:55,538 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-25 17:17:55,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2022-11-25 17:17:55,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-11-25 17:17:55,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:55,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:55,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,542 INFO L748 eck$LassoCheckResult]: Stem: 307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 249#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 245#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 281#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 300#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 298#L275 assume !(0 == ~q_read_ev~0); 299#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 284#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 283#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 241#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 242#L315 assume !(0 != activate_threads_~tmp~1#1); 251#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 252#L84 assume 1 == ~c_dr_pc~0; 291#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 262#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 263#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 224#L323 assume !(0 != activate_threads_~tmp___0~1#1); 225#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306#L293 assume !(1 == ~q_read_ev~0); 213#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 214#L298-1 assume { :end_inline_reset_delta_events } true; 247#L419-2 [2022-11-25 17:17:55,543 INFO L750 eck$LassoCheckResult]: Loop: 247#L419-2 assume !false; 248#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 236#L364 assume !false; 285#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 259#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 266#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 267#L344 assume !(0 != eval_~tmp___1~0#1); 230#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L222-3 assume !(1 == ~q_req_up~0); 292#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 280#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 232#L65-3 assume !(1 == ~p_dw_pc~0); 233#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 270#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 264#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 265#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 293#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 278#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 222#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 223#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 276#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 228#L293-5 assume !(1 == ~q_write_ev~0); 229#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 288#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 289#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 215#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 216#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 239#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 261#L436 assume !(0 != start_simulation_~tmp~4#1); 247#L419-2 [2022-11-25 17:17:55,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:55,544 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2022-11-25 17:17:55,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:55,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803253691] [2022-11-25 17:17:55,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:55,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:55,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:55,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:55,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:55,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803253691] [2022-11-25 17:17:55,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803253691] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:55,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:55,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 17:17:55,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17957115] [2022-11-25 17:17:55,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:55,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:55,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:55,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1517218729, now seen corresponding path program 1 times [2022-11-25 17:17:55,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:55,675 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245329926] [2022-11-25 17:17:55,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:55,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:55,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:55,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:55,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:55,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245329926] [2022-11-25 17:17:55,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245329926] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:55,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:55,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:55,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405918595] [2022-11-25 17:17:55,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:55,727 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:55,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:55,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:17:55,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:17:55,729 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:55,875 INFO L93 Difference]: Finished difference Result 312 states and 446 transitions. [2022-11-25 17:17:55,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 446 transitions. [2022-11-25 17:17:55,881 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2022-11-25 17:17:55,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 446 transitions. [2022-11-25 17:17:55,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2022-11-25 17:17:55,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2022-11-25 17:17:55,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 446 transitions. [2022-11-25 17:17:55,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:55,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 446 transitions. [2022-11-25 17:17:55,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 446 transitions. [2022-11-25 17:17:55,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2022-11-25 17:17:55,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4429530201342282) internal successors, (430), 297 states have internal predecessors, (430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:55,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 430 transitions. [2022-11-25 17:17:55,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298 states and 430 transitions. [2022-11-25 17:17:55,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:17:55,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 298 states and 430 transitions. [2022-11-25 17:17:55,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-25 17:17:55,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 430 transitions. [2022-11-25 17:17:55,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2022-11-25 17:17:55,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:55,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:55,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:55,940 INFO L748 eck$LassoCheckResult]: Stem: 729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 668#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 669#L222 assume !(1 == ~q_req_up~0); 664#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 665#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 699#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 718#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 715#L275 assume !(0 == ~q_read_ev~0); 716#L275-2 assume !(0 == ~q_write_ev~0); 704#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 705#L65 assume !(1 == ~p_dw_pc~0); 702#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 701#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 660#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 661#L315 assume !(0 != activate_threads_~tmp~1#1); 670#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 671#L84 assume !(1 == ~c_dr_pc~0); 687#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 680#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 681#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 643#L323 assume !(0 != activate_threads_~tmp___0~1#1); 644#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728#L293 assume !(1 == ~q_read_ev~0); 635#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 636#L298-1 assume { :end_inline_reset_delta_events } true; 666#L419-2 [2022-11-25 17:17:55,941 INFO L750 eck$LassoCheckResult]: Loop: 666#L419-2 assume !false; 667#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 675#L364 assume !false; 703#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 674#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 642#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 682#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 683#L344 assume !(0 != eval_~tmp___1~0#1); 692#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 928#L222-3 assume !(1 == ~q_req_up~0); 927#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 926#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 925#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 924#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 923#L65-3 assume !(1 == ~p_dw_pc~0); 921#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 723#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 724#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 726#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 710#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 711#L84-3 assume !(1 == ~c_dr_pc~0); 917#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 695#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 696#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 912#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 693#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 694#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 645#L293-5 assume !(1 == ~q_write_ev~0); 646#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 706#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 707#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 633#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 634#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 656#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 657#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 677#L436 assume !(0 != start_simulation_~tmp~4#1); 666#L419-2 [2022-11-25 17:17:55,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:55,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2022-11-25 17:17:55,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:55,942 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077987251] [2022-11-25 17:17:55,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:55,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:55,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077987251] [2022-11-25 17:17:56,004 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077987251] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,004 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 17:17:56,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445715635] [2022-11-25 17:17:56,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:56,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,006 INFO L85 PathProgramCache]: Analyzing trace with hash -340614410, now seen corresponding path program 1 times [2022-11-25 17:17:56,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913728347] [2022-11-25 17:17:56,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913728347] [2022-11-25 17:17:56,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913728347] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,044 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,044 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:56,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020695468] [2022-11-25 17:17:56,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,045 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:56,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:56,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:56,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:56,047 INFO L87 Difference]: Start difference. First operand 298 states and 430 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:56,244 INFO L93 Difference]: Finished difference Result 683 states and 957 transitions. [2022-11-25 17:17:56,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 957 transitions. [2022-11-25 17:17:56,252 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-11-25 17:17:56,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 957 transitions. [2022-11-25 17:17:56,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2022-11-25 17:17:56,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2022-11-25 17:17:56,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 957 transitions. [2022-11-25 17:17:56,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:56,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-11-25 17:17:56,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 957 transitions. [2022-11-25 17:17:56,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2022-11-25 17:17:56,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.4011713030746706) internal successors, (957), 682 states have internal predecessors, (957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 957 transitions. [2022-11-25 17:17:56,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-11-25 17:17:56,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:56,331 INFO L428 stractBuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2022-11-25 17:17:56,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-25 17:17:56,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 957 transitions. [2022-11-25 17:17:56,340 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-11-25 17:17:56,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:56,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:56,343 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,344 INFO L748 eck$LassoCheckResult]: Stem: 1735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1661#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1662#L222 assume !(1 == ~q_req_up~0); 1657#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1658#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1694#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1715#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1711#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1712#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1726#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1767#L65 assume !(1 == ~p_dw_pc~0); 1765#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1764#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1763#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1762#L315 assume !(0 != activate_threads_~tmp~1#1); 1761#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1760#L84 assume !(1 == ~c_dr_pc~0); 1759#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1758#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1757#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1756#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1755#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1754#L293 assume !(1 == ~q_read_ev~0); 1753#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1724#L298-1 assume { :end_inline_reset_delta_events } true; 1725#L419-2 [2022-11-25 17:17:56,344 INFO L750 eck$LassoCheckResult]: Loop: 1725#L419-2 assume !false; 2123#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2065#L364 assume !false; 1697#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1698#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2115#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2076#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1685#L344 assume !(0 != eval_~tmp___1~0#1); 1687#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2261#L222-3 assume !(1 == ~q_req_up~0); 2258#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2255#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2227#L275-5 assume !(0 == ~q_write_ev~0); 2253#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2291#L65-3 assume !(1 == ~p_dw_pc~0); 2289#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2288#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2287#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2284#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2282#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2280#L84-3 assume !(1 == ~c_dr_pc~0); 2279#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2277#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2276#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2274#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2271#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2268#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2204#L293-5 assume !(1 == ~q_write_ev~0); 2201#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2197#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2195#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2193#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2143#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2139#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2135#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2131#L436 assume !(0 != start_simulation_~tmp~4#1); 1725#L419-2 [2022-11-25 17:17:56,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2022-11-25 17:17:56,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271240544] [2022-11-25 17:17:56,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271240544] [2022-11-25 17:17:56,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271240544] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,432 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,432 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:56,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187395320] [2022-11-25 17:17:56,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,436 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:56,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,438 INFO L85 PathProgramCache]: Analyzing trace with hash -474627916, now seen corresponding path program 1 times [2022-11-25 17:17:56,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971778123] [2022-11-25 17:17:56,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971778123] [2022-11-25 17:17:56,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971778123] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,557 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,557 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:56,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455558026] [2022-11-25 17:17:56,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,558 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:56,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:56,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:56,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:56,559 INFO L87 Difference]: Start difference. First operand 683 states and 957 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:56,597 INFO L93 Difference]: Finished difference Result 952 states and 1311 transitions. [2022-11-25 17:17:56,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1311 transitions. [2022-11-25 17:17:56,606 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2022-11-25 17:17:56,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1311 transitions. [2022-11-25 17:17:56,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2022-11-25 17:17:56,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2022-11-25 17:17:56,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1311 transitions. [2022-11-25 17:17:56,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:56,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 952 states and 1311 transitions. [2022-11-25 17:17:56,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1311 transitions. [2022-11-25 17:17:56,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2022-11-25 17:17:56,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3794117647058823) internal successors, (938), 679 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 938 transitions. [2022-11-25 17:17:56,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 938 transitions. [2022-11-25 17:17:56,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:56,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 680 states and 938 transitions. [2022-11-25 17:17:56,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-25 17:17:56,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 938 transitions. [2022-11-25 17:17:56,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2022-11-25 17:17:56,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:56,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:56,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,649 INFO L748 eck$LassoCheckResult]: Stem: 3379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3302#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3303#L222 assume !(1 == ~q_req_up~0); 3300#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3301#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3336#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3358#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3355#L275 assume !(0 == ~q_read_ev~0); 3356#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3371#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3394#L65 assume !(1 == ~p_dw_pc~0); 3338#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3392#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3393#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3368#L315 assume !(0 != activate_threads_~tmp~1#1); 3369#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3375#L84 assume !(1 == ~c_dr_pc~0); 3376#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3314#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3315#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3279#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3280#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3377#L293 assume !(1 == ~q_read_ev~0); 3378#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3270#L298-1 assume { :end_inline_reset_delta_events } true; 3370#L419-2 [2022-11-25 17:17:56,655 INFO L750 eck$LassoCheckResult]: Loop: 3370#L419-2 assume !false; 3439#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3311#L364 assume !false; 3438#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3437#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3435#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3434#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3432#L344 assume !(0 != eval_~tmp___1~0#1); 3433#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3473#L222-3 assume !(1 == ~q_req_up~0); 3471#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3469#L275-3 assume !(0 == ~q_read_ev~0); 3466#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3465#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3463#L65-3 assume !(1 == ~p_dw_pc~0); 3462#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3461#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3460#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3459#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3458#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3457#L84-3 assume !(1 == ~c_dr_pc~0); 3456#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3455#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3454#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3453#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3452#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3451#L293-3 assume !(1 == ~q_read_ev~0); 3450#L293-5 assume !(1 == ~q_write_ev~0); 3448#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3446#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3445#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3444#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3443#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3442#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3441#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3440#L436 assume !(0 != start_simulation_~tmp~4#1); 3370#L419-2 [2022-11-25 17:17:56,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,656 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2022-11-25 17:17:56,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057116545] [2022-11-25 17:17:56,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1057116545] [2022-11-25 17:17:56,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1057116545] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,711 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-25 17:17:56,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435311589] [2022-11-25 17:17:56,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,712 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:56,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,713 INFO L85 PathProgramCache]: Analyzing trace with hash -593092810, now seen corresponding path program 1 times [2022-11-25 17:17:56,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884181803] [2022-11-25 17:17:56,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884181803] [2022-11-25 17:17:56,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884181803] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:56,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032599130] [2022-11-25 17:17:56,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:56,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:56,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:56,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:56,740 INFO L87 Difference]: Start difference. First operand 680 states and 938 transitions. cyclomatic complexity: 260 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:56,793 INFO L93 Difference]: Finished difference Result 830 states and 1136 transitions. [2022-11-25 17:17:56,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1136 transitions. [2022-11-25 17:17:56,798 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2022-11-25 17:17:56,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1136 transitions. [2022-11-25 17:17:56,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-11-25 17:17:56,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-11-25 17:17:56,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1136 transitions. [2022-11-25 17:17:56,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:56,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1136 transitions. [2022-11-25 17:17:56,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1136 transitions. [2022-11-25 17:17:56,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2022-11-25 17:17:56,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.3717105263157894) internal successors, (834), 607 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:56,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 834 transitions. [2022-11-25 17:17:56,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 608 states and 834 transitions. [2022-11-25 17:17:56,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-25 17:17:56,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 608 states and 834 transitions. [2022-11-25 17:17:56,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-25 17:17:56,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 834 transitions. [2022-11-25 17:17:56,826 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2022-11-25 17:17:56,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:56,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:56,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:56,827 INFO L748 eck$LassoCheckResult]: Stem: 4890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4825#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4826#L222 assume !(1 == ~q_req_up~0); 4821#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4822#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4856#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4876#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4873#L275 assume !(0 == ~q_read_ev~0); 4874#L275-2 assume !(0 == ~q_write_ev~0); 4861#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4862#L65 assume !(1 == ~p_dw_pc~0); 4858#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4868#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4819#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4820#L315 assume !(0 != activate_threads_~tmp~1#1); 4827#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4828#L84 assume !(1 == ~c_dr_pc~0); 4844#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4837#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4838#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4799#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4800#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L293 assume !(1 == ~q_read_ev~0); 4791#L293-2 assume !(1 == ~q_write_ev~0); 4792#L298-1 assume { :end_inline_reset_delta_events } true; 4885#L419-2 [2022-11-25 17:17:56,828 INFO L750 eck$LassoCheckResult]: Loop: 4885#L419-2 assume !false; 5096#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4832#L364 assume !false; 5093#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4831#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4798#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4839#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4840#L344 assume !(0 != eval_~tmp___1~0#1); 4850#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5373#L222-3 assume !(1 == ~q_req_up~0); 5371#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5369#L275-3 assume !(0 == ~q_read_ev~0); 5367#L275-5 assume !(0 == ~q_write_ev~0); 5364#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5360#L65-3 assume !(1 == ~p_dw_pc~0); 5358#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5357#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5356#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5353#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5352#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5351#L84-3 assume !(1 == ~c_dr_pc~0); 5350#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5171#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5154#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5152#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5150#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5140#L293-3 assume !(1 == ~q_read_ev~0); 5135#L293-5 assume !(1 == ~q_write_ev~0); 5133#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5129#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5127#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5125#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5123#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5121#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5113#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5108#L436 assume !(0 != start_simulation_~tmp~4#1); 4885#L419-2 [2022-11-25 17:17:56,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2022-11-25 17:17:56,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,829 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030376027] [2022-11-25 17:17:56,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:56,840 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:56,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:56,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:56,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:56,888 INFO L85 PathProgramCache]: Analyzing trace with hash -727106316, now seen corresponding path program 1 times [2022-11-25 17:17:56,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:56,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348454055] [2022-11-25 17:17:56,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:56,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:56,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:56,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:56,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:56,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348454055] [2022-11-25 17:17:56,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348454055] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:56,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:56,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:56,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944329364] [2022-11-25 17:17:56,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:56,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:56,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:56,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:17:56,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:17:56,963 INFO L87 Difference]: Start difference. First operand 608 states and 834 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,036 INFO L93 Difference]: Finished difference Result 919 states and 1251 transitions. [2022-11-25 17:17:57,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1251 transitions. [2022-11-25 17:17:57,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2022-11-25 17:17:57,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1251 transitions. [2022-11-25 17:17:57,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2022-11-25 17:17:57,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2022-11-25 17:17:57,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1251 transitions. [2022-11-25 17:17:57,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:57,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 919 states and 1251 transitions. [2022-11-25 17:17:57,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1251 transitions. [2022-11-25 17:17:57,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2022-11-25 17:17:57,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3559055118110237) internal successors, (861), 634 states have internal predecessors, (861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 861 transitions. [2022-11-25 17:17:57,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 635 states and 861 transitions. [2022-11-25 17:17:57,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-25 17:17:57,068 INFO L428 stractBuchiCegarLoop]: Abstraction has 635 states and 861 transitions. [2022-11-25 17:17:57,068 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-25 17:17:57,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 861 transitions. [2022-11-25 17:17:57,071 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2022-11-25 17:17:57,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,075 INFO L748 eck$LassoCheckResult]: Stem: 6446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6369#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6370#L222 assume !(1 == ~q_req_up~0); 6365#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6366#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6402#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6424#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6420#L275 assume !(0 == ~q_read_ev~0); 6421#L275-2 assume !(0 == ~q_write_ev~0); 6406#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6407#L65 assume !(1 == ~p_dw_pc~0); 6404#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6414#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6363#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6364#L315 assume !(0 != activate_threads_~tmp~1#1); 6371#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6372#L84 assume !(1 == ~c_dr_pc~0); 6390#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6381#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6382#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6343#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6344#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6444#L293 assume !(1 == ~q_read_ev~0); 6334#L293-2 assume !(1 == ~q_write_ev~0); 6335#L298-1 assume { :end_inline_reset_delta_events } true; 6435#L419-2 [2022-11-25 17:17:57,075 INFO L750 eck$LassoCheckResult]: Loop: 6435#L419-2 assume !false; 6958#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6376#L364 assume !false; 6957#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6956#L255 assume !(0 == ~p_dw_st~0); 6954#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6955#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6927#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6887#L344 assume !(0 != eval_~tmp___1~0#1); 6349#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6350#L222-3 assume !(1 == ~q_req_up~0); 6430#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6431#L275-3 assume !(0 == ~q_read_ev~0); 6438#L275-5 assume !(0 == ~q_write_ev~0); 6439#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6351#L65-3 assume !(1 == ~p_dw_pc~0); 6352#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6436#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6437#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6440#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6441#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6339#L84-3 assume !(1 == ~c_dr_pc~0); 6340#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6398#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6399#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6459#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6460#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6433#L293-3 assume !(1 == ~q_read_ev~0); 6434#L293-5 assume !(1 == ~q_write_ev~0); 6455#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6456#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6964#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6963#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6962#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6961#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6960#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6959#L436 assume !(0 != start_simulation_~tmp~4#1); 6435#L419-2 [2022-11-25 17:17:57,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2022-11-25 17:17:57,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686612749] [2022-11-25 17:17:57,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,092 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,108 INFO L85 PathProgramCache]: Analyzing trace with hash -366252558, now seen corresponding path program 1 times [2022-11-25 17:17:57,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816271847] [2022-11-25 17:17:57,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816271847] [2022-11-25 17:17:57,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816271847] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:57,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444522692] [2022-11-25 17:17:57,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,215 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:57,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:57,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:17:57,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:17:57,216 INFO L87 Difference]: Start difference. First operand 635 states and 861 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,301 INFO L93 Difference]: Finished difference Result 1521 states and 2071 transitions. [2022-11-25 17:17:57,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1521 states and 2071 transitions. [2022-11-25 17:17:57,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1493 [2022-11-25 17:17:57,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1521 states to 1521 states and 2071 transitions. [2022-11-25 17:17:57,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1521 [2022-11-25 17:17:57,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1521 [2022-11-25 17:17:57,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1521 states and 2071 transitions. [2022-11-25 17:17:57,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:57,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1521 states and 2071 transitions. [2022-11-25 17:17:57,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1521 states and 2071 transitions. [2022-11-25 17:17:57,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1521 to 653. [2022-11-25 17:17:57,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 653 states, 653 states have (on average 1.333843797856049) internal successors, (871), 652 states have internal predecessors, (871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 653 states to 653 states and 871 transitions. [2022-11-25 17:17:57,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 653 states and 871 transitions. [2022-11-25 17:17:57,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:17:57,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 653 states and 871 transitions. [2022-11-25 17:17:57,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-25 17:17:57,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 653 states and 871 transitions. [2022-11-25 17:17:57,357 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2022-11-25 17:17:57,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,358 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,358 INFO L748 eck$LassoCheckResult]: Stem: 8606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8538#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8539#L222 assume !(1 == ~q_req_up~0); 8534#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8535#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8571#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8591#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8589#L275 assume !(0 == ~q_read_ev~0); 8590#L275-2 assume !(0 == ~q_write_ev~0); 8574#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8575#L65 assume !(1 == ~p_dw_pc~0); 8573#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8583#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8532#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8533#L315 assume !(0 != activate_threads_~tmp~1#1); 8540#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8541#L84 assume !(1 == ~c_dr_pc~0); 8559#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8550#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8551#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8512#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8513#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8605#L293 assume !(1 == ~q_read_ev~0); 8503#L293-2 assume !(1 == ~q_write_ev~0); 8504#L298-1 assume { :end_inline_reset_delta_events } true; 8598#L419-2 [2022-11-25 17:17:57,358 INFO L750 eck$LassoCheckResult]: Loop: 8598#L419-2 assume !false; 9009#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8991#L364 assume !false; 9008#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9007#L255 assume !(0 == ~p_dw_st~0); 9005#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 9006#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9001#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9002#L344 assume !(0 != eval_~tmp___1~0#1); 9039#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9038#L222-3 assume !(1 == ~q_req_up~0); 9037#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9036#L275-3 assume !(0 == ~q_read_ev~0); 9035#L275-5 assume !(0 == ~q_write_ev~0); 9034#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9032#L65-3 assume !(1 == ~p_dw_pc~0); 9031#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 9030#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9029#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9028#L315-3 assume !(0 != activate_threads_~tmp~1#1); 9027#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9026#L84-3 assume !(1 == ~c_dr_pc~0); 9025#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 9024#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9023#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9022#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9021#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9020#L293-3 assume !(1 == ~q_read_ev~0); 9019#L293-5 assume !(1 == ~q_write_ev~0); 9018#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9016#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9015#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9014#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9013#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 9012#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9011#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9010#L436 assume !(0 != start_simulation_~tmp~4#1); 8598#L419-2 [2022-11-25 17:17:57,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2022-11-25 17:17:57,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713679654] [2022-11-25 17:17:57,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,366 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1934570032, now seen corresponding path program 1 times [2022-11-25 17:17:57,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147918544] [2022-11-25 17:17:57,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,398 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147918544] [2022-11-25 17:17:57,398 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147918544] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,398 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:57,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360687308] [2022-11-25 17:17:57,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,399 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:57,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:57,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:57,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:57,400 INFO L87 Difference]: Start difference. First operand 653 states and 871 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,425 INFO L93 Difference]: Finished difference Result 936 states and 1217 transitions. [2022-11-25 17:17:57,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1217 transitions. [2022-11-25 17:17:57,430 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-11-25 17:17:57,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1217 transitions. [2022-11-25 17:17:57,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2022-11-25 17:17:57,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2022-11-25 17:17:57,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1217 transitions. [2022-11-25 17:17:57,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:57,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-11-25 17:17:57,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1217 transitions. [2022-11-25 17:17:57,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2022-11-25 17:17:57,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 936 states, 936 states have (on average 1.3002136752136753) internal successors, (1217), 935 states have internal predecessors, (1217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1217 transitions. [2022-11-25 17:17:57,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-11-25 17:17:57,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:57,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 936 states and 1217 transitions. [2022-11-25 17:17:57,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-25 17:17:57,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1217 transitions. [2022-11-25 17:17:57,461 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-11-25 17:17:57,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,462 INFO L748 eck$LassoCheckResult]: Stem: 10198#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10131#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10132#L222 assume !(1 == ~q_req_up~0); 10129#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10130#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 10163#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10182#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10192#L275 assume !(0 == ~q_read_ev~0); 10845#L275-2 assume !(0 == ~q_write_ev~0); 10843#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10840#L65 assume !(1 == ~p_dw_pc~0); 10839#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10838#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10837#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10836#L315 assume !(0 != activate_threads_~tmp~1#1); 10835#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10834#L84 assume !(1 == ~c_dr_pc~0); 10833#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10832#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10831#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10830#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10208#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10197#L293 assume !(1 == ~q_read_ev~0); 10096#L293-2 assume !(1 == ~q_write_ev~0); 10097#L298-1 assume { :end_inline_reset_delta_events } true; 10189#L419-2 [2022-11-25 17:17:57,462 INFO L750 eck$LassoCheckResult]: Loop: 10189#L419-2 assume !false; 10957#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10140#L364 assume !false; 10169#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10139#L255 assume !(0 == ~p_dw_st~0); 10100#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10102#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10223#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10221#L344 assume !(0 != eval_~tmp___1~0#1); 10222#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11012#L222-3 assume !(1 == ~q_req_up~0); 11010#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11008#L275-3 assume !(0 == ~q_read_ev~0); 11006#L275-5 assume !(0 == ~q_write_ev~0); 11004#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11002#L65-3 assume !(1 == ~p_dw_pc~0); 11000#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 10998#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10996#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10993#L315-3 assume !(0 != activate_threads_~tmp~1#1); 10991#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10990#L84-3 assume !(1 == ~c_dr_pc~0); 10987#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 10985#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10983#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10981#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10979#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10977#L293-3 assume !(1 == ~q_read_ev~0); 10975#L293-5 assume !(1 == ~q_write_ev~0); 10974#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10972#L255-1 assume !(0 == ~p_dw_st~0); 10970#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10968#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10966#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10964#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10963#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10961#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10959#L436 assume !(0 != start_simulation_~tmp~4#1); 10189#L419-2 [2022-11-25 17:17:57,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2022-11-25 17:17:57,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961201385] [2022-11-25 17:17:57,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961201385] [2022-11-25 17:17:57,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961201385] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,483 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,483 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:57,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269441321] [2022-11-25 17:17:57,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:57,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,484 INFO L85 PathProgramCache]: Analyzing trace with hash -282414912, now seen corresponding path program 1 times [2022-11-25 17:17:57,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067760808] [2022-11-25 17:17:57,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067760808] [2022-11-25 17:17:57,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067760808] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,582 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:57,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613056424] [2022-11-25 17:17:57,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,583 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:57,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:57,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:57,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:57,584 INFO L87 Difference]: Start difference. First operand 936 states and 1217 transitions. cyclomatic complexity: 284 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,592 INFO L93 Difference]: Finished difference Result 915 states and 1193 transitions. [2022-11-25 17:17:57,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 915 states and 1193 transitions. [2022-11-25 17:17:57,597 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-11-25 17:17:57,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 915 states to 915 states and 1193 transitions. [2022-11-25 17:17:57,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 915 [2022-11-25 17:17:57,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 915 [2022-11-25 17:17:57,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 915 states and 1193 transitions. [2022-11-25 17:17:57,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:57,604 INFO L218 hiAutomatonCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-11-25 17:17:57,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 915 states and 1193 transitions. [2022-11-25 17:17:57,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 915 to 915. [2022-11-25 17:17:57,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 915 states, 915 states have (on average 1.303825136612022) internal successors, (1193), 914 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 915 states to 915 states and 1193 transitions. [2022-11-25 17:17:57,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-11-25 17:17:57,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:57,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2022-11-25 17:17:57,623 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-25 17:17:57,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 915 states and 1193 transitions. [2022-11-25 17:17:57,627 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2022-11-25 17:17:57,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,628 INFO L748 eck$LassoCheckResult]: Stem: 12063#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11991#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11992#L222 assume !(1 == ~q_req_up~0); 11989#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11990#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12026#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12049#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12047#L275 assume !(0 == ~q_read_ev~0); 12048#L275-2 assume !(0 == ~q_write_ev~0); 12029#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12030#L65 assume !(1 == ~p_dw_pc~0); 12028#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12041#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11984#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11985#L315 assume !(0 != activate_threads_~tmp~1#1); 11995#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11996#L84 assume !(1 == ~c_dr_pc~0); 12013#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 12003#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12004#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11967#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11968#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12062#L293 assume !(1 == ~q_read_ev~0); 11956#L293-2 assume !(1 == ~q_write_ev~0); 11957#L298-1 assume { :end_inline_reset_delta_events } true; 11993#L419-2 assume !false; 11994#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12762#L364 [2022-11-25 17:17:57,628 INFO L750 eck$LassoCheckResult]: Loop: 12762#L364 assume !false; 12031#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12032#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12806#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12805#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12803#L344 assume 0 != eval_~tmp___1~0#1; 12098#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 12017#L353 assume !(0 != eval_~tmp~2#1); 12019#L349 assume !(0 == ~c_dr_st~0); 12762#L364 [2022-11-25 17:17:57,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,629 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2022-11-25 17:17:57,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356081943] [2022-11-25 17:17:57,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,644 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,656 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,657 INFO L85 PathProgramCache]: Analyzing trace with hash -479000201, now seen corresponding path program 1 times [2022-11-25 17:17:57,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190054530] [2022-11-25 17:17:57,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,664 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,676 INFO L85 PathProgramCache]: Analyzing trace with hash 519639655, now seen corresponding path program 1 times [2022-11-25 17:17:57,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962797344] [2022-11-25 17:17:57,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962797344] [2022-11-25 17:17:57,732 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962797344] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:57,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161786557] [2022-11-25 17:17:57,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:57,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:57,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:57,809 INFO L87 Difference]: Start difference. First operand 915 states and 1193 transitions. cyclomatic complexity: 281 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,836 INFO L93 Difference]: Finished difference Result 1272 states and 1634 transitions. [2022-11-25 17:17:57,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1272 states and 1634 transitions. [2022-11-25 17:17:57,843 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2022-11-25 17:17:57,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1272 states to 1272 states and 1634 transitions. [2022-11-25 17:17:57,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1272 [2022-11-25 17:17:57,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1272 [2022-11-25 17:17:57,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1272 states and 1634 transitions. [2022-11-25 17:17:57,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:57,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-11-25 17:17:57,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states and 1634 transitions. [2022-11-25 17:17:57,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1272. [2022-11-25 17:17:57,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1272 states, 1272 states have (on average 1.2845911949685536) internal successors, (1634), 1271 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1272 states to 1272 states and 1634 transitions. [2022-11-25 17:17:57,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-11-25 17:17:57,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:57,919 INFO L428 stractBuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2022-11-25 17:17:57,920 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-25 17:17:57,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1272 states and 1634 transitions. [2022-11-25 17:17:57,926 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2022-11-25 17:17:57,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,927 INFO L748 eck$LassoCheckResult]: Stem: 14255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14185#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14186#L222 assume !(1 == ~q_req_up~0); 14183#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14184#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 14220#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 14242#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14240#L275 assume !(0 == ~q_read_ev~0); 14241#L275-2 assume !(0 == ~q_write_ev~0); 14223#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 14224#L65 assume !(1 == ~p_dw_pc~0); 14222#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 14232#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 14178#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14179#L315 assume !(0 != activate_threads_~tmp~1#1); 14189#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 14190#L84 assume !(1 == ~c_dr_pc~0); 14207#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 14198#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 14199#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14161#L323 assume !(0 != activate_threads_~tmp___0~1#1); 14162#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14254#L293 assume !(1 == ~q_read_ev~0); 14151#L293-2 assume !(1 == ~q_write_ev~0); 14152#L298-1 assume { :end_inline_reset_delta_events } true; 14249#L419-2 assume !false; 14945#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 14663#L364 [2022-11-25 17:17:57,927 INFO L750 eck$LassoCheckResult]: Loop: 14663#L364 assume !false; 14676#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14673#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14671#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14669#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 14668#L344 assume 0 != eval_~tmp___1~0#1; 14667#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 14665#L353 assume !(0 != eval_~tmp~2#1); 14664#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 14662#L368 assume !(0 != eval_~tmp___0~2#1); 14663#L364 [2022-11-25 17:17:57,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,928 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2022-11-25 17:17:57,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023648921] [2022-11-25 17:17:57,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,956 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,957 INFO L85 PathProgramCache]: Analyzing trace with hash -1964106000, now seen corresponding path program 1 times [2022-11-25 17:17:57,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411644533] [2022-11-25 17:17:57,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,967 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:57,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041536, now seen corresponding path program 1 times [2022-11-25 17:17:57,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72858822] [2022-11-25 17:17:57,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,977 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:57,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:57,986 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:17:58,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:58,859 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:17:58,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:17:58,946 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 05:17:58 BoogieIcfgContainer [2022-11-25 17:17:58,946 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-25 17:17:58,946 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-25 17:17:58,946 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-25 17:17:58,947 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-25 17:17:58,947 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:17:54" (3/4) ... [2022-11-25 17:17:58,950 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-25 17:17:59,010 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/witness.graphml [2022-11-25 17:17:59,014 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-25 17:17:59,015 INFO L158 Benchmark]: Toolchain (without parser) took 5186.41ms. Allocated memory was 138.4MB in the beginning and 209.7MB in the end (delta: 71.3MB). Free memory was 70.7MB in the beginning and 123.2MB in the end (delta: -52.4MB). Peak memory consumption was 20.9MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,015 INFO L158 Benchmark]: CDTParser took 0.23ms. Allocated memory is still 138.4MB. Free memory was 110.9MB in the beginning and 110.8MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-25 17:17:59,015 INFO L158 Benchmark]: CACSL2BoogieTranslator took 362.38ms. Allocated memory was 138.4MB in the beginning and 174.1MB in the end (delta: 35.7MB). Free memory was 70.5MB in the beginning and 137.5MB in the end (delta: -67.0MB). Peak memory consumption was 9.9MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,016 INFO L158 Benchmark]: Boogie Procedure Inliner took 43.68ms. Allocated memory is still 174.1MB. Free memory was 137.5MB in the beginning and 135.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,016 INFO L158 Benchmark]: Boogie Preprocessor took 37.35ms. Allocated memory is still 174.1MB. Free memory was 135.4MB in the beginning and 133.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,016 INFO L158 Benchmark]: RCFGBuilder took 718.54ms. Allocated memory is still 174.1MB. Free memory was 133.3MB in the beginning and 134.2MB in the end (delta: -883.6kB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,017 INFO L158 Benchmark]: BuchiAutomizer took 3949.95ms. Allocated memory was 174.1MB in the beginning and 209.7MB in the end (delta: 35.7MB). Free memory was 134.2MB in the beginning and 127.4MB in the end (delta: 6.9MB). Peak memory consumption was 44.6MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,017 INFO L158 Benchmark]: Witness Printer took 67.71ms. Allocated memory is still 209.7MB. Free memory was 127.4MB in the beginning and 123.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-25 17:17:59,019 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23ms. Allocated memory is still 138.4MB. Free memory was 110.9MB in the beginning and 110.8MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 362.38ms. Allocated memory was 138.4MB in the beginning and 174.1MB in the end (delta: 35.7MB). Free memory was 70.5MB in the beginning and 137.5MB in the end (delta: -67.0MB). Peak memory consumption was 9.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 43.68ms. Allocated memory is still 174.1MB. Free memory was 137.5MB in the beginning and 135.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 37.35ms. Allocated memory is still 174.1MB. Free memory was 135.4MB in the beginning and 133.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 718.54ms. Allocated memory is still 174.1MB. Free memory was 133.3MB in the beginning and 134.2MB in the end (delta: -883.6kB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 3949.95ms. Allocated memory was 174.1MB in the beginning and 209.7MB in the end (delta: 35.7MB). Free memory was 134.2MB in the beginning and 127.4MB in the end (delta: 6.9MB). Peak memory consumption was 44.6MB. Max. memory is 16.1GB. * Witness Printer took 67.71ms. Allocated memory is still 209.7MB. Free memory was 127.4MB in the beginning and 123.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1272 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.8s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.2s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 10 MinimizatonAttempts, 1660 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1998 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1998 mSDsluCounter, 3046 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1683 mSDsCounter, 71 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 229 IncrementalHoareTripleChecker+Invalid, 300 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 71 mSolverCounterUnsat, 1363 mSDtfsCounter, 229 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-25 17:17:59,120 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6e25836a-d8bf-4497-8b57-016f11cb9c5d/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)