./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-25 17:59:20,237 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-25 17:59:20,239 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-25 17:59:20,268 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-25 17:59:20,271 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-25 17:59:20,273 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-25 17:59:20,275 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-25 17:59:20,279 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-25 17:59:20,282 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-25 17:59:20,283 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-25 17:59:20,285 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-25 17:59:20,286 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-25 17:59:20,288 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-25 17:59:20,291 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-25 17:59:20,295 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-25 17:59:20,297 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-25 17:59:20,299 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-25 17:59:20,303 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-25 17:59:20,305 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-25 17:59:20,306 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-25 17:59:20,308 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-25 17:59:20,311 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-25 17:59:20,315 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-25 17:59:20,317 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-25 17:59:20,321 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-25 17:59:20,330 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-25 17:59:20,330 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-25 17:59:20,331 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-25 17:59:20,332 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-25 17:59:20,333 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-25 17:59:20,333 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-25 17:59:20,334 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-25 17:59:20,336 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-25 17:59:20,337 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-25 17:59:20,339 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-25 17:59:20,340 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-25 17:59:20,341 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-25 17:59:20,341 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-25 17:59:20,342 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-25 17:59:20,344 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-25 17:59:20,344 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-25 17:59:20,345 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-25 17:59:20,367 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-25 17:59:20,367 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-25 17:59:20,367 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-25 17:59:20,367 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-25 17:59:20,368 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-25 17:59:20,369 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-25 17:59:20,369 INFO L138 SettingsManager]: * Use SBE=true [2022-11-25 17:59:20,369 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-25 17:59:20,369 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-25 17:59:20,369 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-25 17:59:20,370 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-25 17:59:20,371 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-25 17:59:20,371 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-25 17:59:20,371 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-25 17:59:20,371 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-25 17:59:20,371 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-25 17:59:20,372 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-25 17:59:20,373 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-25 17:59:20,373 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-25 17:59:20,373 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-25 17:59:20,373 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-25 17:59:20,373 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-25 17:59:20,373 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-25 17:59:20,374 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-25 17:59:20,374 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-25 17:59:20,374 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-25 17:59:20,376 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-25 17:59:20,376 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2022-11-25 17:59:20,699 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-25 17:59:20,737 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-25 17:59:20,740 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-25 17:59:20,741 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-25 17:59:20,741 INFO L275 PluginConnector]: CDTParser initialized [2022-11-25 17:59:20,743 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2022-11-25 17:59:23,713 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-25 17:59:23,917 INFO L351 CDTParser]: Found 1 translation units. [2022-11-25 17:59:23,917 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2022-11-25 17:59:23,928 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/data/f59b906f4/ba12cd7e2ab64f66a7f1aa9b5a23ee83/FLAGb2528ebd0 [2022-11-25 17:59:23,953 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/data/f59b906f4/ba12cd7e2ab64f66a7f1aa9b5a23ee83 [2022-11-25 17:59:23,958 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-25 17:59:23,960 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-25 17:59:23,971 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-25 17:59:23,973 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-25 17:59:23,979 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-25 17:59:23,980 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:59:23" (1/1) ... [2022-11-25 17:59:23,981 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c2c89ba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:23, skipping insertion in model container [2022-11-25 17:59:23,981 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:59:23" (1/1) ... [2022-11-25 17:59:23,990 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-25 17:59:24,048 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-25 17:59:24,242 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2022-11-25 17:59:24,339 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:59:24,354 INFO L203 MainTranslator]: Completed pre-run [2022-11-25 17:59:24,372 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2022-11-25 17:59:24,439 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:59:24,456 INFO L208 MainTranslator]: Completed translation [2022-11-25 17:59:24,457 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24 WrapperNode [2022-11-25 17:59:24,459 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-25 17:59:24,460 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-25 17:59:24,460 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-25 17:59:24,461 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-25 17:59:24,467 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,481 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,533 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1353 [2022-11-25 17:59:24,533 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-25 17:59:24,534 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-25 17:59:24,534 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-25 17:59:24,534 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-25 17:59:24,544 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,544 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,550 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,550 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,567 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,580 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,585 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,589 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,597 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-25 17:59:24,598 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-25 17:59:24,598 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-25 17:59:24,598 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-25 17:59:24,599 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (1/1) ... [2022-11-25 17:59:24,620 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-25 17:59:24,632 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 17:59:24,668 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-25 17:59:24,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-25 17:59:24,715 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-25 17:59:24,715 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-25 17:59:24,715 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-25 17:59:24,716 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-25 17:59:24,894 INFO L235 CfgBuilder]: Building ICFG [2022-11-25 17:59:24,896 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-25 17:59:26,150 INFO L276 CfgBuilder]: Performing block encoding [2022-11-25 17:59:26,179 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-25 17:59:26,180 INFO L300 CfgBuilder]: Removed 8 assume(true) statements. [2022-11-25 17:59:26,183 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:59:26 BoogieIcfgContainer [2022-11-25 17:59:26,185 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-25 17:59:26,186 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-25 17:59:26,187 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-25 17:59:26,191 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-25 17:59:26,191 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:59:26,192 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 05:59:23" (1/3) ... [2022-11-25 17:59:26,193 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38d45bf9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:59:26, skipping insertion in model container [2022-11-25 17:59:26,193 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:59:26,194 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:59:24" (2/3) ... [2022-11-25 17:59:26,196 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38d45bf9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:59:26, skipping insertion in model container [2022-11-25 17:59:26,196 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:59:26,196 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:59:26" (3/3) ... [2022-11-25 17:59:26,203 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2022-11-25 17:59:26,304 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-25 17:59:26,304 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-25 17:59:26,304 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-25 17:59:26,304 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-25 17:59:26,304 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-25 17:59:26,305 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-25 17:59:26,305 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-25 17:59:26,305 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-25 17:59:26,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:26,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2022-11-25 17:59:26,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:26,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:26,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-25 17:59:26,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:26,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2022-11-25 17:59:26,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:26,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:26,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,402 INFO L748 eck$LassoCheckResult]: Stem: 540#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 466#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 249#L903true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6#L419true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 261#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 318#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 148#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 312#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 134#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 501#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 353#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 204#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 377#L611-2true assume !(0 == ~T1_E~0); 371#L616-1true assume !(0 == ~T2_E~0); 384#L621-1true assume !(0 == ~T3_E~0); 67#L626-1true assume !(0 == ~T4_E~0); 343#L631-1true assume !(0 == ~T5_E~0); 173#L636-1true assume !(0 == ~E_M~0); 88#L641-1true assume !(0 == ~E_1~0); 184#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 491#L651-1true assume !(0 == ~E_3~0); 442#L656-1true assume !(0 == ~E_4~0); 351#L661-1true assume !(0 == ~E_5~0); 401#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523#L304true assume !(1 == ~m_pc~0); 98#L304-2true is_master_triggered_~__retres1~0#1 := 0; 55#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#L316true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28#L755true assume !(0 != activate_threads_~tmp~1#1); 546#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7#L323true assume 1 == ~t1_pc~0; 298#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310#L335true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 492#L763true assume !(0 != activate_threads_~tmp___0~0#1); 503#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40#L342true assume 1 == ~t2_pc~0; 520#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 482#L354true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 525#L771true assume !(0 != activate_threads_~tmp___1~0#1); 344#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L361true assume !(1 == ~t3_pc~0); 251#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 459#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126#L373true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 433#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231#L380true assume 1 == ~t4_pc~0; 78#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 365#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 471#L392true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268#L787true assume !(0 != activate_threads_~tmp___3~0#1); 518#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79#L399true assume !(1 == ~t5_pc~0); 154#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 380#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481#L411true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149#L795true assume !(0 != activate_threads_~tmp___4~0#1); 453#L795-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 526#L679true assume !(1 == ~M_E~0); 202#L679-2true assume !(1 == ~T1_E~0); 109#L684-1true assume !(1 == ~T2_E~0); 240#L689-1true assume !(1 == ~T3_E~0); 535#L694-1true assume !(1 == ~T4_E~0); 239#L699-1true assume !(1 == ~T5_E~0); 352#L704-1true assume !(1 == ~E_M~0); 220#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 176#L714-1true assume !(1 == ~E_2~0); 335#L719-1true assume !(1 == ~E_3~0); 477#L724-1true assume !(1 == ~E_4~0); 61#L729-1true assume !(1 == ~E_5~0); 462#L734-1true assume { :end_inline_reset_delta_events } true; 325#L940-2true [2022-11-25 17:59:26,404 INFO L750 eck$LassoCheckResult]: Loop: 325#L940-2true assume !false; 395#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107#L586true assume !true; 484#L601true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 415#L419-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 62#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 306#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 59#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 31#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 555#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 32#L636-3true assume !(0 == ~E_M~0); 68#L641-3true assume 0 == ~E_1~0;~E_1~0 := 1; 236#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 74#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 212#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 493#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 505#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151#L304-21true assume 1 == ~m_pc~0; 516#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 264#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506#L316-7true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194#L755-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 214#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 489#L323-21true assume 1 == ~t1_pc~0; 15#L324-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 402#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 311#L335-7true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 420#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 552#L342-21true assume 1 == ~t2_pc~0; 26#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 256#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390#L354-7true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 346#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472#L361-21true assume !(1 == ~t3_pc~0); 455#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 476#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 367#L373-7true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514#L380-21true assume !(1 == ~t4_pc~0); 65#L380-23true is_transmit4_triggered_~__retres1~4#1 := 0; 94#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320#L392-7true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 334#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 270#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139#L399-21true assume 1 == ~t5_pc~0; 122#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418#L411-7true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 498#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 447#L795-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 181#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 164#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L699-3true assume !(1 == ~T5_E~0); 296#L704-3true assume 1 == ~E_M~0;~E_M~0 := 2; 394#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 287#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 158#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 20#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 274#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 315#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 37#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 213#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44#L497-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 248#L959true assume !(0 == start_simulation_~tmp~3#1); 513#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 178#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 375#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 456#L497-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 362#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 120#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 542#L922true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 297#L972true assume !(0 != start_simulation_~tmp___0~1#1); 325#L940-2true [2022-11-25 17:59:26,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:26,410 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2022-11-25 17:59:26,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:26,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558018370] [2022-11-25 17:59:26,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:26,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:26,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:26,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:26,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:26,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558018370] [2022-11-25 17:59:26,696 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558018370] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:26,696 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:26,696 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:26,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128221357] [2022-11-25 17:59:26,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:26,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:26,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:26,705 INFO L85 PathProgramCache]: Analyzing trace with hash 2078945365, now seen corresponding path program 1 times [2022-11-25 17:59:26,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:26,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637869366] [2022-11-25 17:59:26,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:26,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:26,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:26,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:26,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:26,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637869366] [2022-11-25 17:59:26,747 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637869366] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:26,747 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:26,748 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:59:26,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672707823] [2022-11-25 17:59:26,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:26,750 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:26,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:26,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:26,784 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:26,787 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.5304659498207884) internal successors, (854), 558 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:26,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:26,848 INFO L93 Difference]: Finished difference Result 557 states and 833 transitions. [2022-11-25 17:59:26,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 833 transitions. [2022-11-25 17:59:26,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:26,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 551 states and 827 transitions. [2022-11-25 17:59:26,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-11-25 17:59:26,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-11-25 17:59:26,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 827 transitions. [2022-11-25 17:59:26,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:26,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-11-25 17:59:26,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 827 transitions. [2022-11-25 17:59:26,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-11-25 17:59:26,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.5009074410163339) internal successors, (827), 550 states have internal predecessors, (827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:26,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 827 transitions. [2022-11-25 17:59:26,965 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-11-25 17:59:26,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:26,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 827 transitions. [2022-11-25 17:59:26,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-25 17:59:26,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 827 transitions. [2022-11-25 17:59:26,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:26,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:26,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:26,992 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,992 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:26,994 INFO L748 eck$LassoCheckResult]: Stem: 1675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1540#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1135#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1136#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1548#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1403#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1404#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1381#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1382#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1611#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1485#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1486#L611-2 assume !(0 == ~T1_E~0); 1622#L616-1 assume !(0 == ~T2_E~0); 1623#L621-1 assume !(0 == ~T3_E~0); 1257#L626-1 assume !(0 == ~T4_E~0); 1258#L631-1 assume !(0 == ~T5_E~0); 1443#L636-1 assume !(0 == ~E_M~0); 1301#L641-1 assume !(0 == ~E_1~0); 1302#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1460#L651-1 assume !(0 == ~E_3~0); 1655#L656-1 assume !(0 == ~E_4~0); 1609#L661-1 assume !(0 == ~E_5~0); 1610#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1635#L304 assume !(1 == ~m_pc~0); 1319#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1233#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1179#L755 assume !(0 != activate_threads_~tmp~1#1); 1180#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1137#L323 assume 1 == ~t1_pc~0; 1138#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1202#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1203#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1583#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1671#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1205#L342 assume 1 == ~t2_pc~0; 1206#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1324#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1667#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1605#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1520#L361 assume !(1 == ~t3_pc~0); 1521#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1541#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1367#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1220#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1221#L380 assume 1 == ~t4_pc~0; 1278#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1279#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1616#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1552#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1553#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1281#L399 assume !(1 == ~t5_pc~0); 1282#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1415#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1625#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1405#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1406#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1661#L679 assume !(1 == ~M_E~0); 1483#L679-2 assume !(1 == ~T1_E~0); 1337#L684-1 assume !(1 == ~T2_E~0); 1338#L689-1 assume !(1 == ~T3_E~0); 1529#L694-1 assume !(1 == ~T4_E~0); 1527#L699-1 assume !(1 == ~T5_E~0); 1528#L704-1 assume !(1 == ~E_M~0); 1506#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1450#L714-1 assume !(1 == ~E_2~0); 1451#L719-1 assume !(1 == ~E_3~0); 1601#L724-1 assume !(1 == ~E_4~0); 1243#L729-1 assume !(1 == ~E_5~0); 1244#L734-1 assume { :end_inline_reset_delta_events } true; 1573#L940-2 [2022-11-25 17:59:26,995 INFO L750 eck$LassoCheckResult]: Loop: 1573#L940-2 assume !false; 1593#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1333#L586 assume !false; 1334#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1659#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1524#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1525#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1515#L511 assume !(0 != eval_~tmp~0#1); 1516#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1644#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1570#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1245#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1241#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1186#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1187#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1188#L636-3 assume !(0 == ~E_M~0); 1189#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1259#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1269#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1270#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1500#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1672#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1410#L304-21 assume 1 == ~m_pc~0; 1411#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1274#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1549#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1473#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1474#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1501#L323-21 assume 1 == ~t1_pc~0; 1150#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1152#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1584#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1585#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1634#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1648#L342-21 assume 1 == ~t2_pc~0; 1174#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1175#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1545#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1606#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1284#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1285#L361-21 assume 1 == ~t3_pc~0; 1666#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1663#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1617#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1446#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1184#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1185#L380-21 assume !(1 == ~t4_pc~0); 1251#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 1252#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1311#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1589#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1555#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1391#L399-21 assume !(1 == ~t5_pc~0); 1255#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1256#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1565#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1646#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1658#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1177#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1178#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1456#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1125#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1126#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1164#L699-3 assume !(1 == ~T5_E~0); 1165#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1571#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1567#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1416#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1162#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1163#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1560#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1197#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1198#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1212#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1213#L959 assume !(0 == start_simulation_~tmp~3#1); 1539#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1447#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1448#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1624#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1614#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1357#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1358#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1572#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1573#L940-2 [2022-11-25 17:59:26,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:26,996 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2022-11-25 17:59:26,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:26,996 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983599517] [2022-11-25 17:59:26,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:26,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,094 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983599517] [2022-11-25 17:59:27,094 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983599517] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,095 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,095 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740558981] [2022-11-25 17:59:27,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,096 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:27,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,096 INFO L85 PathProgramCache]: Analyzing trace with hash 602778604, now seen corresponding path program 1 times [2022-11-25 17:59:27,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257802992] [2022-11-25 17:59:27,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257802992] [2022-11-25 17:59:27,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257802992] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,204 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,205 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205449544] [2022-11-25 17:59:27,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,205 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:27,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:27,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:27,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:27,207 INFO L87 Difference]: Start difference. First operand 551 states and 827 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:27,251 INFO L93 Difference]: Finished difference Result 551 states and 826 transitions. [2022-11-25 17:59:27,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 826 transitions. [2022-11-25 17:59:27,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 826 transitions. [2022-11-25 17:59:27,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-11-25 17:59:27,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-11-25 17:59:27,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 826 transitions. [2022-11-25 17:59:27,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:27,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-11-25 17:59:27,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 826 transitions. [2022-11-25 17:59:27,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-11-25 17:59:27,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4990925589836661) internal successors, (826), 550 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 826 transitions. [2022-11-25 17:59:27,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-11-25 17:59:27,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:27,305 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 826 transitions. [2022-11-25 17:59:27,305 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-25 17:59:27,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 826 transitions. [2022-11-25 17:59:27,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:27,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:27,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,317 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,319 INFO L748 eck$LassoCheckResult]: Stem: 2784#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2649#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2244#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2245#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2657#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2512#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2513#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2490#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2491#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2720#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2594#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2595#L611-2 assume !(0 == ~T1_E~0); 2731#L616-1 assume !(0 == ~T2_E~0); 2732#L621-1 assume !(0 == ~T3_E~0); 2366#L626-1 assume !(0 == ~T4_E~0); 2367#L631-1 assume !(0 == ~T5_E~0); 2555#L636-1 assume !(0 == ~E_M~0); 2410#L641-1 assume !(0 == ~E_1~0); 2411#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2569#L651-1 assume !(0 == ~E_3~0); 2764#L656-1 assume !(0 == ~E_4~0); 2718#L661-1 assume !(0 == ~E_5~0); 2719#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2744#L304 assume !(1 == ~m_pc~0); 2428#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2342#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2343#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2290#L755 assume !(0 != activate_threads_~tmp~1#1); 2291#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2246#L323 assume 1 == ~t1_pc~0; 2247#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2311#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2312#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2692#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2318#L342 assume 1 == ~t2_pc~0; 2319#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2433#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2434#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2776#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2714#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2629#L361 assume !(1 == ~t3_pc~0); 2630#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2650#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2475#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2476#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2329#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2330#L380 assume 1 == ~t4_pc~0; 2387#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2388#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2725#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2662#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2663#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2390#L399 assume !(1 == ~t5_pc~0); 2391#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2524#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2734#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2514#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2515#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2770#L679 assume !(1 == ~M_E~0); 2592#L679-2 assume !(1 == ~T1_E~0); 2446#L684-1 assume !(1 == ~T2_E~0); 2447#L689-1 assume !(1 == ~T3_E~0); 2638#L694-1 assume !(1 == ~T4_E~0); 2636#L699-1 assume !(1 == ~T5_E~0); 2637#L704-1 assume !(1 == ~E_M~0); 2615#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2559#L714-1 assume !(1 == ~E_2~0); 2560#L719-1 assume !(1 == ~E_3~0); 2710#L724-1 assume !(1 == ~E_4~0); 2352#L729-1 assume !(1 == ~E_5~0); 2353#L734-1 assume { :end_inline_reset_delta_events } true; 2682#L940-2 [2022-11-25 17:59:27,321 INFO L750 eck$LassoCheckResult]: Loop: 2682#L940-2 assume !false; 2702#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2444#L586 assume !false; 2445#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2768#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2633#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2634#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2624#L511 assume !(0 != eval_~tmp~0#1); 2625#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2753#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2679#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2354#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2355#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2351#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2295#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2296#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2297#L636-3 assume !(0 == ~E_M~0); 2298#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2368#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2378#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2379#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2609#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2781#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2519#L304-21 assume 1 == ~m_pc~0; 2520#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2383#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2658#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2582#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2583#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2610#L323-21 assume 1 == ~t1_pc~0; 2259#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2261#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2693#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2694#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2743#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2757#L342-21 assume 1 == ~t2_pc~0; 2283#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2284#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2654#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2715#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2393#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2394#L361-21 assume !(1 == ~t3_pc~0); 2771#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2772#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2726#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2554#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2288#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2289#L380-21 assume !(1 == ~t4_pc~0); 2358#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 2359#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2420#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2698#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2664#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2500#L399-21 assume 1 == ~t5_pc~0; 2468#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2365#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2674#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2755#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2767#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2286#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2287#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2565#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2234#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2235#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2273#L699-3 assume !(1 == ~T5_E~0); 2274#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2680#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2676#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2526#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2271#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2272#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2669#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2306#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2307#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2321#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2322#L959 assume !(0 == start_simulation_~tmp~3#1); 2648#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2556#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2557#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2733#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2723#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2466#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2467#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2681#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2682#L940-2 [2022-11-25 17:59:27,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2022-11-25 17:59:27,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736538770] [2022-11-25 17:59:27,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736538770] [2022-11-25 17:59:27,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736538770] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885369844] [2022-11-25 17:59:27,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:27,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,430 INFO L85 PathProgramCache]: Analyzing trace with hash -22187412, now seen corresponding path program 1 times [2022-11-25 17:59:27,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934478141] [2022-11-25 17:59:27,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934478141] [2022-11-25 17:59:27,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934478141] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,489 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,489 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844673286] [2022-11-25 17:59:27,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,490 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:27,491 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:27,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:27,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:27,492 INFO L87 Difference]: Start difference. First operand 551 states and 826 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:27,510 INFO L93 Difference]: Finished difference Result 551 states and 825 transitions. [2022-11-25 17:59:27,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 825 transitions. [2022-11-25 17:59:27,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 825 transitions. [2022-11-25 17:59:27,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-11-25 17:59:27,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-11-25 17:59:27,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 825 transitions. [2022-11-25 17:59:27,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:27,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-11-25 17:59:27,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 825 transitions. [2022-11-25 17:59:27,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-11-25 17:59:27,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4972776769509981) internal successors, (825), 550 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 825 transitions. [2022-11-25 17:59:27,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-11-25 17:59:27,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:27,536 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 825 transitions. [2022-11-25 17:59:27,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-25 17:59:27,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 825 transitions. [2022-11-25 17:59:27,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:27,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:27,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,543 INFO L748 eck$LassoCheckResult]: Stem: 3893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3758#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3353#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3354#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3766#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3621#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3622#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3599#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3829#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3703#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3704#L611-2 assume !(0 == ~T1_E~0); 3840#L616-1 assume !(0 == ~T2_E~0); 3841#L621-1 assume !(0 == ~T3_E~0); 3475#L626-1 assume !(0 == ~T4_E~0); 3476#L631-1 assume !(0 == ~T5_E~0); 3664#L636-1 assume !(0 == ~E_M~0); 3519#L641-1 assume !(0 == ~E_1~0); 3520#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3678#L651-1 assume !(0 == ~E_3~0); 3873#L656-1 assume !(0 == ~E_4~0); 3827#L661-1 assume !(0 == ~E_5~0); 3828#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3853#L304 assume !(1 == ~m_pc~0); 3539#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3451#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3452#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3399#L755 assume !(0 != activate_threads_~tmp~1#1); 3400#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3355#L323 assume 1 == ~t1_pc~0; 3356#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3420#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3421#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3803#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3889#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3427#L342 assume 1 == ~t2_pc~0; 3428#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3542#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3543#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3885#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3823#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3738#L361 assume !(1 == ~t3_pc~0); 3739#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3759#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3584#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3585#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3438#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3439#L380 assume 1 == ~t4_pc~0; 3496#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3497#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3834#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3771#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3772#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3499#L399 assume !(1 == ~t5_pc~0); 3500#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3633#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3843#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3623#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3624#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3879#L679 assume !(1 == ~M_E~0); 3701#L679-2 assume !(1 == ~T1_E~0); 3555#L684-1 assume !(1 == ~T2_E~0); 3556#L689-1 assume !(1 == ~T3_E~0); 3747#L694-1 assume !(1 == ~T4_E~0); 3745#L699-1 assume !(1 == ~T5_E~0); 3746#L704-1 assume !(1 == ~E_M~0); 3724#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3668#L714-1 assume !(1 == ~E_2~0); 3669#L719-1 assume !(1 == ~E_3~0); 3819#L724-1 assume !(1 == ~E_4~0); 3461#L729-1 assume !(1 == ~E_5~0); 3462#L734-1 assume { :end_inline_reset_delta_events } true; 3791#L940-2 [2022-11-25 17:59:27,543 INFO L750 eck$LassoCheckResult]: Loop: 3791#L940-2 assume !false; 3811#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3553#L586 assume !false; 3554#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3877#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3742#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3743#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3733#L511 assume !(0 != eval_~tmp~0#1); 3734#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3862#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3788#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3463#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3464#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3460#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3404#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3405#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3406#L636-3 assume !(0 == ~E_M~0); 3407#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3477#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3487#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3488#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3718#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3890#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3628#L304-21 assume !(1 == ~m_pc~0); 3491#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3492#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3768#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3691#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3692#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3719#L323-21 assume 1 == ~t1_pc~0; 3368#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3370#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3801#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3802#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3852#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3866#L342-21 assume 1 == ~t2_pc~0; 3392#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3393#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3763#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3824#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3502#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3503#L361-21 assume !(1 == ~t3_pc~0); 3880#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3881#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3835#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3663#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3397#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3398#L380-21 assume !(1 == ~t4_pc~0); 3467#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 3468#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3529#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3807#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3773#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3609#L399-21 assume !(1 == ~t5_pc~0); 3473#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3474#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3783#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3864#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3876#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3395#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3396#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3674#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3343#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3344#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3382#L699-3 assume !(1 == ~T5_E~0); 3383#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3789#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3785#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3635#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3380#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3381#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3778#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3415#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3416#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3430#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3431#L959 assume !(0 == start_simulation_~tmp~3#1); 3757#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3665#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3666#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3842#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3832#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3575#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3576#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3790#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3791#L940-2 [2022-11-25 17:59:27,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,544 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2022-11-25 17:59:27,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242274448] [2022-11-25 17:59:27,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242274448] [2022-11-25 17:59:27,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242274448] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,600 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592094844] [2022-11-25 17:59:27,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:27,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,602 INFO L85 PathProgramCache]: Analyzing trace with hash -765126226, now seen corresponding path program 1 times [2022-11-25 17:59:27,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266220021] [2022-11-25 17:59:27,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266220021] [2022-11-25 17:59:27,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266220021] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973468036] [2022-11-25 17:59:27,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,676 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:27,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:27,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:27,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:27,677 INFO L87 Difference]: Start difference. First operand 551 states and 825 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:27,693 INFO L93 Difference]: Finished difference Result 551 states and 824 transitions. [2022-11-25 17:59:27,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 824 transitions. [2022-11-25 17:59:27,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 824 transitions. [2022-11-25 17:59:27,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-11-25 17:59:27,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-11-25 17:59:27,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 824 transitions. [2022-11-25 17:59:27,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:27,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-11-25 17:59:27,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 824 transitions. [2022-11-25 17:59:27,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-11-25 17:59:27,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4954627949183303) internal successors, (824), 550 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 824 transitions. [2022-11-25 17:59:27,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-11-25 17:59:27,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:27,716 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 824 transitions. [2022-11-25 17:59:27,716 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-25 17:59:27,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 824 transitions. [2022-11-25 17:59:27,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:27,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:27,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,728 INFO L748 eck$LassoCheckResult]: Stem: 5002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4867#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4464#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4465#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4875#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4730#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4731#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4708#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4709#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4938#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4812#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4813#L611-2 assume !(0 == ~T1_E~0); 4949#L616-1 assume !(0 == ~T2_E~0); 4950#L621-1 assume !(0 == ~T3_E~0); 4584#L626-1 assume !(0 == ~T4_E~0); 4585#L631-1 assume !(0 == ~T5_E~0); 4773#L636-1 assume !(0 == ~E_M~0); 4628#L641-1 assume !(0 == ~E_1~0); 4629#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4787#L651-1 assume !(0 == ~E_3~0); 4982#L656-1 assume !(0 == ~E_4~0); 4936#L661-1 assume !(0 == ~E_5~0); 4937#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4962#L304 assume !(1 == ~m_pc~0); 4648#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4560#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4561#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4508#L755 assume !(0 != activate_threads_~tmp~1#1); 4509#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4466#L323 assume 1 == ~t1_pc~0; 4467#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4529#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4530#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4912#L763 assume !(0 != activate_threads_~tmp___0~0#1); 4998#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4536#L342 assume 1 == ~t2_pc~0; 4537#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4651#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4652#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4994#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4932#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4847#L361 assume !(1 == ~t3_pc~0); 4848#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4868#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4693#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4694#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4547#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4548#L380 assume 1 == ~t4_pc~0; 4605#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4606#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4943#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4880#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4881#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4608#L399 assume !(1 == ~t5_pc~0); 4609#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4742#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4952#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4732#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4733#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4988#L679 assume !(1 == ~M_E~0); 4811#L679-2 assume !(1 == ~T1_E~0); 4664#L684-1 assume !(1 == ~T2_E~0); 4665#L689-1 assume !(1 == ~T3_E~0); 4856#L694-1 assume !(1 == ~T4_E~0); 4854#L699-1 assume !(1 == ~T5_E~0); 4855#L704-1 assume !(1 == ~E_M~0); 4833#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4778#L714-1 assume !(1 == ~E_2~0); 4779#L719-1 assume !(1 == ~E_3~0); 4928#L724-1 assume !(1 == ~E_4~0); 4570#L729-1 assume !(1 == ~E_5~0); 4571#L734-1 assume { :end_inline_reset_delta_events } true; 4900#L940-2 [2022-11-25 17:59:27,728 INFO L750 eck$LassoCheckResult]: Loop: 4900#L940-2 assume !false; 4920#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4662#L586 assume !false; 4663#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4986#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4851#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4852#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4843#L511 assume !(0 != eval_~tmp~0#1); 4844#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4971#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4897#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4572#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4573#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4569#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4513#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4514#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4515#L636-3 assume !(0 == ~E_M~0); 4516#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4586#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4596#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4597#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4827#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4999#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4737#L304-21 assume 1 == ~m_pc~0; 4738#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4601#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4876#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4800#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4801#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4828#L323-21 assume 1 == ~t1_pc~0; 4477#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4479#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4911#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4961#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4975#L342-21 assume 1 == ~t2_pc~0; 4501#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4502#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4872#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4933#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4611#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4612#L361-21 assume 1 == ~t3_pc~0; 4993#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4990#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4944#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4772#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4506#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4507#L380-21 assume !(1 == ~t4_pc~0); 4578#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4579#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4638#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4916#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4882#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4718#L399-21 assume !(1 == ~t5_pc~0); 4582#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4583#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4892#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4973#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4985#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4504#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4505#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4783#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4452#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4453#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4491#L699-3 assume !(1 == ~T5_E~0); 4492#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4898#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4894#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4744#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4489#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4490#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4887#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4526#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4527#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4541#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4542#L959 assume !(0 == start_simulation_~tmp~3#1); 4866#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4775#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4776#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4951#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4941#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4684#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4685#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4899#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4900#L940-2 [2022-11-25 17:59:27,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,729 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2022-11-25 17:59:27,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840311742] [2022-11-25 17:59:27,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840311742] [2022-11-25 17:59:27,793 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840311742] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,794 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [229815136] [2022-11-25 17:59:27,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,796 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:27,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,797 INFO L85 PathProgramCache]: Analyzing trace with hash 602778604, now seen corresponding path program 2 times [2022-11-25 17:59:27,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,798 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689795518] [2022-11-25 17:59:27,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:27,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:27,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:27,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689795518] [2022-11-25 17:59:27,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689795518] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:27,905 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:27,905 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:27,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220509977] [2022-11-25 17:59:27,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:27,906 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:27,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:27,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:27,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:27,909 INFO L87 Difference]: Start difference. First operand 551 states and 824 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:27,926 INFO L93 Difference]: Finished difference Result 551 states and 823 transitions. [2022-11-25 17:59:27,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 823 transitions. [2022-11-25 17:59:27,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 823 transitions. [2022-11-25 17:59:27,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-11-25 17:59:27,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-11-25 17:59:27,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 823 transitions. [2022-11-25 17:59:27,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:27,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-11-25 17:59:27,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 823 transitions. [2022-11-25 17:59:27,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-11-25 17:59:27,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4936479128856623) internal successors, (823), 550 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:27,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 823 transitions. [2022-11-25 17:59:27,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-11-25 17:59:27,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:27,952 INFO L428 stractBuchiCegarLoop]: Abstraction has 551 states and 823 transitions. [2022-11-25 17:59:27,952 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-25 17:59:27,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 823 transitions. [2022-11-25 17:59:27,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 472 [2022-11-25 17:59:27,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:27,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:27,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:27,961 INFO L748 eck$LassoCheckResult]: Stem: 6111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5976#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5573#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5574#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 5984#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5839#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5840#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5817#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5818#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6047#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5922#L611-2 assume !(0 == ~T1_E~0); 6058#L616-1 assume !(0 == ~T2_E~0); 6059#L621-1 assume !(0 == ~T3_E~0); 5697#L626-1 assume !(0 == ~T4_E~0); 5698#L631-1 assume !(0 == ~T5_E~0); 5882#L636-1 assume !(0 == ~E_M~0); 5739#L641-1 assume !(0 == ~E_1~0); 5740#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5896#L651-1 assume !(0 == ~E_3~0); 6091#L656-1 assume !(0 == ~E_4~0); 6045#L661-1 assume !(0 == ~E_5~0); 6046#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6071#L304 assume !(1 == ~m_pc~0); 5758#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5669#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5670#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5620#L755 assume !(0 != activate_threads_~tmp~1#1); 5621#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5575#L323 assume 1 == ~t1_pc~0; 5576#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5638#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5639#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6021#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6107#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5645#L342 assume 1 == ~t2_pc~0; 5646#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5760#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5761#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6103#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6041#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5956#L361 assume !(1 == ~t3_pc~0); 5957#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5977#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5802#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5803#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5656#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5657#L380 assume 1 == ~t4_pc~0; 5714#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5715#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6052#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5989#L787 assume !(0 != activate_threads_~tmp___3~0#1); 5990#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5717#L399 assume !(1 == ~t5_pc~0); 5718#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5851#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6062#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5841#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5842#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6097#L679 assume !(1 == ~M_E~0); 5920#L679-2 assume !(1 == ~T1_E~0); 5773#L684-1 assume !(1 == ~T2_E~0); 5774#L689-1 assume !(1 == ~T3_E~0); 5965#L694-1 assume !(1 == ~T4_E~0); 5963#L699-1 assume !(1 == ~T5_E~0); 5964#L704-1 assume !(1 == ~E_M~0); 5942#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5887#L714-1 assume !(1 == ~E_2~0); 5888#L719-1 assume !(1 == ~E_3~0); 6037#L724-1 assume !(1 == ~E_4~0); 5679#L729-1 assume !(1 == ~E_5~0); 5680#L734-1 assume { :end_inline_reset_delta_events } true; 6010#L940-2 [2022-11-25 17:59:27,961 INFO L750 eck$LassoCheckResult]: Loop: 6010#L940-2 assume !false; 6029#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5771#L586 assume !false; 5772#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6095#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5960#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5961#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5952#L511 assume !(0 != eval_~tmp~0#1); 5953#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6080#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6006#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5681#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5682#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5677#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5622#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5623#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5624#L636-3 assume !(0 == ~E_M~0); 5625#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5691#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5705#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5706#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5936#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6108#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5846#L304-21 assume 1 == ~m_pc~0; 5847#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5710#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5985#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5909#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5910#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5937#L323-21 assume 1 == ~t1_pc~0; 5586#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5588#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6019#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6020#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6070#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6084#L342-21 assume 1 == ~t2_pc~0; 5610#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5611#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5981#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6042#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5720#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5721#L361-21 assume !(1 == ~t3_pc~0); 6098#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6099#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6053#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5881#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5618#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5619#L380-21 assume !(1 == ~t4_pc~0); 5687#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5688#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5747#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6025#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5991#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5827#L399-21 assume 1 == ~t5_pc~0; 5796#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5696#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6001#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6083#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6094#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5613#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5614#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5892#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5561#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5562#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5600#L699-3 assume !(1 == ~T5_E~0); 5601#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6008#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6003#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5855#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5598#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5599#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5996#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5635#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5636#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5650#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5651#L959 assume !(0 == start_simulation_~tmp~3#1); 5975#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5884#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5885#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6060#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6050#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5793#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5794#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6009#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6010#L940-2 [2022-11-25 17:59:27,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:27,962 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2022-11-25 17:59:27,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:27,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413546512] [2022-11-25 17:59:27,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:27,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:27,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413546512] [2022-11-25 17:59:28,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413546512] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,018 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,018 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:59:28,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504693997] [2022-11-25 17:59:28,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:28,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,020 INFO L85 PathProgramCache]: Analyzing trace with hash -22187412, now seen corresponding path program 2 times [2022-11-25 17:59:28,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030846027] [2022-11-25 17:59:28,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030846027] [2022-11-25 17:59:28,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030846027] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,078 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,079 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:28,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445880264] [2022-11-25 17:59:28,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,080 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:28,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:28,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:28,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:28,081 INFO L87 Difference]: Start difference. First operand 551 states and 823 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:28,143 INFO L93 Difference]: Finished difference Result 979 states and 1457 transitions. [2022-11-25 17:59:28,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1457 transitions. [2022-11-25 17:59:28,150 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-11-25 17:59:28,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 979 states and 1457 transitions. [2022-11-25 17:59:28,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 979 [2022-11-25 17:59:28,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 979 [2022-11-25 17:59:28,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 979 states and 1457 transitions. [2022-11-25 17:59:28,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:28,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-11-25 17:59:28,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 979 states and 1457 transitions. [2022-11-25 17:59:28,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 979 to 979. [2022-11-25 17:59:28,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4882533197139938) internal successors, (1457), 978 states have internal predecessors, (1457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1457 transitions. [2022-11-25 17:59:28,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-11-25 17:59:28,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:28,188 INFO L428 stractBuchiCegarLoop]: Abstraction has 979 states and 1457 transitions. [2022-11-25 17:59:28,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-25 17:59:28,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1457 transitions. [2022-11-25 17:59:28,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-11-25 17:59:28,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:28,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:28,195 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,196 INFO L748 eck$LassoCheckResult]: Stem: 7706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7526#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7113#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7114#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7536#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7380#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7381#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7356#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7357#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7612#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7468#L611 assume !(0 == ~M_E~0); 7469#L611-2 assume !(0 == ~T1_E~0); 7624#L616-1 assume !(0 == ~T2_E~0); 7625#L621-1 assume !(0 == ~T3_E~0); 7235#L626-1 assume !(0 == ~T4_E~0); 7236#L631-1 assume !(0 == ~T5_E~0); 7427#L636-1 assume !(0 == ~E_M~0); 7277#L641-1 assume !(0 == ~E_1~0); 7278#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7442#L651-1 assume !(0 == ~E_3~0); 7674#L656-1 assume !(0 == ~E_4~0); 7610#L661-1 assume !(0 == ~E_5~0); 7611#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7643#L304 assume !(1 == ~m_pc~0); 7294#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7206#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7207#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7152#L755 assume !(0 != activate_threads_~tmp~1#1); 7153#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7106#L323 assume 1 == ~t1_pc~0; 7107#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7175#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7176#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7579#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7695#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7178#L342 assume 1 == ~t2_pc~0; 7179#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7299#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7300#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7689#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7606#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7506#L361 assume !(1 == ~t3_pc~0); 7507#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7527#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7341#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7342#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7191#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7192#L380 assume 1 == ~t4_pc~0; 7252#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7253#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7617#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7540#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7541#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7255#L399 assume !(1 == ~t5_pc~0); 7256#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7393#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7628#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7382#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7383#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7680#L679 assume !(1 == ~M_E~0); 7466#L679-2 assume !(1 == ~T1_E~0); 7312#L684-1 assume !(1 == ~T2_E~0); 7313#L689-1 assume !(1 == ~T3_E~0); 7515#L694-1 assume !(1 == ~T4_E~0); 7513#L699-1 assume !(1 == ~T5_E~0); 7514#L704-1 assume !(1 == ~E_M~0); 7491#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7428#L714-1 assume !(1 == ~E_2~0); 7429#L719-1 assume !(1 == ~E_3~0); 7602#L724-1 assume !(1 == ~E_4~0); 7217#L729-1 assume !(1 == ~E_5~0); 7218#L734-1 assume { :end_inline_reset_delta_events } true; 7567#L940-2 [2022-11-25 17:59:28,196 INFO L750 eck$LassoCheckResult]: Loop: 7567#L940-2 assume !false; 7591#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7308#L586 assume !false; 7309#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7678#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7593#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7742#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7740#L511 assume !(0 != eval_~tmp~0#1); 7739#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7738#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7563#L611-3 assume !(0 == ~M_E~0); 7219#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7220#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7576#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7735#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7734#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7733#L636-3 assume !(0 == ~E_M~0); 7732#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7731#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7730#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7729#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7728#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7727#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7726#L304-21 assume 1 == ~m_pc~0; 7703#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7248#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7698#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7485#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7486#L323-21 assume !(1 == ~t1_pc~0); 7692#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7644#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7645#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7639#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7640#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7722#L342-21 assume 1 == ~t2_pc~0; 7720#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7531#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7532#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7607#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7258#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7259#L361-21 assume !(1 == ~t3_pc~0); 7681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7619#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7425#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7426#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7714#L380-21 assume 1 == ~t4_pc~0; 7671#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7226#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7586#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7587#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7713#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7712#L399-21 assume !(1 == ~t5_pc~0); 7233#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7234#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7661#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7662#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7677#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7150#L679-3 assume !(1 == ~M_E~0); 7151#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8047#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7098#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7099#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7137#L699-3 assume !(1 == ~T5_E~0); 7138#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7565#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7560#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7398#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7135#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7136#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7549#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7583#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7484#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7187#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7188#L959 assume !(0 == start_simulation_~tmp~3#1); 7525#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7431#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7432#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7774#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7772#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7771#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7770#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7566#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7567#L940-2 [2022-11-25 17:59:28,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2022-11-25 17:59:28,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959753580] [2022-11-25 17:59:28,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959753580] [2022-11-25 17:59:28,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959753580] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,246 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,246 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:59:28,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407230349] [2022-11-25 17:59:28,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,246 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:28,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1295691757, now seen corresponding path program 1 times [2022-11-25 17:59:28,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130907076] [2022-11-25 17:59:28,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130907076] [2022-11-25 17:59:28,285 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130907076] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,285 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:28,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997754284] [2022-11-25 17:59:28,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,287 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:28,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:28,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:28,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:28,288 INFO L87 Difference]: Start difference. First operand 979 states and 1457 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:28,337 INFO L93 Difference]: Finished difference Result 979 states and 1435 transitions. [2022-11-25 17:59:28,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1435 transitions. [2022-11-25 17:59:28,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-11-25 17:59:28,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 979 states and 1435 transitions. [2022-11-25 17:59:28,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 979 [2022-11-25 17:59:28,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 979 [2022-11-25 17:59:28,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 979 states and 1435 transitions. [2022-11-25 17:59:28,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:28,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-11-25 17:59:28,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 979 states and 1435 transitions. [2022-11-25 17:59:28,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 979 to 979. [2022-11-25 17:59:28,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4657814096016344) internal successors, (1435), 978 states have internal predecessors, (1435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1435 transitions. [2022-11-25 17:59:28,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-11-25 17:59:28,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:28,374 INFO L428 stractBuchiCegarLoop]: Abstraction has 979 states and 1435 transitions. [2022-11-25 17:59:28,374 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-25 17:59:28,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1435 transitions. [2022-11-25 17:59:28,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2022-11-25 17:59:28,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:28,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:28,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,382 INFO L748 eck$LassoCheckResult]: Stem: 9660#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9489#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9075#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9076#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9498#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9343#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9344#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9319#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9320#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9571#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9431#L611 assume !(0 == ~M_E~0); 9432#L611-2 assume !(0 == ~T1_E~0); 9582#L616-1 assume !(0 == ~T2_E~0); 9583#L621-1 assume !(0 == ~T3_E~0); 9198#L626-1 assume !(0 == ~T4_E~0); 9199#L631-1 assume !(0 == ~T5_E~0); 9389#L636-1 assume !(0 == ~E_M~0); 9240#L641-1 assume !(0 == ~E_1~0); 9241#L646-1 assume !(0 == ~E_2~0); 9406#L651-1 assume !(0 == ~E_3~0); 9625#L656-1 assume !(0 == ~E_4~0); 9569#L661-1 assume !(0 == ~E_5~0); 9570#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9599#L304 assume !(1 == ~m_pc~0); 9260#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9170#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9171#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9121#L755 assume !(0 != activate_threads_~tmp~1#1); 9122#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9077#L323 assume 1 == ~t1_pc~0; 9078#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9139#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9140#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9538#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9647#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9146#L342 assume !(1 == ~t2_pc~0); 9148#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9262#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9263#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9640#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9564#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9469#L361 assume !(1 == ~t3_pc~0); 9470#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9490#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9304#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9305#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9157#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9158#L380 assume 1 == ~t4_pc~0; 9215#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9216#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9576#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9503#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9504#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9218#L399 assume !(1 == ~t5_pc~0); 9219#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9356#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9586#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9345#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9346#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9633#L679 assume !(1 == ~M_E~0); 9430#L679-2 assume !(1 == ~T1_E~0); 9275#L684-1 assume !(1 == ~T2_E~0); 9276#L689-1 assume !(1 == ~T3_E~0); 9478#L694-1 assume !(1 == ~T4_E~0); 9476#L699-1 assume !(1 == ~T5_E~0); 9477#L704-1 assume !(1 == ~E_M~0); 9454#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9396#L714-1 assume !(1 == ~E_2~0); 9397#L719-1 assume !(1 == ~E_3~0); 9559#L724-1 assume !(1 == ~E_4~0); 9180#L729-1 assume !(1 == ~E_5~0); 9181#L734-1 assume { :end_inline_reset_delta_events } true; 9526#L940-2 [2022-11-25 17:59:28,382 INFO L750 eck$LassoCheckResult]: Loop: 9526#L940-2 assume !false; 9598#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9273#L586 assume !false; 9274#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9697#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9473#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9474#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9662#L511 assume !(0 != eval_~tmp~0#1); 9693#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9610#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9611#L611-3 assume !(0 == ~M_E~0); 9692#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9533#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9178#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9123#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9124#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9125#L636-3 assume !(0 == ~E_M~0); 9126#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9192#L646-3 assume !(0 == ~E_2~0); 9206#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9207#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9684#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9683#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9682#L304-21 assume 1 == ~m_pc~0; 9657#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9211#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9499#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9652#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9448#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9449#L323-21 assume !(1 == ~t1_pc~0); 9644#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 9600#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9601#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9596#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9597#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9678#L342-21 assume !(1 == ~t2_pc~0); 9676#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9494#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9495#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9565#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9221#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9222#L361-21 assume !(1 == ~t3_pc~0); 9634#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 9635#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9639#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9670#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9119#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9120#L380-21 assume 1 == ~t4_pc~0; 9654#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9248#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9249#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9557#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9505#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9329#L399-21 assume 1 == ~t5_pc~0; 9330#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9516#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9517#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9666#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9665#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9114#L679-3 assume !(1 == ~M_E~0); 9115#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9880#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9878#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9876#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9874#L699-3 assume !(1 == ~T5_E~0); 9871#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9869#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9867#L714-3 assume !(1 == ~E_2~0); 9865#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9863#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9861#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9858#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9763#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9757#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9755#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9753#L959 assume !(0 == start_simulation_~tmp~3#1); 9749#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9726#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9720#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9719#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9718#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9710#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9706#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9525#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9526#L940-2 [2022-11-25 17:59:28,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,383 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2022-11-25 17:59:28,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890074652] [2022-11-25 17:59:28,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890074652] [2022-11-25 17:59:28,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890074652] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,459 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:28,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071511436] [2022-11-25 17:59:28,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,462 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:28,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,463 INFO L85 PathProgramCache]: Analyzing trace with hash -2079916563, now seen corresponding path program 1 times [2022-11-25 17:59:28,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428783828] [2022-11-25 17:59:28,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428783828] [2022-11-25 17:59:28,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428783828] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,541 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:28,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450673586] [2022-11-25 17:59:28,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,542 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:28,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:28,542 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:59:28,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:59:28,543 INFO L87 Difference]: Start difference. First operand 979 states and 1435 transitions. cyclomatic complexity: 457 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:28,766 INFO L93 Difference]: Finished difference Result 2612 states and 3762 transitions. [2022-11-25 17:59:28,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2612 states and 3762 transitions. [2022-11-25 17:59:28,785 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2437 [2022-11-25 17:59:28,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2612 states to 2612 states and 3762 transitions. [2022-11-25 17:59:28,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2612 [2022-11-25 17:59:28,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2612 [2022-11-25 17:59:28,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2612 states and 3762 transitions. [2022-11-25 17:59:28,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:28,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2612 states and 3762 transitions. [2022-11-25 17:59:28,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2612 states and 3762 transitions. [2022-11-25 17:59:28,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2612 to 2452. [2022-11-25 17:59:28,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2452 states, 2452 states have (on average 1.4469820554649266) internal successors, (3548), 2451 states have internal predecessors, (3548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:28,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2452 states to 2452 states and 3548 transitions. [2022-11-25 17:59:28,853 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2452 states and 3548 transitions. [2022-11-25 17:59:28,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:59:28,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 2452 states and 3548 transitions. [2022-11-25 17:59:28,855 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-25 17:59:28,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2452 states and 3548 transitions. [2022-11-25 17:59:28,869 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2022-11-25 17:59:28,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:28,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:28,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:28,871 INFO L748 eck$LassoCheckResult]: Stem: 13309#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 13094#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12672#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12673#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 13105#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12947#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12948#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12924#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12925#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13190#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13032#L611 assume !(0 == ~M_E~0); 13033#L611-2 assume !(0 == ~T1_E~0); 13207#L616-1 assume !(0 == ~T2_E~0); 13208#L621-1 assume !(0 == ~T3_E~0); 12797#L626-1 assume !(0 == ~T4_E~0); 12798#L631-1 assume !(0 == ~T5_E~0); 12990#L636-1 assume !(0 == ~E_M~0); 12841#L641-1 assume !(0 == ~E_1~0); 12842#L646-1 assume !(0 == ~E_2~0); 13005#L651-1 assume !(0 == ~E_3~0); 13255#L656-1 assume !(0 == ~E_4~0); 13188#L661-1 assume !(0 == ~E_5~0); 13189#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13226#L304 assume !(1 == ~m_pc~0); 12859#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12772#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12773#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12718#L755 assume !(0 != activate_threads_~tmp~1#1); 12719#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12674#L323 assume !(1 == ~t1_pc~0); 12675#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12739#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12740#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13155#L763 assume !(0 != activate_threads_~tmp___0~0#1); 13287#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12746#L342 assume !(1 == ~t2_pc~0); 12748#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12866#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12867#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13280#L771 assume !(0 != activate_threads_~tmp___1~0#1); 13180#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13071#L361 assume !(1 == ~t3_pc~0); 13072#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13095#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12909#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12910#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12756#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12757#L380 assume 1 == ~t4_pc~0; 12819#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12820#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13200#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13110#L787 assume !(0 != activate_threads_~tmp___3~0#1); 13111#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12822#L399 assume !(1 == ~t5_pc~0); 12823#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12959#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13213#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12949#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12950#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13267#L679 assume !(1 == ~M_E~0); 13030#L679-2 assume !(1 == ~T1_E~0); 12880#L684-1 assume !(1 == ~T2_E~0); 12881#L689-1 assume !(1 == ~T3_E~0); 13082#L694-1 assume !(1 == ~T4_E~0); 13080#L699-1 assume !(1 == ~T5_E~0); 13081#L704-1 assume !(1 == ~E_M~0); 13056#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12991#L714-1 assume !(1 == ~E_2~0); 12992#L719-1 assume !(1 == ~E_3~0); 13174#L724-1 assume !(1 == ~E_4~0); 12783#L729-1 assume !(1 == ~E_5~0); 12784#L734-1 assume { :end_inline_reset_delta_events } true; 13137#L940-2 [2022-11-25 17:59:28,871 INFO L750 eck$LassoCheckResult]: Loop: 13137#L940-2 assume !false; 13166#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12878#L586 assume !false; 12879#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14407#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14399#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14398#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14396#L511 assume !(0 != eval_~tmp~0#1); 14397#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14700#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14699#L611-3 assume !(0 == ~M_E~0); 14698#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14697#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14696#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14695#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14694#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14693#L636-3 assume !(0 == ~E_M~0); 14692#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14691#L646-3 assume !(0 == ~E_2~0); 14690#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14689#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14687#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14685#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14683#L304-21 assume !(1 == ~m_pc~0); 14681#L304-23 is_master_triggered_~__retres1~0#1 := 0; 14679#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14677#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14675#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14673#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14671#L323-21 assume !(1 == ~t1_pc~0); 14669#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 14668#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14667#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14666#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14665#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14664#L342-21 assume !(1 == ~t2_pc~0); 14662#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 14661#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14660#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14659#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14658#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14657#L361-21 assume 1 == ~t3_pc~0; 14656#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14653#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14651#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14649#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14647#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14645#L380-21 assume 1 == ~t4_pc~0; 14641#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14639#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14637#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14635#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14633#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14631#L399-21 assume !(1 == ~t5_pc~0); 14627#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 14625#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14623#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14621#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14619#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14618#L679-3 assume !(1 == ~M_E~0); 14616#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14615#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14614#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14613#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14612#L699-3 assume !(1 == ~T5_E~0); 14610#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14608#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14606#L714-3 assume !(1 == ~E_2~0); 14604#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14602#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14600#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14598#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14593#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14587#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14585#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 14582#L959 assume !(0 == start_simulation_~tmp~3#1); 14579#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14570#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14564#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14562#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 13199#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12900#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12901#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 13136#L972 assume !(0 != start_simulation_~tmp___0~1#1); 13137#L940-2 [2022-11-25 17:59:28,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2022-11-25 17:59:28,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529845755] [2022-11-25 17:59:28,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:28,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:28,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:28,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529845755] [2022-11-25 17:59:28,969 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529845755] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:28,969 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:28,969 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:59:28,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494809235] [2022-11-25 17:59:28,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:28,970 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:28,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:28,970 INFO L85 PathProgramCache]: Analyzing trace with hash -426418386, now seen corresponding path program 1 times [2022-11-25 17:59:28,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:28,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803739019] [2022-11-25 17:59:28,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:28,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:28,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:29,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:29,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:29,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803739019] [2022-11-25 17:59:29,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803739019] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:29,009 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:29,009 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:29,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518408930] [2022-11-25 17:59:29,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:29,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:29,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:29,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:59:29,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:59:29,010 INFO L87 Difference]: Start difference. First operand 2452 states and 3548 transitions. cyclomatic complexity: 1098 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:29,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:29,235 INFO L93 Difference]: Finished difference Result 6124 states and 8898 transitions. [2022-11-25 17:59:29,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6124 states and 8898 transitions. [2022-11-25 17:59:29,271 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5960 [2022-11-25 17:59:29,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6124 states to 6124 states and 8898 transitions. [2022-11-25 17:59:29,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6124 [2022-11-25 17:59:29,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6124 [2022-11-25 17:59:29,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6124 states and 8898 transitions. [2022-11-25 17:59:29,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:29,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6124 states and 8898 transitions. [2022-11-25 17:59:29,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6124 states and 8898 transitions. [2022-11-25 17:59:29,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6124 to 2572. [2022-11-25 17:59:29,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2572 states, 2572 states have (on average 1.4261275272161742) internal successors, (3668), 2571 states have internal predecessors, (3668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:29,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2572 states to 2572 states and 3668 transitions. [2022-11-25 17:59:29,377 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2572 states and 3668 transitions. [2022-11-25 17:59:29,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:59:29,378 INFO L428 stractBuchiCegarLoop]: Abstraction has 2572 states and 3668 transitions. [2022-11-25 17:59:29,378 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-25 17:59:29,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2572 states and 3668 transitions. [2022-11-25 17:59:29,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2482 [2022-11-25 17:59:29,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:29,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:29,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:29,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:29,391 INFO L748 eck$LassoCheckResult]: Stem: 21920#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21881#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21687#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21265#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21266#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 21701#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21534#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21535#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21511#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21512#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21782#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21624#L611 assume !(0 == ~M_E~0); 21625#L611-2 assume !(0 == ~T1_E~0); 21802#L616-1 assume !(0 == ~T2_E~0); 21803#L621-1 assume !(0 == ~T3_E~0); 21390#L626-1 assume !(0 == ~T4_E~0); 21391#L631-1 assume !(0 == ~T5_E~0); 21579#L636-1 assume !(0 == ~E_M~0); 21430#L641-1 assume !(0 == ~E_1~0); 21431#L646-1 assume !(0 == ~E_2~0); 21596#L651-1 assume !(0 == ~E_3~0); 21864#L656-1 assume !(0 == ~E_4~0); 21780#L661-1 assume !(0 == ~E_5~0); 21781#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21826#L304 assume !(1 == ~m_pc~0); 21450#L304-2 is_master_triggered_~__retres1~0#1 := 0; 21362#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21363#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21310#L755 assume !(0 != activate_threads_~tmp~1#1); 21311#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21267#L323 assume !(1 == ~t1_pc~0); 21268#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21328#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21329#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21750#L763 assume !(0 != activate_threads_~tmp___0~0#1); 21895#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21336#L342 assume !(1 == ~t2_pc~0); 21338#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21452#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21453#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21889#L771 assume !(0 != activate_threads_~tmp___1~0#1); 21772#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21664#L361 assume !(1 == ~t3_pc~0); 21665#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21688#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21878#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21860#L779 assume !(0 != activate_threads_~tmp___2~0#1); 21346#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21347#L380 assume 1 == ~t4_pc~0; 21407#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21408#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21793#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21707#L787 assume !(0 != activate_threads_~tmp___3~0#1); 21708#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21410#L399 assume !(1 == ~t5_pc~0); 21411#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21546#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21808#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21536#L795 assume !(0 != activate_threads_~tmp___4~0#1); 21537#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21874#L679 assume !(1 == ~M_E~0); 21623#L679-2 assume !(1 == ~T1_E~0); 21466#L684-1 assume !(1 == ~T2_E~0); 21467#L689-1 assume !(1 == ~T3_E~0); 21673#L694-1 assume !(1 == ~T4_E~0); 21671#L699-1 assume !(1 == ~T5_E~0); 21672#L704-1 assume !(1 == ~E_M~0); 21650#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21586#L714-1 assume !(1 == ~E_2~0); 21587#L719-1 assume !(1 == ~E_3~0); 21768#L724-1 assume !(1 == ~E_4~0); 21372#L729-1 assume !(1 == ~E_5~0); 21373#L734-1 assume { :end_inline_reset_delta_events } true; 21879#L940-2 [2022-11-25 17:59:29,391 INFO L750 eck$LassoCheckResult]: Loop: 21879#L940-2 assume !false; 22679#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22676#L586 assume !false; 22675#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22650#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22645#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22643#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22640#L511 assume !(0 != eval_~tmp~0#1); 22641#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22826#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22825#L611-3 assume !(0 == ~M_E~0); 22824#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22823#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22822#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22821#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22820#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22819#L636-3 assume !(0 == ~E_M~0); 22818#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22817#L646-3 assume !(0 == ~E_2~0); 22816#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22815#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22814#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22813#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22812#L304-21 assume !(1 == ~m_pc~0); 22811#L304-23 is_master_triggered_~__retres1~0#1 := 0; 22810#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22809#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22808#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22807#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22806#L323-21 assume !(1 == ~t1_pc~0); 22805#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 22804#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22803#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22802#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22801#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22800#L342-21 assume !(1 == ~t2_pc~0); 22798#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 22797#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22796#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22795#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22794#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22793#L361-21 assume 1 == ~t3_pc~0; 22791#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22789#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22787#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22785#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22783#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22781#L380-21 assume 1 == ~t4_pc~0; 22777#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22775#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22773#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22771#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22769#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22767#L399-21 assume !(1 == ~t5_pc~0); 22763#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 22761#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22759#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22757#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22755#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22754#L679-3 assume !(1 == ~M_E~0); 22751#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22750#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22749#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22748#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22747#L699-3 assume !(1 == ~T5_E~0); 22746#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22745#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22744#L714-3 assume !(1 == ~E_2~0); 22743#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22742#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22741#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22740#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22722#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22716#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22713#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 22711#L959 assume !(0 == start_simulation_~tmp~3#1); 22708#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22701#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22695#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22693#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 22691#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22689#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22688#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22684#L972 assume !(0 != start_simulation_~tmp___0~1#1); 21879#L940-2 [2022-11-25 17:59:29,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:29,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2022-11-25 17:59:29,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:29,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680909138] [2022-11-25 17:59:29,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:29,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:29,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:29,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:29,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:29,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680909138] [2022-11-25 17:59:29,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680909138] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:29,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:29,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:59:29,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684015760] [2022-11-25 17:59:29,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:29,434 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:29,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:29,434 INFO L85 PathProgramCache]: Analyzing trace with hash -426418386, now seen corresponding path program 2 times [2022-11-25 17:59:29,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:29,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332094358] [2022-11-25 17:59:29,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:29,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:29,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:29,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:29,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:29,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332094358] [2022-11-25 17:59:29,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332094358] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:29,469 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:29,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:29,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202190345] [2022-11-25 17:59:29,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:29,469 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:29,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:29,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:29,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:29,470 INFO L87 Difference]: Start difference. First operand 2572 states and 3668 transitions. cyclomatic complexity: 1098 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:29,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:29,545 INFO L93 Difference]: Finished difference Result 4748 states and 6742 transitions. [2022-11-25 17:59:29,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4748 states and 6742 transitions. [2022-11-25 17:59:29,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4637 [2022-11-25 17:59:29,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4748 states to 4748 states and 6742 transitions. [2022-11-25 17:59:29,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4748 [2022-11-25 17:59:29,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4748 [2022-11-25 17:59:29,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4748 states and 6742 transitions. [2022-11-25 17:59:29,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:29,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4748 states and 6742 transitions. [2022-11-25 17:59:29,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4748 states and 6742 transitions. [2022-11-25 17:59:29,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4748 to 4736. [2022-11-25 17:59:29,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4210304054054055) internal successors, (6730), 4735 states have internal predecessors, (6730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:29,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6730 transitions. [2022-11-25 17:59:29,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6730 transitions. [2022-11-25 17:59:29,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:29,751 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6730 transitions. [2022-11-25 17:59:29,751 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-25 17:59:29,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6730 transitions. [2022-11-25 17:59:29,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-11-25 17:59:29,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:29,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:29,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:29,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:29,776 INFO L748 eck$LassoCheckResult]: Stem: 29241#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 29201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 29010#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28592#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28593#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 29023#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28855#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28856#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28834#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28835#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29111#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28949#L611 assume !(0 == ~M_E~0); 28950#L611-2 assume !(0 == ~T1_E~0); 29126#L616-1 assume !(0 == ~T2_E~0); 29127#L621-1 assume !(0 == ~T3_E~0); 28716#L626-1 assume !(0 == ~T4_E~0); 28717#L631-1 assume !(0 == ~T5_E~0); 28901#L636-1 assume !(0 == ~E_M~0); 28753#L641-1 assume !(0 == ~E_1~0); 28754#L646-1 assume !(0 == ~E_2~0); 28918#L651-1 assume !(0 == ~E_3~0); 29184#L656-1 assume !(0 == ~E_4~0); 29109#L661-1 assume !(0 == ~E_5~0); 29110#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29149#L304 assume !(1 == ~m_pc~0); 28774#L304-2 is_master_triggered_~__retres1~0#1 := 0; 28688#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28689#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28637#L755 assume !(0 != activate_threads_~tmp~1#1); 28638#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28594#L323 assume !(1 == ~t1_pc~0); 28595#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28654#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28655#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29072#L763 assume !(0 != activate_threads_~tmp___0~0#1); 29215#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28662#L342 assume !(1 == ~t2_pc~0); 28664#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28776#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28777#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29208#L771 assume !(0 != activate_threads_~tmp___1~0#1); 29102#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28987#L361 assume !(1 == ~t3_pc~0); 28988#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29011#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28818#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28819#L779 assume !(0 != activate_threads_~tmp___2~0#1); 28672#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28673#L380 assume !(1 == ~t4_pc~0); 28984#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29118#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29119#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29028#L787 assume !(0 != activate_threads_~tmp___3~0#1); 29029#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28733#L399 assume !(1 == ~t5_pc~0); 28734#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28867#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29133#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28857#L795 assume !(0 != activate_threads_~tmp___4~0#1); 28858#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29193#L679 assume !(1 == ~M_E~0); 28948#L679-2 assume !(1 == ~T1_E~0); 28789#L684-1 assume !(1 == ~T2_E~0); 28790#L689-1 assume !(1 == ~T3_E~0); 28997#L694-1 assume !(1 == ~T4_E~0); 28995#L699-1 assume !(1 == ~T5_E~0); 28996#L704-1 assume !(1 == ~E_M~0); 28972#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28906#L714-1 assume !(1 == ~E_2~0); 28907#L719-1 assume !(1 == ~E_3~0); 29094#L724-1 assume !(1 == ~E_4~0); 28698#L729-1 assume !(1 == ~E_5~0); 28699#L734-1 assume { :end_inline_reset_delta_events } true; 29199#L940-2 [2022-11-25 17:59:29,776 INFO L750 eck$LassoCheckResult]: Loop: 29199#L940-2 assume !false; 29147#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28874#L586 assume !false; 29190#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 29191#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28992#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28993#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28981#L511 assume !(0 != eval_~tmp~0#1); 28982#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29163#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29056#L611-3 assume !(0 == ~M_E~0); 28700#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28701#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28697#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28639#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28640#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28641#L636-3 assume !(0 == ~E_M~0); 28642#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28712#L646-3 assume !(0 == ~E_2~0); 28724#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28725#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28964#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29216#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28862#L304-21 assume !(1 == ~m_pc~0); 28728#L304-23 is_master_triggered_~__retres1~0#1 := 0; 28729#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29024#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28933#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28934#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28966#L323-21 assume !(1 == ~t1_pc~0); 29114#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 29115#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29070#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29071#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29145#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29170#L342-21 assume !(1 == ~t2_pc~0); 28629#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 29016#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29017#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29103#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28736#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28737#L361-21 assume 1 == ~t3_pc~0; 29203#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29221#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33235#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33229#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28632#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28633#L380-21 assume !(1 == ~t4_pc~0); 28704#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 28705#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28762#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29076#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29030#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28843#L399-21 assume !(1 == ~t5_pc~0); 28710#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 28711#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29045#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29169#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29189#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28630#L679-3 assume !(1 == ~M_E~0); 28631#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33141#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33138#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33136#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33134#L699-3 assume !(1 == ~T5_E~0); 33132#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33130#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33128#L714-3 assume !(1 == ~E_2~0); 33126#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33123#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33121#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33119#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33116#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33110#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28666#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 28667#L959 assume !(0 == start_simulation_~tmp~3#1); 29009#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 29227#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33094#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33093#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 33092#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33091#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33090#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 32982#L972 assume !(0 != start_simulation_~tmp___0~1#1); 29199#L940-2 [2022-11-25 17:59:29,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:29,777 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2022-11-25 17:59:29,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:29,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234857835] [2022-11-25 17:59:29,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:29,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:29,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:29,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:29,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:29,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234857835] [2022-11-25 17:59:29,839 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234857835] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:29,839 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:29,840 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:29,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107434122] [2022-11-25 17:59:29,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:29,840 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:29,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:29,841 INFO L85 PathProgramCache]: Analyzing trace with hash 698841583, now seen corresponding path program 1 times [2022-11-25 17:59:29,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:29,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448390183] [2022-11-25 17:59:29,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:29,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:29,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:29,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:29,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:29,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448390183] [2022-11-25 17:59:29,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448390183] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:29,879 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:29,879 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:29,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774490905] [2022-11-25 17:59:29,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:29,880 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:29,880 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:29,881 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:59:29,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:59:29,881 INFO L87 Difference]: Start difference. First operand 4736 states and 6730 transitions. cyclomatic complexity: 1998 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:30,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:30,012 INFO L93 Difference]: Finished difference Result 7546 states and 10646 transitions. [2022-11-25 17:59:30,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7546 states and 10646 transitions. [2022-11-25 17:59:30,047 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7321 [2022-11-25 17:59:30,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7546 states to 7546 states and 10646 transitions. [2022-11-25 17:59:30,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7546 [2022-11-25 17:59:30,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7546 [2022-11-25 17:59:30,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7546 states and 10646 transitions. [2022-11-25 17:59:30,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:30,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7546 states and 10646 transitions. [2022-11-25 17:59:30,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7546 states and 10646 transitions. [2022-11-25 17:59:30,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7546 to 5465. [2022-11-25 17:59:30,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5465 states, 5465 states have (on average 1.413540713632205) internal successors, (7725), 5464 states have internal predecessors, (7725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:30,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5465 states to 5465 states and 7725 transitions. [2022-11-25 17:59:30,297 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5465 states and 7725 transitions. [2022-11-25 17:59:30,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:59:30,298 INFO L428 stractBuchiCegarLoop]: Abstraction has 5465 states and 7725 transitions. [2022-11-25 17:59:30,298 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-25 17:59:30,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5465 states and 7725 transitions. [2022-11-25 17:59:30,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5299 [2022-11-25 17:59:30,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:30,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:30,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:30,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:30,318 INFO L748 eck$LassoCheckResult]: Stem: 41511#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 41464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 41298#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40880#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40881#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 41309#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41150#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41151#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41129#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41130#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41382#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41237#L611 assume !(0 == ~M_E~0); 41238#L611-2 assume !(0 == ~T1_E~0); 41397#L616-1 assume !(0 == ~T2_E~0); 41398#L621-1 assume !(0 == ~T3_E~0); 41001#L626-1 assume !(0 == ~T4_E~0); 41002#L631-1 assume !(0 == ~T5_E~0); 41192#L636-1 assume !(0 == ~E_M~0); 41044#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 41045#L646-1 assume !(0 == ~E_2~0); 41210#L651-1 assume !(0 == ~E_3~0); 41448#L656-1 assume !(0 == ~E_4~0); 41449#L661-1 assume !(0 == ~E_5~0); 41412#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41413#L304 assume !(1 == ~m_pc~0); 41063#L304-2 is_master_triggered_~__retres1~0#1 := 0; 41064#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41509#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41510#L755 assume !(0 != activate_threads_~tmp~1#1); 41516#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41517#L323 assume !(1 == ~t1_pc~0); 41260#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41261#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41345#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41346#L763 assume !(0 != activate_threads_~tmp___0~0#1); 41488#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41489#L342 assume !(1 == ~t2_pc~0); 41377#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41378#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41565#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41564#L771 assume !(0 != activate_threads_~tmp___1~0#1); 41563#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41562#L361 assume !(1 == ~t3_pc~0); 41561#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41559#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41554#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41552#L779 assume !(0 != activate_threads_~tmp___2~0#1); 40961#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40962#L380 assume !(1 == ~t4_pc~0); 41273#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41550#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41549#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41548#L787 assume !(0 != activate_threads_~tmp___3~0#1); 41547#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41025#L399 assume !(1 == ~t5_pc~0); 41026#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41546#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41545#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41152#L795 assume !(0 != activate_threads_~tmp___4~0#1); 41153#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41458#L679 assume !(1 == ~M_E~0); 41543#L679-2 assume !(1 == ~T1_E~0); 41542#L684-1 assume !(1 == ~T2_E~0); 41541#L689-1 assume !(1 == ~T3_E~0); 41508#L694-1 assume !(1 == ~T4_E~0); 41284#L699-1 assume !(1 == ~T5_E~0); 41285#L704-1 assume !(1 == ~E_M~0); 41539#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 41196#L714-1 assume !(1 == ~E_2~0); 41197#L719-1 assume !(1 == ~E_3~0); 41368#L724-1 assume !(1 == ~E_4~0); 40989#L729-1 assume !(1 == ~E_5~0); 40990#L734-1 assume { :end_inline_reset_delta_events } true; 41462#L940-2 [2022-11-25 17:59:30,318 INFO L750 eck$LassoCheckResult]: Loop: 41462#L940-2 assume !false; 45581#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45578#L586 assume !false; 45576#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 45507#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45503#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45501#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45499#L511 assume !(0 != eval_~tmp~0#1); 45498#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45496#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45494#L611-3 assume !(0 == ~M_E~0); 45492#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45490#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45487#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45485#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45483#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45481#L636-3 assume !(0 == ~E_M~0); 45478#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45477#L646-3 assume !(0 == ~E_2~0); 45476#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45475#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45474#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45473#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45472#L304-21 assume !(1 == ~m_pc~0); 45471#L304-23 is_master_triggered_~__retres1~0#1 := 0; 45470#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45469#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45468#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45467#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45466#L323-21 assume !(1 == ~t1_pc~0); 45465#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 45464#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45463#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45462#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45461#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45460#L342-21 assume !(1 == ~t2_pc~0); 45458#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 45457#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45456#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45455#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45454#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45453#L361-21 assume 1 == ~t3_pc~0; 45451#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45449#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45447#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45445#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45444#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45443#L380-21 assume !(1 == ~t4_pc~0); 45442#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 45441#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45440#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45439#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45438#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45437#L399-21 assume !(1 == ~t5_pc~0); 45435#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 45434#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45433#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45432#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45431#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45430#L679-3 assume !(1 == ~M_E~0); 42492#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45429#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45428#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45427#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45426#L699-3 assume !(1 == ~T5_E~0); 45425#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45423#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45421#L714-3 assume !(1 == ~E_2~0); 45419#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45417#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45324#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45321#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 45304#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45299#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45288#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 41296#L959 assume !(0 == start_simulation_~tmp~3#1); 41297#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 45673#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 45667#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 45665#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 45663#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45654#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45645#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 45584#L972 assume !(0 != start_simulation_~tmp___0~1#1); 41462#L940-2 [2022-11-25 17:59:30,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:30,319 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2022-11-25 17:59:30,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:30,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152132696] [2022-11-25 17:59:30,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:30,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:30,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:30,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:30,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:30,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152132696] [2022-11-25 17:59:30,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152132696] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:30,365 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:30,366 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:30,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298978326] [2022-11-25 17:59:30,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:30,366 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:30,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:30,367 INFO L85 PathProgramCache]: Analyzing trace with hash 698841583, now seen corresponding path program 2 times [2022-11-25 17:59:30,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:30,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141133631] [2022-11-25 17:59:30,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:30,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:30,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:30,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:30,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:30,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141133631] [2022-11-25 17:59:30,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141133631] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:30,399 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:30,400 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:30,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019231572] [2022-11-25 17:59:30,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:30,400 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:30,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:30,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:59:30,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:59:30,401 INFO L87 Difference]: Start difference. First operand 5465 states and 7725 transitions. cyclomatic complexity: 2264 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:30,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:30,511 INFO L93 Difference]: Finished difference Result 6670 states and 9389 transitions. [2022-11-25 17:59:30,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6670 states and 9389 transitions. [2022-11-25 17:59:30,540 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6505 [2022-11-25 17:59:30,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6670 states to 6670 states and 9389 transitions. [2022-11-25 17:59:30,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6670 [2022-11-25 17:59:30,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6670 [2022-11-25 17:59:30,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6670 states and 9389 transitions. [2022-11-25 17:59:30,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:30,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6670 states and 9389 transitions. [2022-11-25 17:59:30,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6670 states and 9389 transitions. [2022-11-25 17:59:30,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6670 to 4736. [2022-11-25 17:59:30,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4079391891891893) internal successors, (6668), 4735 states have internal predecessors, (6668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:30,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6668 transitions. [2022-11-25 17:59:30,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6668 transitions. [2022-11-25 17:59:30,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:59:30,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6668 transitions. [2022-11-25 17:59:30,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-25 17:59:30,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6668 transitions. [2022-11-25 17:59:30,773 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-11-25 17:59:30,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:30,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:30,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:30,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:30,775 INFO L748 eck$LassoCheckResult]: Stem: 53646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53439#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53029#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53030#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 53451#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53295#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53296#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53274#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53275#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53531#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53380#L611 assume !(0 == ~M_E~0); 53381#L611-2 assume !(0 == ~T1_E~0); 53548#L616-1 assume !(0 == ~T2_E~0); 53549#L621-1 assume !(0 == ~T3_E~0); 53154#L626-1 assume !(0 == ~T4_E~0); 53155#L631-1 assume !(0 == ~T5_E~0); 53339#L636-1 assume !(0 == ~E_M~0); 53193#L641-1 assume !(0 == ~E_1~0); 53194#L646-1 assume !(0 == ~E_2~0); 53354#L651-1 assume !(0 == ~E_3~0); 53603#L656-1 assume !(0 == ~E_4~0); 53529#L661-1 assume !(0 == ~E_5~0); 53530#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53569#L304 assume !(1 == ~m_pc~0); 53214#L304-2 is_master_triggered_~__retres1~0#1 := 0; 53125#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53126#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53073#L755 assume !(0 != activate_threads_~tmp~1#1); 53074#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53031#L323 assume !(1 == ~t1_pc~0); 53032#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53091#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53092#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53498#L763 assume !(0 != activate_threads_~tmp___0~0#1); 53630#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53099#L342 assume !(1 == ~t2_pc~0); 53101#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53216#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53217#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53624#L771 assume !(0 != activate_threads_~tmp___1~0#1); 53522#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53418#L361 assume !(1 == ~t3_pc~0); 53419#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53440#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53258#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53259#L779 assume !(0 != activate_threads_~tmp___2~0#1); 53110#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53111#L380 assume !(1 == ~t4_pc~0); 53414#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53541#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53542#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53456#L787 assume !(0 != activate_threads_~tmp___3~0#1); 53457#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53171#L399 assume !(1 == ~t5_pc~0); 53172#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53307#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53553#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53297#L795 assume !(0 != activate_threads_~tmp___4~0#1); 53298#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53611#L679 assume !(1 == ~M_E~0); 53379#L679-2 assume !(1 == ~T1_E~0); 53229#L684-1 assume !(1 == ~T2_E~0); 53230#L689-1 assume !(1 == ~T3_E~0); 53427#L694-1 assume !(1 == ~T4_E~0); 53425#L699-1 assume !(1 == ~T5_E~0); 53426#L704-1 assume !(1 == ~E_M~0); 53403#L709-1 assume !(1 == ~E_1~0); 53344#L714-1 assume !(1 == ~E_2~0); 53345#L719-1 assume !(1 == ~E_3~0); 53517#L724-1 assume !(1 == ~E_4~0); 53135#L729-1 assume !(1 == ~E_5~0); 53136#L734-1 assume { :end_inline_reset_delta_events } true; 53485#L940-2 [2022-11-25 17:59:30,775 INFO L750 eck$LassoCheckResult]: Loop: 53485#L940-2 assume !false; 53508#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53227#L586 assume !false; 53228#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53608#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53422#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53423#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53411#L511 assume !(0 != eval_~tmp~0#1); 53412#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57741#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57739#L611-3 assume !(0 == ~M_E~0); 57737#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57695#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57694#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57690#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57689#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57650#L636-3 assume !(0 == ~E_M~0); 57649#L641-3 assume !(0 == ~E_1~0); 57648#L646-3 assume !(0 == ~E_2~0); 57647#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57646#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57645#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57644#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57643#L304-21 assume !(1 == ~m_pc~0); 57642#L304-23 is_master_triggered_~__retres1~0#1 := 0; 57641#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57640#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57638#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57636#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57635#L323-21 assume !(1 == ~t1_pc~0); 57634#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 57633#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57632#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57631#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57630#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57628#L342-21 assume !(1 == ~t2_pc~0); 57626#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 57625#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57623#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57621#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57619#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57614#L361-21 assume !(1 == ~t3_pc~0); 57612#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 57610#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57608#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57606#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 57603#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57601#L380-21 assume !(1 == ~t4_pc~0); 57599#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 57597#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57595#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57593#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57590#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57588#L399-21 assume !(1 == ~t5_pc~0); 57585#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 57583#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57581#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57580#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57579#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57578#L679-3 assume !(1 == ~M_E~0); 55775#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57542#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57541#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57540#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57539#L699-3 assume !(1 == ~T5_E~0); 57538#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57537#L709-3 assume !(1 == ~E_1~0); 57536#L714-3 assume !(1 == ~E_2~0); 57535#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57534#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57533#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57532#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 56354#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 56348#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 56346#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 53437#L959 assume !(0 == start_simulation_~tmp~3#1); 53438#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 53340#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 53341#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 53550#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 53536#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53249#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53250#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 53484#L972 assume !(0 != start_simulation_~tmp___0~1#1); 53485#L940-2 [2022-11-25 17:59:30,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:30,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2022-11-25 17:59:30,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:30,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45812773] [2022-11-25 17:59:30,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:30,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:30,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:30,786 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:30,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:30,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:30,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:30,827 INFO L85 PathProgramCache]: Analyzing trace with hash 1836673586, now seen corresponding path program 1 times [2022-11-25 17:59:30,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:30,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118756150] [2022-11-25 17:59:30,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:30,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:30,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:30,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:30,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:30,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118756150] [2022-11-25 17:59:30,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118756150] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:30,861 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:30,862 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:30,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728853985] [2022-11-25 17:59:30,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:30,862 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:30,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:30,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:30,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:30,863 INFO L87 Difference]: Start difference. First operand 4736 states and 6668 transitions. cyclomatic complexity: 1936 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:30,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:30,904 INFO L93 Difference]: Finished difference Result 5469 states and 7686 transitions. [2022-11-25 17:59:30,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5469 states and 7686 transitions. [2022-11-25 17:59:30,926 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5303 [2022-11-25 17:59:30,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5469 states to 5469 states and 7686 transitions. [2022-11-25 17:59:30,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5469 [2022-11-25 17:59:30,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5469 [2022-11-25 17:59:30,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5469 states and 7686 transitions. [2022-11-25 17:59:30,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:30,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-11-25 17:59:30,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5469 states and 7686 transitions. [2022-11-25 17:59:31,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5469 to 5469. [2022-11-25 17:59:31,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5469 states, 5469 states have (on average 1.4053757542512342) internal successors, (7686), 5468 states have internal predecessors, (7686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:31,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5469 states to 5469 states and 7686 transitions. [2022-11-25 17:59:31,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-11-25 17:59:31,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:31,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 5469 states and 7686 transitions. [2022-11-25 17:59:31,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-25 17:59:31,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5469 states and 7686 transitions. [2022-11-25 17:59:31,102 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5303 [2022-11-25 17:59:31,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:31,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:31,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:31,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:31,104 INFO L748 eck$LassoCheckResult]: Stem: 63866#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 63829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 63651#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63236#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63237#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 63664#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63503#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63504#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63482#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63483#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63746#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63591#L611 assume !(0 == ~M_E~0); 63592#L611-2 assume !(0 == ~T1_E~0); 63762#L616-1 assume !(0 == ~T2_E~0); 63763#L621-1 assume !(0 == ~T3_E~0); 63357#L626-1 assume !(0 == ~T4_E~0); 63358#L631-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63734#L636-1 assume !(0 == ~E_M~0); 63401#L641-1 assume !(0 == ~E_1~0); 63402#L646-1 assume !(0 == ~E_2~0); 63841#L651-1 assume !(0 == ~E_3~0); 63842#L656-1 assume !(0 == ~E_4~0); 63744#L661-1 assume !(0 == ~E_5~0); 63745#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63858#L304 assume !(1 == ~m_pc~0); 63859#L304-2 is_master_triggered_~__retres1~0#1 := 0; 63335#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63336#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63279#L755 assume !(0 != activate_threads_~tmp~1#1); 63280#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63238#L323 assume !(1 == ~t1_pc~0); 63239#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63302#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63303#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63843#L763 assume !(0 != activate_threads_~tmp___0~0#1); 63844#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63306#L342 assume !(1 == ~t2_pc~0); 63308#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63425#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63426#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63860#L771 assume !(0 != activate_threads_~tmp___1~0#1); 63861#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63630#L361 assume !(1 == ~t3_pc~0); 63631#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63959#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63467#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63468#L779 assume !(0 != activate_threads_~tmp___2~0#1); 63318#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63319#L380 assume !(1 == ~t4_pc~0); 63627#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63892#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63891#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63668#L787 assume !(0 != activate_threads_~tmp___3~0#1); 63669#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63380#L399 assume !(1 == ~t5_pc~0); 63381#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63515#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63766#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63505#L795 assume !(0 != activate_threads_~tmp___4~0#1); 63506#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63821#L679 assume !(1 == ~M_E~0); 63879#L679-2 assume !(1 == ~T1_E~0); 63878#L684-1 assume !(1 == ~T2_E~0); 63639#L689-1 assume !(1 == ~T3_E~0); 63640#L694-1 assume !(1 == ~T4_E~0); 63637#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63638#L704-1 assume !(1 == ~E_M~0); 63613#L709-1 assume !(1 == ~E_1~0); 63549#L714-1 assume !(1 == ~E_2~0); 63550#L719-1 assume !(1 == ~E_3~0); 63730#L724-1 assume !(1 == ~E_4~0); 63345#L729-1 assume !(1 == ~E_5~0); 63346#L734-1 assume { :end_inline_reset_delta_events } true; 63825#L940-2 [2022-11-25 17:59:31,104 INFO L750 eck$LassoCheckResult]: Loop: 63825#L940-2 assume !false; 65995#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65984#L586 assume !false; 65978#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 65966#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65957#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 65955#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65952#L511 assume !(0 != eval_~tmp~0#1); 65953#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66762#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66760#L611-3 assume !(0 == ~M_E~0); 66758#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66756#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66754#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66752#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66744#L631-3 assume !(0 == ~T5_E~0); 66736#L636-3 assume !(0 == ~E_M~0); 66731#L641-3 assume !(0 == ~E_1~0); 66724#L646-3 assume !(0 == ~E_2~0); 66717#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66711#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66704#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66700#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66697#L304-21 assume !(1 == ~m_pc~0); 66693#L304-23 is_master_triggered_~__retres1~0#1 := 0; 66692#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66691#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66690#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66689#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66687#L323-21 assume !(1 == ~t1_pc~0); 66686#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 66685#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66684#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66682#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66680#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66678#L342-21 assume !(1 == ~t2_pc~0); 66675#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 66673#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66671#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66668#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66666#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66661#L361-21 assume !(1 == ~t3_pc~0); 66659#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 66657#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66655#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66653#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 66650#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66647#L380-21 assume !(1 == ~t4_pc~0); 66645#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 66643#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66641#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66639#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66637#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66636#L399-21 assume !(1 == ~t5_pc~0); 66633#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 66631#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66629#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66627#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66504#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66501#L679-3 assume !(1 == ~M_E~0); 66497#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66495#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66493#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66491#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66479#L699-3 assume !(1 == ~T5_E~0); 66474#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66468#L709-3 assume !(1 == ~E_1~0); 66462#L714-3 assume !(1 == ~E_2~0); 66456#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66448#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66444#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66441#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66353#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66341#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66335#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 66329#L959 assume !(0 == start_simulation_~tmp~3#1); 66325#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66311#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66299#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66293#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 66287#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66282#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66277#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 66272#L972 assume !(0 != start_simulation_~tmp___0~1#1); 63825#L940-2 [2022-11-25 17:59:31,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:31,105 INFO L85 PathProgramCache]: Analyzing trace with hash 549210245, now seen corresponding path program 1 times [2022-11-25 17:59:31,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:31,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39860488] [2022-11-25 17:59:31,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:31,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:31,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:31,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:31,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:31,153 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39860488] [2022-11-25 17:59:31,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39860488] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:31,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:31,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:31,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033453609] [2022-11-25 17:59:31,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:31,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:31,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:31,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1344047412, now seen corresponding path program 1 times [2022-11-25 17:59:31,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:31,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637573727] [2022-11-25 17:59:31,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:31,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:31,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:31,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:31,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:31,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637573727] [2022-11-25 17:59:31,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637573727] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:31,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:31,208 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:59:31,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714467942] [2022-11-25 17:59:31,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:31,208 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:31,209 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:31,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:59:31,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:59:31,210 INFO L87 Difference]: Start difference. First operand 5469 states and 7686 transitions. cyclomatic complexity: 2221 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:31,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:31,287 INFO L93 Difference]: Finished difference Result 6863 states and 9627 transitions. [2022-11-25 17:59:31,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6863 states and 9627 transitions. [2022-11-25 17:59:31,380 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6729 [2022-11-25 17:59:31,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6863 states to 6863 states and 9627 transitions. [2022-11-25 17:59:31,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6863 [2022-11-25 17:59:31,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6863 [2022-11-25 17:59:31,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6863 states and 9627 transitions. [2022-11-25 17:59:31,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:31,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6863 states and 9627 transitions. [2022-11-25 17:59:31,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6863 states and 9627 transitions. [2022-11-25 17:59:31,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6863 to 4736. [2022-11-25 17:59:31,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.4051942567567568) internal successors, (6655), 4735 states have internal predecessors, (6655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:31,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6655 transitions. [2022-11-25 17:59:31,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4736 states and 6655 transitions. [2022-11-25 17:59:31,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:59:31,527 INFO L428 stractBuchiCegarLoop]: Abstraction has 4736 states and 6655 transitions. [2022-11-25 17:59:31,527 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-25 17:59:31,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6655 transitions. [2022-11-25 17:59:31,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4625 [2022-11-25 17:59:31,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:31,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:31,547 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:31,548 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:31,548 INFO L748 eck$LassoCheckResult]: Stem: 76193#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 76162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 75995#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75580#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75581#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 76005#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75851#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75852#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75829#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75830#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76078#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75938#L611 assume !(0 == ~M_E~0); 75939#L611-2 assume !(0 == ~T1_E~0); 76099#L616-1 assume !(0 == ~T2_E~0); 76100#L621-1 assume !(0 == ~T3_E~0); 75701#L626-1 assume !(0 == ~T4_E~0); 75702#L631-1 assume !(0 == ~T5_E~0); 75891#L636-1 assume !(0 == ~E_M~0); 75745#L641-1 assume !(0 == ~E_1~0); 75746#L646-1 assume !(0 == ~E_2~0); 75910#L651-1 assume !(0 == ~E_3~0); 76148#L656-1 assume !(0 == ~E_4~0); 76076#L661-1 assume !(0 == ~E_5~0); 76077#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76117#L304 assume !(1 == ~m_pc~0); 75764#L304-2 is_master_triggered_~__retres1~0#1 := 0; 75679#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75680#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75623#L755 assume !(0 != activate_threads_~tmp~1#1); 75624#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75582#L323 assume !(1 == ~t1_pc~0); 75583#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75645#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75646#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76045#L763 assume !(0 != activate_threads_~tmp___0~0#1); 76179#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75649#L342 assume !(1 == ~t2_pc~0); 75651#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75770#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75771#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76169#L771 assume !(0 != activate_threads_~tmp___1~0#1); 76071#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75974#L361 assume !(1 == ~t3_pc~0); 75975#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75996#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75814#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75815#L779 assume !(0 != activate_threads_~tmp___2~0#1); 75661#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75662#L380 assume !(1 == ~t4_pc~0); 75971#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76089#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76090#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76008#L787 assume !(0 != activate_threads_~tmp___3~0#1); 76009#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75724#L399 assume !(1 == ~t5_pc~0); 75725#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75862#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76102#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75853#L795 assume !(0 != activate_threads_~tmp___4~0#1); 75854#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76155#L679 assume !(1 == ~M_E~0); 75936#L679-2 assume !(1 == ~T1_E~0); 75784#L684-1 assume !(1 == ~T2_E~0); 75785#L689-1 assume !(1 == ~T3_E~0); 75984#L694-1 assume !(1 == ~T4_E~0); 75982#L699-1 assume !(1 == ~T5_E~0); 75983#L704-1 assume !(1 == ~E_M~0); 75960#L709-1 assume !(1 == ~E_1~0); 75895#L714-1 assume !(1 == ~E_2~0); 75896#L719-1 assume !(1 == ~E_3~0); 76065#L724-1 assume !(1 == ~E_4~0); 75689#L729-1 assume !(1 == ~E_5~0); 75690#L734-1 assume { :end_inline_reset_delta_events } true; 76160#L940-2 [2022-11-25 17:59:31,548 INFO L750 eck$LassoCheckResult]: Loop: 76160#L940-2 assume !false; 79493#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79485#L586 assume !false; 79480#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79471#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79463#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79458#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 79454#L511 assume !(0 != eval_~tmp~0#1); 79455#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76129#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76031#L611-3 assume !(0 == ~M_E~0); 75691#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75692#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75687#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75630#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75631#L631-3 assume !(0 == ~T5_E~0); 75632#L636-3 assume !(0 == ~E_M~0); 75633#L641-3 assume !(0 == ~E_1~0); 75703#L646-3 assume !(0 == ~E_2~0); 75715#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75716#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 75953#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76180#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75858#L304-21 assume !(1 == ~m_pc~0); 75719#L304-23 is_master_triggered_~__retres1~0#1 := 0; 75720#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76006#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75925#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75926#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75954#L323-21 assume !(1 == ~t1_pc~0); 76083#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 76084#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76046#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76047#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76114#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76133#L342-21 assume !(1 == ~t2_pc~0); 75620#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 76001#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76002#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76072#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75727#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75728#L361-21 assume 1 == ~t3_pc~0; 76164#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76184#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80183#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80181#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75628#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75629#L380-21 assume !(1 == ~t4_pc~0); 75697#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 75698#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75756#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76052#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76011#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75838#L399-21 assume 1 == ~t5_pc~0; 75808#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75708#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76023#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76132#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76151#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75621#L679-3 assume !(1 == ~M_E~0); 75622#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75904#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75572#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75573#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75609#L699-3 assume !(1 == ~T5_E~0); 75610#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76033#L709-3 assume !(1 == ~E_1~0); 76025#L714-3 assume !(1 == ~E_2~0); 75866#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75607#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75608#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76017#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75642#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75643#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75657#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 75658#L959 assume !(0 == start_simulation_~tmp~3#1); 75994#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79528#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79522#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79520#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 79518#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79517#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79513#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 79511#L972 assume !(0 != start_simulation_~tmp___0~1#1); 76160#L940-2 [2022-11-25 17:59:31,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:31,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2022-11-25 17:59:31,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:31,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858542883] [2022-11-25 17:59:31,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:31,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:31,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:31,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:31,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:31,587 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:31,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:31,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1232612048, now seen corresponding path program 1 times [2022-11-25 17:59:31,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:31,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360550339] [2022-11-25 17:59:31,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:31,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:31,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:31,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:31,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360550339] [2022-11-25 17:59:31,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360550339] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:31,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:31,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:59:31,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557027028] [2022-11-25 17:59:31,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:31,652 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:31,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:31,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:59:31,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:59:31,653 INFO L87 Difference]: Start difference. First operand 4736 states and 6655 transitions. cyclomatic complexity: 1923 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:31,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:31,799 INFO L93 Difference]: Finished difference Result 8463 states and 11736 transitions. [2022-11-25 17:59:31,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8463 states and 11736 transitions. [2022-11-25 17:59:31,842 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8320 [2022-11-25 17:59:31,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8463 states to 8463 states and 11736 transitions. [2022-11-25 17:59:31,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8463 [2022-11-25 17:59:31,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8463 [2022-11-25 17:59:31,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8463 states and 11736 transitions. [2022-11-25 17:59:31,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:31,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8463 states and 11736 transitions. [2022-11-25 17:59:31,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8463 states and 11736 transitions. [2022-11-25 17:59:32,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8463 to 4772. [2022-11-25 17:59:32,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4772 states, 4772 states have (on average 1.4021374685666388) internal successors, (6691), 4771 states have internal predecessors, (6691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:32,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4772 states to 4772 states and 6691 transitions. [2022-11-25 17:59:32,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4772 states and 6691 transitions. [2022-11-25 17:59:32,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-25 17:59:32,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 4772 states and 6691 transitions. [2022-11-25 17:59:32,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-25 17:59:32,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4772 states and 6691 transitions. [2022-11-25 17:59:32,104 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4661 [2022-11-25 17:59:32,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:32,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:32,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:32,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:32,106 INFO L748 eck$LassoCheckResult]: Stem: 89396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 89369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 89201#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88799#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88800#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 89211#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89061#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89062#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89040#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89041#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 89287#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89148#L611 assume !(0 == ~M_E~0); 89149#L611-2 assume !(0 == ~T1_E~0); 89301#L616-1 assume !(0 == ~T2_E~0); 89302#L621-1 assume !(0 == ~T3_E~0); 88922#L626-1 assume !(0 == ~T4_E~0); 88923#L631-1 assume !(0 == ~T5_E~0); 89106#L636-1 assume !(0 == ~E_M~0); 88959#L641-1 assume !(0 == ~E_1~0); 88960#L646-1 assume !(0 == ~E_2~0); 89122#L651-1 assume !(0 == ~E_3~0); 89354#L656-1 assume !(0 == ~E_4~0); 89285#L661-1 assume !(0 == ~E_5~0); 89286#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89321#L304 assume !(1 == ~m_pc~0); 88979#L304-2 is_master_triggered_~__retres1~0#1 := 0; 88894#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88895#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88843#L755 assume !(0 != activate_threads_~tmp~1#1); 88844#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88801#L323 assume !(1 == ~t1_pc~0); 88802#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88861#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88862#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 89253#L763 assume !(0 != activate_threads_~tmp___0~0#1); 89379#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88869#L342 assume !(1 == ~t2_pc~0); 88871#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88981#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88982#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 89373#L771 assume !(0 != activate_threads_~tmp___1~0#1); 89280#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89182#L361 assume !(1 == ~t3_pc~0); 89183#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89202#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89024#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89025#L779 assume !(0 != activate_threads_~tmp___2~0#1); 88879#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88880#L380 assume !(1 == ~t4_pc~0); 89179#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89294#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89295#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89216#L787 assume !(0 != activate_threads_~tmp___3~0#1); 89217#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88939#L399 assume !(1 == ~t5_pc~0); 88940#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 89073#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89306#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89063#L795 assume !(0 != activate_threads_~tmp___4~0#1); 89064#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89364#L679 assume !(1 == ~M_E~0); 89147#L679-2 assume !(1 == ~T1_E~0); 88994#L684-1 assume !(1 == ~T2_E~0); 88995#L689-1 assume !(1 == ~T3_E~0); 89191#L694-1 assume !(1 == ~T4_E~0); 89189#L699-1 assume !(1 == ~T5_E~0); 89190#L704-1 assume !(1 == ~E_M~0); 89169#L709-1 assume !(1 == ~E_1~0); 89111#L714-1 assume !(1 == ~E_2~0); 89112#L719-1 assume !(1 == ~E_3~0); 89276#L724-1 assume !(1 == ~E_4~0); 88904#L729-1 assume !(1 == ~E_5~0); 88905#L734-1 assume { :end_inline_reset_delta_events } true; 89367#L940-2 [2022-11-25 17:59:32,106 INFO L750 eck$LassoCheckResult]: Loop: 89367#L940-2 assume !false; 91393#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91388#L586 assume !false; 91350#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 91307#L464 assume !(0 == ~m_st~0); 91308#L468 assume !(0 == ~t1_st~0); 91310#L472 assume !(0 == ~t2_st~0); 91304#L476 assume !(0 == ~t3_st~0); 91306#L480 assume !(0 == ~t4_st~0); 91309#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 91302#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 91229#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 91230#L511 assume !(0 != eval_~tmp~0#1); 91627#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91625#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91623#L611-3 assume !(0 == ~M_E~0); 91621#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 91619#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91617#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91615#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91613#L631-3 assume !(0 == ~T5_E~0); 91611#L636-3 assume !(0 == ~E_M~0); 91609#L641-3 assume !(0 == ~E_1~0); 91607#L646-3 assume !(0 == ~E_2~0); 91605#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91603#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 91601#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91599#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91597#L304-21 assume !(1 == ~m_pc~0); 91595#L304-23 is_master_triggered_~__retres1~0#1 := 0; 91593#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91591#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91589#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91587#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91585#L323-21 assume !(1 == ~t1_pc~0); 91583#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 91581#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91579#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91577#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91575#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91573#L342-21 assume !(1 == ~t2_pc~0); 91569#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 91567#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91565#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91563#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 91561#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91559#L361-21 assume !(1 == ~t3_pc~0); 91557#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 91553#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91549#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91545#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 91541#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91539#L380-21 assume !(1 == ~t4_pc~0); 91537#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 91535#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91533#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 91531#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91529#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91527#L399-21 assume 1 == ~t5_pc~0; 91525#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 91521#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91519#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 91517#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 91515#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91513#L679-3 assume !(1 == ~M_E~0); 91510#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91509#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91508#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91507#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91506#L699-3 assume !(1 == ~T5_E~0); 91505#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91504#L709-3 assume !(1 == ~E_1~0); 91503#L714-3 assume !(1 == ~E_2~0); 91502#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 91501#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 91500#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91499#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 91497#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 91492#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 91483#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 91477#L959 assume !(0 == start_simulation_~tmp~3#1); 91473#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 91471#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 91460#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 91455#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 91448#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 91430#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 91426#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 91424#L972 assume !(0 != start_simulation_~tmp___0~1#1); 89367#L940-2 [2022-11-25 17:59:32,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:32,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2022-11-25 17:59:32,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:32,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482755629] [2022-11-25 17:59:32,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:32,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:32,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:32,117 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:32,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:32,137 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:32,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:32,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1288557122, now seen corresponding path program 1 times [2022-11-25 17:59:32,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:32,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355241266] [2022-11-25 17:59:32,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:32,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:32,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:32,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:32,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355241266] [2022-11-25 17:59:32,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355241266] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:32,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:32,232 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:59:32,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835272949] [2022-11-25 17:59:32,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:32,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:32,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:32,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:59:32,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:59:32,233 INFO L87 Difference]: Start difference. First operand 4772 states and 6691 transitions. cyclomatic complexity: 1923 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:32,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:32,471 INFO L93 Difference]: Finished difference Result 11016 states and 15346 transitions. [2022-11-25 17:59:32,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11016 states and 15346 transitions. [2022-11-25 17:59:32,516 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10889 [2022-11-25 17:59:32,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11016 states to 11016 states and 15346 transitions. [2022-11-25 17:59:32,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11016 [2022-11-25 17:59:32,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11016 [2022-11-25 17:59:32,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11016 states and 15346 transitions. [2022-11-25 17:59:32,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:32,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11016 states and 15346 transitions. [2022-11-25 17:59:32,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11016 states and 15346 transitions. [2022-11-25 17:59:32,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11016 to 4928. [2022-11-25 17:59:32,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4928 states, 4928 states have (on average 1.385146103896104) internal successors, (6826), 4927 states have internal predecessors, (6826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:32,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4928 states to 4928 states and 6826 transitions. [2022-11-25 17:59:32,758 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4928 states and 6826 transitions. [2022-11-25 17:59:32,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:59:32,760 INFO L428 stractBuchiCegarLoop]: Abstraction has 4928 states and 6826 transitions. [2022-11-25 17:59:32,760 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-25 17:59:32,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4928 states and 6826 transitions. [2022-11-25 17:59:32,774 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4817 [2022-11-25 17:59:32,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:32,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:32,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:32,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:32,776 INFO L748 eck$LassoCheckResult]: Stem: 105243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 105200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 105022#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104600#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104601#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 105035#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104871#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104872#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104847#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104848#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105118#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104961#L611 assume !(0 == ~M_E~0); 104962#L611-2 assume !(0 == ~T1_E~0); 105132#L616-1 assume !(0 == ~T2_E~0); 105133#L621-1 assume !(0 == ~T3_E~0); 104723#L626-1 assume !(0 == ~T4_E~0); 104724#L631-1 assume !(0 == ~T5_E~0); 104918#L636-1 assume !(0 == ~E_M~0); 104765#L641-1 assume !(0 == ~E_1~0); 104766#L646-1 assume !(0 == ~E_2~0); 104934#L651-1 assume !(0 == ~E_3~0); 105187#L656-1 assume !(0 == ~E_4~0); 105116#L661-1 assume !(0 == ~E_5~0); 105117#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105151#L304 assume !(1 == ~m_pc~0); 104785#L304-2 is_master_triggered_~__retres1~0#1 := 0; 104695#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104696#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104644#L755 assume !(0 != activate_threads_~tmp~1#1); 104645#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104602#L323 assume !(1 == ~t1_pc~0); 104603#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104661#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104662#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105083#L763 assume !(0 != activate_threads_~tmp___0~0#1); 105218#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104669#L342 assume !(1 == ~t2_pc~0); 104671#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104787#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104788#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105211#L771 assume !(0 != activate_threads_~tmp___1~0#1); 105108#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104996#L361 assume !(1 == ~t3_pc~0); 104997#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105023#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104831#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104832#L779 assume !(0 != activate_threads_~tmp___2~0#1); 104680#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104681#L380 assume !(1 == ~t4_pc~0); 104993#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105125#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105126#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105040#L787 assume !(0 != activate_threads_~tmp___3~0#1); 105041#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104740#L399 assume !(1 == ~t5_pc~0); 104741#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104885#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105138#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104873#L795 assume !(0 != activate_threads_~tmp___4~0#1); 104874#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105195#L679 assume !(1 == ~M_E~0); 104960#L679-2 assume !(1 == ~T1_E~0); 104800#L684-1 assume !(1 == ~T2_E~0); 104801#L689-1 assume !(1 == ~T3_E~0); 105005#L694-1 assume !(1 == ~T4_E~0); 105003#L699-1 assume !(1 == ~T5_E~0); 105004#L704-1 assume !(1 == ~E_M~0); 104982#L709-1 assume !(1 == ~E_1~0); 104923#L714-1 assume !(1 == ~E_2~0); 104924#L719-1 assume !(1 == ~E_3~0); 105104#L724-1 assume !(1 == ~E_4~0); 104705#L729-1 assume !(1 == ~E_5~0); 104706#L734-1 assume { :end_inline_reset_delta_events } true; 105198#L940-2 [2022-11-25 17:59:32,776 INFO L750 eck$LassoCheckResult]: Loop: 105198#L940-2 assume !false; 106334#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106332#L586 assume !false; 106331#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106326#L464 assume !(0 == ~m_st~0); 106327#L468 assume !(0 == ~t1_st~0); 106329#L472 assume !(0 == ~t2_st~0); 106324#L476 assume !(0 == ~t3_st~0); 106325#L480 assume !(0 == ~t4_st~0); 106328#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 106330#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106307#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 106308#L511 assume !(0 != eval_~tmp~0#1); 106596#L601 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106594#L419-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106592#L611-3 assume !(0 == ~M_E~0); 106590#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106588#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106586#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 106584#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 106582#L631-3 assume !(0 == ~T5_E~0); 106580#L636-3 assume !(0 == ~E_M~0); 106578#L641-3 assume !(0 == ~E_1~0); 106576#L646-3 assume !(0 == ~E_2~0); 106574#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106572#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106570#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106568#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106566#L304-21 assume !(1 == ~m_pc~0); 106564#L304-23 is_master_triggered_~__retres1~0#1 := 0; 106562#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106560#L316-7 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106558#L755-21 assume !(0 != activate_threads_~tmp~1#1); 106556#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106554#L323-21 assume !(1 == ~t1_pc~0); 106552#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 106550#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106548#L335-7 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106546#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106544#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106542#L342-21 assume !(1 == ~t2_pc~0); 106538#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 106536#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106534#L354-7 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106532#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 106530#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106528#L361-21 assume 1 == ~t3_pc~0; 106525#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 106521#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106517#L373-7 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106513#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106509#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106506#L380-21 assume !(1 == ~t4_pc~0); 106503#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 106500#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106497#L392-7 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106493#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106489#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106485#L399-21 assume 1 == ~t5_pc~0; 106481#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106475#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106470#L411-7 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106466#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106462#L795-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106458#L679-3 assume !(1 == ~M_E~0); 106453#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106449#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106445#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106439#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106434#L699-3 assume !(1 == ~T5_E~0); 106429#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 106424#L709-3 assume !(1 == ~E_1~0); 106420#L714-3 assume !(1 == ~E_2~0); 106416#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106413#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106410#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106407#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106322#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106318#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106305#L497-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 106306#L959 assume !(0 == start_simulation_~tmp~3#1); 106360#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106356#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106350#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106348#L497-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 106346#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106344#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106340#L922 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 106338#L972 assume !(0 != start_simulation_~tmp___0~1#1); 105198#L940-2 [2022-11-25 17:59:32,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:32,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2022-11-25 17:59:32,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:32,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12984287] [2022-11-25 17:59:32,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:32,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:32,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:32,790 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:32,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:32,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:32,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:32,824 INFO L85 PathProgramCache]: Analyzing trace with hash -80803011, now seen corresponding path program 1 times [2022-11-25 17:59:32,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:32,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714515629] [2022-11-25 17:59:32,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:32,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:32,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:32,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:32,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:32,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714515629] [2022-11-25 17:59:32,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714515629] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:32,861 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:32,861 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:32,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209702924] [2022-11-25 17:59:32,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:32,864 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:59:32,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:32,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:32,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:32,865 INFO L87 Difference]: Start difference. First operand 4928 states and 6826 transitions. cyclomatic complexity: 1902 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:32,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:32,932 INFO L93 Difference]: Finished difference Result 8309 states and 11344 transitions. [2022-11-25 17:59:32,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8309 states and 11344 transitions. [2022-11-25 17:59:32,966 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8196 [2022-11-25 17:59:32,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8309 states to 8309 states and 11344 transitions. [2022-11-25 17:59:32,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8309 [2022-11-25 17:59:33,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8309 [2022-11-25 17:59:33,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8309 states and 11344 transitions. [2022-11-25 17:59:33,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:33,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8309 states and 11344 transitions. [2022-11-25 17:59:33,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8309 states and 11344 transitions. [2022-11-25 17:59:33,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8309 to 7997. [2022-11-25 17:59:33,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7997 states, 7997 states have (on average 1.3675128173064899) internal successors, (10936), 7996 states have internal predecessors, (10936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:33,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7997 states to 7997 states and 10936 transitions. [2022-11-25 17:59:33,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7997 states and 10936 transitions. [2022-11-25 17:59:33,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:33,237 INFO L428 stractBuchiCegarLoop]: Abstraction has 7997 states and 10936 transitions. [2022-11-25 17:59:33,238 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-25 17:59:33,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7997 states and 10936 transitions. [2022-11-25 17:59:33,262 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7884 [2022-11-25 17:59:33,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:33,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:33,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:33,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:33,264 INFO L748 eck$LassoCheckResult]: Stem: 118472#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 118439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 118260#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117841#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117842#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 118272#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118110#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118111#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118088#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118089#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118348#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118199#L611 assume !(0 == ~M_E~0); 118200#L611-2 assume !(0 == ~T1_E~0); 118370#L616-1 assume !(0 == ~T2_E~0); 118371#L621-1 assume !(0 == ~T3_E~0); 117966#L626-1 assume !(0 == ~T4_E~0); 117967#L631-1 assume !(0 == ~T5_E~0); 118156#L636-1 assume !(0 == ~E_M~0); 118005#L641-1 assume !(0 == ~E_1~0); 118006#L646-1 assume !(0 == ~E_2~0); 118171#L651-1 assume !(0 == ~E_3~0); 118423#L656-1 assume !(0 == ~E_4~0); 118346#L661-1 assume !(0 == ~E_5~0); 118347#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118392#L304 assume !(1 == ~m_pc~0); 118026#L304-2 is_master_triggered_~__retres1~0#1 := 0; 117938#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117939#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117887#L755 assume !(0 != activate_threads_~tmp~1#1); 117888#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117843#L323 assume !(1 == ~t1_pc~0); 117844#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117904#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117905#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118318#L763 assume !(0 != activate_threads_~tmp___0~0#1); 118452#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117912#L342 assume !(1 == ~t2_pc~0); 117914#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118028#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118029#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118446#L771 assume !(0 != activate_threads_~tmp___1~0#1); 118342#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118236#L361 assume !(1 == ~t3_pc~0); 118237#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118261#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118072#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118073#L779 assume !(0 != activate_threads_~tmp___2~0#1); 117923#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117924#L380 assume !(1 == ~t4_pc~0); 118233#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118360#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118361#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118278#L787 assume !(0 != activate_threads_~tmp___3~0#1); 118279#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117982#L399 assume !(1 == ~t5_pc~0); 117983#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118122#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118375#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118112#L795 assume !(0 != activate_threads_~tmp___4~0#1); 118113#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118431#L679 assume !(1 == ~M_E~0); 118198#L679-2 assume !(1 == ~T1_E~0); 118041#L684-1 assume !(1 == ~T2_E~0); 118042#L689-1 assume !(1 == ~T3_E~0); 118247#L694-1 assume !(1 == ~T4_E~0); 118245#L699-1 assume !(1 == ~T5_E~0); 118246#L704-1 assume !(1 == ~E_M~0); 118221#L709-1 assume !(1 == ~E_1~0); 118158#L714-1 assume !(1 == ~E_2~0); 118159#L719-1 assume !(1 == ~E_3~0); 118337#L724-1 assume !(1 == ~E_4~0); 117948#L729-1 assume !(1 == ~E_5~0); 117949#L734-1 assume { :end_inline_reset_delta_events } true; 118437#L940-2 assume !false; 119107#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119101#L586 [2022-11-25 17:59:33,264 INFO L750 eck$LassoCheckResult]: Loop: 119101#L586 assume !false; 119098#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119093#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119094#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 123028#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 123026#L511 assume 0 != eval_~tmp~0#1; 119077#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 118242#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 118243#L516 assume !(0 == ~t1_st~0); 120255#L530 assume !(0 == ~t2_st~0); 119122#L544 assume !(0 == ~t3_st~0); 119115#L558 assume !(0 == ~t4_st~0); 119105#L572 assume !(0 == ~t5_st~0); 119101#L586 [2022-11-25 17:59:33,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:33,265 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2022-11-25 17:59:33,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:33,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635899413] [2022-11-25 17:59:33,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:33,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:33,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:33,278 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:33,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:33,300 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:33,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:33,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1854600747, now seen corresponding path program 1 times [2022-11-25 17:59:33,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:33,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228935435] [2022-11-25 17:59:33,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:33,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:33,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:33,308 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:33,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:33,312 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:33,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:33,313 INFO L85 PathProgramCache]: Analyzing trace with hash 1112358501, now seen corresponding path program 1 times [2022-11-25 17:59:33,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:33,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008950255] [2022-11-25 17:59:33,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:33,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:33,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:33,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:33,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:33,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008950255] [2022-11-25 17:59:33,353 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008950255] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:33,353 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:33,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:33,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417557584] [2022-11-25 17:59:33,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:33,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:33,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:33,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:33,468 INFO L87 Difference]: Start difference. First operand 7997 states and 10936 transitions. cyclomatic complexity: 2945 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:33,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:33,557 INFO L93 Difference]: Finished difference Result 15210 states and 20633 transitions. [2022-11-25 17:59:33,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15210 states and 20633 transitions. [2022-11-25 17:59:33,717 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14611 [2022-11-25 17:59:33,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15210 states to 15210 states and 20633 transitions. [2022-11-25 17:59:33,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15210 [2022-11-25 17:59:33,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15210 [2022-11-25 17:59:33,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15210 states and 20633 transitions. [2022-11-25 17:59:33,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:33,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15210 states and 20633 transitions. [2022-11-25 17:59:33,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15210 states and 20633 transitions. [2022-11-25 17:59:34,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15210 to 14934. [2022-11-25 17:59:34,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14934 states, 14934 states have (on average 1.3572385161376723) internal successors, (20269), 14933 states have internal predecessors, (20269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:34,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14934 states to 14934 states and 20269 transitions. [2022-11-25 17:59:34,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14934 states and 20269 transitions. [2022-11-25 17:59:34,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:34,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 14934 states and 20269 transitions. [2022-11-25 17:59:34,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-25 17:59:34,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14934 states and 20269 transitions. [2022-11-25 17:59:34,141 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14335 [2022-11-25 17:59:34,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:34,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:34,142 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:34,143 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:34,143 INFO L748 eck$LassoCheckResult]: Stem: 141678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 141648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 141470#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 141058#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141059#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 141481#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 141531#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 148858#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 148857#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148856#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 148855#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148854#L611 assume !(0 == ~M_E~0); 148853#L611-2 assume !(0 == ~T1_E~0); 148852#L616-1 assume !(0 == ~T2_E~0); 148851#L621-1 assume !(0 == ~T3_E~0); 148850#L626-1 assume !(0 == ~T4_E~0); 148849#L631-1 assume !(0 == ~T5_E~0); 148848#L636-1 assume !(0 == ~E_M~0); 148847#L641-1 assume !(0 == ~E_1~0); 148846#L646-1 assume !(0 == ~E_2~0); 148845#L651-1 assume !(0 == ~E_3~0); 148844#L656-1 assume !(0 == ~E_4~0); 148843#L661-1 assume !(0 == ~E_5~0); 148842#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148841#L304 assume !(1 == ~m_pc~0); 148840#L304-2 is_master_triggered_~__retres1~0#1 := 0; 148839#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148838#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 148837#L755 assume !(0 != activate_threads_~tmp~1#1); 148836#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148835#L323 assume !(1 == ~t1_pc~0); 148834#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 148833#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148832#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148831#L763 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 141659#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141126#L342 assume !(1 == ~t2_pc~0); 141128#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 141242#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141243#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141654#L771 assume !(0 != activate_threads_~tmp___1~0#1); 141554#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141447#L361 assume !(1 == ~t3_pc~0); 141448#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 141471#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141286#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 141287#L779 assume !(0 != activate_threads_~tmp___2~0#1); 141137#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141138#L380 assume !(1 == ~t4_pc~0); 141444#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141570#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141571#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141485#L787 assume !(0 != activate_threads_~tmp___3~0#1); 141486#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141196#L399 assume !(1 == ~t5_pc~0); 141197#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 141334#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141585#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141325#L795 assume !(0 != activate_threads_~tmp___4~0#1); 141326#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141640#L679 assume !(1 == ~M_E~0); 141409#L679-2 assume !(1 == ~T1_E~0); 141257#L684-1 assume !(1 == ~T2_E~0); 141258#L689-1 assume !(1 == ~T3_E~0); 141458#L694-1 assume !(1 == ~T4_E~0); 141456#L699-1 assume !(1 == ~T5_E~0); 141457#L704-1 assume !(1 == ~E_M~0); 141434#L709-1 assume !(1 == ~E_1~0); 141370#L714-1 assume !(1 == ~E_2~0); 141371#L719-1 assume !(1 == ~E_3~0); 141549#L724-1 assume !(1 == ~E_4~0); 141162#L729-1 assume !(1 == ~E_5~0); 141163#L734-1 assume { :end_inline_reset_delta_events } true; 141646#L940-2 assume !false; 149842#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 149840#L586 [2022-11-25 17:59:34,143 INFO L750 eck$LassoCheckResult]: Loop: 149840#L586 assume !false; 149832#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 149833#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 149823#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 149824#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 149816#L511 assume 0 != eval_~tmp~0#1; 149817#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 149805#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 149806#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 148978#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 149668#L530 assume !(0 == ~t2_st~0); 152581#L544 assume !(0 == ~t3_st~0); 152239#L558 assume !(0 == ~t4_st~0); 149839#L572 assume !(0 == ~t5_st~0); 149840#L586 [2022-11-25 17:59:34,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:34,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2022-11-25 17:59:34,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:34,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916002377] [2022-11-25 17:59:34,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:34,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:34,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:34,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:34,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:34,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916002377] [2022-11-25 17:59:34,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916002377] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:34,178 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:34,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:34,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971946403] [2022-11-25 17:59:34,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:34,180 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:59:34,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:34,182 INFO L85 PathProgramCache]: Analyzing trace with hash 710157811, now seen corresponding path program 1 times [2022-11-25 17:59:34,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:34,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974368623] [2022-11-25 17:59:34,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:34,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:34,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,187 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:34,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:34,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:34,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:34,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:34,415 INFO L87 Difference]: Start difference. First operand 14934 states and 20269 transitions. cyclomatic complexity: 5347 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:34,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:34,463 INFO L93 Difference]: Finished difference Result 12393 states and 16854 transitions. [2022-11-25 17:59:34,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12393 states and 16854 transitions. [2022-11-25 17:59:34,517 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12266 [2022-11-25 17:59:34,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12393 states to 12393 states and 16854 transitions. [2022-11-25 17:59:34,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12393 [2022-11-25 17:59:34,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12393 [2022-11-25 17:59:34,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12393 states and 16854 transitions. [2022-11-25 17:59:34,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:34,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-11-25 17:59:34,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12393 states and 16854 transitions. [2022-11-25 17:59:34,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12393 to 12393. [2022-11-25 17:59:34,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12393 states, 12393 states have (on average 1.3599612684580005) internal successors, (16854), 12392 states have internal predecessors, (16854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:34,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12393 states to 12393 states and 16854 transitions. [2022-11-25 17:59:34,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-11-25 17:59:34,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:34,770 INFO L428 stractBuchiCegarLoop]: Abstraction has 12393 states and 16854 transitions. [2022-11-25 17:59:34,770 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-25 17:59:34,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12393 states and 16854 transitions. [2022-11-25 17:59:34,813 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12266 [2022-11-25 17:59:34,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:34,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:34,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:34,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:34,815 INFO L748 eck$LassoCheckResult]: Stem: 169015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 168978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 168800#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168389#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168390#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 168811#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168653#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168654#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168633#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 168634#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168895#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168742#L611 assume !(0 == ~M_E~0); 168743#L611-2 assume !(0 == ~T1_E~0); 168911#L616-1 assume !(0 == ~T2_E~0); 168912#L621-1 assume !(0 == ~T3_E~0); 168514#L626-1 assume !(0 == ~T4_E~0); 168515#L631-1 assume !(0 == ~T5_E~0); 168699#L636-1 assume !(0 == ~E_M~0); 168551#L641-1 assume !(0 == ~E_1~0); 168552#L646-1 assume !(0 == ~E_2~0); 168713#L651-1 assume !(0 == ~E_3~0); 168961#L656-1 assume !(0 == ~E_4~0); 168893#L661-1 assume !(0 == ~E_5~0); 168894#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168930#L304 assume !(1 == ~m_pc~0); 168571#L304-2 is_master_triggered_~__retres1~0#1 := 0; 168486#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168487#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 168435#L755 assume !(0 != activate_threads_~tmp~1#1); 168436#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168391#L323 assume !(1 == ~t1_pc~0); 168392#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168452#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168453#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 168859#L763 assume !(0 != activate_threads_~tmp___0~0#1); 168991#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168460#L342 assume !(1 == ~t2_pc~0); 168462#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 168573#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168574#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168983#L771 assume !(0 != activate_threads_~tmp___1~0#1); 168887#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168776#L361 assume !(1 == ~t3_pc~0); 168777#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168801#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168616#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 168617#L779 assume !(0 != activate_threads_~tmp___2~0#1); 168471#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168472#L380 assume !(1 == ~t4_pc~0); 168773#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168902#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168903#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168817#L787 assume !(0 != activate_threads_~tmp___3~0#1); 168818#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168530#L399 assume !(1 == ~t5_pc~0); 168531#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 168665#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168917#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168655#L795 assume !(0 != activate_threads_~tmp___4~0#1); 168656#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168970#L679 assume !(1 == ~M_E~0); 168741#L679-2 assume !(1 == ~T1_E~0); 168586#L684-1 assume !(1 == ~T2_E~0); 168587#L689-1 assume !(1 == ~T3_E~0); 168787#L694-1 assume !(1 == ~T4_E~0); 168785#L699-1 assume !(1 == ~T5_E~0); 168786#L704-1 assume !(1 == ~E_M~0); 168763#L709-1 assume !(1 == ~E_1~0); 168701#L714-1 assume !(1 == ~E_2~0); 168702#L719-1 assume !(1 == ~E_3~0); 168883#L724-1 assume !(1 == ~E_4~0); 168496#L729-1 assume !(1 == ~E_5~0); 168497#L734-1 assume { :end_inline_reset_delta_events } true; 168975#L940-2 assume !false; 179006#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179002#L586 [2022-11-25 17:59:34,816 INFO L750 eck$LassoCheckResult]: Loop: 179002#L586 assume !false; 178999#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 178994#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 178991#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 178987#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 178984#L511 assume 0 != eval_~tmp~0#1; 178980#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 178975#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 178972#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 178967#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 178962#L530 assume !(0 == ~t2_st~0); 178960#L544 assume !(0 == ~t3_st~0); 178956#L558 assume !(0 == ~t4_st~0); 178951#L572 assume !(0 == ~t5_st~0); 179002#L586 [2022-11-25 17:59:34,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:34,816 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2022-11-25 17:59:34,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:34,817 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350374114] [2022-11-25 17:59:34,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:34,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:34,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,829 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:34,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,855 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:34,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:34,856 INFO L85 PathProgramCache]: Analyzing trace with hash 710157811, now seen corresponding path program 2 times [2022-11-25 17:59:34,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:34,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504968006] [2022-11-25 17:59:34,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:34,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:34,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,862 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:34,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:34,868 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:34,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:34,869 INFO L85 PathProgramCache]: Analyzing trace with hash -824515335, now seen corresponding path program 1 times [2022-11-25 17:59:34,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:34,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291586220] [2022-11-25 17:59:34,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:34,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:34,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:34,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:34,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:34,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291586220] [2022-11-25 17:59:34,932 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291586220] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:34,932 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:34,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:34,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919858366] [2022-11-25 17:59:34,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:35,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:35,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:35,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:35,084 INFO L87 Difference]: Start difference. First operand 12393 states and 16854 transitions. cyclomatic complexity: 4467 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:35,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:35,307 INFO L93 Difference]: Finished difference Result 23117 states and 31364 transitions. [2022-11-25 17:59:35,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23117 states and 31364 transitions. [2022-11-25 17:59:35,396 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 22944 [2022-11-25 17:59:35,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23117 states to 23117 states and 31364 transitions. [2022-11-25 17:59:35,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23117 [2022-11-25 17:59:35,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23117 [2022-11-25 17:59:35,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23117 states and 31364 transitions. [2022-11-25 17:59:35,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:35,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23117 states and 31364 transitions. [2022-11-25 17:59:35,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23117 states and 31364 transitions. [2022-11-25 17:59:35,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23117 to 22127. [2022-11-25 17:59:35,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22127 states, 22127 states have (on average 1.359696298639671) internal successors, (30086), 22126 states have internal predecessors, (30086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:35,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22127 states to 22127 states and 30086 transitions. [2022-11-25 17:59:35,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22127 states and 30086 transitions. [2022-11-25 17:59:35,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:35,809 INFO L428 stractBuchiCegarLoop]: Abstraction has 22127 states and 30086 transitions. [2022-11-25 17:59:35,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-25 17:59:35,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22127 states and 30086 transitions. [2022-11-25 17:59:35,942 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21954 [2022-11-25 17:59:35,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:35,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:35,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:35,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:35,944 INFO L748 eck$LassoCheckResult]: Stem: 204548#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 204517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 204325#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 203907#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 203908#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 204339#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 204171#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 204172#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 204151#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 204152#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 204430#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 204261#L611 assume !(0 == ~M_E~0); 204262#L611-2 assume !(0 == ~T1_E~0); 204445#L616-1 assume !(0 == ~T2_E~0); 204446#L621-1 assume !(0 == ~T3_E~0); 204034#L626-1 assume !(0 == ~T4_E~0); 204035#L631-1 assume !(0 == ~T5_E~0); 204216#L636-1 assume !(0 == ~E_M~0); 204071#L641-1 assume !(0 == ~E_1~0); 204072#L646-1 assume !(0 == ~E_2~0); 204231#L651-1 assume !(0 == ~E_3~0); 204497#L656-1 assume !(0 == ~E_4~0); 204428#L661-1 assume !(0 == ~E_5~0); 204429#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204466#L304 assume !(1 == ~m_pc~0); 204090#L304-2 is_master_triggered_~__retres1~0#1 := 0; 204004#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 204005#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 203950#L755 assume !(0 != activate_threads_~tmp~1#1); 203951#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203909#L323 assume !(1 == ~t1_pc~0); 203910#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 203969#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203970#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 204391#L763 assume !(0 != activate_threads_~tmp___0~0#1); 204529#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203977#L342 assume !(1 == ~t2_pc~0); 203979#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 204092#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204093#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 204522#L771 assume !(0 != activate_threads_~tmp___1~0#1); 204421#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 204300#L361 assume !(1 == ~t3_pc~0); 204301#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 204326#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 204135#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 204136#L779 assume !(0 != activate_threads_~tmp___2~0#1); 203989#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 203990#L380 assume !(1 == ~t4_pc~0); 204297#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 204436#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 204437#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204344#L787 assume !(0 != activate_threads_~tmp___3~0#1); 204345#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204050#L399 assume !(1 == ~t5_pc~0); 204051#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 204184#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204453#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 204173#L795 assume !(0 != activate_threads_~tmp___4~0#1); 204174#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204508#L679 assume !(1 == ~M_E~0); 204260#L679-2 assume !(1 == ~T1_E~0); 204106#L684-1 assume !(1 == ~T2_E~0); 204107#L689-1 assume !(1 == ~T3_E~0); 204313#L694-1 assume !(1 == ~T4_E~0); 204311#L699-1 assume !(1 == ~T5_E~0); 204312#L704-1 assume !(1 == ~E_M~0); 204286#L709-1 assume !(1 == ~E_1~0); 204218#L714-1 assume !(1 == ~E_2~0); 204219#L719-1 assume !(1 == ~E_3~0); 204415#L724-1 assume !(1 == ~E_4~0); 204015#L729-1 assume !(1 == ~E_5~0); 204016#L734-1 assume { :end_inline_reset_delta_events } true; 204513#L940-2 assume !false; 218909#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 218900#L586 [2022-11-25 17:59:35,944 INFO L750 eck$LassoCheckResult]: Loop: 218900#L586 assume !false; 218893#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 218886#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 218816#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 218745#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 218739#L511 assume 0 != eval_~tmp~0#1; 218731#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 218724#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 209186#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 207473#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 207474#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 217449#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 218924#L544 assume !(0 == ~t3_st~0); 218920#L558 assume !(0 == ~t4_st~0); 218907#L572 assume !(0 == ~t5_st~0); 218900#L586 [2022-11-25 17:59:35,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:35,945 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2022-11-25 17:59:35,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:35,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823268560] [2022-11-25 17:59:35,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:35,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:35,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:35,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:35,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:35,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:35,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:35,985 INFO L85 PathProgramCache]: Analyzing trace with hash 370932868, now seen corresponding path program 1 times [2022-11-25 17:59:35,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:35,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060716476] [2022-11-25 17:59:35,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:35,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:35,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:35,989 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:35,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:35,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:35,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:35,994 INFO L85 PathProgramCache]: Analyzing trace with hash 40705598, now seen corresponding path program 1 times [2022-11-25 17:59:35,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:35,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212627607] [2022-11-25 17:59:35,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:35,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:36,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:36,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:36,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:36,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212627607] [2022-11-25 17:59:36,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212627607] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:36,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:36,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:36,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439377480] [2022-11-25 17:59:36,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:36,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:36,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:36,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:36,209 INFO L87 Difference]: Start difference. First operand 22127 states and 30086 transitions. cyclomatic complexity: 7965 Second operand has 3 states, 3 states have (on average 30.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:36,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:36,368 INFO L93 Difference]: Finished difference Result 40277 states and 54772 transitions. [2022-11-25 17:59:36,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40277 states and 54772 transitions. [2022-11-25 17:59:36,535 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40012 [2022-11-25 17:59:36,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40277 states to 40277 states and 54772 transitions. [2022-11-25 17:59:36,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40277 [2022-11-25 17:59:36,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40277 [2022-11-25 17:59:36,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40277 states and 54772 transitions. [2022-11-25 17:59:36,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:36,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40277 states and 54772 transitions. [2022-11-25 17:59:36,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40277 states and 54772 transitions. [2022-11-25 17:59:37,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40277 to 39017. [2022-11-25 17:59:37,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39017 states, 39017 states have (on average 1.3622779813927262) internal successors, (53152), 39016 states have internal predecessors, (53152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:37,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39017 states to 39017 states and 53152 transitions. [2022-11-25 17:59:37,676 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39017 states and 53152 transitions. [2022-11-25 17:59:37,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:37,677 INFO L428 stractBuchiCegarLoop]: Abstraction has 39017 states and 53152 transitions. [2022-11-25 17:59:37,677 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-25 17:59:37,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39017 states and 53152 transitions. [2022-11-25 17:59:37,827 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38752 [2022-11-25 17:59:37,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:37,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:37,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:37,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:37,829 INFO L748 eck$LassoCheckResult]: Stem: 266981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 266945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 266738#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266317#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 266318#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 266751#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 266582#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 266583#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 266562#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 266563#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 266842#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 266671#L611 assume !(0 == ~M_E~0); 266672#L611-2 assume !(0 == ~T1_E~0); 266859#L616-1 assume !(0 == ~T2_E~0); 266860#L621-1 assume !(0 == ~T3_E~0); 266440#L626-1 assume !(0 == ~T4_E~0); 266441#L631-1 assume !(0 == ~T5_E~0); 266628#L636-1 assume !(0 == ~E_M~0); 266481#L641-1 assume !(0 == ~E_1~0); 266482#L646-1 assume !(0 == ~E_2~0); 266643#L651-1 assume !(0 == ~E_3~0); 266924#L656-1 assume !(0 == ~E_4~0); 266840#L661-1 assume !(0 == ~E_5~0); 266841#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 266885#L304 assume !(1 == ~m_pc~0); 266499#L304-2 is_master_triggered_~__retres1~0#1 := 0; 266415#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266416#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 266362#L755 assume !(0 != activate_threads_~tmp~1#1); 266363#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 266319#L323 assume !(1 == ~t1_pc~0); 266320#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 266382#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 266383#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 266798#L763 assume !(0 != activate_threads_~tmp___0~0#1); 266959#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 266390#L342 assume !(1 == ~t2_pc~0); 266392#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 266504#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 266505#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 266952#L771 assume !(0 != activate_threads_~tmp___1~0#1); 266830#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 266712#L361 assume !(1 == ~t3_pc~0); 266713#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266739#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266547#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 266548#L779 assume !(0 != activate_threads_~tmp___2~0#1); 266401#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266402#L380 assume !(1 == ~t4_pc~0); 266709#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 266850#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266851#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266757#L787 assume !(0 != activate_threads_~tmp___3~0#1); 266758#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266461#L399 assume !(1 == ~t5_pc~0); 266462#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 266594#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 266866#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 266584#L795 assume !(0 != activate_threads_~tmp___4~0#1); 266585#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266932#L679 assume !(1 == ~M_E~0); 266669#L679-2 assume !(1 == ~T1_E~0); 266518#L684-1 assume !(1 == ~T2_E~0); 266519#L689-1 assume !(1 == ~T3_E~0); 266726#L694-1 assume !(1 == ~T4_E~0); 266724#L699-1 assume !(1 == ~T5_E~0); 266725#L704-1 assume !(1 == ~E_M~0); 266697#L709-1 assume !(1 == ~E_1~0); 266629#L714-1 assume !(1 == ~E_2~0); 266630#L719-1 assume !(1 == ~E_3~0); 266826#L724-1 assume !(1 == ~E_4~0); 266426#L729-1 assume !(1 == ~E_5~0); 266427#L734-1 assume { :end_inline_reset_delta_events } true; 266938#L940-2 assume !false; 287364#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 287361#L586 [2022-11-25 17:59:37,830 INFO L750 eck$LassoCheckResult]: Loop: 287361#L586 assume !false; 287360#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 287354#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 287352#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 287350#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 287346#L511 assume 0 != eval_~tmp~0#1; 287343#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 287339#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 287337#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 287334#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 287333#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 287133#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 287332#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 286908#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 287378#L558 assume !(0 == ~t4_st~0); 287362#L572 assume !(0 == ~t5_st~0); 287361#L586 [2022-11-25 17:59:37,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:37,830 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2022-11-25 17:59:37,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:37,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483370419] [2022-11-25 17:59:37,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:37,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:37,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:37,843 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:37,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:37,867 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:37,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:37,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1391436902, now seen corresponding path program 1 times [2022-11-25 17:59:37,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:37,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [821955350] [2022-11-25 17:59:37,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:37,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:37,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:37,874 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:37,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:37,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:37,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:37,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1256419616, now seen corresponding path program 1 times [2022-11-25 17:59:37,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:37,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157442254] [2022-11-25 17:59:37,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:37,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:37,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:38,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:38,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:38,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157442254] [2022-11-25 17:59:38,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157442254] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:38,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:38,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:59:38,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270679683] [2022-11-25 17:59:38,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:38,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:38,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:38,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:38,284 INFO L87 Difference]: Start difference. First operand 39017 states and 53152 transitions. cyclomatic complexity: 14141 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:38,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:38,560 INFO L93 Difference]: Finished difference Result 45199 states and 61510 transitions. [2022-11-25 17:59:38,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45199 states and 61510 transitions. [2022-11-25 17:59:38,737 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44978 [2022-11-25 17:59:38,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45199 states to 45199 states and 61510 transitions. [2022-11-25 17:59:38,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45199 [2022-11-25 17:59:38,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45199 [2022-11-25 17:59:38,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45199 states and 61510 transitions. [2022-11-25 17:59:39,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:39,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45199 states and 61510 transitions. [2022-11-25 17:59:39,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45199 states and 61510 transitions. [2022-11-25 17:59:39,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45199 to 44407. [2022-11-25 17:59:39,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44407 states, 44407 states have (on average 1.362442858107956) internal successors, (60502), 44406 states have internal predecessors, (60502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:39,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44407 states to 44407 states and 60502 transitions. [2022-11-25 17:59:39,772 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44407 states and 60502 transitions. [2022-11-25 17:59:39,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:39,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 44407 states and 60502 transitions. [2022-11-25 17:59:39,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-25 17:59:39,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44407 states and 60502 transitions. [2022-11-25 17:59:40,101 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 44186 [2022-11-25 17:59:40,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:40,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:40,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:40,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:40,103 INFO L748 eck$LassoCheckResult]: Stem: 351244#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 351194#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 350969#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350545#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 350546#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 350982#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 350807#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350808#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 350787#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 350788#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351079#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350904#L611 assume !(0 == ~M_E~0); 350905#L611-2 assume !(0 == ~T1_E~0); 351101#L616-1 assume !(0 == ~T2_E~0); 351102#L621-1 assume !(0 == ~T3_E~0); 350669#L626-1 assume !(0 == ~T4_E~0); 350670#L631-1 assume !(0 == ~T5_E~0); 350858#L636-1 assume !(0 == ~E_M~0); 350708#L641-1 assume !(0 == ~E_1~0); 350709#L646-1 assume !(0 == ~E_2~0); 350874#L651-1 assume !(0 == ~E_3~0); 351172#L656-1 assume !(0 == ~E_4~0); 351077#L661-1 assume !(0 == ~E_5~0); 351078#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 351127#L304 assume !(1 == ~m_pc~0); 350727#L304-2 is_master_triggered_~__retres1~0#1 := 0; 350637#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350638#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 350589#L755 assume !(0 != activate_threads_~tmp~1#1); 350590#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350547#L323 assume !(1 == ~t1_pc~0); 350548#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350605#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350606#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 351037#L763 assume !(0 != activate_threads_~tmp___0~0#1); 351216#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350612#L342 assume !(1 == ~t2_pc~0); 350614#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350729#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350730#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 351209#L771 assume !(0 != activate_threads_~tmp___1~0#1); 351071#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350943#L361 assume !(1 == ~t3_pc~0); 350944#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350970#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350772#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350773#L779 assume !(0 != activate_threads_~tmp___2~0#1); 350622#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350623#L380 assume !(1 == ~t4_pc~0); 350940#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 351089#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 351090#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350987#L787 assume !(0 != activate_threads_~tmp___3~0#1); 350988#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350685#L399 assume !(1 == ~t5_pc~0); 350686#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 350821#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 351109#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 350809#L795 assume !(0 != activate_threads_~tmp___4~0#1); 350810#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 351181#L679 assume !(1 == ~M_E~0); 350903#L679-2 assume !(1 == ~T1_E~0); 350742#L684-1 assume !(1 == ~T2_E~0); 350743#L689-1 assume !(1 == ~T3_E~0); 350957#L694-1 assume !(1 == ~T4_E~0); 350955#L699-1 assume !(1 == ~T5_E~0); 350956#L704-1 assume !(1 == ~E_M~0); 350928#L709-1 assume !(1 == ~E_1~0); 350862#L714-1 assume !(1 == ~E_2~0); 350863#L719-1 assume !(1 == ~E_3~0); 351065#L724-1 assume !(1 == ~E_4~0); 350649#L729-1 assume !(1 == ~E_5~0); 350650#L734-1 assume { :end_inline_reset_delta_events } true; 351189#L940-2 assume !false; 386957#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 386953#L586 [2022-11-25 17:59:40,104 INFO L750 eck$LassoCheckResult]: Loop: 386953#L586 assume !false; 386951#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 386948#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 386949#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 388997#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 388995#L511 assume 0 != eval_~tmp~0#1; 388994#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 388991#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 388990#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 388989#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 388988#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 388887#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 386990#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 386979#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 386972#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 386961#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 386955#L572 assume !(0 == ~t5_st~0); 386953#L586 [2022-11-25 17:59:40,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:40,104 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2022-11-25 17:59:40,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:40,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963408489] [2022-11-25 17:59:40,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:40,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:40,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:40,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:40,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:40,135 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:40,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:40,135 INFO L85 PathProgramCache]: Analyzing trace with hash -185045283, now seen corresponding path program 1 times [2022-11-25 17:59:40,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:40,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056596933] [2022-11-25 17:59:40,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:40,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:40,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:40,142 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:40,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:40,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:40,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:40,150 INFO L85 PathProgramCache]: Analyzing trace with hash 294128151, now seen corresponding path program 1 times [2022-11-25 17:59:40,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:40,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334647185] [2022-11-25 17:59:40,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:40,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:40,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:59:40,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:59:40,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:59:40,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334647185] [2022-11-25 17:59:40,199 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334647185] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:59:40,199 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:59:40,199 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:59:40,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736163389] [2022-11-25 17:59:40,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:59:40,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:59:40,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:59:40,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:59:40,414 INFO L87 Difference]: Start difference. First operand 44407 states and 60502 transitions. cyclomatic complexity: 16101 Second operand has 3 states, 2 states have (on average 46.0) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:40,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:59:40,688 INFO L93 Difference]: Finished difference Result 77457 states and 105418 transitions. [2022-11-25 17:59:40,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77457 states and 105418 transitions. [2022-11-25 17:59:41,201 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 77096 [2022-11-25 17:59:41,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77457 states to 77457 states and 105418 transitions. [2022-11-25 17:59:41,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77457 [2022-11-25 17:59:41,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77457 [2022-11-25 17:59:41,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77457 states and 105418 transitions. [2022-11-25 17:59:41,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:59:41,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77457 states and 105418 transitions. [2022-11-25 17:59:41,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77457 states and 105418 transitions. [2022-11-25 17:59:42,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77457 to 76721. [2022-11-25 17:59:42,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76721 states, 76721 states have (on average 1.364450411230302) internal successors, (104682), 76720 states have internal predecessors, (104682), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:59:42,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76721 states to 76721 states and 104682 transitions. [2022-11-25 17:59:42,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76721 states and 104682 transitions. [2022-11-25 17:59:42,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:59:42,809 INFO L428 stractBuchiCegarLoop]: Abstraction has 76721 states and 104682 transitions. [2022-11-25 17:59:42,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-11-25 17:59:42,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76721 states and 104682 transitions. [2022-11-25 17:59:43,076 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 76360 [2022-11-25 17:59:43,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:59:43,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:59:43,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:43,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:59:43,078 INFO L748 eck$LassoCheckResult]: Stem: 473148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 473090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 472846#L903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 472413#L419 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 472414#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 472859#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 472686#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 472687#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 472664#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 472665#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 472965#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 472777#L611 assume !(0 == ~M_E~0); 472778#L611-2 assume !(0 == ~T1_E~0); 472986#L616-1 assume !(0 == ~T2_E~0); 472987#L621-1 assume !(0 == ~T3_E~0); 472534#L626-1 assume !(0 == ~T4_E~0); 472535#L631-1 assume !(0 == ~T5_E~0); 472731#L636-1 assume !(0 == ~E_M~0); 472579#L641-1 assume !(0 == ~E_1~0); 472580#L646-1 assume !(0 == ~E_2~0); 472750#L651-1 assume !(0 == ~E_3~0); 473066#L656-1 assume !(0 == ~E_4~0); 472963#L661-1 assume !(0 == ~E_5~0); 472964#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 473020#L304 assume !(1 == ~m_pc~0); 472599#L304-2 is_master_triggered_~__retres1~0#1 := 0; 472511#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 472512#L316 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 472456#L755 assume !(0 != activate_threads_~tmp~1#1); 472457#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 472415#L323 assume !(1 == ~t1_pc~0); 472416#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 472477#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472478#L335 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472918#L763 assume !(0 != activate_threads_~tmp___0~0#1); 473112#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 472481#L342 assume !(1 == ~t2_pc~0); 472483#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 472604#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 472605#L354 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 473103#L771 assume !(0 != activate_threads_~tmp___1~0#1); 472953#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472817#L361 assume !(1 == ~t3_pc~0); 472818#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472847#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472649#L373 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 472650#L779 assume !(0 != activate_threads_~tmp___2~0#1); 472493#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 472494#L380 assume !(1 == ~t4_pc~0); 472814#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 472975#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472976#L392 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 472865#L787 assume !(0 != activate_threads_~tmp___3~0#1); 472866#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472558#L399 assume !(1 == ~t5_pc~0); 472559#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472699#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472996#L411 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 472688#L795 assume !(0 != activate_threads_~tmp___4~0#1); 472689#L795-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473077#L679 assume !(1 == ~M_E~0); 472775#L679-2 assume !(1 == ~T1_E~0); 472617#L684-1 assume !(1 == ~T2_E~0); 472618#L689-1 assume !(1 == ~T3_E~0); 472830#L694-1 assume !(1 == ~T4_E~0); 472828#L699-1 assume !(1 == ~T5_E~0); 472829#L704-1 assume !(1 == ~E_M~0); 472803#L709-1 assume !(1 == ~E_1~0); 472735#L714-1 assume !(1 == ~E_2~0); 472736#L719-1 assume !(1 == ~E_3~0); 472947#L724-1 assume !(1 == ~E_4~0); 472522#L729-1 assume !(1 == ~E_5~0); 472523#L734-1 assume { :end_inline_reset_delta_events } true; 473084#L940-2 assume !false; 504243#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 504240#L586 [2022-11-25 17:59:43,078 INFO L750 eck$LassoCheckResult]: Loop: 504240#L586 assume !false; 504238#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 504236#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 504233#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 504231#L497 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 504229#L511 assume 0 != eval_~tmp~0#1; 504226#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 504221#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 504222#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 498459#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 498460#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 510292#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 510291#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 510288#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 510286#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 510283#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 504247#L572 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 504244#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 504240#L586 [2022-11-25 17:59:43,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:43,079 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2022-11-25 17:59:43,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:43,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712102619] [2022-11-25 17:59:43,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:43,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:43,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:43,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:43,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:43,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1441440447, now seen corresponding path program 1 times [2022-11-25 17:59:43,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:43,115 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241245919] [2022-11-25 17:59:43,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:43,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:43,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:43,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,125 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:43,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:59:43,126 INFO L85 PathProgramCache]: Analyzing trace with hash 528034119, now seen corresponding path program 1 times [2022-11-25 17:59:43,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:59:43,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949177172] [2022-11-25 17:59:43,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:59:43,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:59:43,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,139 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:43,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:43,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-11-25 17:59:45,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:45,452 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-25 17:59:45,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-25 17:59:45,723 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 05:59:45 BoogieIcfgContainer [2022-11-25 17:59:45,723 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-11-25 17:59:45,724 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-25 17:59:45,724 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-25 17:59:45,724 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-25 17:59:45,725 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:59:26" (3/4) ... [2022-11-25 17:59:45,728 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-11-25 17:59:46,104 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/witness.graphml [2022-11-25 17:59:46,104 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-25 17:59:46,104 INFO L158 Benchmark]: Toolchain (without parser) took 22144.44ms. Allocated memory was 153.1MB in the beginning and 9.1GB in the end (delta: 9.0GB). Free memory was 109.7MB in the beginning and 8.2GB in the end (delta: -8.1GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2022-11-25 17:59:46,105 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 107.0MB. Free memory is still 75.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-25 17:59:46,105 INFO L158 Benchmark]: CACSL2BoogieTranslator took 488.19ms. Allocated memory is still 153.1MB. Free memory was 109.0MB in the beginning and 116.5MB in the end (delta: -7.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-25 17:59:46,105 INFO L158 Benchmark]: Boogie Procedure Inliner took 73.08ms. Allocated memory is still 153.1MB. Free memory was 116.5MB in the beginning and 111.5MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-25 17:59:46,106 INFO L158 Benchmark]: Boogie Preprocessor took 63.71ms. Allocated memory is still 153.1MB. Free memory was 111.5MB in the beginning and 106.6MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-25 17:59:46,106 INFO L158 Benchmark]: RCFGBuilder took 1587.13ms. Allocated memory is still 153.1MB. Free memory was 106.6MB in the beginning and 47.8MB in the end (delta: 58.7MB). Peak memory consumption was 58.7MB. Max. memory is 16.1GB. [2022-11-25 17:59:46,106 INFO L158 Benchmark]: BuchiAutomizer took 19536.98ms. Allocated memory was 153.1MB in the beginning and 9.1GB in the end (delta: 9.0GB). Free memory was 47.8MB in the beginning and 7.9GB in the end (delta: -7.8GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2022-11-25 17:59:46,107 INFO L158 Benchmark]: Witness Printer took 380.13ms. Allocated memory is still 9.1GB. Free memory was 7.9GB in the beginning and 8.2GB in the end (delta: -311.4MB). Peak memory consumption was 100.7MB. Max. memory is 16.1GB. [2022-11-25 17:59:46,108 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 107.0MB. Free memory is still 75.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 488.19ms. Allocated memory is still 153.1MB. Free memory was 109.0MB in the beginning and 116.5MB in the end (delta: -7.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 73.08ms. Allocated memory is still 153.1MB. Free memory was 116.5MB in the beginning and 111.5MB in the end (delta: 5.0MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 63.71ms. Allocated memory is still 153.1MB. Free memory was 111.5MB in the beginning and 106.6MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1587.13ms. Allocated memory is still 153.1MB. Free memory was 106.6MB in the beginning and 47.8MB in the end (delta: 58.7MB). Peak memory consumption was 58.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 19536.98ms. Allocated memory was 153.1MB in the beginning and 9.1GB in the end (delta: 9.0GB). Free memory was 47.8MB in the beginning and 7.9GB in the end (delta: -7.8GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 380.13ms. Allocated memory is still 9.1GB. Free memory was 7.9GB in the beginning and 8.2GB in the end (delta: -311.4MB). Peak memory consumption was 100.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 76721 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 19.2s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 6.5s. Construction of modules took 0.9s. Büchi inclusion checks took 10.3s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 5.2s AutomataMinimizationTime, 23 MinimizatonAttempts, 24011 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 2.5s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 23488 SdHoareTripleChecker+Valid, 1.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 23488 mSDsluCounter, 39044 SdHoareTripleChecker+Invalid, 0.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18650 mSDsCounter, 312 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 665 IncrementalHoareTripleChecker+Invalid, 977 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 312 mSolverCounterUnsat, 20394 mSDtfsCounter, 665 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [__retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-11-25 17:59:46,232 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cab4c2e-3951-4efa-b1be-dee22b74bee8/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)