./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-25 17:17:28,159 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-25 17:17:28,161 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-25 17:17:28,206 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-25 17:17:28,206 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-25 17:17:28,207 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-25 17:17:28,209 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-25 17:17:28,227 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-25 17:17:28,229 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-25 17:17:28,230 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-25 17:17:28,231 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-25 17:17:28,235 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-25 17:17:28,235 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-25 17:17:28,239 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-25 17:17:28,241 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-25 17:17:28,242 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-25 17:17:28,243 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-25 17:17:28,243 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-25 17:17:28,245 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-25 17:17:28,247 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-25 17:17:28,248 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-25 17:17:28,254 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-25 17:17:28,258 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-25 17:17:28,259 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-25 17:17:28,272 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-25 17:17:28,272 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-25 17:17:28,273 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-25 17:17:28,273 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-25 17:17:28,274 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-25 17:17:28,275 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-25 17:17:28,275 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-25 17:17:28,276 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-25 17:17:28,277 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-25 17:17:28,277 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-25 17:17:28,278 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-25 17:17:28,279 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-25 17:17:28,279 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-25 17:17:28,280 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-25 17:17:28,280 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-25 17:17:28,281 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-25 17:17:28,281 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-25 17:17:28,282 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-11-25 17:17:28,303 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-25 17:17:28,303 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-25 17:17:28,304 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-25 17:17:28,304 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-25 17:17:28,305 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-11-25 17:17:28,305 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-11-25 17:17:28,305 INFO L138 SettingsManager]: * Use SBE=true [2022-11-25 17:17:28,306 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-11-25 17:17:28,306 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-11-25 17:17:28,306 INFO L138 SettingsManager]: * Use old map elimination=false [2022-11-25 17:17:28,306 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-11-25 17:17:28,307 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-11-25 17:17:28,307 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-11-25 17:17:28,307 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-25 17:17:28,307 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-25 17:17:28,307 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-11-25 17:17:28,308 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-25 17:17:28,308 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-25 17:17:28,308 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-25 17:17:28,308 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-11-25 17:17:28,309 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-11-25 17:17:28,309 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-11-25 17:17:28,309 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-25 17:17:28,309 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-25 17:17:28,309 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-11-25 17:17:28,310 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-25 17:17:28,310 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-11-25 17:17:28,310 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-25 17:17:28,310 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-25 17:17:28,311 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-25 17:17:28,311 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-11-25 17:17:28,312 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-11-25 17:17:28,312 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2022-11-25 17:17:28,617 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-25 17:17:28,642 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-25 17:17:28,645 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-25 17:17:28,646 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-25 17:17:28,647 INFO L275 PluginConnector]: CDTParser initialized [2022-11-25 17:17:28,648 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2022-11-25 17:17:31,767 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-25 17:17:32,027 INFO L351 CDTParser]: Found 1 translation units. [2022-11-25 17:17:32,027 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2022-11-25 17:17:32,039 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/data/63c6ee4e6/53df86b30a114bd88598f7817225599e/FLAG62737af81 [2022-11-25 17:17:32,060 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/data/63c6ee4e6/53df86b30a114bd88598f7817225599e [2022-11-25 17:17:32,063 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-25 17:17:32,064 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-25 17:17:32,066 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-25 17:17:32,066 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-25 17:17:32,075 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-25 17:17:32,076 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,076 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@28d1b8b7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32, skipping insertion in model container [2022-11-25 17:17:32,077 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,086 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-25 17:17:32,159 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-25 17:17:32,319 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2022-11-25 17:17:32,422 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:17:32,437 INFO L203 MainTranslator]: Completed pre-run [2022-11-25 17:17:32,449 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2022-11-25 17:17:32,515 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-25 17:17:32,546 INFO L208 MainTranslator]: Completed translation [2022-11-25 17:17:32,547 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32 WrapperNode [2022-11-25 17:17:32,547 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-25 17:17:32,548 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-25 17:17:32,548 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-25 17:17:32,548 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-25 17:17:32,554 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,566 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,658 INFO L138 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 182, statements flattened = 2757 [2022-11-25 17:17:32,658 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-25 17:17:32,659 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-25 17:17:32,659 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-25 17:17:32,659 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-25 17:17:32,689 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,689 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,699 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,699 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,761 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,815 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,819 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,833 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,847 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-25 17:17:32,849 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-25 17:17:32,849 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-25 17:17:32,850 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-25 17:17:32,851 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (1/1) ... [2022-11-25 17:17:32,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-11-25 17:17:32,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/z3 [2022-11-25 17:17:32,888 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-11-25 17:17:32,915 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_14df3e78-73bf-4ebb-9e5f-8f17bd3ace2e/bin/uautomizer-ZsLfNo2U6R/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-11-25 17:17:32,946 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-25 17:17:32,946 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-25 17:17:32,946 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-25 17:17:32,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-25 17:17:33,120 INFO L235 CfgBuilder]: Building ICFG [2022-11-25 17:17:33,123 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-25 17:17:35,109 INFO L276 CfgBuilder]: Performing block encoding [2022-11-25 17:17:35,137 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-25 17:17:35,138 INFO L300 CfgBuilder]: Removed 12 assume(true) statements. [2022-11-25 17:17:35,142 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:17:35 BoogieIcfgContainer [2022-11-25 17:17:35,142 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-25 17:17:35,144 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-11-25 17:17:35,144 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-11-25 17:17:35,148 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-11-25 17:17:35,150 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:35,150 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 05:17:32" (1/3) ... [2022-11-25 17:17:35,152 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@33822c7e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:17:35, skipping insertion in model container [2022-11-25 17:17:35,153 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:35,153 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:17:32" (2/3) ... [2022-11-25 17:17:35,154 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@33822c7e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 05:17:35, skipping insertion in model container [2022-11-25 17:17:35,154 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-11-25 17:17:35,154 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:17:35" (3/3) ... [2022-11-25 17:17:35,160 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2022-11-25 17:17:35,275 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-11-25 17:17:35,275 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-11-25 17:17:35,276 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-11-25 17:17:35,276 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-11-25 17:17:35,276 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-11-25 17:17:35,276 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-11-25 17:17:35,276 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-11-25 17:17:35,276 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-11-25 17:17:35,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:35,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2022-11-25 17:17:35,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:35,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:35,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:35,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:35,373 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-11-25 17:17:35,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:35,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2022-11-25 17:17:35,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:35,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:35,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:35,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:35,410 INFO L748 eck$LassoCheckResult]: Stem: 547#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1060#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 499#L1391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 866#L651true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 750#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 399#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 771#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 715#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 274#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 810#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 622#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1029#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 105#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 334#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1019#L939true assume !(0 == ~M_E~0); 530#L939-2true assume !(0 == ~T1_E~0); 744#L944-1true assume !(0 == ~T2_E~0); 355#L949-1true assume !(0 == ~T3_E~0); 353#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1068#L959-1true assume !(0 == ~T5_E~0); 772#L964-1true assume !(0 == ~T6_E~0); 186#L969-1true assume !(0 == ~T7_E~0); 887#L974-1true assume !(0 == ~T8_E~0); 702#L979-1true assume !(0 == ~T9_E~0); 1095#L984-1true assume !(0 == ~E_M~0); 281#L989-1true assume !(0 == ~E_1~0); 509#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 213#L999-1true assume !(0 == ~E_3~0); 669#L1004-1true assume !(0 == ~E_4~0); 39#L1009-1true assume !(0 == ~E_5~0); 208#L1014-1true assume !(0 == ~E_6~0); 629#L1019-1true assume !(0 == ~E_7~0); 937#L1024-1true assume !(0 == ~E_8~0); 169#L1029-1true assume !(0 == ~E_9~0); 221#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 952#L460true assume 1 == ~m_pc~0; 2#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 595#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1050#L472true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1023#L1167true assume !(0 != activate_threads_~tmp~1#1); 345#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 492#L479true assume 1 == ~t1_pc~0; 335#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1039#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 890#L491true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 387#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97#L498true assume !(1 == ~t2_pc~0); 638#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 333#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 830#L510true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 670#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 586#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1119#L517true assume 1 == ~t3_pc~0; 898#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1062#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 382#L529true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 194#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 640#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 811#L536true assume !(1 == ~t4_pc~0); 1097#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 761#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1086#L548true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1084#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 558#L555true assume 1 == ~t5_pc~0; 1164#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 699#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54#L567true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 170#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 108#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58#L574true assume !(1 == ~t6_pc~0); 631#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1101#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111#L586true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 664#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1092#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 967#L593true assume 1 == ~t7_pc~0; 1137#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 777#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1083#L605true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1077#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 901#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279#L612true assume !(1 == ~t8_pc~0); 1016#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 891#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 473#L624true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 806#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 443#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 498#L631true assume 1 == ~t9_pc~0; 455#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38#L643true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1049#L1239-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 642#L1047true assume !(1 == ~M_E~0); 25#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 437#L1052-1true assume !(1 == ~T2_E~0); 17#L1057-1true assume !(1 == ~T3_E~0); 160#L1062-1true assume !(1 == ~T4_E~0); 773#L1067-1true assume !(1 == ~T5_E~0); 347#L1072-1true assume !(1 == ~T6_E~0); 610#L1077-1true assume !(1 == ~T7_E~0); 103#L1082-1true assume !(1 == ~T8_E~0); 418#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 5#L1092-1true assume !(1 == ~E_M~0); 18#L1097-1true assume !(1 == ~E_1~0); 941#L1102-1true assume !(1 == ~E_2~0); 494#L1107-1true assume !(1 == ~E_3~0); 439#L1112-1true assume !(1 == ~E_4~0); 474#L1117-1true assume !(1 == ~E_5~0); 1152#L1122-1true assume !(1 == ~E_6~0); 383#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 223#L1132-1true assume !(1 == ~E_8~0); 945#L1137-1true assume !(1 == ~E_9~0); 159#L1142-1true assume { :end_inline_reset_delta_events } true; 89#L1428-2true [2022-11-25 17:17:35,413 INFO L750 eck$LassoCheckResult]: Loop: 89#L1428-2true assume !false; 436#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 970#L914true assume false; 215#L929true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 493#L651-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 758#L939-3true assume !(0 == ~M_E~0); 116#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 143#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 4#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 718#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 359#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 40#L964-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 142#L974-3true assume !(0 == ~T8_E~0); 1054#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 413#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1141#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 173#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 968#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 537#L1004-3true assume 0 == ~E_4~0;~E_4~0 := 1; 81#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 616#L1014-3true assume !(0 == ~E_6~0); 400#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1112#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 390#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 361#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 921#L460-33true assume !(1 == ~m_pc~0); 570#L460-35true is_master_triggered_~__retres1~0#1 := 0; 549#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 225#L472-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 500#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189#L479-33true assume 1 == ~t1_pc~0; 933#L480-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 171#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604#L491-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 869#L1175-33true assume !(0 != activate_threads_~tmp___0~0#1); 991#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193#L498-33true assume !(1 == ~t2_pc~0); 60#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 320#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129#L510-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 428#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 999#L517-33true assume 1 == ~t3_pc~0; 1034#L518-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 736#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1090#L529-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 524#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 665#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 249#L536-33true assume !(1 == ~t4_pc~0); 1009#L536-35true is_transmit4_triggered_~__retres1~4#1 := 0; 289#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 417#L548-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 708#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 812#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29#L555-33true assume !(1 == ~t5_pc~0); 799#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 469#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 165#L567-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 489#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1033#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16#L574-33true assume 1 == ~t6_pc~0; 721#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 845#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 174#L586-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 571#L1215-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 331#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50#L593-33true assume 1 == ~t7_pc~0; 398#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 953#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102#L605-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 548#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 694#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1118#L612-33true assume 1 == ~t8_pc~0; 918#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 852#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1087#L624-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 609#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1161#L631-33true assume !(1 == ~t9_pc~0); 496#L631-35true is_transmit9_triggered_~__retres1~9#1 := 0; 72#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#L643-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 207#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 130#L1239-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226#L1047-3true assume !(1 == ~M_E~0); 770#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1172#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 676#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1166#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 78#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1024#L1072-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 294#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 198#L1082-3true assume !(1 == ~T8_E~0); 247#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 433#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1177#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 381#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 951#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 727#L1112-3true assume 1 == ~E_4~0;~E_4~0 := 2; 195#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 734#L1122-3true assume !(1 == ~E_6~0); 227#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 508#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1079#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 485#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 132#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 491#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 486#L769-1true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 306#L1447true assume !(0 == start_simulation_~tmp~3#1); 701#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1139#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 731#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 510#L769-2true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 212#L1402true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 84#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 532#L1410true start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 348#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 89#L1428-2true [2022-11-25 17:17:35,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:35,421 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2022-11-25 17:17:35,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:35,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318424973] [2022-11-25 17:17:35,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:35,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:35,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:35,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:35,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:35,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318424973] [2022-11-25 17:17:35,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318424973] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:35,745 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:35,745 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:35,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996372762] [2022-11-25 17:17:35,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:35,752 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:35,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:35,756 INFO L85 PathProgramCache]: Analyzing trace with hash -748013534, now seen corresponding path program 1 times [2022-11-25 17:17:35,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:35,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578917638] [2022-11-25 17:17:35,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:35,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:35,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:35,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:35,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:35,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578917638] [2022-11-25 17:17:35,883 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578917638] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:35,883 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:35,883 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:35,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86519473] [2022-11-25 17:17:35,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:35,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:35,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:35,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:35,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:35,934 INFO L87 Difference]: Start difference. First operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:36,029 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2022-11-25 17:17:36,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2022-11-25 17:17:36,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1170 states and 1742 transitions. [2022-11-25 17:17:36,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:36,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:36,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1742 transitions. [2022-11-25 17:17:36,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:36,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-11-25 17:17:36,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1742 transitions. [2022-11-25 17:17:36,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:36,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1742 transitions. [2022-11-25 17:17:36,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-11-25 17:17:36,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:36,167 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-11-25 17:17:36,167 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-11-25 17:17:36,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1742 transitions. [2022-11-25 17:17:36,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:36,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:36,178 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,178 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,179 INFO L748 eck$LassoCheckResult]: Stem: 3232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3182#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3183#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3401#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3068#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3069#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3378#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2877#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2878#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3306#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3307#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2376#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2377#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2580#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2968#L939 assume !(0 == ~M_E~0); 3212#L939-2 assume !(0 == ~T1_E~0); 3213#L944-1 assume !(0 == ~T2_E~0); 2997#L949-1 assume !(0 == ~T3_E~0); 2995#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2996#L959-1 assume !(0 == ~T5_E~0); 3415#L964-1 assume !(0 == ~T6_E~0); 2728#L969-1 assume !(0 == ~T7_E~0); 2729#L974-1 assume !(0 == ~T8_E~0); 3366#L979-1 assume !(0 == ~T9_E~0); 3367#L984-1 assume !(0 == ~E_M~0); 2889#L989-1 assume !(0 == ~E_1~0); 2890#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2778#L999-1 assume !(0 == ~E_3~0); 2779#L1004-1 assume !(0 == ~E_4~0); 2444#L1009-1 assume !(0 == ~E_5~0); 2445#L1014-1 assume !(0 == ~E_6~0); 2772#L1019-1 assume !(0 == ~E_7~0); 3311#L1024-1 assume !(0 == ~E_8~0); 2701#L1029-1 assume !(0 == ~E_9~0); 2702#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2792#L460 assume 1 == ~m_pc~0; 2360#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2361#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3277#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3516#L1167 assume !(0 != activate_threads_~tmp~1#1); 2985#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2986#L479 assume 1 == ~t1_pc~0; 2969#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2970#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2713#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2714#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L498 assume !(1 == ~t2_pc~0); 2563#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2967#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3344#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3268#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3269#L517 assume 1 == ~t3_pc~0; 3477#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3478#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2746#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2747#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3322#L536 assume !(1 == ~t4_pc~0); 3030#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3029#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3406#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3023#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3242#L555 assume 1 == ~t5_pc~0; 3243#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3312#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2475#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2476#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2583#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2483#L574 assume !(1 == ~t6_pc~0); 2484#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3115#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2588#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2589#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3340#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3500#L593 assume 1 == ~t7_pc~0; 3501#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2720#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3418#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3521#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3481#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2884#L612 assume !(1 == ~t8_pc~0); 2885#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3294#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3152#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3153#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3117#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3118#L631 assume 1 == ~t9_pc~0; 3136#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2474#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2442#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2443#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2972#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3323#L1047 assume !(1 == ~M_E~0); 2412#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2413#L1052-1 assume !(1 == ~T2_E~0); 2395#L1057-1 assume !(1 == ~T3_E~0); 2396#L1062-1 assume !(1 == ~T4_E~0); 2685#L1067-1 assume !(1 == ~T5_E~0); 2988#L1072-1 assume !(1 == ~T6_E~0); 2989#L1077-1 assume !(1 == ~T7_E~0); 2576#L1082-1 assume !(1 == ~T8_E~0); 2577#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2370#L1092-1 assume !(1 == ~E_M~0); 2371#L1097-1 assume !(1 == ~E_1~0); 2397#L1102-1 assume !(1 == ~E_2~0); 3178#L1107-1 assume !(1 == ~E_3~0); 3113#L1112-1 assume !(1 == ~E_4~0); 3114#L1117-1 assume !(1 == ~E_5~0); 3154#L1122-1 assume !(1 == ~E_6~0); 3041#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2797#L1132-1 assume !(1 == ~E_8~0); 2798#L1137-1 assume !(1 == ~E_9~0); 2684#L1142-1 assume { :end_inline_reset_delta_events } true; 2544#L1428-2 [2022-11-25 17:17:36,179 INFO L750 eck$LassoCheckResult]: Loop: 2544#L1428-2 assume !false; 2545#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2619#L914 assume !false; 3109#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3110#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2381#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2382#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3341#L783 assume !(0 != eval_~tmp~0#1); 2781#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2782#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3177#L939-3 assume !(0 == ~M_E~0); 2600#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2601#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3003#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2446#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2447#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2653#L974-3 assume !(0 == ~T8_E~0); 2654#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3084#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3085#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2707#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2708#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3219#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2530#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2531#L1014-3 assume !(0 == ~E_6~0); 3070#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3071#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3052#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3004#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3005#L460-33 assume 1 == ~m_pc~0; 3042#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3043#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2799#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2374#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2375#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2736#L479-33 assume !(1 == ~t1_pc~0); 2737#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2703#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3288#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3461#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2744#L498-33 assume 1 == ~t2_pc~0; 2745#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2490#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2626#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2627#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2602#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2603#L517-33 assume !(1 == ~t3_pc~0); 3509#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3392#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3205#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3206#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2831#L536-33 assume 1 == ~t4_pc~0; 2832#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2901#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2902#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3092#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3371#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2421#L555-33 assume !(1 == ~t5_pc~0); 2422#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3147#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2694#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2695#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3174#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2387#L574-33 assume 1 == ~t6_pc~0; 2388#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3383#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2709#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2710#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2963#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2463#L593-33 assume !(1 == ~t7_pc~0); 2464#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2919#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2574#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2575#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3234#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3361#L612-33 assume 1 == ~t8_pc~0; 3488#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3452#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3453#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3295#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2570#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2571#L631-33 assume 1 == ~t9_pc~0; 3413#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2512#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2513#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2767#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2624#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2625#L1047-3 assume !(1 == ~M_E~0); 2800#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3414#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3346#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3347#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2525#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2526#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2908#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2753#L1082-3 assume !(1 == ~T8_E~0); 2754#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2827#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3108#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3038#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3039#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3384#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2748#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2749#L1122-3 assume !(1 == ~E_6~0); 2801#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2802#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3191#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3168#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2628#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2506#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3169#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2926#L1447 assume !(0 == start_simulation_~tmp~3#1); 2927#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3365#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2667#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3192#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2777#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2534#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2535#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2990#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2544#L1428-2 [2022-11-25 17:17:36,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2022-11-25 17:17:36,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084674663] [2022-11-25 17:17:36,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:36,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:36,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:36,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084674663] [2022-11-25 17:17:36,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084674663] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:36,282 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:36,282 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:36,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765036848] [2022-11-25 17:17:36,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:36,283 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:36,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,284 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 1 times [2022-11-25 17:17:36,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847674685] [2022-11-25 17:17:36,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:36,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:36,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:36,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847674685] [2022-11-25 17:17:36,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847674685] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:36,472 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:36,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:36,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692772775] [2022-11-25 17:17:36,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:36,474 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:36,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:36,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:36,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:36,475 INFO L87 Difference]: Start difference. First operand 1170 states and 1742 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:36,511 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2022-11-25 17:17:36,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1741 transitions. [2022-11-25 17:17:36,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1741 transitions. [2022-11-25 17:17:36,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:36,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:36,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1741 transitions. [2022-11-25 17:17:36,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:36,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-11-25 17:17:36,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1741 transitions. [2022-11-25 17:17:36,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:36,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1741 transitions. [2022-11-25 17:17:36,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-11-25 17:17:36,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:36,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-11-25 17:17:36,566 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-11-25 17:17:36,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1741 transitions. [2022-11-25 17:17:36,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:36,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:36,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,583 INFO L748 eck$LassoCheckResult]: Stem: 5579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5529#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5530#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5748#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5415#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5416#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5725#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5224#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5225#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5654#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4723#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4724#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4927#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5315#L939 assume !(0 == ~M_E~0); 5559#L939-2 assume !(0 == ~T1_E~0); 5560#L944-1 assume !(0 == ~T2_E~0); 5344#L949-1 assume !(0 == ~T3_E~0); 5342#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5343#L959-1 assume !(0 == ~T5_E~0); 5762#L964-1 assume !(0 == ~T6_E~0); 5075#L969-1 assume !(0 == ~T7_E~0); 5076#L974-1 assume !(0 == ~T8_E~0); 5715#L979-1 assume !(0 == ~T9_E~0); 5716#L984-1 assume !(0 == ~E_M~0); 5236#L989-1 assume !(0 == ~E_1~0); 5237#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5125#L999-1 assume !(0 == ~E_3~0); 5126#L1004-1 assume !(0 == ~E_4~0); 4791#L1009-1 assume !(0 == ~E_5~0); 4792#L1014-1 assume !(0 == ~E_6~0); 5121#L1019-1 assume !(0 == ~E_7~0); 5658#L1024-1 assume !(0 == ~E_8~0); 5048#L1029-1 assume !(0 == ~E_9~0); 5049#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5139#L460 assume 1 == ~m_pc~0; 4710#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4711#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5624#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5863#L1167 assume !(0 != activate_threads_~tmp~1#1); 5332#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5333#L479 assume 1 == ~t1_pc~0; 5316#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5317#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5820#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5060#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5061#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4909#L498 assume !(1 == ~t2_pc~0); 4910#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5313#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5314#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5691#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5615#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5616#L517 assume 1 == ~t3_pc~0; 5824#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5387#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5093#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5094#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5669#L536 assume !(1 == ~t4_pc~0); 5377#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5376#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5753#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5369#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5589#L555 assume 1 == ~t5_pc~0; 5590#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5659#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4822#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4823#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4930#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4830#L574 assume !(1 == ~t6_pc~0); 4831#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5462#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4935#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4936#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5687#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5847#L593 assume 1 == ~t7_pc~0; 5848#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5067#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5765#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5868#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5828#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5231#L612 assume !(1 == ~t8_pc~0); 5232#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5641#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5500#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5501#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5466#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5467#L631 assume 1 == ~t9_pc~0; 5483#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4821#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4789#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4790#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5319#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5670#L1047 assume !(1 == ~M_E~0); 4759#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4760#L1052-1 assume !(1 == ~T2_E~0); 4742#L1057-1 assume !(1 == ~T3_E~0); 4743#L1062-1 assume !(1 == ~T4_E~0); 5032#L1067-1 assume !(1 == ~T5_E~0); 5335#L1072-1 assume !(1 == ~T6_E~0); 5336#L1077-1 assume !(1 == ~T7_E~0); 4923#L1082-1 assume !(1 == ~T8_E~0); 4924#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4719#L1092-1 assume !(1 == ~E_M~0); 4720#L1097-1 assume !(1 == ~E_1~0); 4744#L1102-1 assume !(1 == ~E_2~0); 5525#L1107-1 assume !(1 == ~E_3~0); 5460#L1112-1 assume !(1 == ~E_4~0); 5461#L1117-1 assume !(1 == ~E_5~0); 5502#L1122-1 assume !(1 == ~E_6~0); 5388#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5144#L1132-1 assume !(1 == ~E_8~0); 5145#L1137-1 assume !(1 == ~E_9~0); 5031#L1142-1 assume { :end_inline_reset_delta_events } true; 4894#L1428-2 [2022-11-25 17:17:36,585 INFO L750 eck$LassoCheckResult]: Loop: 4894#L1428-2 assume !false; 4895#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4966#L914 assume !false; 5456#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5457#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4728#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4729#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5688#L783 assume !(0 != eval_~tmp~0#1); 5128#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5129#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5524#L939-3 assume !(0 == ~M_E~0); 4949#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4950#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4713#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4714#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5350#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4793#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4794#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5000#L974-3 assume !(0 == ~T8_E~0); 5001#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5431#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5432#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5054#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5055#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5566#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4877#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4878#L1014-3 assume !(0 == ~E_6~0); 5417#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5418#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5399#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5351#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5352#L460-33 assume !(1 == ~m_pc~0); 5392#L460-35 is_master_triggered_~__retres1~0#1 := 0; 5391#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5146#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4721#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4722#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5083#L479-33 assume !(1 == ~t1_pc~0); 5084#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5050#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5051#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5635#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 5808#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5088#L498-33 assume 1 == ~t2_pc~0; 5089#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4834#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4971#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4972#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4947#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4948#L517-33 assume !(1 == ~t3_pc~0); 5856#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5739#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5740#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5552#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5553#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5175#L536-33 assume 1 == ~t4_pc~0; 5176#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5248#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5249#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5439#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5718#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4768#L555-33 assume !(1 == ~t5_pc~0); 4769#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 5494#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5041#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5042#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5521#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4737#L574-33 assume 1 == ~t6_pc~0; 4738#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5730#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5056#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5057#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5310#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4813#L593-33 assume !(1 == ~t7_pc~0); 4814#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 5267#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4921#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4922#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5581#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5708#L612-33 assume 1 == ~t8_pc~0; 5835#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5799#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5800#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5642#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4917#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4918#L631-33 assume 1 == ~t9_pc~0; 5760#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4861#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4862#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5114#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4973#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4974#L1047-3 assume !(1 == ~M_E~0); 5147#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5761#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5694#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4872#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4873#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5255#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5100#L1082-3 assume !(1 == ~T8_E~0); 5101#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5174#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5455#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5385#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5386#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5731#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5095#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5096#L1122-3 assume !(1 == ~E_6~0); 5148#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5149#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5538#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5515#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4975#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4853#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5516#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5273#L1447 assume !(0 == start_simulation_~tmp~3#1); 5274#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5712#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5014#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5539#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 5124#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4881#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4882#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5337#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4894#L1428-2 [2022-11-25 17:17:36,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2022-11-25 17:17:36,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157566618] [2022-11-25 17:17:36,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:36,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:36,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:36,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157566618] [2022-11-25 17:17:36,710 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157566618] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:36,711 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:36,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:36,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466029280] [2022-11-25 17:17:36,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:36,712 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:36,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1367214863, now seen corresponding path program 1 times [2022-11-25 17:17:36,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517131375] [2022-11-25 17:17:36,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:36,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:36,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:36,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517131375] [2022-11-25 17:17:36,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517131375] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:36,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:36,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:36,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808353526] [2022-11-25 17:17:36,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:36,783 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:36,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:36,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:36,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:36,784 INFO L87 Difference]: Start difference. First operand 1170 states and 1741 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:36,813 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2022-11-25 17:17:36,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1740 transitions. [2022-11-25 17:17:36,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1740 transitions. [2022-11-25 17:17:36,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:36,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:36,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1740 transitions. [2022-11-25 17:17:36,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:36,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-11-25 17:17:36,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1740 transitions. [2022-11-25 17:17:36,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:36,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:36,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1740 transitions. [2022-11-25 17:17:36,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-11-25 17:17:36,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:36,856 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-11-25 17:17:36,856 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-11-25 17:17:36,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1740 transitions. [2022-11-25 17:17:36,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:36,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:36,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:36,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:36,871 INFO L748 eck$LassoCheckResult]: Stem: 7926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7876#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7877#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8095#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7764#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8072#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7571#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7572#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8000#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8001#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7070#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7071#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7274#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7662#L939 assume !(0 == ~M_E~0); 7906#L939-2 assume !(0 == ~T1_E~0); 7907#L944-1 assume !(0 == ~T2_E~0); 7691#L949-1 assume !(0 == ~T3_E~0); 7689#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7690#L959-1 assume !(0 == ~T5_E~0); 8109#L964-1 assume !(0 == ~T6_E~0); 7422#L969-1 assume !(0 == ~T7_E~0); 7423#L974-1 assume !(0 == ~T8_E~0); 8062#L979-1 assume !(0 == ~T9_E~0); 8063#L984-1 assume !(0 == ~E_M~0); 7585#L989-1 assume !(0 == ~E_1~0); 7586#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7472#L999-1 assume !(0 == ~E_3~0); 7473#L1004-1 assume !(0 == ~E_4~0); 7138#L1009-1 assume !(0 == ~E_5~0); 7139#L1014-1 assume !(0 == ~E_6~0); 7468#L1019-1 assume !(0 == ~E_7~0); 8005#L1024-1 assume !(0 == ~E_8~0); 7395#L1029-1 assume !(0 == ~E_9~0); 7396#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7488#L460 assume 1 == ~m_pc~0; 7057#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7058#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7971#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8210#L1167 assume !(0 != activate_threads_~tmp~1#1); 7679#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7680#L479 assume 1 == ~t1_pc~0; 7663#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7664#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8167#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7408#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7409#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7256#L498 assume !(1 == ~t2_pc~0); 7257#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7660#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7661#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8038#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7962#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7963#L517 assume 1 == ~t3_pc~0; 8172#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8173#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7734#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7440#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7441#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8016#L536 assume !(1 == ~t4_pc~0); 7724#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7723#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8100#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7716#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7717#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7938#L555 assume 1 == ~t5_pc~0; 7939#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8006#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7171#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7172#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7279#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7177#L574 assume !(1 == ~t6_pc~0); 7178#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7809#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7282#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7283#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8034#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8194#L593 assume 1 == ~t7_pc~0; 8195#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7414#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8114#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8215#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8175#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7578#L612 assume !(1 == ~t8_pc~0); 7579#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7988#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7847#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7848#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7813#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7814#L631 assume 1 == ~t9_pc~0; 7830#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7168#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7136#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7137#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7666#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8017#L1047 assume !(1 == ~M_E~0); 7108#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7109#L1052-1 assume !(1 == ~T2_E~0); 7089#L1057-1 assume !(1 == ~T3_E~0); 7090#L1062-1 assume !(1 == ~T4_E~0); 7379#L1067-1 assume !(1 == ~T5_E~0); 7682#L1072-1 assume !(1 == ~T6_E~0); 7683#L1077-1 assume !(1 == ~T7_E~0); 7270#L1082-1 assume !(1 == ~T8_E~0); 7271#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7066#L1092-1 assume !(1 == ~E_M~0); 7067#L1097-1 assume !(1 == ~E_1~0); 7091#L1102-1 assume !(1 == ~E_2~0); 7872#L1107-1 assume !(1 == ~E_3~0); 7807#L1112-1 assume !(1 == ~E_4~0); 7808#L1117-1 assume !(1 == ~E_5~0); 7849#L1122-1 assume !(1 == ~E_6~0); 7735#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7491#L1132-1 assume !(1 == ~E_8~0); 7492#L1137-1 assume !(1 == ~E_9~0); 7378#L1142-1 assume { :end_inline_reset_delta_events } true; 7241#L1428-2 [2022-11-25 17:17:36,872 INFO L750 eck$LassoCheckResult]: Loop: 7241#L1428-2 assume !false; 7242#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7313#L914 assume !false; 7803#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7804#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7077#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7078#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8035#L783 assume !(0 != eval_~tmp~0#1); 7475#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7476#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7871#L939-3 assume !(0 == ~M_E~0); 7296#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7297#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7060#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7061#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7697#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7142#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7143#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7347#L974-3 assume !(0 == ~T8_E~0); 7348#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7778#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7779#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7401#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7402#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7913#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7224#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7225#L1014-3 assume !(0 == ~E_6~0); 7762#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7763#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7744#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7698#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7699#L460-33 assume 1 == ~m_pc~0; 7736#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7737#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7493#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7068#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7069#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7429#L479-33 assume !(1 == ~t1_pc~0); 7430#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7397#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7398#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7980#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 8155#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7438#L498-33 assume 1 == ~t2_pc~0; 7439#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7184#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7318#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7319#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7294#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7295#L517-33 assume !(1 == ~t3_pc~0); 8203#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8086#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8087#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7899#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7900#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7525#L536-33 assume 1 == ~t4_pc~0; 7526#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7595#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7596#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7786#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8065#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7115#L555-33 assume !(1 == ~t5_pc~0); 7116#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7841#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7388#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7389#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7868#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7086#L574-33 assume !(1 == ~t6_pc~0); 7088#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8077#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7403#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7404#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7657#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7162#L593-33 assume !(1 == ~t7_pc~0); 7163#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7618#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7268#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7269#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7928#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8055#L612-33 assume 1 == ~t8_pc~0; 8182#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8146#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8147#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7989#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7264#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7265#L631-33 assume !(1 == ~t9_pc~0); 7875#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7208#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7209#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7461#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7320#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L1047-3 assume !(1 == ~M_E~0); 7494#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8108#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8040#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8041#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7219#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7220#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7602#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7447#L1082-3 assume !(1 == ~T8_E~0); 7448#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7521#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7802#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7732#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7733#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8078#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7442#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7443#L1122-3 assume !(1 == ~E_6~0); 7495#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7496#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7885#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7862#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7325#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7200#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7863#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7620#L1447 assume !(0 == start_simulation_~tmp~3#1); 7621#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8059#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7361#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7886#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7471#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7228#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7229#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7684#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7241#L1428-2 [2022-11-25 17:17:36,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2022-11-25 17:17:36,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592334416] [2022-11-25 17:17:36,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:36,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:36,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:36,956 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592334416] [2022-11-25 17:17:36,956 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592334416] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:36,956 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:36,957 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:36,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929778153] [2022-11-25 17:17:36,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:36,962 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:36,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:36,963 INFO L85 PathProgramCache]: Analyzing trace with hash -466631152, now seen corresponding path program 1 times [2022-11-25 17:17:36,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:36,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519351030] [2022-11-25 17:17:36,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:36,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:36,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519351030] [2022-11-25 17:17:37,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519351030] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,077 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:37,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496704765] [2022-11-25 17:17:37,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:37,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:37,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:37,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:37,079 INFO L87 Difference]: Start difference. First operand 1170 states and 1740 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:37,106 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2022-11-25 17:17:37,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1739 transitions. [2022-11-25 17:17:37,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1739 transitions. [2022-11-25 17:17:37,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:37,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:37,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1739 transitions. [2022-11-25 17:17:37,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:37,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-11-25 17:17:37,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1739 transitions. [2022-11-25 17:17:37,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:37,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1739 transitions. [2022-11-25 17:17:37,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-11-25 17:17:37,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:37,148 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-11-25 17:17:37,148 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-11-25 17:17:37,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1739 transitions. [2022-11-25 17:17:37,156 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:37,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:37,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,159 INFO L748 eck$LassoCheckResult]: Stem: 10275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10225#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10226#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10444#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10111#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10112#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10421#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9920#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9921#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10347#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10348#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9419#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9420#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9623#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10011#L939 assume !(0 == ~M_E~0); 10255#L939-2 assume !(0 == ~T1_E~0); 10256#L944-1 assume !(0 == ~T2_E~0); 10040#L949-1 assume !(0 == ~T3_E~0); 10038#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10039#L959-1 assume !(0 == ~T5_E~0); 10458#L964-1 assume !(0 == ~T6_E~0); 9771#L969-1 assume !(0 == ~T7_E~0); 9772#L974-1 assume !(0 == ~T8_E~0); 10409#L979-1 assume !(0 == ~T9_E~0); 10410#L984-1 assume !(0 == ~E_M~0); 9932#L989-1 assume !(0 == ~E_1~0); 9933#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9821#L999-1 assume !(0 == ~E_3~0); 9822#L1004-1 assume !(0 == ~E_4~0); 9487#L1009-1 assume !(0 == ~E_5~0); 9488#L1014-1 assume !(0 == ~E_6~0); 9813#L1019-1 assume !(0 == ~E_7~0); 10354#L1024-1 assume !(0 == ~E_8~0); 9744#L1029-1 assume !(0 == ~E_9~0); 9745#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9835#L460 assume 1 == ~m_pc~0; 9403#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9404#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10320#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1167 assume !(0 != activate_threads_~tmp~1#1); 10028#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10029#L479 assume 1 == ~t1_pc~0; 10012#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10013#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10516#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9756#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9757#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9605#L498 assume !(1 == ~t2_pc~0); 9606#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10009#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10010#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10387#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10310#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10311#L517 assume 1 == ~t3_pc~0; 10518#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10519#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10083#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9789#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9790#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10363#L536 assume !(1 == ~t4_pc~0); 10073#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10065#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10066#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10283#L555 assume 1 == ~t5_pc~0; 10284#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10355#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9518#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9519#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9626#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9526#L574 assume !(1 == ~t6_pc~0); 9527#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9631#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9632#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10381#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10543#L593 assume 1 == ~t7_pc~0; 10544#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9763#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10461#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10564#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10524#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9927#L612 assume !(1 == ~t8_pc~0); 9928#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10337#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10195#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10196#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10161#L631 assume 1 == ~t9_pc~0; 10179#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9517#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9485#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9486#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10015#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10366#L1047 assume !(1 == ~M_E~0); 9455#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9456#L1052-1 assume !(1 == ~T2_E~0); 9438#L1057-1 assume !(1 == ~T3_E~0); 9439#L1062-1 assume !(1 == ~T4_E~0); 9728#L1067-1 assume !(1 == ~T5_E~0); 10031#L1072-1 assume !(1 == ~T6_E~0); 10032#L1077-1 assume !(1 == ~T7_E~0); 9619#L1082-1 assume !(1 == ~T8_E~0); 9620#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9411#L1092-1 assume !(1 == ~E_M~0); 9412#L1097-1 assume !(1 == ~E_1~0); 9440#L1102-1 assume !(1 == ~E_2~0); 10221#L1107-1 assume !(1 == ~E_3~0); 10156#L1112-1 assume !(1 == ~E_4~0); 10157#L1117-1 assume !(1 == ~E_5~0); 10197#L1122-1 assume !(1 == ~E_6~0); 10084#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9838#L1132-1 assume !(1 == ~E_8~0); 9839#L1137-1 assume !(1 == ~E_9~0); 9727#L1142-1 assume { :end_inline_reset_delta_events } true; 9587#L1428-2 [2022-11-25 17:17:37,159 INFO L750 eck$LassoCheckResult]: Loop: 9587#L1428-2 assume !false; 9588#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9662#L914 assume !false; 10152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9424#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9425#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10384#L783 assume !(0 != eval_~tmp~0#1); 9824#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9825#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10220#L939-3 assume !(0 == ~M_E~0); 9643#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9644#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9409#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9410#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9489#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9696#L974-3 assume !(0 == ~T8_E~0); 9697#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10127#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10128#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9750#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9751#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10262#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9573#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9574#L1014-3 assume !(0 == ~E_6~0); 10113#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10114#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10095#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10047#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10048#L460-33 assume 1 == ~m_pc~0; 10085#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10086#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9842#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9417#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9418#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9778#L479-33 assume !(1 == ~t1_pc~0); 9779#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9746#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9747#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10331#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 10504#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9787#L498-33 assume 1 == ~t2_pc~0; 9788#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9533#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9667#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9668#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9645#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9646#L517-33 assume !(1 == ~t3_pc~0); 10552#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10435#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10436#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10248#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10249#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9874#L536-33 assume 1 == ~t4_pc~0; 9875#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9944#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9945#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10135#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9464#L555-33 assume !(1 == ~t5_pc~0); 9465#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 10190#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9737#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9738#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10217#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9435#L574-33 assume 1 == ~t6_pc~0; 9436#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10426#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9752#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9753#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10006#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9511#L593-33 assume !(1 == ~t7_pc~0); 9512#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9967#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9617#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9618#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10277#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10404#L612-33 assume 1 == ~t8_pc~0; 10531#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10495#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10496#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9615#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9616#L631-33 assume !(1 == ~t9_pc~0); 10224#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9557#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9558#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9812#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9669#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9670#L1047-3 assume !(1 == ~M_E~0); 9843#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10457#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10389#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10390#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9568#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9569#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9951#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9796#L1082-3 assume !(1 == ~T8_E~0); 9797#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9870#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10081#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10082#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10427#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9791#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9792#L1122-3 assume !(1 == ~E_6~0); 9844#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9845#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10234#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10211#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9674#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9552#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10212#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9969#L1447 assume !(0 == start_simulation_~tmp~3#1); 9970#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10408#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9710#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10235#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9820#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9577#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9578#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10033#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9587#L1428-2 [2022-11-25 17:17:37,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,160 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2022-11-25 17:17:37,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091298313] [2022-11-25 17:17:37,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091298313] [2022-11-25 17:17:37,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091298313] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,219 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,219 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143469862] [2022-11-25 17:17:37,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,220 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:37,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,221 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 1 times [2022-11-25 17:17:37,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858436268] [2022-11-25 17:17:37,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858436268] [2022-11-25 17:17:37,284 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858436268] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,284 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,285 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640961803] [2022-11-25 17:17:37,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,285 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:37,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:37,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:37,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:37,286 INFO L87 Difference]: Start difference. First operand 1170 states and 1739 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:37,319 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-11-25 17:17:37,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2022-11-25 17:17:37,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-11-25 17:17:37,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:37,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:37,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2022-11-25 17:17:37,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:37,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-11-25 17:17:37,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2022-11-25 17:17:37,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:37,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-11-25 17:17:37,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-11-25 17:17:37,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:37,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-11-25 17:17:37,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-11-25 17:17:37,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1738 transitions. [2022-11-25 17:17:37,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:37,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:37,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,372 INFO L748 eck$LassoCheckResult]: Stem: 12622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12572#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12573#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12791#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12458#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12459#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12768#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12267#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12268#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12694#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12695#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11766#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11767#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11970#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12358#L939 assume !(0 == ~M_E~0); 12602#L939-2 assume !(0 == ~T1_E~0); 12603#L944-1 assume !(0 == ~T2_E~0); 12387#L949-1 assume !(0 == ~T3_E~0); 12385#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12386#L959-1 assume !(0 == ~T5_E~0); 12805#L964-1 assume !(0 == ~T6_E~0); 12118#L969-1 assume !(0 == ~T7_E~0); 12119#L974-1 assume !(0 == ~T8_E~0); 12756#L979-1 assume !(0 == ~T9_E~0); 12757#L984-1 assume !(0 == ~E_M~0); 12279#L989-1 assume !(0 == ~E_1~0); 12280#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12168#L999-1 assume !(0 == ~E_3~0); 12169#L1004-1 assume !(0 == ~E_4~0); 11834#L1009-1 assume !(0 == ~E_5~0); 11835#L1014-1 assume !(0 == ~E_6~0); 12160#L1019-1 assume !(0 == ~E_7~0); 12701#L1024-1 assume !(0 == ~E_8~0); 12091#L1029-1 assume !(0 == ~E_9~0); 12092#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12182#L460 assume 1 == ~m_pc~0; 11750#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11751#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12667#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12906#L1167 assume !(0 != activate_threads_~tmp~1#1); 12375#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12376#L479 assume 1 == ~t1_pc~0; 12359#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12360#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12863#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12103#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12104#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11952#L498 assume !(1 == ~t2_pc~0); 11953#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12356#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12357#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12734#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12657#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12658#L517 assume 1 == ~t3_pc~0; 12865#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12866#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12430#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12136#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12137#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12710#L536 assume !(1 == ~t4_pc~0); 12420#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12419#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12796#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12412#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12413#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12630#L555 assume 1 == ~t5_pc~0; 12631#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12702#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11865#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 11973#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11873#L574 assume !(1 == ~t6_pc~0); 11874#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12505#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11978#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11979#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12728#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12890#L593 assume 1 == ~t7_pc~0; 12891#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12110#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12808#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12911#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12871#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12274#L612 assume !(1 == ~t8_pc~0); 12275#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12684#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12542#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12543#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12507#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12508#L631 assume 1 == ~t9_pc~0; 12526#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11864#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11832#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11833#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12362#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12713#L1047 assume !(1 == ~M_E~0); 11802#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11803#L1052-1 assume !(1 == ~T2_E~0); 11785#L1057-1 assume !(1 == ~T3_E~0); 11786#L1062-1 assume !(1 == ~T4_E~0); 12075#L1067-1 assume !(1 == ~T5_E~0); 12378#L1072-1 assume !(1 == ~T6_E~0); 12379#L1077-1 assume !(1 == ~T7_E~0); 11966#L1082-1 assume !(1 == ~T8_E~0); 11967#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11758#L1092-1 assume !(1 == ~E_M~0); 11759#L1097-1 assume !(1 == ~E_1~0); 11787#L1102-1 assume !(1 == ~E_2~0); 12568#L1107-1 assume !(1 == ~E_3~0); 12503#L1112-1 assume !(1 == ~E_4~0); 12504#L1117-1 assume !(1 == ~E_5~0); 12544#L1122-1 assume !(1 == ~E_6~0); 12431#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12185#L1132-1 assume !(1 == ~E_8~0); 12186#L1137-1 assume !(1 == ~E_9~0); 12074#L1142-1 assume { :end_inline_reset_delta_events } true; 11934#L1428-2 [2022-11-25 17:17:37,373 INFO L750 eck$LassoCheckResult]: Loop: 11934#L1428-2 assume !false; 11935#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12009#L914 assume !false; 12499#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12500#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11771#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11772#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12731#L783 assume !(0 != eval_~tmp~0#1); 12171#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12172#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12567#L939-3 assume !(0 == ~M_E~0); 11990#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11991#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11756#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11757#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12393#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11836#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12043#L974-3 assume !(0 == ~T8_E~0); 12044#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12474#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12475#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12097#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12098#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12609#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11920#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11921#L1014-3 assume !(0 == ~E_6~0); 12460#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12461#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12442#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12394#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12395#L460-33 assume 1 == ~m_pc~0; 12432#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12433#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12189#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11764#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11765#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12125#L479-33 assume !(1 == ~t1_pc~0); 12126#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12093#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12094#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12678#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 12851#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12134#L498-33 assume 1 == ~t2_pc~0; 12135#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12014#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12015#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11992#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11993#L517-33 assume !(1 == ~t3_pc~0); 12899#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12782#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12783#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12595#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12596#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12221#L536-33 assume 1 == ~t4_pc~0; 12222#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12291#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12292#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12482#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12761#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11811#L555-33 assume !(1 == ~t5_pc~0); 11812#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12537#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12084#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12085#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12564#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11782#L574-33 assume 1 == ~t6_pc~0; 11783#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12773#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12099#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12100#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12353#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11858#L593-33 assume !(1 == ~t7_pc~0); 11859#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12314#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11964#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11965#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12624#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12751#L612-33 assume 1 == ~t8_pc~0; 12878#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12842#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12843#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12685#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11962#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11963#L631-33 assume 1 == ~t9_pc~0; 12803#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11904#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11905#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12159#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12016#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12017#L1047-3 assume !(1 == ~M_E~0); 12190#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12804#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12736#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12737#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11915#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11916#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12298#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12143#L1082-3 assume !(1 == ~T8_E~0); 12144#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12217#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12498#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12428#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12429#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12774#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12138#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1122-3 assume !(1 == ~E_6~0); 12191#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12192#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12581#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12021#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11899#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12559#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12316#L1447 assume !(0 == start_simulation_~tmp~3#1); 12317#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12755#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12057#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12582#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 12167#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11924#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11925#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12380#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 11934#L1428-2 [2022-11-25 17:17:37,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,374 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2022-11-25 17:17:37,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427459940] [2022-11-25 17:17:37,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427459940] [2022-11-25 17:17:37,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427459940] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600996800] [2022-11-25 17:17:37,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:37,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,444 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 2 times [2022-11-25 17:17:37,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262027727] [2022-11-25 17:17:37,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262027727] [2022-11-25 17:17:37,504 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262027727] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,504 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,504 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711622864] [2022-11-25 17:17:37,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,505 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:37,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:37,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:37,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:37,506 INFO L87 Difference]: Start difference. First operand 1170 states and 1738 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:37,531 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2022-11-25 17:17:37,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1737 transitions. [2022-11-25 17:17:37,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1737 transitions. [2022-11-25 17:17:37,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:37,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:37,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1737 transitions. [2022-11-25 17:17:37,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:37,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-11-25 17:17:37,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1737 transitions. [2022-11-25 17:17:37,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:37,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1737 transitions. [2022-11-25 17:17:37,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-11-25 17:17:37,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:37,570 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-11-25 17:17:37,570 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-11-25 17:17:37,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1737 transitions. [2022-11-25 17:17:37,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:37,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:37,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,578 INFO L748 eck$LassoCheckResult]: Stem: 14969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14919#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14920#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15138#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14805#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14806#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15115#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14614#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14615#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15041#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15042#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14113#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14114#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14317#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14705#L939 assume !(0 == ~M_E~0); 14949#L939-2 assume !(0 == ~T1_E~0); 14950#L944-1 assume !(0 == ~T2_E~0); 14734#L949-1 assume !(0 == ~T3_E~0); 14732#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14733#L959-1 assume !(0 == ~T5_E~0); 15152#L964-1 assume !(0 == ~T6_E~0); 14465#L969-1 assume !(0 == ~T7_E~0); 14466#L974-1 assume !(0 == ~T8_E~0); 15103#L979-1 assume !(0 == ~T9_E~0); 15104#L984-1 assume !(0 == ~E_M~0); 14626#L989-1 assume !(0 == ~E_1~0); 14627#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14515#L999-1 assume !(0 == ~E_3~0); 14516#L1004-1 assume !(0 == ~E_4~0); 14181#L1009-1 assume !(0 == ~E_5~0); 14182#L1014-1 assume !(0 == ~E_6~0); 14507#L1019-1 assume !(0 == ~E_7~0); 15048#L1024-1 assume !(0 == ~E_8~0); 14438#L1029-1 assume !(0 == ~E_9~0); 14439#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14529#L460 assume 1 == ~m_pc~0; 14097#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14098#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15014#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15253#L1167 assume !(0 != activate_threads_~tmp~1#1); 14722#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14723#L479 assume 1 == ~t1_pc~0; 14706#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14707#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15210#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14450#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14451#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14299#L498 assume !(1 == ~t2_pc~0); 14300#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14703#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14704#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15081#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15004#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15005#L517 assume 1 == ~t3_pc~0; 15212#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15213#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14777#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14483#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14484#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15057#L536 assume !(1 == ~t4_pc~0); 14767#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14766#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15143#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14759#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14760#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14977#L555 assume 1 == ~t5_pc~0; 14978#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15049#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14212#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14213#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14320#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14220#L574 assume !(1 == ~t6_pc~0); 14221#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14852#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14325#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14326#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15075#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15237#L593 assume 1 == ~t7_pc~0; 15238#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14457#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15155#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15258#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15218#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14621#L612 assume !(1 == ~t8_pc~0); 14622#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15031#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14889#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14890#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14854#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14855#L631 assume 1 == ~t9_pc~0; 14873#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14211#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14179#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14180#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14709#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15060#L1047 assume !(1 == ~M_E~0); 14149#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14150#L1052-1 assume !(1 == ~T2_E~0); 14132#L1057-1 assume !(1 == ~T3_E~0); 14133#L1062-1 assume !(1 == ~T4_E~0); 14422#L1067-1 assume !(1 == ~T5_E~0); 14725#L1072-1 assume !(1 == ~T6_E~0); 14726#L1077-1 assume !(1 == ~T7_E~0); 14313#L1082-1 assume !(1 == ~T8_E~0); 14314#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14105#L1092-1 assume !(1 == ~E_M~0); 14106#L1097-1 assume !(1 == ~E_1~0); 14134#L1102-1 assume !(1 == ~E_2~0); 14915#L1107-1 assume !(1 == ~E_3~0); 14850#L1112-1 assume !(1 == ~E_4~0); 14851#L1117-1 assume !(1 == ~E_5~0); 14891#L1122-1 assume !(1 == ~E_6~0); 14778#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14532#L1132-1 assume !(1 == ~E_8~0); 14533#L1137-1 assume !(1 == ~E_9~0); 14421#L1142-1 assume { :end_inline_reset_delta_events } true; 14281#L1428-2 [2022-11-25 17:17:37,579 INFO L750 eck$LassoCheckResult]: Loop: 14281#L1428-2 assume !false; 14282#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14356#L914 assume !false; 14846#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14847#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14118#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14119#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15078#L783 assume !(0 != eval_~tmp~0#1); 14518#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14519#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14914#L939-3 assume !(0 == ~M_E~0); 14337#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14338#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14103#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14104#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14740#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14183#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14184#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14390#L974-3 assume !(0 == ~T8_E~0); 14391#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14821#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14822#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14444#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14445#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14956#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14267#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14268#L1014-3 assume !(0 == ~E_6~0); 14807#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14808#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14789#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14741#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14742#L460-33 assume 1 == ~m_pc~0; 14779#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14780#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14536#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14111#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14112#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14472#L479-33 assume !(1 == ~t1_pc~0); 14473#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14440#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14441#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15025#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 15198#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14481#L498-33 assume 1 == ~t2_pc~0; 14482#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14227#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14361#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14362#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14339#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14340#L517-33 assume !(1 == ~t3_pc~0); 15246#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15129#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15130#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14942#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14943#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14568#L536-33 assume 1 == ~t4_pc~0; 14569#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14638#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14639#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14829#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15108#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14158#L555-33 assume 1 == ~t5_pc~0; 14160#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14884#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14431#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14432#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14911#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14129#L574-33 assume 1 == ~t6_pc~0; 14130#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15120#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14446#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14447#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14700#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14205#L593-33 assume !(1 == ~t7_pc~0); 14206#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14661#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14311#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14312#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14971#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15098#L612-33 assume 1 == ~t8_pc~0; 15225#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15189#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15190#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15032#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14309#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14310#L631-33 assume !(1 == ~t9_pc~0); 14918#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14251#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14252#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14506#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14363#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14364#L1047-3 assume !(1 == ~M_E~0); 14537#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15151#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15083#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15084#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14262#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14263#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14645#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14490#L1082-3 assume !(1 == ~T8_E~0); 14491#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14564#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14845#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14775#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14776#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15121#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14485#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14486#L1122-3 assume !(1 == ~E_6~0); 14538#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14539#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14928#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14905#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14368#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14246#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14906#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14663#L1447 assume !(0 == start_simulation_~tmp~3#1); 14664#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15102#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14404#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14929#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14514#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14271#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14272#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14727#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14281#L1428-2 [2022-11-25 17:17:37,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,580 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2022-11-25 17:17:37,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,580 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580837093] [2022-11-25 17:17:37,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580837093] [2022-11-25 17:17:37,620 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580837093] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,621 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,621 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [520076205] [2022-11-25 17:17:37,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:37,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1283827122, now seen corresponding path program 1 times [2022-11-25 17:17:37,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524892892] [2022-11-25 17:17:37,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524892892] [2022-11-25 17:17:37,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524892892] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,673 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499084964] [2022-11-25 17:17:37,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,673 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:37,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:37,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:37,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:37,674 INFO L87 Difference]: Start difference. First operand 1170 states and 1737 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:37,699 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2022-11-25 17:17:37,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1736 transitions. [2022-11-25 17:17:37,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1736 transitions. [2022-11-25 17:17:37,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:37,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:37,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1736 transitions. [2022-11-25 17:17:37,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:37,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-11-25 17:17:37,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1736 transitions. [2022-11-25 17:17:37,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:37,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1736 transitions. [2022-11-25 17:17:37,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-11-25 17:17:37,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:37,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-11-25 17:17:37,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-11-25 17:17:37,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1736 transitions. [2022-11-25 17:17:37,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:37,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:37,749 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,749 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,753 INFO L748 eck$LassoCheckResult]: Stem: 17316#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17266#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17267#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17485#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17152#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17153#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17462#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16961#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16962#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17390#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17391#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16460#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16461#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16664#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17052#L939 assume !(0 == ~M_E~0); 17296#L939-2 assume !(0 == ~T1_E~0); 17297#L944-1 assume !(0 == ~T2_E~0); 17081#L949-1 assume !(0 == ~T3_E~0); 17079#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17080#L959-1 assume !(0 == ~T5_E~0); 17499#L964-1 assume !(0 == ~T6_E~0); 16812#L969-1 assume !(0 == ~T7_E~0); 16813#L974-1 assume !(0 == ~T8_E~0); 17450#L979-1 assume !(0 == ~T9_E~0); 17451#L984-1 assume !(0 == ~E_M~0); 16973#L989-1 assume !(0 == ~E_1~0); 16974#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16862#L999-1 assume !(0 == ~E_3~0); 16863#L1004-1 assume !(0 == ~E_4~0); 16528#L1009-1 assume !(0 == ~E_5~0); 16529#L1014-1 assume !(0 == ~E_6~0); 16854#L1019-1 assume !(0 == ~E_7~0); 17395#L1024-1 assume !(0 == ~E_8~0); 16785#L1029-1 assume !(0 == ~E_9~0); 16786#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16876#L460 assume 1 == ~m_pc~0; 16444#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16445#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17361#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17600#L1167 assume !(0 != activate_threads_~tmp~1#1); 17069#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17070#L479 assume 1 == ~t1_pc~0; 17053#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17054#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17557#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16797#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16798#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16646#L498 assume !(1 == ~t2_pc~0); 16647#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17050#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17051#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17428#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17352#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17353#L517 assume 1 == ~t3_pc~0; 17559#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17560#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17124#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16830#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16831#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17404#L536 assume !(1 == ~t4_pc~0); 17114#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17113#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17490#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17106#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17107#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17324#L555 assume 1 == ~t5_pc~0; 17325#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17396#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16559#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16560#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16667#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16567#L574 assume !(1 == ~t6_pc~0); 16568#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17199#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16672#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16673#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17422#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17584#L593 assume 1 == ~t7_pc~0; 17585#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16804#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17502#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17605#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17565#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16968#L612 assume !(1 == ~t8_pc~0); 16969#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17378#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17236#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17237#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17201#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17202#L631 assume 1 == ~t9_pc~0; 17220#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16526#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16527#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17056#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17407#L1047 assume !(1 == ~M_E~0); 16496#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16497#L1052-1 assume !(1 == ~T2_E~0); 16479#L1057-1 assume !(1 == ~T3_E~0); 16480#L1062-1 assume !(1 == ~T4_E~0); 16769#L1067-1 assume !(1 == ~T5_E~0); 17072#L1072-1 assume !(1 == ~T6_E~0); 17073#L1077-1 assume !(1 == ~T7_E~0); 16660#L1082-1 assume !(1 == ~T8_E~0); 16661#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16452#L1092-1 assume !(1 == ~E_M~0); 16453#L1097-1 assume !(1 == ~E_1~0); 16481#L1102-1 assume !(1 == ~E_2~0); 17262#L1107-1 assume !(1 == ~E_3~0); 17197#L1112-1 assume !(1 == ~E_4~0); 17198#L1117-1 assume !(1 == ~E_5~0); 17238#L1122-1 assume !(1 == ~E_6~0); 17125#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16879#L1132-1 assume !(1 == ~E_8~0); 16880#L1137-1 assume !(1 == ~E_9~0); 16768#L1142-1 assume { :end_inline_reset_delta_events } true; 16628#L1428-2 [2022-11-25 17:17:37,754 INFO L750 eck$LassoCheckResult]: Loop: 16628#L1428-2 assume !false; 16629#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16703#L914 assume !false; 17193#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17194#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16465#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16466#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17425#L783 assume !(0 != eval_~tmp~0#1); 16865#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16866#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17261#L939-3 assume !(0 == ~M_E~0); 16684#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16685#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16450#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16451#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17087#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16530#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16531#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16737#L974-3 assume !(0 == ~T8_E~0); 16738#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17168#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17169#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16791#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16792#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17303#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16614#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16615#L1014-3 assume !(0 == ~E_6~0); 17154#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17155#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17136#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17088#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17089#L460-33 assume 1 == ~m_pc~0; 17126#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17127#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16883#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16458#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16459#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16820#L479-33 assume !(1 == ~t1_pc~0); 16821#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16787#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16788#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17372#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 17545#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16828#L498-33 assume 1 == ~t2_pc~0; 16829#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16574#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16708#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16709#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16686#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16687#L517-33 assume !(1 == ~t3_pc~0); 17593#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17476#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17477#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17289#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17290#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16915#L536-33 assume 1 == ~t4_pc~0; 16916#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16985#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16986#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17176#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17455#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16505#L555-33 assume !(1 == ~t5_pc~0); 16506#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17231#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16778#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16779#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17258#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16476#L574-33 assume 1 == ~t6_pc~0; 16477#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17467#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16793#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16794#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17047#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16552#L593-33 assume !(1 == ~t7_pc~0); 16553#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 17009#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16658#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16659#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17318#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17445#L612-33 assume 1 == ~t8_pc~0; 17572#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17536#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17537#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17379#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16656#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16657#L631-33 assume !(1 == ~t9_pc~0); 17265#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 16598#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16599#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16853#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16710#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16711#L1047-3 assume !(1 == ~M_E~0); 16884#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17498#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17430#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17431#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16609#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16610#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16992#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16837#L1082-3 assume !(1 == ~T8_E~0); 16838#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16911#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17192#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17122#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17123#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17468#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16832#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16833#L1122-3 assume !(1 == ~E_6~0); 16885#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16886#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17275#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17252#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16715#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16593#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17253#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17010#L1447 assume !(0 == start_simulation_~tmp~3#1); 17011#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17449#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16751#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17276#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16861#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16618#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16619#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17074#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16628#L1428-2 [2022-11-25 17:17:37,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2022-11-25 17:17:37,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480885080] [2022-11-25 17:17:37,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480885080] [2022-11-25 17:17:37,807 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480885080] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,807 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,807 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043094964] [2022-11-25 17:17:37,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,810 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:37,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,811 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 2 times [2022-11-25 17:17:37,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406222771] [2022-11-25 17:17:37,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:37,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:37,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:37,903 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406222771] [2022-11-25 17:17:37,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406222771] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:37,904 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:37,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:37,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695820699] [2022-11-25 17:17:37,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:37,904 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:37,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:37,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:37,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:37,905 INFO L87 Difference]: Start difference. First operand 1170 states and 1736 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:37,932 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2022-11-25 17:17:37,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1735 transitions. [2022-11-25 17:17:37,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1735 transitions. [2022-11-25 17:17:37,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-11-25 17:17:37,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-11-25 17:17:37,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1735 transitions. [2022-11-25 17:17:37,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:37,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-11-25 17:17:37,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1735 transitions. [2022-11-25 17:17:37,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-11-25 17:17:37,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:37,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1735 transitions. [2022-11-25 17:17:37,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-11-25 17:17:37,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:37,969 INFO L428 stractBuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-11-25 17:17:37,969 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-11-25 17:17:37,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1735 transitions. [2022-11-25 17:17:37,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-11-25 17:17:37,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:37,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:37,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:37,976 INFO L748 eck$LassoCheckResult]: Stem: 19663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19613#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19614#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19832#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19499#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19500#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19809#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19308#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19309#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19737#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19738#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18807#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18808#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19011#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19399#L939 assume !(0 == ~M_E~0); 19643#L939-2 assume !(0 == ~T1_E~0); 19644#L944-1 assume !(0 == ~T2_E~0); 19428#L949-1 assume !(0 == ~T3_E~0); 19426#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19427#L959-1 assume !(0 == ~T5_E~0); 19846#L964-1 assume !(0 == ~T6_E~0); 19159#L969-1 assume !(0 == ~T7_E~0); 19160#L974-1 assume !(0 == ~T8_E~0); 19797#L979-1 assume !(0 == ~T9_E~0); 19798#L984-1 assume !(0 == ~E_M~0); 19320#L989-1 assume !(0 == ~E_1~0); 19321#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19209#L999-1 assume !(0 == ~E_3~0); 19210#L1004-1 assume !(0 == ~E_4~0); 18875#L1009-1 assume !(0 == ~E_5~0); 18876#L1014-1 assume !(0 == ~E_6~0); 19203#L1019-1 assume !(0 == ~E_7~0); 19742#L1024-1 assume !(0 == ~E_8~0); 19132#L1029-1 assume !(0 == ~E_9~0); 19133#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19223#L460 assume 1 == ~m_pc~0; 18791#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18792#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19708#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19947#L1167 assume !(0 != activate_threads_~tmp~1#1); 19416#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19417#L479 assume 1 == ~t1_pc~0; 19400#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19401#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19904#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19144#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19145#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18993#L498 assume !(1 == ~t2_pc~0); 18994#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19397#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19398#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19775#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19699#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19700#L517 assume 1 == ~t3_pc~0; 19908#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19909#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19471#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19177#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19178#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19753#L536 assume !(1 == ~t4_pc~0); 19461#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19460#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19837#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19453#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19454#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19673#L555 assume 1 == ~t5_pc~0; 19674#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19743#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18906#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18907#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19014#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18914#L574 assume !(1 == ~t6_pc~0); 18915#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19546#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19019#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19020#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19771#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19931#L593 assume 1 == ~t7_pc~0; 19932#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19151#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19849#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19952#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 19912#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19315#L612 assume !(1 == ~t8_pc~0); 19316#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19725#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19583#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19584#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19550#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19551#L631 assume 1 == ~t9_pc~0; 19567#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18905#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18873#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18874#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19754#L1047 assume !(1 == ~M_E~0); 18843#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18844#L1052-1 assume !(1 == ~T2_E~0); 18826#L1057-1 assume !(1 == ~T3_E~0); 18827#L1062-1 assume !(1 == ~T4_E~0); 19116#L1067-1 assume !(1 == ~T5_E~0); 19419#L1072-1 assume !(1 == ~T6_E~0); 19420#L1077-1 assume !(1 == ~T7_E~0); 19007#L1082-1 assume !(1 == ~T8_E~0); 19008#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18801#L1092-1 assume !(1 == ~E_M~0); 18802#L1097-1 assume !(1 == ~E_1~0); 18828#L1102-1 assume !(1 == ~E_2~0); 19609#L1107-1 assume !(1 == ~E_3~0); 19544#L1112-1 assume !(1 == ~E_4~0); 19545#L1117-1 assume !(1 == ~E_5~0); 19585#L1122-1 assume !(1 == ~E_6~0); 19472#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19228#L1132-1 assume !(1 == ~E_8~0); 19229#L1137-1 assume !(1 == ~E_9~0); 19115#L1142-1 assume { :end_inline_reset_delta_events } true; 18975#L1428-2 [2022-11-25 17:17:37,977 INFO L750 eck$LassoCheckResult]: Loop: 18975#L1428-2 assume !false; 18976#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19050#L914 assume !false; 19540#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19541#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18812#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18813#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19772#L783 assume !(0 != eval_~tmp~0#1); 19212#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19213#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19608#L939-3 assume !(0 == ~M_E~0); 19031#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19032#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18797#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18798#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19434#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18877#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18878#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19084#L974-3 assume !(0 == ~T8_E~0); 19085#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19515#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19516#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19138#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19139#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19650#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18961#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18962#L1014-3 assume !(0 == ~E_6~0); 19501#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19502#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19483#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19435#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19436#L460-33 assume 1 == ~m_pc~0; 19473#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19474#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19230#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18805#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18806#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19167#L479-33 assume !(1 == ~t1_pc~0); 19168#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19134#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19135#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19719#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 19892#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19175#L498-33 assume 1 == ~t2_pc~0; 19176#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18921#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19057#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19058#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19033#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19034#L517-33 assume !(1 == ~t3_pc~0); 19940#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 19823#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19824#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19636#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19637#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19262#L536-33 assume !(1 == ~t4_pc~0); 19264#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 19332#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19333#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19523#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19802#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18852#L555-33 assume !(1 == ~t5_pc~0); 18853#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 19578#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19125#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19126#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19605#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18818#L574-33 assume 1 == ~t6_pc~0; 18819#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19814#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19140#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19141#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19394#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18894#L593-33 assume 1 == ~t7_pc~0; 18896#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19350#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19005#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19006#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19665#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19792#L612-33 assume !(1 == ~t8_pc~0); 19920#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19883#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19884#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19726#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19001#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19002#L631-33 assume 1 == ~t9_pc~0; 19844#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18945#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18946#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19198#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19055#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19056#L1047-3 assume !(1 == ~M_E~0); 19231#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19845#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19777#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19778#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18956#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18957#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19339#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19184#L1082-3 assume !(1 == ~T8_E~0); 19185#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19258#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19539#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19469#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19470#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19815#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19179#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19180#L1122-3 assume !(1 == ~E_6~0); 19232#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19233#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19622#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19599#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19059#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18937#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19600#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19357#L1447 assume !(0 == start_simulation_~tmp~3#1); 19358#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19796#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19098#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19623#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19208#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18965#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18966#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19421#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 18975#L1428-2 [2022-11-25 17:17:37,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:37,977 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2022-11-25 17:17:37,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:37,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332850139] [2022-11-25 17:17:37,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:37,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:37,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332850139] [2022-11-25 17:17:38,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332850139] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,059 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,059 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:38,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407274550] [2022-11-25 17:17:38,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,060 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:38,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:38,060 INFO L85 PathProgramCache]: Analyzing trace with hash -1679945009, now seen corresponding path program 1 times [2022-11-25 17:17:38,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:38,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018128159] [2022-11-25 17:17:38,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:38,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:38,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018128159] [2022-11-25 17:17:38,111 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018128159] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,111 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:38,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165723413] [2022-11-25 17:17:38,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,112 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:38,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:38,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:38,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:38,113 INFO L87 Difference]: Start difference. First operand 1170 states and 1735 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:38,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:38,265 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2022-11-25 17:17:38,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3163 transitions. [2022-11-25 17:17:38,280 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-11-25 17:17:38,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3163 transitions. [2022-11-25 17:17:38,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2022-11-25 17:17:38,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2022-11-25 17:17:38,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3163 transitions. [2022-11-25 17:17:38,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:38,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-11-25 17:17:38,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3163 transitions. [2022-11-25 17:17:38,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2022-11-25 17:17:38,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:38,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3163 transitions. [2022-11-25 17:17:38,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-11-25 17:17:38,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:38,357 INFO L428 stractBuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-11-25 17:17:38,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-11-25 17:17:38,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3163 transitions. [2022-11-25 17:17:38,367 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-11-25 17:17:38,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:38,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:38,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:38,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:38,370 INFO L748 eck$LassoCheckResult]: Stem: 22999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22947#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22948#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23188#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 22828#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22829#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23164#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22634#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22635#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23082#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23083#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22128#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22129#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22332#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22725#L939 assume !(0 == ~M_E~0); 22977#L939-2 assume !(0 == ~T1_E~0); 22978#L944-1 assume !(0 == ~T2_E~0); 22754#L949-1 assume !(0 == ~T3_E~0); 22752#L954-1 assume !(0 == ~T4_E~0); 22753#L959-1 assume !(0 == ~T5_E~0); 23206#L964-1 assume !(0 == ~T6_E~0); 22481#L969-1 assume !(0 == ~T7_E~0); 22482#L974-1 assume !(0 == ~T8_E~0); 23152#L979-1 assume !(0 == ~T9_E~0); 23153#L984-1 assume !(0 == ~E_M~0); 22648#L989-1 assume !(0 == ~E_1~0); 22649#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22531#L999-1 assume !(0 == ~E_3~0); 22532#L1004-1 assume !(0 == ~E_4~0); 22196#L1009-1 assume !(0 == ~E_5~0); 22197#L1014-1 assume !(0 == ~E_6~0); 22527#L1019-1 assume !(0 == ~E_7~0); 23087#L1024-1 assume !(0 == ~E_8~0); 22454#L1029-1 assume !(0 == ~E_9~0); 22455#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22547#L460 assume 1 == ~m_pc~0; 22115#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22116#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23052#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23334#L1167 assume !(0 != activate_threads_~tmp~1#1); 22742#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22743#L479 assume 1 == ~t1_pc~0; 22726#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22727#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23276#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22467#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22468#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22314#L498 assume !(1 == ~t2_pc~0); 22315#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22723#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22724#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23125#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23042#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23043#L517 assume 1 == ~t3_pc~0; 23281#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23282#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22798#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22499#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22500#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23099#L536 assume !(1 == ~t4_pc~0); 22788#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22787#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23195#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22780#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22781#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23011#L555 assume 1 == ~t5_pc~0; 23012#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23088#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22229#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22230#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22335#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22235#L574 assume !(1 == ~t6_pc~0); 22236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22878#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22340#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22341#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23120#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23314#L593 assume 1 == ~t7_pc~0; 23315#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22473#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23210#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23343#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23284#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22641#L612 assume !(1 == ~t8_pc~0); 22642#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23069#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22916#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22917#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 22882#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22883#L631 assume 1 == ~t9_pc~0; 22899#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22226#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22194#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22195#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22729#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23100#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22166#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22167#L1052-1 assume !(1 == ~T2_E~0); 23558#L1057-1 assume !(1 == ~T3_E~0); 23557#L1062-1 assume !(1 == ~T4_E~0); 22437#L1067-1 assume !(1 == ~T5_E~0); 22745#L1072-1 assume !(1 == ~T6_E~0); 22746#L1077-1 assume !(1 == ~T7_E~0); 22328#L1082-1 assume !(1 == ~T8_E~0); 22329#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22124#L1092-1 assume !(1 == ~E_M~0); 22125#L1097-1 assume !(1 == ~E_1~0); 22149#L1102-1 assume !(1 == ~E_2~0); 22943#L1107-1 assume !(1 == ~E_3~0); 22876#L1112-1 assume !(1 == ~E_4~0); 22877#L1117-1 assume !(1 == ~E_5~0); 22918#L1122-1 assume !(1 == ~E_6~0); 22799#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22550#L1132-1 assume !(1 == ~E_8~0); 22551#L1137-1 assume !(1 == ~E_9~0); 22436#L1142-1 assume { :end_inline_reset_delta_events } true; 22299#L1428-2 [2022-11-25 17:17:38,371 INFO L750 eck$LassoCheckResult]: Loop: 22299#L1428-2 assume !false; 22300#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23317#L914 assume !false; 23318#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23073#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22135#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22136#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23121#L783 assume !(0 != eval_~tmp~0#1); 23122#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22941#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22942#L939-3 assume !(0 == ~M_E~0); 22354#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22355#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22118#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22119#L954-3 assume !(0 == ~T4_E~0); 22760#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22200#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22201#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22405#L974-3 assume !(0 == ~T8_E~0); 22406#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22842#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22843#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22460#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22461#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22986#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22282#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22283#L1014-3 assume !(0 == ~E_6~0); 22826#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22827#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22808#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22761#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22762#L460-33 assume 1 == ~m_pc~0; 22800#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22801#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22552#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22126#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22127#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22485#L479-33 assume !(1 == ~t1_pc~0); 22486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23663#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23662#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23661#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 23660#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23659#L498-33 assume 1 == ~t2_pc~0; 23657#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23656#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23655#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23654#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23653#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23652#L517-33 assume 1 == ~t3_pc~0; 23650#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23649#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23648#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23647#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23646#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23645#L536-33 assume 1 == ~t4_pc~0; 23643#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23642#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23641#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23640#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23639#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23638#L555-33 assume !(1 == ~t5_pc~0); 23636#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 23635#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23634#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23633#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23632#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23631#L574-33 assume 1 == ~t6_pc~0; 23629#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23628#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23627#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23626#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23625#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23624#L593-33 assume !(1 == ~t7_pc~0); 23622#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 23621#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23620#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23619#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23618#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23617#L612-33 assume !(1 == ~t8_pc~0); 23616#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 23614#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23613#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23612#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23611#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23360#L631-33 assume !(1 == ~t9_pc~0); 22946#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 22266#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22267#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22520#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22378#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22379#L1047-3 assume !(1 == ~M_E~0); 22553#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23205#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23362#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23361#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22277#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22278#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22665#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22506#L1082-3 assume !(1 == ~T8_E~0); 22507#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22581#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22869#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22796#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22797#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23171#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22501#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22502#L1122-3 assume !(1 == ~E_6~0); 22554#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22555#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22956#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22932#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22383#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22258#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22933#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22683#L1447 assume !(0 == start_simulation_~tmp~3#1); 22684#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23489#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23479#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23478#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23477#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23476#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 22747#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 22299#L1428-2 [2022-11-25 17:17:38,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:38,372 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2022-11-25 17:17:38,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:38,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88627193] [2022-11-25 17:17:38,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:38,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:38,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88627193] [2022-11-25 17:17:38,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88627193] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:38,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259890515] [2022-11-25 17:17:38,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:38,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:38,513 INFO L85 PathProgramCache]: Analyzing trace with hash 442140877, now seen corresponding path program 1 times [2022-11-25 17:17:38,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:38,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296449266] [2022-11-25 17:17:38,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:38,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:38,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296449266] [2022-11-25 17:17:38,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296449266] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,582 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,582 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:38,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595066807] [2022-11-25 17:17:38,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,583 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:38,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:38,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:38,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:38,585 INFO L87 Difference]: Start difference. First operand 2141 states and 3163 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:38,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:38,682 INFO L93 Difference]: Finished difference Result 2141 states and 3133 transitions. [2022-11-25 17:17:38,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3133 transitions. [2022-11-25 17:17:38,697 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-11-25 17:17:38,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3133 transitions. [2022-11-25 17:17:38,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2022-11-25 17:17:38,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2022-11-25 17:17:38,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3133 transitions. [2022-11-25 17:17:38,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:38,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-11-25 17:17:38,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3133 transitions. [2022-11-25 17:17:38,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2022-11-25 17:17:38,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:38,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3133 transitions. [2022-11-25 17:17:38,764 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-11-25 17:17:38,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:38,765 INFO L428 stractBuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-11-25 17:17:38,765 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-11-25 17:17:38,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3133 transitions. [2022-11-25 17:17:38,775 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-11-25 17:17:38,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:38,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:38,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:38,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:38,777 INFO L748 eck$LassoCheckResult]: Stem: 27318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27263#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27264#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27534#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 27132#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27133#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27496#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26931#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26932#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27407#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27408#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26417#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26418#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26621#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27027#L939 assume !(0 == ~M_E~0); 27297#L939-2 assume !(0 == ~T1_E~0); 27298#L944-1 assume !(0 == ~T2_E~0); 27056#L949-1 assume !(0 == ~T3_E~0); 27054#L954-1 assume !(0 == ~T4_E~0); 27055#L959-1 assume !(0 == ~T5_E~0); 27551#L964-1 assume !(0 == ~T6_E~0); 26770#L969-1 assume !(0 == ~T7_E~0); 26771#L974-1 assume !(0 == ~T8_E~0); 27484#L979-1 assume !(0 == ~T9_E~0); 27485#L984-1 assume !(0 == ~E_M~0); 26943#L989-1 assume !(0 == ~E_1~0); 26944#L994-1 assume !(0 == ~E_2~0); 26822#L999-1 assume !(0 == ~E_3~0); 26823#L1004-1 assume !(0 == ~E_4~0); 26485#L1009-1 assume !(0 == ~E_5~0); 26486#L1014-1 assume !(0 == ~E_6~0); 26818#L1019-1 assume !(0 == ~E_7~0); 27412#L1024-1 assume !(0 == ~E_8~0); 26743#L1029-1 assume !(0 == ~E_9~0); 26744#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26839#L460 assume 1 == ~m_pc~0; 26404#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26405#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27371#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27694#L1167 assume !(0 != activate_threads_~tmp~1#1); 27044#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27045#L479 assume 1 == ~t1_pc~0; 27028#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27029#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27626#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26756#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26757#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26603#L498 assume !(1 == ~t2_pc~0); 26604#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27025#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27026#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27454#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27361#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27362#L517 assume 1 == ~t3_pc~0; 27631#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27632#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27100#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26788#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 26789#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27423#L536 assume !(1 == ~t4_pc~0); 27090#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27089#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27541#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27082#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 27083#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27332#L555 assume 1 == ~t5_pc~0; 27333#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27413#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26518#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26519#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26626#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26524#L574 assume !(1 == ~t6_pc~0); 26525#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27188#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26629#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26630#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 27449#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27672#L593 assume 1 == ~t7_pc~0; 27673#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26762#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27558#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27706#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 27634#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26936#L612 assume !(1 == ~t8_pc~0); 26937#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27391#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27229#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27230#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 27192#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27193#L631 assume 1 == ~t9_pc~0; 27209#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26515#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26483#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26484#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 27031#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27424#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 26455#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26456#L1052-1 assume !(1 == ~T2_E~0); 26436#L1057-1 assume !(1 == ~T3_E~0); 26437#L1062-1 assume !(1 == ~T4_E~0); 26727#L1067-1 assume !(1 == ~T5_E~0); 27047#L1072-1 assume !(1 == ~T6_E~0); 27048#L1077-1 assume !(1 == ~T7_E~0); 26617#L1082-1 assume !(1 == ~T8_E~0); 26618#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27797#L1092-1 assume !(1 == ~E_M~0); 27796#L1097-1 assume !(1 == ~E_1~0); 27658#L1102-1 assume !(1 == ~E_2~0); 27256#L1107-1 assume !(1 == ~E_3~0); 27257#L1112-1 assume !(1 == ~E_4~0); 27752#L1117-1 assume !(1 == ~E_5~0); 27751#L1122-1 assume !(1 == ~E_6~0); 27750#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27749#L1132-1 assume !(1 == ~E_8~0); 27661#L1137-1 assume !(1 == ~E_9~0); 26726#L1142-1 assume { :end_inline_reset_delta_events } true; 26588#L1428-2 [2022-11-25 17:17:38,778 INFO L750 eck$LassoCheckResult]: Loop: 26588#L1428-2 assume !false; 26589#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27675#L914 assume !false; 27676#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27398#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26424#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26425#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27450#L783 assume !(0 != eval_~tmp~0#1); 27451#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27254#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27255#L939-3 assume !(0 == ~M_E~0); 26643#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26644#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26407#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26408#L954-3 assume !(0 == ~T4_E~0); 27063#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26489#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26694#L974-3 assume !(0 == ~T8_E~0); 26695#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27148#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27149#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26749#L994-3 assume !(0 == ~E_2~0); 26750#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27306#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26571#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26572#L1014-3 assume !(0 == ~E_6~0); 27130#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27131#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27110#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27064#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27065#L460-33 assume !(1 == ~m_pc~0); 27104#L460-35 is_master_triggered_~__retres1~0#1 := 0; 27103#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26844#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26415#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26416#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26777#L479-33 assume !(1 == ~t1_pc~0); 26778#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 26745#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26746#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27893#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 27891#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27889#L498-33 assume !(1 == ~t2_pc~0); 27885#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 27007#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26665#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26666#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26641#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26642#L517-33 assume !(1 == ~t3_pc~0); 27685#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 27520#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27521#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27290#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27291#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26880#L536-33 assume 1 == ~t4_pc~0; 26881#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27869#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27868#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27867#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27866#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27865#L555-33 assume !(1 == ~t5_pc~0); 27863#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 27862#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27861#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27860#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27859#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27858#L574-33 assume 1 == ~t6_pc~0; 27856#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27855#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27854#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27851#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27022#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26509#L593-33 assume !(1 == ~t7_pc~0); 26510#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 27665#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26615#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26616#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27320#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27714#L612-33 assume 1 == ~t8_pc~0; 27715#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27600#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27601#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27392#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27393#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27826#L631-33 assume 1 == ~t9_pc~0; 27549#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27262#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27135#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27136#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26667#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26668#L1047-3 assume !(1 == ~M_E~0); 26847#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27819#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27457#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27458#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27728#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27805#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26961#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26795#L1082-3 assume !(1 == ~T8_E~0); 26796#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27176#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27177#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27730#L1102-3 assume !(1 == ~E_2~0); 27664#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27506#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27507#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27516#L1122-3 assume !(1 == ~E_6~0); 27517#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27788#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27785#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27245#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26672#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26546#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27246#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 26981#L1447 assume !(0 == start_simulation_~tmp~3#1); 26982#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27481#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26709#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27275#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 27276#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 27760#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27758#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27049#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 26588#L1428-2 [2022-11-25 17:17:38,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:38,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2022-11-25 17:17:38,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:38,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946035545] [2022-11-25 17:17:38,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:38,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:38,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946035545] [2022-11-25 17:17:38,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946035545] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,835 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:38,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183105258] [2022-11-25 17:17:38,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,836 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:38,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:38,837 INFO L85 PathProgramCache]: Analyzing trace with hash -748148786, now seen corresponding path program 1 times [2022-11-25 17:17:38,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:38,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796122747] [2022-11-25 17:17:38,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:38,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:38,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:38,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:38,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:38,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796122747] [2022-11-25 17:17:38,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796122747] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:38,894 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:38,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:38,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648288154] [2022-11-25 17:17:38,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:38,895 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:38,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:38,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:38,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:38,896 INFO L87 Difference]: Start difference. First operand 2141 states and 3133 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:39,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:39,023 INFO L93 Difference]: Finished difference Result 4105 states and 5952 transitions. [2022-11-25 17:17:39,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4105 states and 5952 transitions. [2022-11-25 17:17:39,046 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3957 [2022-11-25 17:17:39,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4105 states to 4105 states and 5952 transitions. [2022-11-25 17:17:39,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4105 [2022-11-25 17:17:39,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4105 [2022-11-25 17:17:39,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4105 states and 5952 transitions. [2022-11-25 17:17:39,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:39,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4105 states and 5952 transitions. [2022-11-25 17:17:39,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4105 states and 5952 transitions. [2022-11-25 17:17:39,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4105 to 3967. [2022-11-25 17:17:39,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:39,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5760 transitions. [2022-11-25 17:17:39,227 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2022-11-25 17:17:39,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:39,228 INFO L428 stractBuchiCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2022-11-25 17:17:39,228 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-11-25 17:17:39,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5760 transitions. [2022-11-25 17:17:39,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3819 [2022-11-25 17:17:39,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:39,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:39,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:39,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:39,248 INFO L748 eck$LassoCheckResult]: Stem: 33525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 33476#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33477#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33706#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 33360#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33361#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33682#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33169#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33170#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33605#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33606#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32667#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32668#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32870#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33261#L939 assume !(0 == ~M_E~0); 33506#L939-2 assume !(0 == ~T1_E~0); 33507#L944-1 assume !(0 == ~T2_E~0); 33290#L949-1 assume !(0 == ~T3_E~0); 33288#L954-1 assume !(0 == ~T4_E~0); 33289#L959-1 assume !(0 == ~T5_E~0); 33722#L964-1 assume !(0 == ~T6_E~0); 33019#L969-1 assume !(0 == ~T7_E~0); 33020#L974-1 assume !(0 == ~T8_E~0); 33669#L979-1 assume !(0 == ~T9_E~0); 33670#L984-1 assume !(0 == ~E_M~0); 33181#L989-1 assume !(0 == ~E_1~0); 33182#L994-1 assume !(0 == ~E_2~0); 33068#L999-1 assume !(0 == ~E_3~0); 33069#L1004-1 assume !(0 == ~E_4~0); 32735#L1009-1 assume !(0 == ~E_5~0); 32736#L1014-1 assume !(0 == ~E_6~0); 33060#L1019-1 assume !(0 == ~E_7~0); 33612#L1024-1 assume !(0 == ~E_8~0); 32992#L1029-1 assume !(0 == ~E_9~0); 32993#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33082#L460 assume !(1 == ~m_pc~0); 33820#L460-2 is_master_triggered_~__retres1~0#1 := 0; 33577#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33578#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33844#L1167 assume !(0 != activate_threads_~tmp~1#1); 33277#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33278#L479 assume 1 == ~t1_pc~0; 33262#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33263#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33789#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33004#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 33005#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32852#L498 assume !(1 == ~t2_pc~0); 32853#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33259#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33260#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33646#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33565#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33566#L517 assume 1 == ~t3_pc~0; 33794#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33795#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33332#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33037#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 33038#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L536 assume !(1 == ~t4_pc~0); 33322#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33321#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33712#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33314#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 33315#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33534#L555 assume 1 == ~t5_pc~0; 33535#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33613#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32766#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32767#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 32873#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32774#L574 assume !(1 == ~t6_pc~0); 32775#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33408#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32878#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32879#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 33640#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33825#L593 assume 1 == ~t7_pc~0; 33826#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33011#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33725#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33849#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 33800#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33176#L612 assume !(1 == ~t8_pc~0); 33177#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33595#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33445#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33446#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 33410#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33411#L631 assume 1 == ~t9_pc~0; 33429#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32765#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32733#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32734#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 33265#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33624#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 33625#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35728#L1052-1 assume !(1 == ~T2_E~0); 35727#L1057-1 assume !(1 == ~T3_E~0); 35726#L1062-1 assume !(1 == ~T4_E~0); 32975#L1067-1 assume !(1 == ~T5_E~0); 35725#L1072-1 assume !(1 == ~T6_E~0); 35723#L1077-1 assume !(1 == ~T7_E~0); 35722#L1082-1 assume !(1 == ~T8_E~0); 35721#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35719#L1092-1 assume !(1 == ~E_M~0); 35708#L1097-1 assume !(1 == ~E_1~0); 35706#L1102-1 assume !(1 == ~E_2~0); 35704#L1107-1 assume !(1 == ~E_3~0); 35702#L1112-1 assume !(1 == ~E_4~0); 35700#L1117-1 assume !(1 == ~E_5~0); 35698#L1122-1 assume !(1 == ~E_6~0); 35697#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 35696#L1132-1 assume !(1 == ~E_8~0); 33815#L1137-1 assume !(1 == ~E_9~0); 32974#L1142-1 assume { :end_inline_reset_delta_events } true; 32834#L1428-2 [2022-11-25 17:17:39,248 INFO L750 eck$LassoCheckResult]: Loop: 32834#L1428-2 assume !false; 32835#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32909#L914 assume !false; 33401#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33402#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32672#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 32673#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33643#L783 assume !(0 != eval_~tmp~0#1); 33071#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33072#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35724#L939-3 assume !(0 == ~M_E~0); 32890#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32891#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32657#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32658#L954-3 assume !(0 == ~T4_E~0); 33296#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32737#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32738#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32943#L974-3 assume !(0 == ~T8_E~0); 32944#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33376#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33377#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32998#L994-3 assume !(0 == ~E_2~0); 32999#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33513#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32820#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32821#L1014-3 assume !(0 == ~E_6~0); 33362#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33363#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33344#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33297#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33298#L460-33 assume !(1 == ~m_pc~0); 33549#L460-35 is_master_triggered_~__retres1~0#1 := 0; 33528#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33089#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32665#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32666#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33026#L479-33 assume !(1 == ~t1_pc~0); 33027#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 32994#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32995#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33589#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 33773#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33035#L498-33 assume !(1 == ~t2_pc~0); 32779#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 32780#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32914#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32915#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32892#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32893#L517-33 assume !(1 == ~t3_pc~0); 33837#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 33697#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33698#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33499#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33500#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33124#L536-33 assume 1 == ~t4_pc~0; 33125#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33193#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33194#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33384#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33675#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32712#L555-33 assume !(1 == ~t5_pc~0); 32713#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 33440#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32985#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32986#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33467#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32683#L574-33 assume 1 == ~t6_pc~0; 32684#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33687#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33000#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33001#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33256#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32759#L593-33 assume !(1 == ~t7_pc~0); 32760#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 33216#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32864#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32865#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33527#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33664#L612-33 assume 1 == ~t8_pc~0; 33808#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33763#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33764#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33596#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32862#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32863#L631-33 assume !(1 == ~t9_pc~0); 33475#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 32803#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32804#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33059#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32916#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32917#L1047-3 assume !(1 == ~M_E~0); 33090#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33721#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33648#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33649#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32814#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32815#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33200#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33044#L1082-3 assume !(1 == ~T8_E~0); 33045#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33120#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33400#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33330#L1102-3 assume !(1 == ~E_2~0); 33331#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33689#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33039#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33040#L1122-3 assume !(1 == ~E_6~0); 33091#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33092#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33485#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33461#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 32921#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32798#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33462#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 33218#L1447 assume !(0 == start_simulation_~tmp~3#1); 33219#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33668#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32957#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33486#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 33067#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 32824#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32825#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 33283#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 32834#L1428-2 [2022-11-25 17:17:39,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:39,250 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2022-11-25 17:17:39,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:39,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988286549] [2022-11-25 17:17:39,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:39,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:39,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:39,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:39,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:39,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988286549] [2022-11-25 17:17:39,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988286549] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:39,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:39,335 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:39,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338803893] [2022-11-25 17:17:39,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:39,335 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:39,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:39,336 INFO L85 PathProgramCache]: Analyzing trace with hash -1705077169, now seen corresponding path program 1 times [2022-11-25 17:17:39,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:39,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426549904] [2022-11-25 17:17:39,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:39,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:39,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:39,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:39,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:39,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426549904] [2022-11-25 17:17:39,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426549904] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:39,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:39,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:39,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930234940] [2022-11-25 17:17:39,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:39,391 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:39,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:39,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:39,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:39,392 INFO L87 Difference]: Start difference. First operand 3967 states and 5760 transitions. cyclomatic complexity: 1797 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:39,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:39,703 INFO L93 Difference]: Finished difference Result 9505 states and 13663 transitions. [2022-11-25 17:17:39,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9505 states and 13663 transitions. [2022-11-25 17:17:39,751 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9204 [2022-11-25 17:17:39,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9505 states to 9505 states and 13663 transitions. [2022-11-25 17:17:39,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9505 [2022-11-25 17:17:39,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9505 [2022-11-25 17:17:39,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9505 states and 13663 transitions. [2022-11-25 17:17:39,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:39,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9505 states and 13663 transitions. [2022-11-25 17:17:39,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9505 states and 13663 transitions. [2022-11-25 17:17:40,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9505 to 7449. [2022-11-25 17:17:40,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:40,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7449 states to 7449 states and 10750 transitions. [2022-11-25 17:17:40,087 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2022-11-25 17:17:40,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:40,090 INFO L428 stractBuchiCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2022-11-25 17:17:40,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-11-25 17:17:40,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7449 states and 10750 transitions. [2022-11-25 17:17:40,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7300 [2022-11-25 17:17:40,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:40,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:40,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:40,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:40,125 INFO L748 eck$LassoCheckResult]: Stem: 47019#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 47020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 46966#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46967#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47204#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 46837#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46838#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47180#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46651#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46652#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47102#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47103#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46149#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46150#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46352#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46742#L939 assume !(0 == ~M_E~0); 46998#L939-2 assume !(0 == ~T1_E~0); 46999#L944-1 assume !(0 == ~T2_E~0); 46768#L949-1 assume !(0 == ~T3_E~0); 46766#L954-1 assume !(0 == ~T4_E~0); 46767#L959-1 assume !(0 == ~T5_E~0); 47221#L964-1 assume !(0 == ~T6_E~0); 46503#L969-1 assume !(0 == ~T7_E~0); 46504#L974-1 assume !(0 == ~T8_E~0); 47165#L979-1 assume !(0 == ~T9_E~0); 47166#L984-1 assume !(0 == ~E_M~0); 46663#L989-1 assume !(0 == ~E_1~0); 46664#L994-1 assume !(0 == ~E_2~0); 46550#L999-1 assume !(0 == ~E_3~0); 46551#L1004-1 assume !(0 == ~E_4~0); 46218#L1009-1 assume !(0 == ~E_5~0); 46219#L1014-1 assume !(0 == ~E_6~0); 46542#L1019-1 assume !(0 == ~E_7~0); 47109#L1024-1 assume !(0 == ~E_8~0); 46475#L1029-1 assume !(0 == ~E_9~0); 46476#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46564#L460 assume !(1 == ~m_pc~0); 47339#L460-2 is_master_triggered_~__retres1~0#1 := 0; 47072#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47073#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47364#L1167 assume !(0 != activate_threads_~tmp~1#1); 46755#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46756#L479 assume !(1 == ~t1_pc~0); 46913#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46914#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47296#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46487#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 46488#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46334#L498 assume !(1 == ~t2_pc~0); 46335#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46740#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46741#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47143#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47059#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47060#L517 assume 1 == ~t3_pc~0; 47301#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47302#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46810#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46520#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 46521#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47118#L536 assume !(1 == ~t4_pc~0); 46800#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46799#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47209#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46792#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 46793#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47028#L555 assume 1 == ~t5_pc~0; 47029#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47110#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46249#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46250#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 46355#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46257#L574 assume !(1 == ~t6_pc~0); 46258#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46890#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46360#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46361#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 47137#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47346#L593 assume 1 == ~t7_pc~0; 47347#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46495#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47226#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47380#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 47307#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46658#L612 assume !(1 == ~t8_pc~0); 46659#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47090#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46933#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46934#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 46892#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46893#L631 assume 1 == ~t9_pc~0; 46911#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46248#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46216#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46217#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 46743#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47121#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 46186#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46187#L1052-1 assume !(1 == ~T2_E~0); 46168#L1057-1 assume !(1 == ~T3_E~0); 46169#L1062-1 assume !(1 == ~T4_E~0); 46458#L1067-1 assume !(1 == ~T5_E~0); 47222#L1072-1 assume !(1 == ~T6_E~0); 47092#L1077-1 assume !(1 == ~T7_E~0); 47093#L1082-1 assume !(1 == ~T8_E~0); 46864#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46865#L1092-1 assume !(1 == ~E_M~0); 46170#L1097-1 assume !(1 == ~E_1~0); 46171#L1102-1 assume !(1 == ~E_2~0); 46961#L1107-1 assume !(1 == ~E_3~0); 46962#L1112-1 assume !(1 == ~E_4~0); 46935#L1117-1 assume !(1 == ~E_5~0); 46936#L1122-1 assume !(1 == ~E_6~0); 46811#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46812#L1132-1 assume !(1 == ~E_8~0); 47333#L1137-1 assume !(1 == ~E_9~0); 47334#L1142-1 assume { :end_inline_reset_delta_events } true; 52797#L1428-2 [2022-11-25 17:17:40,126 INFO L750 eck$LassoCheckResult]: Loop: 52797#L1428-2 assume !false; 52791#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52787#L914 assume !false; 52786#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 52784#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 52775#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 52774#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 52772#L783 assume !(0 != eval_~tmp~0#1); 52773#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53584#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53583#L939-3 assume !(0 == ~M_E~0); 53582#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53581#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53580#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53579#L954-3 assume !(0 == ~T4_E~0); 53578#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53577#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53576#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53575#L974-3 assume !(0 == ~T8_E~0); 53574#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53573#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53572#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53571#L994-3 assume !(0 == ~E_2~0); 53570#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53569#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53568#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53567#L1014-3 assume !(0 == ~E_6~0); 53566#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53565#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53564#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53563#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53562#L460-33 assume !(1 == ~m_pc~0); 53561#L460-35 is_master_triggered_~__retres1~0#1 := 0; 53560#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53559#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53558#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53557#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53556#L479-33 assume !(1 == ~t1_pc~0); 52724#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 53555#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53554#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53553#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 53552#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53516#L498-33 assume !(1 == ~t2_pc~0); 53513#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 53511#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53509#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53506#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53504#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53503#L517-33 assume 1 == ~t3_pc~0; 47368#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47195#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47196#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46991#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46992#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46603#L536-33 assume 1 == ~t4_pc~0; 46604#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46675#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46676#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53434#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53433#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53432#L555-33 assume !(1 == ~t5_pc~0); 53430#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 53429#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53428#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53427#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53426#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53425#L574-33 assume !(1 == ~t6_pc~0); 53424#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 53422#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53421#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53420#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53419#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53418#L593-33 assume !(1 == ~t7_pc~0); 53416#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 53415#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53414#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53413#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53412#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53411#L612-33 assume 1 == ~t8_pc~0; 53409#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53408#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53407#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53406#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53405#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53404#L631-33 assume !(1 == ~t9_pc~0); 53402#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 53401#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53400#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53398#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53396#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53394#L1047-3 assume !(1 == ~M_E~0); 46573#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53391#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53388#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53386#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47399#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53383#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53381#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53379#L1082-3 assume !(1 == ~T8_E~0); 53376#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53374#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53053#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53052#L1102-3 assume !(1 == ~E_2~0); 53051#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53050#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53049#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53048#L1122-3 assume !(1 == ~E_6~0); 53047#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53046#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53045#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53044#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53042#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53033#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53032#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 53031#L1447 assume !(0 == start_simulation_~tmp~3#1); 46851#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53027#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53017#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53015#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 53013#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 52833#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52812#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 52804#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 52797#L1428-2 [2022-11-25 17:17:40,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:40,127 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2022-11-25 17:17:40,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:40,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243191086] [2022-11-25 17:17:40,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:40,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:40,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:40,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:40,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:40,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243191086] [2022-11-25 17:17:40,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243191086] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:40,228 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:40,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:40,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001276548] [2022-11-25 17:17:40,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:40,229 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:40,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:40,230 INFO L85 PathProgramCache]: Analyzing trace with hash -1605909361, now seen corresponding path program 1 times [2022-11-25 17:17:40,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:40,230 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907685506] [2022-11-25 17:17:40,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:40,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:40,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:40,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:40,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:40,310 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907685506] [2022-11-25 17:17:40,310 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907685506] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:40,310 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:40,310 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:40,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323108863] [2022-11-25 17:17:40,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:40,312 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:40,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:40,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-25 17:17:40,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-25 17:17:40,314 INFO L87 Difference]: Start difference. First operand 7449 states and 10750 transitions. cyclomatic complexity: 3305 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:40,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:40,650 INFO L93 Difference]: Finished difference Result 9557 states and 13735 transitions. [2022-11-25 17:17:40,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9557 states and 13735 transitions. [2022-11-25 17:17:40,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9404 [2022-11-25 17:17:40,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9557 states to 9557 states and 13735 transitions. [2022-11-25 17:17:40,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9557 [2022-11-25 17:17:40,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9557 [2022-11-25 17:17:40,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9557 states and 13735 transitions. [2022-11-25 17:17:40,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:40,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9557 states and 13735 transitions. [2022-11-25 17:17:40,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9557 states and 13735 transitions. [2022-11-25 17:17:40,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9557 to 7461. [2022-11-25 17:17:40,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:40,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7461 states to 7461 states and 10681 transitions. [2022-11-25 17:17:40,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2022-11-25 17:17:40,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-25 17:17:40,914 INFO L428 stractBuchiCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2022-11-25 17:17:40,914 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-11-25 17:17:40,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7461 states and 10681 transitions. [2022-11-25 17:17:40,946 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7312 [2022-11-25 17:17:40,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:40,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:40,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:40,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:40,949 INFO L748 eck$LassoCheckResult]: Stem: 64127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 64128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 64054#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64055#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64386#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 63911#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63912#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64343#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63697#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63698#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64239#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64240#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63170#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63171#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63374#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63799#L939 assume !(0 == ~M_E~0); 64097#L939-2 assume !(0 == ~T1_E~0); 64098#L944-1 assume !(0 == ~T2_E~0); 63831#L949-1 assume !(0 == ~T3_E~0); 63829#L954-1 assume !(0 == ~T4_E~0); 63830#L959-1 assume !(0 == ~T5_E~0); 64407#L964-1 assume !(0 == ~T6_E~0); 63531#L969-1 assume !(0 == ~T7_E~0); 63532#L974-1 assume !(0 == ~T8_E~0); 64328#L979-1 assume !(0 == ~T9_E~0); 64329#L984-1 assume !(0 == ~E_M~0); 63709#L989-1 assume !(0 == ~E_1~0); 63710#L994-1 assume !(0 == ~E_2~0); 63585#L999-1 assume !(0 == ~E_3~0); 63586#L1004-1 assume !(0 == ~E_4~0); 63238#L1009-1 assume !(0 == ~E_5~0); 63239#L1014-1 assume !(0 == ~E_6~0); 63576#L1019-1 assume !(0 == ~E_7~0); 64247#L1024-1 assume !(0 == ~E_8~0); 63504#L1029-1 assume !(0 == ~E_9~0); 63505#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63600#L460 assume !(1 == ~m_pc~0); 64609#L460-2 is_master_triggered_~__retres1~0#1 := 0; 64204#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64205#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64670#L1167 assume !(0 != activate_threads_~tmp~1#1); 63815#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63816#L479 assume !(1 == ~t1_pc~0); 63998#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63999#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64542#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63516#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 63517#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63355#L498 assume !(1 == ~t2_pc~0); 63356#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63797#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63798#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64295#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 64190#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64191#L517 assume 1 == ~t3_pc~0; 64549#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64550#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63879#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63550#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 63551#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64260#L536 assume !(1 == ~t4_pc~0); 63869#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63868#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64394#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63860#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 63861#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64148#L555 assume 1 == ~t5_pc~0; 64149#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64248#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63270#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63271#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 63377#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63278#L574 assume !(1 == ~t6_pc~0); 63279#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63972#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63382#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63383#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 64288#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64620#L593 assume 1 == ~t7_pc~0; 64621#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63523#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64410#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64711#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 64556#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63704#L612 assume !(1 == ~t8_pc~0); 63705#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64226#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64019#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64020#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 63975#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63976#L631 assume 1 == ~t9_pc~0; 63996#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63269#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63236#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63237#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 63800#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64264#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 64265#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67062#L1052-1 assume !(1 == ~T2_E~0); 67061#L1057-1 assume !(1 == ~T3_E~0); 67060#L1062-1 assume !(1 == ~T4_E~0); 63486#L1067-1 assume !(1 == ~T5_E~0); 67059#L1072-1 assume !(1 == ~T6_E~0); 67058#L1077-1 assume !(1 == ~T7_E~0); 67057#L1082-1 assume !(1 == ~T8_E~0); 67056#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67055#L1092-1 assume !(1 == ~E_M~0); 67054#L1097-1 assume !(1 == ~E_1~0); 67053#L1102-1 assume !(1 == ~E_2~0); 67052#L1107-1 assume !(1 == ~E_3~0); 67051#L1112-1 assume !(1 == ~E_4~0); 67050#L1117-1 assume !(1 == ~E_5~0); 67049#L1122-1 assume !(1 == ~E_6~0); 67048#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 67047#L1132-1 assume !(1 == ~E_8~0); 67046#L1137-1 assume !(1 == ~E_9~0); 63484#L1142-1 assume { :end_inline_reset_delta_events } true; 63485#L1428-2 [2022-11-25 17:17:40,949 INFO L750 eck$LassoCheckResult]: Loop: 63485#L1428-2 assume !false; 65386#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65383#L914 assume !false; 65359#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65360#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65319#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65320#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65309#L783 assume !(0 != eval_~tmp~0#1); 65310#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66982#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66980#L939-3 assume !(0 == ~M_E~0); 66976#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66977#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66972#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66973#L954-3 assume !(0 == ~T4_E~0); 66968#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66969#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66964#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66965#L974-3 assume !(0 == ~T8_E~0); 66960#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 66961#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66956#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66957#L994-3 assume !(0 == ~E_2~0); 66952#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66953#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66948#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66949#L1014-3 assume !(0 == ~E_6~0); 66944#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66945#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66940#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66941#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66936#L460-33 assume !(1 == ~m_pc~0); 66937#L460-35 is_master_triggered_~__retres1~0#1 := 0; 66932#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66933#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66928#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66929#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65251#L479-33 assume !(1 == ~t1_pc~0); 65252#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 65247#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65248#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65244#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 65243#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65242#L498-33 assume !(1 == ~t2_pc~0); 65240#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 63777#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63420#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63421#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 63396#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63397#L517-33 assume !(1 == ~t3_pc~0); 64652#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 64369#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64370#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64089#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64090#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64289#L536-33 assume 1 == ~t4_pc~0; 64208#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63722#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63723#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63943#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64334#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63212#L555-33 assume !(1 == ~t5_pc~0); 63213#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64012#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63496#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63497#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64044#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63183#L574-33 assume 1 == ~t6_pc~0; 63184#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64351#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63512#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63513#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63794#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63259#L593-33 assume !(1 == ~t7_pc~0); 63260#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 65175#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65174#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65173#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65172#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64745#L612-33 assume !(1 == ~t8_pc~0); 64576#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 64486#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64487#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64227#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63365#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63366#L631-33 assume 1 == ~t9_pc~0; 64405#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63307#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63308#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63574#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63575#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65145#L1047-3 assume !(1 == ~M_E~0); 65144#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65143#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65142#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65141#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63318#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63319#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63729#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63559#L1082-3 assume !(1 == ~T8_E~0); 63560#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63644#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63962#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63877#L1102-3 assume !(1 == ~E_2~0); 63878#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64358#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63552#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63553#L1122-3 assume !(1 == ~E_6~0); 63611#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63612#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65114#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65113#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 63427#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 63302#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64039#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 63751#L1447 assume !(0 == start_simulation_~tmp~3#1); 63752#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65930#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67036#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67035#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 67034#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 67033#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67032#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 65438#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 63485#L1428-2 [2022-11-25 17:17:40,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:40,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2022-11-25 17:17:40,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:40,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301170784] [2022-11-25 17:17:40,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:40,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:40,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:41,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:41,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:41,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301170784] [2022-11-25 17:17:41,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301170784] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:41,105 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:41,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:41,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074602512] [2022-11-25 17:17:41,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:41,106 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:41,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:41,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1594560879, now seen corresponding path program 1 times [2022-11-25 17:17:41,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:41,107 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837026501] [2022-11-25 17:17:41,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:41,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:41,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:41,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:41,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:41,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837026501] [2022-11-25 17:17:41,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837026501] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:41,176 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:41,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:41,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490217071] [2022-11-25 17:17:41,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:41,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:41,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:41,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:41,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:41,179 INFO L87 Difference]: Start difference. First operand 7461 states and 10681 transitions. cyclomatic complexity: 3224 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:41,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:41,528 INFO L93 Difference]: Finished difference Result 17949 states and 25479 transitions. [2022-11-25 17:17:41,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17949 states and 25479 transitions. [2022-11-25 17:17:41,641 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17495 [2022-11-25 17:17:41,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17949 states to 17949 states and 25479 transitions. [2022-11-25 17:17:41,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17949 [2022-11-25 17:17:41,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17949 [2022-11-25 17:17:41,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17949 states and 25479 transitions. [2022-11-25 17:17:41,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:41,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17949 states and 25479 transitions. [2022-11-25 17:17:41,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17949 states and 25479 transitions. [2022-11-25 17:17:42,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17949 to 14108. [2022-11-25 17:17:42,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14108 states, 14108 states have (on average 1.424581797561667) internal successors, (20098), 14107 states have internal predecessors, (20098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:42,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14108 states to 14108 states and 20098 transitions. [2022-11-25 17:17:42,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14108 states and 20098 transitions. [2022-11-25 17:17:42,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:42,207 INFO L428 stractBuchiCegarLoop]: Abstraction has 14108 states and 20098 transitions. [2022-11-25 17:17:42,207 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-11-25 17:17:42,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14108 states and 20098 transitions. [2022-11-25 17:17:42,257 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13956 [2022-11-25 17:17:42,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:42,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:42,260 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:42,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:42,260 INFO L748 eck$LassoCheckResult]: Stem: 89472#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 89416#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89417#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89670#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 89288#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89289#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89645#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89097#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89098#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 89559#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 89560#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88590#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88591#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 88795#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89188#L939 assume !(0 == ~M_E~0); 89451#L939-2 assume !(0 == ~T1_E~0); 89452#L944-1 assume !(0 == ~T2_E~0); 89218#L949-1 assume !(0 == ~T3_E~0); 89216#L954-1 assume !(0 == ~T4_E~0); 89217#L959-1 assume !(0 == ~T5_E~0); 89688#L964-1 assume !(0 == ~T6_E~0); 88949#L969-1 assume !(0 == ~T7_E~0); 88950#L974-1 assume !(0 == ~T8_E~0); 89631#L979-1 assume !(0 == ~T9_E~0); 89632#L984-1 assume !(0 == ~E_M~0); 89109#L989-1 assume !(0 == ~E_1~0); 89110#L994-1 assume !(0 == ~E_2~0); 88996#L999-1 assume !(0 == ~E_3~0); 88997#L1004-1 assume !(0 == ~E_4~0); 88659#L1009-1 assume !(0 == ~E_5~0); 88660#L1014-1 assume !(0 == ~E_6~0); 88988#L1019-1 assume !(0 == ~E_7~0); 89567#L1024-1 assume !(0 == ~E_8~0); 88920#L1029-1 assume !(0 == ~E_9~0); 88921#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89011#L460 assume !(1 == ~m_pc~0); 89805#L460-2 is_master_triggered_~__retres1~0#1 := 0; 89526#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89527#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89834#L1167 assume !(0 != activate_threads_~tmp~1#1); 89203#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89204#L479 assume !(1 == ~t1_pc~0); 89363#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89364#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89765#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88932#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 88933#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88777#L498 assume !(1 == ~t2_pc~0); 88778#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89186#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89187#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89607#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 89513#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89514#L517 assume !(1 == ~t3_pc~0); 89855#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89856#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89261#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88966#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 88967#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89577#L536 assume !(1 == ~t4_pc~0); 89251#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89250#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89679#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89243#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 89244#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89482#L555 assume 1 == ~t5_pc~0; 89483#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89568#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88690#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88691#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 88800#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88698#L574 assume !(1 == ~t6_pc~0); 88699#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89340#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88805#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88806#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 89600#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89813#L593 assume 1 == ~t7_pc~0; 89814#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88939#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89693#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89858#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 89773#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89104#L612 assume !(1 == ~t8_pc~0); 89105#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89544#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89383#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89384#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 89342#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89343#L631 assume 1 == ~t9_pc~0; 89361#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88689#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88657#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88658#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 89189#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89580#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 88627#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88628#L1052-1 assume !(1 == ~T2_E~0); 88609#L1057-1 assume !(1 == ~T3_E~0); 88610#L1062-1 assume !(1 == ~T4_E~0); 88903#L1067-1 assume !(1 == ~T5_E~0); 89689#L1072-1 assume !(1 == ~T6_E~0); 89546#L1077-1 assume !(1 == ~T7_E~0); 89547#L1082-1 assume !(1 == ~T8_E~0); 89315#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89316#L1092-1 assume !(1 == ~E_M~0); 88611#L1097-1 assume !(1 == ~E_1~0); 88612#L1102-1 assume !(1 == ~E_2~0); 89411#L1107-1 assume !(1 == ~E_3~0); 89412#L1112-1 assume !(1 == ~E_4~0); 89385#L1117-1 assume !(1 == ~E_5~0); 89386#L1122-1 assume !(1 == ~E_6~0); 89262#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89263#L1132-1 assume !(1 == ~E_8~0); 89798#L1137-1 assume !(1 == ~E_9~0); 89799#L1142-1 assume { :end_inline_reset_delta_events } true; 101106#L1428-2 [2022-11-25 17:17:42,261 INFO L750 eck$LassoCheckResult]: Loop: 101106#L1428-2 assume !false; 100946#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100940#L914 assume !false; 100938#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 100932#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 100921#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 100919#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 100916#L783 assume !(0 != eval_~tmp~0#1); 100917#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102621#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102620#L939-3 assume !(0 == ~M_E~0); 102617#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102616#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102533#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102532#L954-3 assume !(0 == ~T4_E~0); 102531#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102530#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102529#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 102527#L974-3 assume !(0 == ~T8_E~0); 102525#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102523#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102521#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102519#L994-3 assume !(0 == ~E_2~0); 102517#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102515#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102514#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102513#L1014-3 assume !(0 == ~E_6~0); 89290#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89291#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89274#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89226#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89227#L460-33 assume !(1 == ~m_pc~0); 89497#L460-35 is_master_triggered_~__retres1~0#1 := 0; 89475#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89018#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88588#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88589#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88953#L479-33 assume !(1 == ~t1_pc~0); 88954#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 101419#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101418#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101415#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 101413#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101411#L498-33 assume !(1 == ~t2_pc~0); 101408#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 101406#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101404#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101401#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 101399#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101397#L517-33 assume !(1 == ~t3_pc~0); 95445#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 101394#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101392#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101389#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101387#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101385#L536-33 assume !(1 == ~t4_pc~0); 101383#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 101380#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101378#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101375#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101373#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101371#L555-33 assume 1 == ~t5_pc~0; 101369#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 101366#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101364#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101361#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101359#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101357#L574-33 assume !(1 == ~t6_pc~0); 101355#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 101352#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101350#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101348#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 101346#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101344#L593-33 assume !(1 == ~t7_pc~0); 101341#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 101339#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101337#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101335#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101333#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101331#L612-33 assume !(1 == ~t8_pc~0); 101329#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 101326#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101324#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101322#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101320#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101318#L631-33 assume !(1 == ~t9_pc~0); 101315#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 101313#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101311#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101309#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101307#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101197#L1047-3 assume !(1 == ~M_E~0); 101195#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101192#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101190#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101188#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101184#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101182#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101180#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101178#L1082-3 assume !(1 == ~T8_E~0); 101176#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101174#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101172#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101170#L1102-3 assume !(1 == ~E_2~0); 101168#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101166#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101164#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101162#L1122-3 assume !(1 == ~E_6~0); 101160#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101158#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101156#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101154#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101148#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101138#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101136#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 101135#L1447 assume !(0 == start_simulation_~tmp~3#1); 101133#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101131#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101119#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101117#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 101115#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 101114#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101109#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 101108#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 101106#L1428-2 [2022-11-25 17:17:42,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:42,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2022-11-25 17:17:42,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:42,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641105526] [2022-11-25 17:17:42,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:42,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:42,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:42,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:42,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:42,343 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641105526] [2022-11-25 17:17:42,343 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641105526] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:42,343 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:42,343 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:42,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627644071] [2022-11-25 17:17:42,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:42,344 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:42,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:42,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1750521709, now seen corresponding path program 1 times [2022-11-25 17:17:42,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:42,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365028037] [2022-11-25 17:17:42,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:42,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:42,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:42,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:42,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:42,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365028037] [2022-11-25 17:17:42,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365028037] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:42,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:42,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:42,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789145445] [2022-11-25 17:17:42,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:42,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:42,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:42,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:42,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:42,419 INFO L87 Difference]: Start difference. First operand 14108 states and 20098 transitions. cyclomatic complexity: 5994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:42,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:42,724 INFO L93 Difference]: Finished difference Result 26783 states and 37979 transitions. [2022-11-25 17:17:42,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26783 states and 37979 transitions. [2022-11-25 17:17:42,857 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26592 [2022-11-25 17:17:42,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26783 states to 26783 states and 37979 transitions. [2022-11-25 17:17:42,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26783 [2022-11-25 17:17:42,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26783 [2022-11-25 17:17:42,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26783 states and 37979 transitions. [2022-11-25 17:17:43,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:43,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26783 states and 37979 transitions. [2022-11-25 17:17:43,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26783 states and 37979 transitions. [2022-11-25 17:17:43,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26783 to 26751. [2022-11-25 17:17:43,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26751 states, 26751 states have (on average 1.4185264102276551) internal successors, (37947), 26750 states have internal predecessors, (37947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:43,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26751 states to 26751 states and 37947 transitions. [2022-11-25 17:17:43,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26751 states and 37947 transitions. [2022-11-25 17:17:43,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:43,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 26751 states and 37947 transitions. [2022-11-25 17:17:43,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-11-25 17:17:43,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26751 states and 37947 transitions. [2022-11-25 17:17:43,881 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26560 [2022-11-25 17:17:43,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:43,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:43,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:43,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:43,892 INFO L748 eck$LassoCheckResult]: Stem: 130377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 130378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 130323#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130324#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130574#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 130193#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130194#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130547#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130001#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130002#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130455#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130456#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 129490#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 129491#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 129694#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130095#L939 assume !(0 == ~M_E~0); 130356#L939-2 assume !(0 == ~T1_E~0); 130357#L944-1 assume !(0 == ~T2_E~0); 130124#L949-1 assume !(0 == ~T3_E~0); 130122#L954-1 assume !(0 == ~T4_E~0); 130123#L959-1 assume !(0 == ~T5_E~0); 130597#L964-1 assume !(0 == ~T6_E~0); 129846#L969-1 assume !(0 == ~T7_E~0); 129847#L974-1 assume !(0 == ~T8_E~0); 130530#L979-1 assume !(0 == ~T9_E~0); 130531#L984-1 assume !(0 == ~E_M~0); 130013#L989-1 assume !(0 == ~E_1~0); 130014#L994-1 assume !(0 == ~E_2~0); 129896#L999-1 assume !(0 == ~E_3~0); 129897#L1004-1 assume !(0 == ~E_4~0); 129557#L1009-1 assume !(0 == ~E_5~0); 129558#L1014-1 assume !(0 == ~E_6~0); 129888#L1019-1 assume !(0 == ~E_7~0); 130463#L1024-1 assume !(0 == ~E_8~0); 129816#L1029-1 assume !(0 == ~E_9~0); 129817#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129910#L460 assume !(1 == ~m_pc~0); 130719#L460-2 is_master_triggered_~__retres1~0#1 := 0; 130427#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130428#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130751#L1167 assume !(0 != activate_threads_~tmp~1#1); 130111#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130112#L479 assume !(1 == ~t1_pc~0); 130269#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130270#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130683#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 129828#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 129829#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129676#L498 assume !(1 == ~t2_pc~0); 129677#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130093#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130094#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130504#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 130415#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130416#L517 assume !(1 == ~t3_pc~0); 130769#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130770#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130166#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 129863#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 129864#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130472#L536 assume !(1 == ~t4_pc~0); 130156#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130155#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130586#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130148#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 130149#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130385#L555 assume !(1 == ~t5_pc~0); 130386#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130464#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129588#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 129589#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 129697#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129597#L574 assume !(1 == ~t6_pc~0); 129598#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130245#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 129702#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129703#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 130497#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130726#L593 assume 1 == ~t7_pc~0; 130727#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 129836#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130602#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 130773#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 130692#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130008#L612 assume !(1 == ~t8_pc~0); 130009#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 130445#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130291#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130292#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 130248#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130249#L631 assume 1 == ~t9_pc~0; 130267#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129587#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129555#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129556#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 130096#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130475#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 130476#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 153125#L1052-1 assume !(1 == ~T2_E~0); 153124#L1057-1 assume !(1 == ~T3_E~0); 153123#L1062-1 assume !(1 == ~T4_E~0); 129799#L1067-1 assume !(1 == ~T5_E~0); 153122#L1072-1 assume !(1 == ~T6_E~0); 153121#L1077-1 assume !(1 == ~T7_E~0); 153120#L1082-1 assume !(1 == ~T8_E~0); 153119#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 153118#L1092-1 assume !(1 == ~E_M~0); 153117#L1097-1 assume !(1 == ~E_1~0); 153116#L1102-1 assume !(1 == ~E_2~0); 153115#L1107-1 assume !(1 == ~E_3~0); 130243#L1112-1 assume !(1 == ~E_4~0); 130244#L1117-1 assume !(1 == ~E_5~0); 130293#L1122-1 assume !(1 == ~E_6~0); 130167#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 129913#L1132-1 assume !(1 == ~E_8~0); 129914#L1137-1 assume !(1 == ~E_9~0); 129798#L1142-1 assume { :end_inline_reset_delta_events } true; 129659#L1428-2 [2022-11-25 17:17:43,893 INFO L750 eck$LassoCheckResult]: Loop: 129659#L1428-2 assume !false; 129660#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129733#L914 assume !false; 130239#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130240#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129495#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 129496#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 130500#L783 assume !(0 != eval_~tmp~0#1); 130501#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 155705#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 155703#L939-3 assume !(0 == ~M_E~0); 155700#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155698#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 155696#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155694#L954-3 assume !(0 == ~T4_E~0); 155692#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155691#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 155690#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 155689#L974-3 assume !(0 == ~T8_E~0); 155688#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 155687#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 155686#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155685#L994-3 assume !(0 == ~E_2~0); 155684#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155683#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155682#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155681#L1014-3 assume !(0 == ~E_6~0); 155680#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 155679#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 155678#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 155676#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155674#L460-33 assume !(1 == ~m_pc~0); 155672#L460-35 is_master_triggered_~__retres1~0#1 := 0; 155670#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155668#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 154696#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 154695#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154694#L479-33 assume !(1 == ~t1_pc~0); 150985#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 155535#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155534#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155533#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 155532#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155531#L498-33 assume !(1 == ~t2_pc~0); 155529#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 155528#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155527#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155526#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 155525#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155524#L517-33 assume !(1 == ~t3_pc~0); 152537#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 155523#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155522#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155520#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 155518#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155516#L536-33 assume !(1 == ~t4_pc~0); 155514#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 155511#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155509#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155507#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 155504#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155502#L555-33 assume !(1 == ~t5_pc~0); 155500#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 155498#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155496#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155494#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 155491#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155489#L574-33 assume 1 == ~t6_pc~0; 155486#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 155484#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155482#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155480#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 155477#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155475#L593-33 assume !(1 == ~t7_pc~0); 155472#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 155470#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155468#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 155466#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 155463#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155461#L612-33 assume 1 == ~t8_pc~0; 155458#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 155456#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155454#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 155452#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 155449#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 155447#L631-33 assume !(1 == ~t9_pc~0); 155444#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 155442#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 155440#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155438#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 155435#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155433#L1047-3 assume !(1 == ~M_E~0); 153587#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 155430#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155428#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155427#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 153582#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 155426#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 155425#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 155424#L1082-3 assume !(1 == ~T8_E~0); 155423#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 155422#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 155421#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 155420#L1102-3 assume !(1 == ~E_2~0); 155419#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 155418#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 155417#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 155416#L1122-3 assume !(1 == ~E_6~0); 155415#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 155414#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 154491#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 130308#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 129745#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129621#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130309#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 130052#L1447 assume !(0 == start_simulation_~tmp~3#1); 130053#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130529#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129781#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130332#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 129895#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 129649#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129650#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 130117#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 129659#L1428-2 [2022-11-25 17:17:43,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:43,894 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2022-11-25 17:17:43,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:43,894 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570630271] [2022-11-25 17:17:43,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:43,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:43,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:44,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:44,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:44,129 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570630271] [2022-11-25 17:17:44,129 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570630271] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:44,129 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:44,129 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:44,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662891579] [2022-11-25 17:17:44,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:44,130 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:44,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:44,131 INFO L85 PathProgramCache]: Analyzing trace with hash -540382702, now seen corresponding path program 1 times [2022-11-25 17:17:44,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:44,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284851436] [2022-11-25 17:17:44,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:44,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:44,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:44,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:44,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:44,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284851436] [2022-11-25 17:17:44,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284851436] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:44,176 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:44,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:44,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386486846] [2022-11-25 17:17:44,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:44,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:44,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:44,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:44,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:44,178 INFO L87 Difference]: Start difference. First operand 26751 states and 37947 transitions. cyclomatic complexity: 11204 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:44,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:44,766 INFO L93 Difference]: Finished difference Result 63922 states and 90012 transitions. [2022-11-25 17:17:44,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63922 states and 90012 transitions. [2022-11-25 17:17:45,181 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 62476 [2022-11-25 17:17:45,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63922 states to 63922 states and 90012 transitions. [2022-11-25 17:17:45,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63922 [2022-11-25 17:17:45,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63922 [2022-11-25 17:17:45,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63922 states and 90012 transitions. [2022-11-25 17:17:45,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:45,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63922 states and 90012 transitions. [2022-11-25 17:17:45,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63922 states and 90012 transitions. [2022-11-25 17:17:46,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63922 to 50750. [2022-11-25 17:17:46,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50750 states, 50750 states have (on average 1.4132019704433498) internal successors, (71720), 50749 states have internal predecessors, (71720), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:46,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50750 states to 50750 states and 71720 transitions. [2022-11-25 17:17:46,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50750 states and 71720 transitions. [2022-11-25 17:17:46,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:46,799 INFO L428 stractBuchiCegarLoop]: Abstraction has 50750 states and 71720 transitions. [2022-11-25 17:17:46,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-11-25 17:17:46,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50750 states and 71720 transitions. [2022-11-25 17:17:46,952 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 50512 [2022-11-25 17:17:46,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:46,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:46,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:46,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:46,956 INFO L748 eck$LassoCheckResult]: Stem: 221057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 221058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 221006#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221007#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221272#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 220879#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220880#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221241#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220681#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220682#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 221149#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221150#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220172#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 220173#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 220374#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 220778#L939 assume !(0 == ~M_E~0); 221037#L939-2 assume !(0 == ~T1_E~0); 221038#L944-1 assume !(0 == ~T2_E~0); 220806#L949-1 assume !(0 == ~T3_E~0); 220804#L954-1 assume !(0 == ~T4_E~0); 220805#L959-1 assume !(0 == ~T5_E~0); 221296#L964-1 assume !(0 == ~T6_E~0); 220528#L969-1 assume !(0 == ~T7_E~0); 220529#L974-1 assume !(0 == ~T8_E~0); 221223#L979-1 assume !(0 == ~T9_E~0); 221224#L984-1 assume !(0 == ~E_M~0); 220693#L989-1 assume !(0 == ~E_1~0); 220694#L994-1 assume !(0 == ~E_2~0); 220577#L999-1 assume !(0 == ~E_3~0); 220578#L1004-1 assume !(0 == ~E_4~0); 220239#L1009-1 assume !(0 == ~E_5~0); 220240#L1014-1 assume !(0 == ~E_6~0); 220569#L1019-1 assume !(0 == ~E_7~0); 221157#L1024-1 assume !(0 == ~E_8~0); 220499#L1029-1 assume !(0 == ~E_9~0); 220500#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220592#L460 assume !(1 == ~m_pc~0); 221431#L460-2 is_master_triggered_~__retres1~0#1 := 0; 221118#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221119#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221461#L1167 assume !(0 != activate_threads_~tmp~1#1); 220793#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220794#L479 assume !(1 == ~t1_pc~0); 220954#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 220955#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221388#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 220511#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 220512#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220356#L498 assume !(1 == ~t2_pc~0); 220357#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220776#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220777#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 221195#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 221105#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221106#L517 assume !(1 == ~t3_pc~0); 221483#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221484#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220849#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220545#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 220546#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221168#L536 assume !(1 == ~t4_pc~0); 220839#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220838#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221284#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220830#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 220831#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221071#L555 assume !(1 == ~t5_pc~0); 221072#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221158#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220270#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220271#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 220379#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220279#L574 assume !(1 == ~t6_pc~0); 220280#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 220930#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220384#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220385#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 221187#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221439#L593 assume !(1 == ~t7_pc~0); 220517#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 220518#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221301#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221491#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 221397#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220688#L612 assume !(1 == ~t8_pc~0); 220689#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221139#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220973#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220974#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 220932#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220933#L631 assume 1 == ~t9_pc~0; 220952#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 220269#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 220237#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220238#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 220779#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221171#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 221172#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269186#L1052-1 assume !(1 == ~T2_E~0); 269185#L1057-1 assume !(1 == ~T3_E~0); 269184#L1062-1 assume !(1 == ~T4_E~0); 220482#L1067-1 assume !(1 == ~T5_E~0); 269183#L1072-1 assume !(1 == ~T6_E~0); 269182#L1077-1 assume !(1 == ~T7_E~0); 269181#L1082-1 assume !(1 == ~T8_E~0); 269180#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 269179#L1092-1 assume !(1 == ~E_M~0); 269178#L1097-1 assume !(1 == ~E_1~0); 269177#L1102-1 assume !(1 == ~E_2~0); 269176#L1107-1 assume !(1 == ~E_3~0); 269175#L1112-1 assume !(1 == ~E_4~0); 269174#L1117-1 assume !(1 == ~E_5~0); 269173#L1122-1 assume !(1 == ~E_6~0); 269172#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 269171#L1132-1 assume !(1 == ~E_8~0); 269169#L1137-1 assume !(1 == ~E_9~0); 269167#L1142-1 assume { :end_inline_reset_delta_events } true; 269164#L1428-2 [2022-11-25 17:17:46,957 INFO L750 eck$LassoCheckResult]: Loop: 269164#L1428-2 assume !false; 269047#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 269041#L914 assume !false; 269039#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269031#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269021#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269019#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 269018#L783 assume !(0 != eval_~tmp~0#1); 220580#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220581#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221279#L939-3 assume !(0 == ~M_E~0); 221280#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220450#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220162#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220163#L954-3 assume !(0 == ~T4_E~0); 220812#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220241#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220242#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220448#L974-3 assume !(0 == ~T8_E~0); 220449#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220897#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220898#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220505#L994-3 assume !(0 == ~E_2~0); 220506#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221045#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 220324#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220325#L1014-3 assume !(0 == ~E_6~0); 220881#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220882#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 220861#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 220813#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220814#L460-33 assume !(1 == ~m_pc~0); 221087#L460-35 is_master_triggered_~__retres1~0#1 := 0; 221060#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221061#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270475#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221008#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221009#L479-33 assume !(1 == ~t1_pc~0); 269455#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 269454#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269453#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269450#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 269448#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269446#L498-33 assume !(1 == ~t2_pc~0); 269444#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 269443#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269442#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269441#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 269440#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269439#L517-33 assume !(1 == ~t3_pc~0); 261921#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 269438#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269437#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269436#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269435#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269434#L536-33 assume 1 == ~t4_pc~0; 269432#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 269431#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269429#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269427#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 269426#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269425#L555-33 assume !(1 == ~t5_pc~0); 269424#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 269423#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269422#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269421#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 269419#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269417#L574-33 assume 1 == ~t6_pc~0; 269414#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269412#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269410#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269408#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 269406#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269404#L593-33 assume !(1 == ~t7_pc~0); 237072#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 269401#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269399#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 269397#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269395#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269393#L612-33 assume 1 == ~t8_pc~0; 269390#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269388#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269386#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269384#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 269382#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269380#L631-33 assume !(1 == ~t9_pc~0); 269377#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 269375#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269373#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269371#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 269369#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269260#L1047-3 assume !(1 == ~M_E~0); 269258#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269256#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 269253#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269251#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269247#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 269245#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 269243#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 269241#L1082-3 assume !(1 == ~T8_E~0); 269238#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 269236#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 269234#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 269232#L1102-3 assume !(1 == ~E_2~0); 269230#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 269229#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 269228#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 269227#L1122-3 assume !(1 == ~E_6~0); 269226#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 269225#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 269224#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 269223#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269221#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269212#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269211#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 269210#L1447 assume !(0 == start_simulation_~tmp~3#1); 220894#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269208#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269196#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269194#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 269192#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 269191#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 269187#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 269166#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 269164#L1428-2 [2022-11-25 17:17:46,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:46,958 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2022-11-25 17:17:46,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:46,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43335299] [2022-11-25 17:17:47,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:47,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:47,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:47,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:47,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:47,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43335299] [2022-11-25 17:17:47,206 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [43335299] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:47,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:47,207 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:47,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752905530] [2022-11-25 17:17:47,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:47,207 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:47,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:47,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1678011567, now seen corresponding path program 1 times [2022-11-25 17:17:47,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:47,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025311643] [2022-11-25 17:17:47,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:47,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:47,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:47,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:47,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:47,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025311643] [2022-11-25 17:17:47,251 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025311643] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:47,251 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:47,251 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:17:47,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586592216] [2022-11-25 17:17:47,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:47,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:47,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:47,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:17:47,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:17:47,253 INFO L87 Difference]: Start difference. First operand 50750 states and 71720 transitions. cyclomatic complexity: 20978 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:48,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:48,280 INFO L93 Difference]: Finished difference Result 120381 states and 168933 transitions. [2022-11-25 17:17:48,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120381 states and 168933 transitions. [2022-11-25 17:17:48,868 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 117648 [2022-11-25 17:17:49,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120381 states to 120381 states and 168933 transitions. [2022-11-25 17:17:49,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120381 [2022-11-25 17:17:49,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120381 [2022-11-25 17:17:49,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120381 states and 168933 transitions. [2022-11-25 17:17:50,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:50,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120381 states and 168933 transitions. [2022-11-25 17:17:50,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120381 states and 168933 transitions. [2022-11-25 17:17:51,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120381 to 96205. [2022-11-25 17:17:51,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96205 states, 96205 states have (on average 1.4085442544566291) internal successors, (135509), 96204 states have internal predecessors, (135509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:52,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96205 states to 96205 states and 135509 transitions. [2022-11-25 17:17:52,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96205 states and 135509 transitions. [2022-11-25 17:17:52,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:17:52,230 INFO L428 stractBuchiCegarLoop]: Abstraction has 96205 states and 135509 transitions. [2022-11-25 17:17:52,230 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-11-25 17:17:52,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96205 states and 135509 transitions. [2022-11-25 17:17:52,471 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 95872 [2022-11-25 17:17:52,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:52,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:52,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:52,476 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:52,476 INFO L748 eck$LassoCheckResult]: Stem: 392215#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 392216#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 392159#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 392160#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 392432#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 392025#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 392026#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 392402#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 391821#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 391822#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 392307#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 392308#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 391313#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 391314#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 391515#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 391920#L939 assume !(0 == ~M_E~0); 392193#L939-2 assume !(0 == ~T1_E~0); 392194#L944-1 assume !(0 == ~T2_E~0); 391951#L949-1 assume !(0 == ~T3_E~0); 391947#L954-1 assume !(0 == ~T4_E~0); 391948#L959-1 assume !(0 == ~T5_E~0); 392453#L964-1 assume !(0 == ~T6_E~0); 391669#L969-1 assume !(0 == ~T7_E~0); 391670#L974-1 assume !(0 == ~T8_E~0); 392388#L979-1 assume !(0 == ~T9_E~0); 392389#L984-1 assume !(0 == ~E_M~0); 391833#L989-1 assume !(0 == ~E_1~0); 391834#L994-1 assume !(0 == ~E_2~0); 391718#L999-1 assume !(0 == ~E_3~0); 391719#L1004-1 assume !(0 == ~E_4~0); 391382#L1009-1 assume !(0 == ~E_5~0); 391383#L1014-1 assume !(0 == ~E_6~0); 391710#L1019-1 assume !(0 == ~E_7~0); 392315#L1024-1 assume !(0 == ~E_8~0); 391639#L1029-1 assume !(0 == ~E_9~0); 391640#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 391733#L460 assume !(1 == ~m_pc~0); 392590#L460-2 is_master_triggered_~__retres1~0#1 := 0; 392274#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 392275#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 392625#L1167 assume !(0 != activate_threads_~tmp~1#1); 391936#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 391937#L479 assume !(1 == ~t1_pc~0); 392103#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 392104#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392540#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 391651#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 391652#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 391497#L498 assume !(1 == ~t2_pc~0); 391498#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 391918#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 391919#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 392358#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 392261#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 392262#L517 assume !(1 == ~t3_pc~0); 392643#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 392644#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 391996#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 391686#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 391687#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392326#L536 assume !(1 == ~t4_pc~0); 391986#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 391985#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 392440#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 391977#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 391978#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392230#L555 assume !(1 == ~t5_pc~0); 392231#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392316#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 391412#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 391413#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 391518#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 391421#L574 assume !(1 == ~t6_pc~0); 391422#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 392082#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 391523#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 391524#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 392351#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 392596#L593 assume !(1 == ~t7_pc~0); 391658#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 391659#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 392459#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 392650#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 392548#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 391828#L612 assume !(1 == ~t8_pc~0); 391829#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 392293#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 392121#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 392122#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 392084#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 392085#L631 assume !(1 == ~t9_pc~0); 392158#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 391411#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 391380#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 391381#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 391921#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392330#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 392331#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 392077#L1052-1 assume !(1 == ~T2_E~0); 392078#L1057-1 assume !(1 == ~T3_E~0); 391622#L1062-1 assume !(1 == ~T4_E~0); 391623#L1067-1 assume !(1 == ~T5_E~0); 391940#L1072-1 assume !(1 == ~T6_E~0); 391941#L1077-1 assume !(1 == ~T7_E~0); 391511#L1082-1 assume !(1 == ~T8_E~0); 391512#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 391305#L1092-1 assume !(1 == ~E_M~0); 391306#L1097-1 assume !(1 == ~E_1~0); 392581#L1102-1 assume !(1 == ~E_2~0); 392582#L1107-1 assume !(1 == ~E_3~0); 392080#L1112-1 assume !(1 == ~E_4~0); 392081#L1117-1 assume !(1 == ~E_5~0); 392680#L1122-1 assume !(1 == ~E_6~0); 392681#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 391736#L1132-1 assume !(1 == ~E_8~0); 391737#L1137-1 assume !(1 == ~E_9~0); 391620#L1142-1 assume { :end_inline_reset_delta_events } true; 391621#L1428-2 [2022-11-25 17:17:52,477 INFO L750 eck$LassoCheckResult]: Loop: 391621#L1428-2 assume !false; 473361#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473352#L914 assume !false; 473349#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473242#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473163#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473160#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 473154#L783 assume !(0 != eval_~tmp~0#1); 473155#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 486428#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 486426#L939-3 assume !(0 == ~M_E~0); 486424#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 486422#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 486420#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 486419#L954-3 assume !(0 == ~T4_E~0); 486418#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 486417#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 486416#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 486415#L974-3 assume !(0 == ~T8_E~0); 486414#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 486413#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 486412#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 486411#L994-3 assume !(0 == ~E_2~0); 486410#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 486409#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 486408#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 486407#L1014-3 assume !(0 == ~E_6~0); 486406#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 486405#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 486404#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 486403#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486402#L460-33 assume !(1 == ~m_pc~0); 486400#L460-35 is_master_triggered_~__retres1~0#1 := 0; 486398#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486396#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 486394#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 486392#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486390#L479-33 assume !(1 == ~t1_pc~0); 484583#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 486385#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486383#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486381#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 486379#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486377#L498-33 assume !(1 == ~t2_pc~0); 486373#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 486371#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486369#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486367#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 486365#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486363#L517-33 assume !(1 == ~t3_pc~0); 473898#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 486361#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 486359#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486357#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 486355#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486353#L536-33 assume !(1 == ~t4_pc~0); 486351#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 486347#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486345#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486343#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 486341#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486339#L555-33 assume !(1 == ~t5_pc~0); 486337#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 486334#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486332#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 486330#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 486328#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 486326#L574-33 assume !(1 == ~t6_pc~0); 486324#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 486320#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486318#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486316#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 486314#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 473656#L593-33 assume !(1 == ~t7_pc~0); 473651#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 473650#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 473649#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 473648#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 473647#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 473646#L612-33 assume !(1 == ~t8_pc~0); 473644#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 473641#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 473639#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 473637#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 473635#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 473633#L631-33 assume !(1 == ~t9_pc~0); 434345#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 473629#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 473627#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 473625#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 473623#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473621#L1047-3 assume !(1 == ~M_E~0); 470274#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 473619#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 473617#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 473615#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 470257#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 473612#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 473610#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 473608#L1082-3 assume !(1 == ~T8_E~0); 473606#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 473604#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 473602#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 473600#L1102-3 assume !(1 == ~E_2~0); 473597#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 473595#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 473593#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 473591#L1122-3 assume !(1 == ~E_6~0); 473589#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 473587#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 473586#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 473584#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473515#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473505#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473503#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 473501#L1447 assume !(0 == start_simulation_~tmp~3#1); 473498#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473490#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473477#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 473475#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 473473#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473462#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 473451#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 391621#L1428-2 [2022-11-25 17:17:52,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:52,478 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2022-11-25 17:17:52,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:52,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832181954] [2022-11-25 17:17:52,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:52,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:52,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:52,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:52,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:52,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832181954] [2022-11-25 17:17:52,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832181954] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:52,540 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:52,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:52,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829126225] [2022-11-25 17:17:52,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:52,541 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:52,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:52,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1173593068, now seen corresponding path program 1 times [2022-11-25 17:17:52,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:52,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [465754901] [2022-11-25 17:17:52,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:52,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:52,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:52,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:52,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:52,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [465754901] [2022-11-25 17:17:52,608 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [465754901] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:52,608 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:52,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:52,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242350406] [2022-11-25 17:17:52,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:52,609 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:52,609 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:52,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:52,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:52,610 INFO L87 Difference]: Start difference. First operand 96205 states and 135509 transitions. cyclomatic complexity: 39312 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:53,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:53,529 INFO L93 Difference]: Finished difference Result 142665 states and 201260 transitions. [2022-11-25 17:17:53,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142665 states and 201260 transitions. [2022-11-25 17:17:54,124 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142240 [2022-11-25 17:17:54,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142665 states to 142665 states and 201260 transitions. [2022-11-25 17:17:54,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142665 [2022-11-25 17:17:54,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142665 [2022-11-25 17:17:54,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142665 states and 201260 transitions. [2022-11-25 17:17:55,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:55,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142665 states and 201260 transitions. [2022-11-25 17:17:55,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142665 states and 201260 transitions. [2022-11-25 17:17:56,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142665 to 97465. [2022-11-25 17:17:56,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4142307494998205) internal successors, (137838), 97464 states have internal predecessors, (137838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137838 transitions. [2022-11-25 17:17:57,175 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97465 states and 137838 transitions. [2022-11-25 17:17:57,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:17:57,176 INFO L428 stractBuchiCegarLoop]: Abstraction has 97465 states and 137838 transitions. [2022-11-25 17:17:57,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-11-25 17:17:57,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137838 transitions. [2022-11-25 17:17:57,409 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2022-11-25 17:17:57,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:17:57,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:17:57,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:17:57,417 INFO L748 eck$LassoCheckResult]: Stem: 631096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 631097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 631038#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 631039#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 631315#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 630907#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 630908#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 631284#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630701#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 630702#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 631185#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 631186#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630192#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630193#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 630393#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 630799#L939 assume !(0 == ~M_E~0); 631071#L939-2 assume !(0 == ~T1_E~0); 631072#L944-1 assume !(0 == ~T2_E~0); 630833#L949-1 assume !(0 == ~T3_E~0); 630829#L954-1 assume !(0 == ~T4_E~0); 630830#L959-1 assume !(0 == ~T5_E~0); 631339#L964-1 assume !(0 == ~T6_E~0); 630543#L969-1 assume !(0 == ~T7_E~0); 630544#L974-1 assume !(0 == ~T8_E~0); 631270#L979-1 assume !(0 == ~T9_E~0); 631271#L984-1 assume !(0 == ~E_M~0); 630714#L989-1 assume !(0 == ~E_1~0); 630715#L994-1 assume !(0 == ~E_2~0); 630593#L999-1 assume !(0 == ~E_3~0); 630594#L1004-1 assume !(0 == ~E_4~0); 630259#L1009-1 assume !(0 == ~E_5~0); 630260#L1014-1 assume !(0 == ~E_6~0); 630589#L1019-1 assume !(0 == ~E_7~0); 631191#L1024-1 assume !(0 == ~E_8~0); 630513#L1029-1 assume !(0 == ~E_9~0); 630514#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630609#L460 assume !(1 == ~m_pc~0); 631479#L460-2 is_master_triggered_~__retres1~0#1 := 0; 631154#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631155#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 631520#L1167 assume !(0 != activate_threads_~tmp~1#1); 630818#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630819#L479 assume !(1 == ~t1_pc~0); 630982#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630983#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 631437#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630528#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 630529#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630374#L498 assume !(1 == ~t2_pc~0); 630375#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630797#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630798#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 631230#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 631144#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 631145#L517 assume !(1 == ~t3_pc~0); 631549#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 631550#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630877#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630560#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 630561#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631202#L536 assume !(1 == ~t4_pc~0); 630867#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630866#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631325#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630859#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 630860#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 631117#L555 assume !(1 == ~t5_pc~0); 631118#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 631192#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630291#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 630292#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 630398#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630297#L574 assume !(1 == ~t6_pc~0); 630298#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 630957#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630401#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630402#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 631225#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631489#L593 assume !(1 == ~t7_pc~0); 630532#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 630533#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 631345#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631559#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 631446#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630707#L612 assume !(1 == ~t8_pc~0); 630708#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 631172#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 631003#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 631004#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 630961#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 630962#L631 assume !(1 == ~t9_pc~0); 631037#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 630288#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 630257#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630258#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 630800#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631203#L1047 assume !(1 == ~M_E~0); 630230#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 630231#L1052-1 assume !(1 == ~T2_E~0); 630211#L1057-1 assume !(1 == ~T3_E~0); 630212#L1062-1 assume !(1 == ~T4_E~0); 630497#L1067-1 assume !(1 == ~T5_E~0); 630822#L1072-1 assume !(1 == ~T6_E~0); 630823#L1077-1 assume !(1 == ~T7_E~0); 630388#L1082-1 assume !(1 == ~T8_E~0); 630389#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 630188#L1092-1 assume !(1 == ~E_M~0); 630189#L1097-1 assume !(1 == ~E_1~0); 630213#L1102-1 assume !(1 == ~E_2~0); 631032#L1107-1 assume !(1 == ~E_3~0); 630955#L1112-1 assume !(1 == ~E_4~0); 630956#L1117-1 assume !(1 == ~E_5~0); 631005#L1122-1 assume !(1 == ~E_6~0); 630878#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 630612#L1132-1 assume !(1 == ~E_8~0); 630613#L1137-1 assume !(1 == ~E_9~0); 630496#L1142-1 assume { :end_inline_reset_delta_events } true; 630360#L1428-2 [2022-11-25 17:17:57,418 INFO L750 eck$LassoCheckResult]: Loop: 630360#L1428-2 assume !false; 630361#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630432#L914 assume !false; 630952#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 630953#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 630197#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 630198#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 631226#L783 assume !(0 != eval_~tmp~0#1); 631227#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 727548#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 727546#L939-3 assume !(0 == ~M_E~0); 727544#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 727542#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 727540#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 727538#L954-3 assume !(0 == ~T4_E~0); 727536#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 727534#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 727532#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 727530#L974-3 assume !(0 == ~T8_E~0); 727528#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 727526#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 727512#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 727511#L994-3 assume !(0 == ~E_2~0); 727509#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 727507#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 727506#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 727504#L1014-3 assume !(0 == ~E_6~0); 727498#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 727497#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 630886#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 630841#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630842#L460-33 assume !(1 == ~m_pc~0); 631129#L460-35 is_master_triggered_~__retres1~0#1 := 0; 631100#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630614#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630190#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630191#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630549#L479-33 assume !(1 == ~t1_pc~0); 630550#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 727623#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 727622#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 727621#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 727620#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630557#L498-33 assume !(1 == ~t2_pc~0); 630559#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 727572#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 727571#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 727570#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 727257#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 723434#L517-33 assume !(1 == ~t3_pc~0); 723433#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 723432#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 723431#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 723430#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 723428#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 723426#L536-33 assume !(1 == ~t4_pc~0); 723424#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 723421#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723418#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 723416#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 723414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 723412#L555-33 assume !(1 == ~t5_pc~0); 723410#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 723408#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 723407#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 723406#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 723403#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 723404#L574-33 assume !(1 == ~t6_pc~0); 724153#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 724150#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 723392#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723390#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 723388#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 723383#L593-33 assume !(1 == ~t7_pc~0); 723381#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 723379#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 723377#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 723375#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 723373#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 723227#L612-33 assume !(1 == ~t8_pc~0); 723199#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 723192#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 723187#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723182#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 722386#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 710532#L631-33 assume !(1 == ~t9_pc~0); 710530#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 710527#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 710525#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 710523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 710521#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 710519#L1047-3 assume !(1 == ~M_E~0); 678798#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 710515#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 710513#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 710511#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 710509#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 710507#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 710505#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 710503#L1082-3 assume !(1 == ~T8_E~0); 710501#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 710499#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 710497#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 710495#L1102-3 assume !(1 == ~E_2~0); 710493#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 710490#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 710488#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 710486#L1122-3 assume !(1 == ~E_6~0); 710484#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 710482#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 710480#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 710478#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 710472#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 710406#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 710398#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 710397#L1447 assume !(0 == start_simulation_~tmp~3#1); 631264#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 631265#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 630479#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 631050#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 630592#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 630347#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630348#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 630824#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 630360#L1428-2 [2022-11-25 17:17:57,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2022-11-25 17:17:57,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925306957] [2022-11-25 17:17:57,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925306957] [2022-11-25 17:17:57,484 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925306957] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,484 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,484 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-25 17:17:57,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343256002] [2022-11-25 17:17:57,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,485 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:17:57,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:17:57,485 INFO L85 PathProgramCache]: Analyzing trace with hash -1173593068, now seen corresponding path program 2 times [2022-11-25 17:17:57,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:17:57,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811601091] [2022-11-25 17:17:57,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:17:57,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:17:57,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:17:57,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:17:57,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:17:57,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811601091] [2022-11-25 17:17:57,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811601091] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:17:57,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:17:57,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:17:57,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717609958] [2022-11-25 17:17:57,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:17:57,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:17:57,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:17:57,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-11-25 17:17:57,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-11-25 17:17:57,548 INFO L87 Difference]: Start difference. First operand 97465 states and 137838 transitions. cyclomatic complexity: 40377 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:17:57,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:17:57,838 INFO L93 Difference]: Finished difference Result 97465 states and 137452 transitions. [2022-11-25 17:17:57,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97465 states and 137452 transitions. [2022-11-25 17:17:58,676 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2022-11-25 17:17:58,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97465 states to 97465 states and 137452 transitions. [2022-11-25 17:17:58,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97465 [2022-11-25 17:17:58,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97465 [2022-11-25 17:17:58,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97465 states and 137452 transitions. [2022-11-25 17:17:59,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:17:59,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97465 states and 137452 transitions. [2022-11-25 17:17:59,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97465 states and 137452 transitions. [2022-11-25 17:18:00,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97465 to 97465. [2022-11-25 17:18:00,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4102703534602166) internal successors, (137452), 97464 states have internal predecessors, (137452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:00,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137452 transitions. [2022-11-25 17:18:00,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97465 states and 137452 transitions. [2022-11-25 17:18:00,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-11-25 17:18:00,444 INFO L428 stractBuchiCegarLoop]: Abstraction has 97465 states and 137452 transitions. [2022-11-25 17:18:00,444 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-11-25 17:18:00,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137452 transitions. [2022-11-25 17:18:00,758 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2022-11-25 17:18:00,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:18:00,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:18:00,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:00,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:00,767 INFO L748 eck$LassoCheckResult]: Stem: 826029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 826030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 825973#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 825974#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 826248#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 825845#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 825846#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 826219#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 825648#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 825649#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 826126#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 826127#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 825131#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 825132#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 825334#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 825743#L939 assume !(0 == ~M_E~0); 826004#L939-2 assume !(0 == ~T1_E~0); 826005#L944-1 assume !(0 == ~T2_E~0); 825774#L949-1 assume !(0 == ~T3_E~0); 825772#L954-1 assume !(0 == ~T4_E~0); 825773#L959-1 assume !(0 == ~T5_E~0); 826272#L964-1 assume !(0 == ~T6_E~0); 825488#L969-1 assume !(0 == ~T7_E~0); 825489#L974-1 assume !(0 == ~T8_E~0); 826203#L979-1 assume !(0 == ~T9_E~0); 826204#L984-1 assume !(0 == ~E_M~0); 825661#L989-1 assume !(0 == ~E_1~0); 825662#L994-1 assume !(0 == ~E_2~0); 825537#L999-1 assume !(0 == ~E_3~0); 825538#L1004-1 assume !(0 == ~E_4~0); 825198#L1009-1 assume !(0 == ~E_5~0); 825199#L1014-1 assume !(0 == ~E_6~0); 825533#L1019-1 assume !(0 == ~E_7~0); 826132#L1024-1 assume !(0 == ~E_8~0); 825457#L1029-1 assume !(0 == ~E_9~0); 825458#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 825553#L460 assume !(1 == ~m_pc~0); 826407#L460-2 is_master_triggered_~__retres1~0#1 := 0; 826090#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 826091#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 826444#L1167 assume !(0 != activate_threads_~tmp~1#1); 825761#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 825762#L479 assume !(1 == ~t1_pc~0); 825920#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 825921#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 826368#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 825472#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 825473#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 825316#L498 assume !(1 == ~t2_pc~0); 825317#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 825741#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 825742#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 826171#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 826079#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 826080#L517 assume !(1 == ~t3_pc~0); 826468#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 826469#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 825817#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 825505#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 825506#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 826145#L536 assume !(1 == ~t4_pc~0); 825807#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 825806#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 826260#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 825799#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 825800#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 826046#L555 assume !(1 == ~t5_pc~0); 826047#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 826133#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 825230#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 825231#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 825339#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 825237#L574 assume !(1 == ~t6_pc~0); 825238#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 825896#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 825342#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 825343#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 826166#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 826413#L593 assume !(1 == ~t7_pc~0); 825477#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 825478#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 826278#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 826481#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 826373#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 825654#L612 assume !(1 == ~t8_pc~0); 825655#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 826111#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 825939#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 825940#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 825900#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 825901#L631 assume !(1 == ~t9_pc~0); 825972#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 825227#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 825196#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 825197#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 825744#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 826146#L1047 assume !(1 == ~M_E~0); 825169#L1047-2 assume !(1 == ~T1_E~0); 825170#L1052-1 assume !(1 == ~T2_E~0); 825150#L1057-1 assume !(1 == ~T3_E~0); 825151#L1062-1 assume !(1 == ~T4_E~0); 825440#L1067-1 assume !(1 == ~T5_E~0); 825765#L1072-1 assume !(1 == ~T6_E~0); 825766#L1077-1 assume !(1 == ~T7_E~0); 825330#L1082-1 assume !(1 == ~T8_E~0); 825331#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 825127#L1092-1 assume !(1 == ~E_M~0); 825128#L1097-1 assume !(1 == ~E_1~0); 825152#L1102-1 assume !(1 == ~E_2~0); 825967#L1107-1 assume !(1 == ~E_3~0); 825894#L1112-1 assume !(1 == ~E_4~0); 825895#L1117-1 assume !(1 == ~E_5~0); 825941#L1122-1 assume !(1 == ~E_6~0); 825818#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 825556#L1132-1 assume !(1 == ~E_8~0); 825557#L1137-1 assume !(1 == ~E_9~0); 825438#L1142-1 assume { :end_inline_reset_delta_events } true; 825439#L1428-2 [2022-11-25 17:18:00,767 INFO L750 eck$LassoCheckResult]: Loop: 825439#L1428-2 assume !false; 901496#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 901493#L914 assume !false; 901491#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 901485#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 901474#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 901472#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 901469#L783 assume !(0 != eval_~tmp~0#1); 901470#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 906295#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 906293#L939-3 assume !(0 == ~M_E~0); 906290#L939-5 assume !(0 == ~T1_E~0); 906288#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 906286#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 906284#L954-3 assume !(0 == ~T4_E~0); 906282#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 906278#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 906277#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 906274#L974-3 assume !(0 == ~T8_E~0); 906272#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 906270#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 906268#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906266#L994-3 assume !(0 == ~E_2~0); 906264#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 906261#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 906259#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 906257#L1014-3 assume !(0 == ~E_6~0); 906255#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 906253#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 906252#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 906251#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 906250#L460-33 assume !(1 == ~m_pc~0); 906248#L460-35 is_master_triggered_~__retres1~0#1 := 0; 906245#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 906243#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 906241#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 906239#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 906237#L479-33 assume !(1 == ~t1_pc~0); 902284#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 906236#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 906235#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 906234#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 906232#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906229#L498-33 assume !(1 == ~t2_pc~0); 906226#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 906224#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 906222#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 906220#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 906218#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 901659#L517-33 assume !(1 == ~t3_pc~0); 901658#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 901657#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 901656#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 901655#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 901654#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 901653#L536-33 assume !(1 == ~t4_pc~0); 901652#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 901650#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 901649#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 901648#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 901646#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 901644#L555-33 assume !(1 == ~t5_pc~0); 901642#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 901640#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 901638#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 901636#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 901634#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 901632#L574-33 assume 1 == ~t6_pc~0; 901629#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 901627#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 901625#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 901623#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 901621#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 901619#L593-33 assume !(1 == ~t7_pc~0); 901617#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 901615#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 901613#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 901611#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 901610#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 901609#L612-33 assume !(1 == ~t8_pc~0); 901608#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 901606#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 901605#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 901604#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 901603#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 901602#L631-33 assume !(1 == ~t9_pc~0); 890412#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 901601#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 901599#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 901597#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 901595#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 901593#L1047-3 assume !(1 == ~M_E~0); 891126#L1047-5 assume !(1 == ~T1_E~0); 901590#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 901587#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 901586#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 901583#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 901581#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 901579#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 901577#L1082-3 assume !(1 == ~T8_E~0); 901575#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 901572#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 901570#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 901568#L1102-3 assume !(1 == ~E_2~0); 901566#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 901564#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 901562#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 901559#L1122-3 assume !(1 == ~E_6~0); 901558#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 901555#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 901553#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 901551#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 901543#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 901533#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 901531#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 901529#L1447 assume !(0 == start_simulation_~tmp~3#1); 901526#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 901520#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 901510#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 901508#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 901505#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 901503#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 901501#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 901499#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 825439#L1428-2 [2022-11-25 17:18:00,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:00,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2022-11-25 17:18:00,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:00,769 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725493701] [2022-11-25 17:18:00,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:00,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:00,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:00,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:00,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:00,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725493701] [2022-11-25 17:18:00,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725493701] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:00,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:00,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:18:00,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808270458] [2022-11-25 17:18:00,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:00,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:18:00,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:00,868 INFO L85 PathProgramCache]: Analyzing trace with hash 588044179, now seen corresponding path program 1 times [2022-11-25 17:18:00,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:00,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673692117] [2022-11-25 17:18:00,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:00,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:00,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:00,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:00,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:00,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673692117] [2022-11-25 17:18:00,925 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673692117] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:00,925 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:00,925 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:18:00,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369808967] [2022-11-25 17:18:00,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:00,926 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:18:00,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:18:00,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:18:00,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:18:00,927 INFO L87 Difference]: Start difference. First operand 97465 states and 137452 transitions. cyclomatic complexity: 39991 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:02,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:18:02,135 INFO L93 Difference]: Finished difference Result 154009 states and 216853 transitions. [2022-11-25 17:18:02,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154009 states and 216853 transitions. [2022-11-25 17:18:02,748 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 153504 [2022-11-25 17:18:02,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154009 states to 154009 states and 216853 transitions. [2022-11-25 17:18:02,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154009 [2022-11-25 17:18:03,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154009 [2022-11-25 17:18:03,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154009 states and 216853 transitions. [2022-11-25 17:18:03,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:18:03,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154009 states and 216853 transitions. [2022-11-25 17:18:03,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154009 states and 216853 transitions. [2022-11-25 17:18:04,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154009 to 108814. [2022-11-25 17:18:04,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108814 states, 108814 states have (on average 1.4118863381550169) internal successors, (153633), 108813 states have internal predecessors, (153633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:04,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108814 states to 108814 states and 153633 transitions. [2022-11-25 17:18:04,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108814 states and 153633 transitions. [2022-11-25 17:18:04,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:18:04,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 108814 states and 153633 transitions. [2022-11-25 17:18:04,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-11-25 17:18:04,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108814 states and 153633 transitions. [2022-11-25 17:18:05,203 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108416 [2022-11-25 17:18:05,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:18:05,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:18:05,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:05,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:05,785 INFO L748 eck$LassoCheckResult]: Stem: 1077529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1077530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1077467#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1077468#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1077754#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1077338#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1077339#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1077727#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1077130#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1077131#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1077618#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1077619#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1076615#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1076616#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1076819#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1077225#L939 assume !(0 == ~M_E~0); 1077506#L939-2 assume !(0 == ~T1_E~0); 1077507#L944-1 assume !(0 == ~T2_E~0); 1077259#L949-1 assume !(0 == ~T3_E~0); 1077255#L954-1 assume !(0 == ~T4_E~0); 1077256#L959-1 assume !(0 == ~T5_E~0); 1077774#L964-1 assume !(0 == ~T6_E~0); 1076975#L969-1 assume !(0 == ~T7_E~0); 1076976#L974-1 assume !(0 == ~T8_E~0); 1077706#L979-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1077707#L984-1 assume !(0 == ~E_M~0); 1077142#L989-1 assume !(0 == ~E_1~0); 1077143#L994-1 assume !(0 == ~E_2~0); 1077023#L999-1 assume !(0 == ~E_3~0); 1077024#L1004-1 assume !(0 == ~E_4~0); 1076683#L1009-1 assume !(0 == ~E_5~0); 1076684#L1014-1 assume !(0 == ~E_6~0); 1077627#L1019-1 assume !(0 == ~E_7~0); 1077628#L1024-1 assume !(0 == ~E_8~0); 1077920#L1029-1 assume !(0 == ~E_9~0); 1078069#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1078068#L460 assume !(1 == ~m_pc~0); 1077970#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1077971#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1077985#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1077956#L1167 assume !(0 != activate_threads_~tmp~1#1); 1077957#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1078066#L479 assume !(1 == ~t1_pc~0); 1078065#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1077972#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1077881#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1077882#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1077314#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1077315#L498 assume !(1 == ~t2_pc~0); 1077638#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1077639#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1078062#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1077672#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1077673#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1078020#L517 assume !(1 == ~t3_pc~0); 1078021#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1077994#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1077995#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1076991#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1076992#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1077818#L536 assume !(1 == ~t4_pc~0); 1077819#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1077760#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1077761#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1077286#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1077287#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1077548#L555 assume !(1 == ~t5_pc~0); 1077549#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1077701#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1076716#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1076717#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1078060#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1078059#L574 assume !(1 == ~t6_pc~0); 1077390#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1077391#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1078058#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1077664#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1077665#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1078057#L593 assume !(1 == ~t7_pc~0); 1076964#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1076965#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1078004#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1078005#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1078056#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1077135#L612 assume !(1 == ~t8_pc~0); 1077136#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1077606#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1077434#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1077435#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1078051#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1078050#L631 assume !(1 == ~t9_pc~0); 1078049#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1076712#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1076713#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1077226#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1077227#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1077644#L1047 assume !(1 == ~M_E~0); 1077645#L1047-2 assume !(1 == ~T1_E~0); 1078048#L1052-1 assume !(1 == ~T2_E~0); 1078047#L1057-1 assume !(1 == ~T3_E~0); 1076927#L1062-1 assume !(1 == ~T4_E~0); 1076928#L1067-1 assume !(1 == ~T5_E~0); 1077248#L1072-1 assume !(1 == ~T6_E~0); 1077249#L1077-1 assume !(1 == ~T7_E~0); 1078046#L1082-1 assume !(1 == ~T8_E~0); 1078045#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1076611#L1092-1 assume !(1 == ~E_M~0); 1076612#L1097-1 assume !(1 == ~E_1~0); 1076636#L1102-1 assume !(1 == ~E_2~0); 1077461#L1107-1 assume !(1 == ~E_3~0); 1077387#L1112-1 assume !(1 == ~E_4~0); 1077388#L1117-1 assume !(1 == ~E_5~0); 1077436#L1122-1 assume !(1 == ~E_6~0); 1077306#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1077043#L1132-1 assume !(1 == ~E_8~0); 1077044#L1137-1 assume !(1 == ~E_9~0); 1076925#L1142-1 assume { :end_inline_reset_delta_events } true; 1076926#L1428-2 [2022-11-25 17:18:05,786 INFO L750 eck$LassoCheckResult]: Loop: 1076926#L1428-2 assume !false; 1172869#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1172765#L914 assume !false; 1172867#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1172859#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1172849#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1172847#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1172845#L783 assume !(0 != eval_~tmp~0#1); 1172846#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1179524#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1179522#L939-3 assume !(0 == ~M_E~0); 1179520#L939-5 assume !(0 == ~T1_E~0); 1179518#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1179516#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1179514#L954-3 assume !(0 == ~T4_E~0); 1179512#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1179510#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1179508#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1179506#L974-3 assume !(0 == ~T8_E~0); 1179503#L979-3 assume !(0 == ~T9_E~0); 1179504#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1184683#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1184681#L994-3 assume !(0 == ~E_2~0); 1183837#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1183836#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1183835#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1183833#L1014-3 assume !(0 == ~E_6~0); 1183830#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1183828#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1183826#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1183824#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1183822#L460-33 assume !(1 == ~m_pc~0); 1183820#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1183816#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1183812#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1183808#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1183803#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1183798#L479-33 assume !(1 == ~t1_pc~0); 1162189#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1183789#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1183784#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1183779#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1183773#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1183769#L498-33 assume !(1 == ~t2_pc~0); 1183763#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1183758#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1183753#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1183752#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1183751#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1173401#L517-33 assume !(1 == ~t3_pc~0); 1173399#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1173396#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1173394#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1173392#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1173390#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1173388#L536-33 assume 1 == ~t4_pc~0; 1173385#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1173383#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1173382#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1173380#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1173378#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1173376#L555-33 assume !(1 == ~t5_pc~0); 1173374#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1173372#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1173369#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1173367#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1173365#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1173363#L574-33 assume !(1 == ~t6_pc~0); 1173361#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1173358#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1173356#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1173354#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1173352#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1173350#L593-33 assume !(1 == ~t7_pc~0); 1119754#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1173347#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1173344#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1173342#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1173340#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1173339#L612-33 assume 1 == ~t8_pc~0; 1173337#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1173336#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1173335#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1173333#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1173331#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1173328#L631-33 assume !(1 == ~t9_pc~0); 1114235#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1173323#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1173320#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1173317#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1173314#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1173311#L1047-3 assume !(1 == ~M_E~0); 1168961#L1047-5 assume !(1 == ~T1_E~0); 1173307#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1173305#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1173303#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1173301#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1173299#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1173294#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1173293#L1082-3 assume !(1 == ~T8_E~0); 1173292#L1087-3 assume !(1 == ~T9_E~0); 1173288#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1173286#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1173284#L1102-3 assume !(1 == ~E_2~0); 1173282#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1173280#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1173278#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1173275#L1122-3 assume !(1 == ~E_6~0); 1173273#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1173271#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1173269#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1173267#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1173241#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1173231#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1172530#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1146742#L1447 assume !(0 == start_simulation_~tmp~3#1); 1146743#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1172893#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1172883#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1172881#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1172878#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1172876#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1172874#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1172872#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1076926#L1428-2 [2022-11-25 17:18:05,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:05,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2022-11-25 17:18:05,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:05,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790794590] [2022-11-25 17:18:05,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:05,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:05,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:05,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:05,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:05,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790794590] [2022-11-25 17:18:05,959 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790794590] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:05,959 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:05,960 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:18:05,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940579856] [2022-11-25 17:18:05,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:05,960 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:18:05,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:05,961 INFO L85 PathProgramCache]: Analyzing trace with hash 548588306, now seen corresponding path program 1 times [2022-11-25 17:18:05,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:05,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190954620] [2022-11-25 17:18:05,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:05,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:05,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:06,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:06,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:06,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190954620] [2022-11-25 17:18:06,029 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190954620] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:06,029 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:06,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:18:06,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882287857] [2022-11-25 17:18:06,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:06,030 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:18:06,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:18:06,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:18:06,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:18:06,031 INFO L87 Difference]: Start difference. First operand 108814 states and 153633 transitions. cyclomatic complexity: 44823 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:06,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:18:06,531 INFO L93 Difference]: Finished difference Result 142649 states and 200202 transitions. [2022-11-25 17:18:06,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142649 states and 200202 transitions. [2022-11-25 17:18:07,087 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142240 [2022-11-25 17:18:08,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142649 states to 142649 states and 200202 transitions. [2022-11-25 17:18:08,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142649 [2022-11-25 17:18:08,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142649 [2022-11-25 17:18:08,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142649 states and 200202 transitions. [2022-11-25 17:18:08,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:18:08,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142649 states and 200202 transitions. [2022-11-25 17:18:08,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142649 states and 200202 transitions. [2022-11-25 17:18:09,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142649 to 97465. [2022-11-25 17:18:09,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4063099574206126) internal successors, (137066), 97464 states have internal predecessors, (137066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:09,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137066 transitions. [2022-11-25 17:18:09,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97465 states and 137066 transitions. [2022-11-25 17:18:09,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:18:09,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 97465 states and 137066 transitions. [2022-11-25 17:18:09,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-11-25 17:18:09,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137066 transitions. [2022-11-25 17:18:10,565 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2022-11-25 17:18:10,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:18:10,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:18:10,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:10,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:10,571 INFO L748 eck$LassoCheckResult]: Stem: 1328999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1329000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1328942#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1328943#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1329213#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1328808#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1328809#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1329183#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1328601#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1328602#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1329089#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1329090#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1328090#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1328091#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1328290#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1328701#L939 assume !(0 == ~M_E~0); 1328974#L939-2 assume !(0 == ~T1_E~0); 1328975#L944-1 assume !(0 == ~T2_E~0); 1328736#L949-1 assume !(0 == ~T3_E~0); 1328732#L954-1 assume !(0 == ~T4_E~0); 1328733#L959-1 assume !(0 == ~T5_E~0); 1329238#L964-1 assume !(0 == ~T6_E~0); 1328445#L969-1 assume !(0 == ~T7_E~0); 1328446#L974-1 assume !(0 == ~T8_E~0); 1329168#L979-1 assume !(0 == ~T9_E~0); 1329169#L984-1 assume !(0 == ~E_M~0); 1328613#L989-1 assume !(0 == ~E_1~0); 1328614#L994-1 assume !(0 == ~E_2~0); 1328494#L999-1 assume !(0 == ~E_3~0); 1328495#L1004-1 assume !(0 == ~E_4~0); 1328157#L1009-1 assume !(0 == ~E_5~0); 1328158#L1014-1 assume !(0 == ~E_6~0); 1328490#L1019-1 assume !(0 == ~E_7~0); 1329097#L1024-1 assume !(0 == ~E_8~0); 1328416#L1029-1 assume !(0 == ~E_9~0); 1328417#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1328509#L460 assume !(1 == ~m_pc~0); 1329363#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1329060#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1329061#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1329406#L1167 assume !(0 != activate_threads_~tmp~1#1); 1328721#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1328722#L479 assume !(1 == ~t1_pc~0); 1328884#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1328885#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1329327#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1328428#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1328429#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1328271#L498 assume !(1 == ~t2_pc~0); 1328272#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1328699#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1328700#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1329134#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1329049#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1329050#L517 assume !(1 == ~t3_pc~0); 1329427#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1329428#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1328780#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1328461#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1328462#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1329109#L536 assume !(1 == ~t4_pc~0); 1328770#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1328769#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1329227#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1328761#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1328762#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1329016#L555 assume !(1 == ~t5_pc~0); 1329017#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1329098#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1328189#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1328190#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1328295#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1328195#L574 assume !(1 == ~t6_pc~0); 1328196#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1328861#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1328300#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1328301#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1329129#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1329372#L593 assume !(1 == ~t7_pc~0); 1328434#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1328435#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1329243#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1329434#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1329332#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1328608#L612 assume !(1 == ~t8_pc~0); 1328609#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1329078#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1328906#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1328907#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1328866#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1328867#L631 assume !(1 == ~t9_pc~0); 1328941#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1328186#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1328155#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1328156#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1328702#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1329110#L1047 assume !(1 == ~M_E~0); 1328126#L1047-2 assume !(1 == ~T1_E~0); 1328127#L1052-1 assume !(1 == ~T2_E~0); 1328109#L1057-1 assume !(1 == ~T3_E~0); 1328110#L1062-1 assume !(1 == ~T4_E~0); 1328399#L1067-1 assume !(1 == ~T5_E~0); 1328725#L1072-1 assume !(1 == ~T6_E~0); 1328726#L1077-1 assume !(1 == ~T7_E~0); 1328285#L1082-1 assume !(1 == ~T8_E~0); 1328286#L1087-1 assume !(1 == ~T9_E~0); 1328086#L1092-1 assume !(1 == ~E_M~0); 1328087#L1097-1 assume !(1 == ~E_1~0); 1328111#L1102-1 assume !(1 == ~E_2~0); 1328936#L1107-1 assume !(1 == ~E_3~0); 1328859#L1112-1 assume !(1 == ~E_4~0); 1328860#L1117-1 assume !(1 == ~E_5~0); 1328908#L1122-1 assume !(1 == ~E_6~0); 1328781#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1328514#L1132-1 assume !(1 == ~E_8~0); 1328515#L1137-1 assume !(1 == ~E_9~0); 1328397#L1142-1 assume { :end_inline_reset_delta_events } true; 1328398#L1428-2 [2022-11-25 17:18:10,571 INFO L750 eck$LassoCheckResult]: Loop: 1328398#L1428-2 assume !false; 1418655#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1418652#L914 assume !false; 1418651#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1418648#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1418638#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1418636#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1418635#L783 assume !(0 != eval_~tmp~0#1); 1328497#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1328498#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1328935#L939-3 assume !(0 == ~M_E~0); 1425541#L939-5 assume !(0 == ~T1_E~0); 1425540#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1425539#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1425538#L954-3 assume !(0 == ~T4_E~0); 1425536#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1328161#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1328162#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1328366#L974-3 assume !(0 == ~T8_E~0); 1328367#L979-3 assume !(0 == ~T9_E~0); 1328828#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1328829#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1422057#L994-3 assume !(0 == ~E_2~0); 1422055#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1422053#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1422051#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1422050#L1014-3 assume !(0 == ~E_6~0); 1422049#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1422048#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1422045#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1422043#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1422041#L460-33 assume !(1 == ~m_pc~0); 1421802#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1421800#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1421797#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1421795#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1421780#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1410418#L479-33 assume !(1 == ~t1_pc~0); 1410416#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1410415#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1410413#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1410411#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1410409#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1410407#L498-33 assume !(1 == ~t2_pc~0); 1410404#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1410401#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410399#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1410397#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1410395#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1410393#L517-33 assume !(1 == ~t3_pc~0); 1396273#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1410390#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1410388#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1410386#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1410384#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1410376#L536-33 assume 1 == ~t4_pc~0; 1410365#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1410359#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1410352#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1410345#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1410337#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1410331#L555-33 assume !(1 == ~t5_pc~0); 1410322#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1410313#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1410306#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1410299#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1410292#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1410286#L574-33 assume !(1 == ~t6_pc~0); 1410281#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1410275#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1410267#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1410260#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1410252#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1410245#L593-33 assume !(1 == ~t7_pc~0); 1381469#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1410230#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1410224#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1410215#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1410207#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1410200#L612-33 assume 1 == ~t8_pc~0; 1410193#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1410185#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1410179#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1410172#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1410163#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1410157#L631-33 assume !(1 == ~t9_pc~0); 1369642#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1410145#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1410138#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1410132#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1410126#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1409843#L1047-3 assume !(1 == ~M_E~0); 1409841#L1047-5 assume !(1 == ~T1_E~0); 1409839#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1409837#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1409835#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1409833#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1409831#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1409829#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1409827#L1082-3 assume !(1 == ~T8_E~0); 1409825#L1087-3 assume !(1 == ~T9_E~0); 1409823#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1409771#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1409755#L1102-3 assume !(1 == ~E_2~0); 1409747#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1409738#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1409729#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1409722#L1122-3 assume !(1 == ~E_6~0); 1409715#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1409704#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1409696#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1409690#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1409542#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1409525#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1409516#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1409514#L1447 assume !(0 == start_simulation_~tmp~3#1); 1409515#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1418679#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1418669#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1418668#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1418664#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1418662#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1418660#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1418659#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1328398#L1428-2 [2022-11-25 17:18:10,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:10,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2022-11-25 17:18:10,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:10,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988425087] [2022-11-25 17:18:10,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:10,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:10,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:10,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:10,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:10,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988425087] [2022-11-25 17:18:10,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988425087] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:10,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:10,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:18:10,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126937907] [2022-11-25 17:18:10,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:10,644 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:18:10,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:10,644 INFO L85 PathProgramCache]: Analyzing trace with hash 548588306, now seen corresponding path program 2 times [2022-11-25 17:18:10,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:10,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903444124] [2022-11-25 17:18:10,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:10,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:10,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:10,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:10,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:10,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903444124] [2022-11-25 17:18:10,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903444124] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:10,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:10,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:18:10,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723803988] [2022-11-25 17:18:10,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:10,705 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:18:10,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:18:10,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:18:10,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:18:10,706 INFO L87 Difference]: Start difference. First operand 97465 states and 137066 transitions. cyclomatic complexity: 39605 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:11,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:18:11,196 INFO L93 Difference]: Finished difference Result 150769 states and 211187 transitions. [2022-11-25 17:18:11,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150769 states and 211187 transitions. [2022-11-25 17:18:11,758 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 150208 [2022-11-25 17:18:12,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150769 states to 150769 states and 211187 transitions. [2022-11-25 17:18:12,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150769 [2022-11-25 17:18:12,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150769 [2022-11-25 17:18:12,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150769 states and 211187 transitions. [2022-11-25 17:18:12,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:18:12,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150769 states and 211187 transitions. [2022-11-25 17:18:13,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150769 states and 211187 transitions. [2022-11-25 17:18:13,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150769 to 108750. [2022-11-25 17:18:13,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108750 states, 108750 states have (on average 1.4026850574712644) internal successors, (152542), 108749 states have internal predecessors, (152542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:14,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108750 states to 108750 states and 152542 transitions. [2022-11-25 17:18:14,833 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108750 states and 152542 transitions. [2022-11-25 17:18:14,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-25 17:18:14,833 INFO L428 stractBuchiCegarLoop]: Abstraction has 108750 states and 152542 transitions. [2022-11-25 17:18:14,834 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-11-25 17:18:14,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108750 states and 152542 transitions. [2022-11-25 17:18:15,076 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108352 [2022-11-25 17:18:15,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-11-25 17:18:15,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-11-25 17:18:15,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:15,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-25 17:18:15,081 INFO L748 eck$LassoCheckResult]: Stem: 1577255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1577256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1577195#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1577196#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1577480#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1577058#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1577059#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1577452#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1576854#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1576855#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1577348#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1577349#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1576336#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1576337#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1576539#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1576949#L939 assume !(0 == ~M_E~0); 1577229#L939-2 assume !(0 == ~T1_E~0); 1577230#L944-1 assume !(0 == ~T2_E~0); 1576982#L949-1 assume !(0 == ~T3_E~0); 1576978#L954-1 assume !(0 == ~T4_E~0); 1576979#L959-1 assume !(0 == ~T5_E~0); 1577502#L964-1 assume !(0 == ~T6_E~0); 1576698#L969-1 assume !(0 == ~T7_E~0); 1576699#L974-1 assume !(0 == ~T8_E~0); 1577435#L979-1 assume !(0 == ~T9_E~0); 1577436#L984-1 assume !(0 == ~E_M~0); 1576866#L989-1 assume !(0 == ~E_1~0); 1576867#L994-1 assume !(0 == ~E_2~0); 1576748#L999-1 assume !(0 == ~E_3~0); 1576749#L1004-1 assume !(0 == ~E_4~0); 1576404#L1009-1 assume !(0 == ~E_5~0); 1576405#L1014-1 assume !(0 == ~E_6~0); 1576742#L1019-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1577356#L1024-1 assume !(0 == ~E_8~0); 1576663#L1029-1 assume !(0 == ~E_9~0); 1576664#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1577775#L460 assume !(1 == ~m_pc~0); 1577681#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1577682#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1577693#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1577669#L1167 assume !(0 != activate_threads_~tmp~1#1); 1577670#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1577773#L479 assume !(1 == ~t1_pc~0); 1577772#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1577683#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1577684#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1576677#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1576678#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1576521#L498 assume !(1 == ~t2_pc~0); 1576522#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1576947#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1576948#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1577403#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1577404#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1577728#L517 assume !(1 == ~t3_pc~0); 1577729#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1577700#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1577701#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1576714#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1576715#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1577537#L536 assume !(1 == ~t4_pc~0); 1577538#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1577489#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1577490#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1577006#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1577007#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1577268#L555 assume !(1 == ~t5_pc~0); 1577269#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1577432#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1577433#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1576665#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1576666#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1577770#L574 assume !(1 == ~t6_pc~0); 1577116#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1577117#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1576549#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1576550#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1577720#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1577642#L593 assume !(1 == ~t7_pc~0); 1577643#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1577508#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1577509#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1577709#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1577609#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1577610#L612 assume !(1 == ~t8_pc~0); 1577766#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1577765#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1577764#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1577531#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1577532#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1577763#L631 assume !(1 == ~t9_pc~0); 1577762#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1576432#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1576433#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1576950#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1576951#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1577374#L1047 assume !(1 == ~M_E~0); 1577375#L1047-2 assume !(1 == ~T1_E~0); 1577110#L1052-1 assume !(1 == ~T2_E~0); 1576355#L1057-1 assume !(1 == ~T3_E~0); 1576356#L1062-1 assume !(1 == ~T4_E~0); 1577503#L1067-1 assume !(1 == ~T5_E~0); 1577504#L1072-1 assume !(1 == ~T6_E~0); 1577336#L1077-1 assume !(1 == ~T7_E~0); 1577337#L1082-1 assume !(1 == ~T8_E~0); 1577088#L1087-1 assume !(1 == ~T9_E~0); 1577089#L1092-1 assume !(1 == ~E_M~0); 1576357#L1097-1 assume !(1 == ~E_1~0); 1576358#L1102-1 assume !(1 == ~E_2~0); 1577188#L1107-1 assume !(1 == ~E_3~0); 1577189#L1112-1 assume !(1 == ~E_4~0); 1577758#L1117-1 assume !(1 == ~E_5~0); 1577747#L1122-1 assume !(1 == ~E_6~0); 1577748#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1576768#L1132-1 assume !(1 == ~E_8~0); 1576769#L1137-1 assume !(1 == ~E_9~0); 1576644#L1142-1 assume { :end_inline_reset_delta_events } true; 1576645#L1428-2 [2022-11-25 17:18:15,081 INFO L750 eck$LassoCheckResult]: Loop: 1576645#L1428-2 assume !false; 1641468#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1641109#L914 assume !false; 1641465#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1641457#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1641439#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1641430#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1641419#L783 assume !(0 != eval_~tmp~0#1); 1641420#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1683421#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1683419#L939-3 assume !(0 == ~M_E~0); 1683417#L939-5 assume !(0 == ~T1_E~0); 1683415#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1683412#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1683410#L954-3 assume !(0 == ~T4_E~0); 1683408#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1683406#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1683404#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1683402#L974-3 assume !(0 == ~T8_E~0); 1683401#L979-3 assume !(0 == ~T9_E~0); 1683400#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1683399#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1683398#L994-3 assume !(0 == ~E_2~0); 1683397#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1683396#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1683395#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1683394#L1014-3 assume !(0 == ~E_6~0); 1683393#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1683392#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1683391#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1683390#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1683389#L460-33 assume !(1 == ~m_pc~0); 1683388#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1683387#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1683386#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1683385#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1683384#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1683383#L479-33 assume !(1 == ~t1_pc~0); 1654393#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1683382#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1683381#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1683380#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1683379#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1683378#L498-33 assume !(1 == ~t2_pc~0); 1683376#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1683375#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1683374#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1683373#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1683372#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1683371#L517-33 assume !(1 == ~t3_pc~0); 1630804#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1683370#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1683369#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1683368#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1683367#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1683366#L536-33 assume !(1 == ~t4_pc~0); 1683365#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1683363#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1683362#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1683361#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1683360#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1683359#L555-33 assume !(1 == ~t5_pc~0); 1683358#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1683357#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1683356#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1683355#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1683354#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1683353#L574-33 assume !(1 == ~t6_pc~0); 1683352#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1683350#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1683349#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1683348#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1683347#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1683346#L593-33 assume !(1 == ~t7_pc~0); 1640029#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1683345#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1683344#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1683343#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1683342#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1683341#L612-33 assume 1 == ~t8_pc~0; 1683339#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1683338#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1683337#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1683336#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1683335#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1683334#L631-33 assume !(1 == ~t9_pc~0); 1630218#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1683333#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1683332#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1683331#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1683330#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1683329#L1047-3 assume !(1 == ~M_E~0); 1621379#L1047-5 assume !(1 == ~T1_E~0); 1683328#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1683327#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1683326#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1683325#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1683324#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1683323#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1683322#L1082-3 assume !(1 == ~T8_E~0); 1683321#L1087-3 assume !(1 == ~T9_E~0); 1683320#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1683319#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1683318#L1102-3 assume !(1 == ~E_2~0); 1683317#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1683316#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1683315#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1683314#L1122-3 assume !(1 == ~E_6~0); 1683313#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1576773#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1577207#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1577178#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1576589#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1576465#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1577179#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1576905#L1447 assume !(0 == start_simulation_~tmp~3#1); 1576906#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1641491#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1641480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1641478#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1641476#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1641474#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1641472#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1641470#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1576645#L1428-2 [2022-11-25 17:18:15,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:15,082 INFO L85 PathProgramCache]: Analyzing trace with hash 19846661, now seen corresponding path program 1 times [2022-11-25 17:18:15,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:15,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651479054] [2022-11-25 17:18:15,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:15,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:15,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:15,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:15,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:15,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651479054] [2022-11-25 17:18:15,146 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651479054] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:15,146 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:15,146 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-25 17:18:15,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624943795] [2022-11-25 17:18:15,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:15,147 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-11-25 17:18:15,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-25 17:18:15,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1686217171, now seen corresponding path program 1 times [2022-11-25 17:18:15,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-11-25 17:18:15,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323117312] [2022-11-25 17:18:15,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-25 17:18:15,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-25 17:18:15,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-25 17:18:15,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-25 17:18:15,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-11-25 17:18:15,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323117312] [2022-11-25 17:18:15,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323117312] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-25 17:18:15,209 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-25 17:18:15,209 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-25 17:18:15,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543342469] [2022-11-25 17:18:15,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-25 17:18:15,210 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-11-25 17:18:15,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-11-25 17:18:15,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-25 17:18:15,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-25 17:18:15,211 INFO L87 Difference]: Start difference. First operand 108750 states and 152542 transitions. cyclomatic complexity: 43796 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-25 17:18:15,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-25 17:18:15,726 INFO L93 Difference]: Finished difference Result 138297 states and 193176 transitions. [2022-11-25 17:18:15,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138297 states and 193176 transitions. [2022-11-25 17:18:16,236 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 137824 [2022-11-25 17:18:17,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138297 states to 138297 states and 193176 transitions. [2022-11-25 17:18:17,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138297 [2022-11-25 17:18:17,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138297 [2022-11-25 17:18:17,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138297 states and 193176 transitions. [2022-11-25 17:18:17,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-11-25 17:18:17,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 138297 states and 193176 transitions. [2022-11-25 17:18:17,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138297 states and 193176 transitions. [2022-11-25 17:18:18,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138297 to 97465. [2022-11-25 17:18:18,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.3970963935771816) internal successors, (136168), 97464 states have internal predecessors, (136168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)